JP2006146998A - Memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory capable of suppressing an off-leak current small with simple control while suppressing a circuit area small. <P>SOLUTION: In a memory in which overwriting is freely performed to designated address, when even one piece of data among pieces of data written in memory blocks 10 to 13, 14 to 17, and 18 to 21 constituting memory banks 110, 120, and 130 corresponding to power control circuits 4, 5, and 6 is valid data, the power control circuits 4, 5 and 6 control to turn on the power of the memory banks, and when all data written in the entire memory blocks constituting the memory banks are invalid data, the power control circuits 4, 5 and 6 control to turn off the power of the memory banks. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a memory in which data input in response to designation of an address is written to a designated address so as to be overwritten.

  In recent years, as the capacity of a memory mounted on a semiconductor chip increases and the process becomes finer, the number of transistors constituting the memory is rapidly increasing. In addition, the value of the off-leakage current (leakage current when the transistor is in an off state) of each transistor is increasing due to the miniaturization of the manufacturing process. With such an increase in the number of transistors and an increase in the off-leak current of each transistor, the off-leak current in the semiconductor chip cannot be ignored.

Therefore, a valid bit storage circuit for storing bit information indicating whether data is valid in word units and a power cut-off circuit for cutting off power in word units, and the power cut-off circuit when the bit information is invalid A technique for reducing off-leakage current by cutting off the power supply in units of words has been proposed (see, for example, Patent Document 1).
JP 2003-45189 A

  However, since the technique proposed in Patent Document 1 described above manages effective bits in units of words and turns off the power in units of words, it can be suitably applied to a small-capacity cache memory or the like. However, when this technique is applied to a large-capacity memory, a large number of effective bit storage circuits and power-off circuits are required. For this reason, a problem arises that a large circuit area is required and a burden for managing a large number of effective bits becomes large.

  In view of the above circumstances, an object of the present invention is to provide a memory capable of suppressing off-leakage current with a simple control while keeping a circuit area small.

The memory of the present invention that achieves the above object is a memory in which data input in response to an address designation is written over the designated address in a freely overwriteable manner.
A flag that is provided for each memory block that constitutes a predetermined memory capacity and indicates whether the data written in the memory block is valid data or invalid data;
A power control circuit that is provided for each memory bank including a plurality of predetermined number of memory blocks, and that controls power on and off of the memory bank;
The power supply control circuit controls the power supply of the memory bank to be on when at least one of the data written in the memory blocks constituting the memory bank corresponding to the power supply control circuit is valid data; When any of the data written in all the memory blocks constituting the memory bank is invalid data, the power source of the memory bank is controlled to be turned off.

  In the conventional technology for managing effective bits in units of words and cutting off power in units of words, it is necessary to provide a large number of effective bit storage circuits and power-off circuits in order to reduce off-leakage current in a large-capacity memory. Moreover, the burden for managing a large number of effective bits also increases.

  In the memory of the present invention, the power supply control circuit provided for each memory bank including a plurality of predetermined number of memory blocks is used to store the data written in all the memory blocks constituting the memory bank corresponding to the power supply control circuit. When both are invalid data, the memory bank is controlled to be turned off. For this reason, even in the case of reducing off-leakage current in a large-capacity memory, the power supply may be turned off for each memory bank, and the circuit configuration is simplified and the control is simple. Therefore, the off-leakage current can be suppressed with a simple control while keeping the circuit area small.

  Here, the memory of the present invention includes a memory management circuit that moves data across a plurality of memory banks so that a memory bank including only memory blocks in which written data is invalid data is formed. It is preferable.

  In this way, valid data written in a plurality of memory banks can be moved and aggregated in one memory bank, thereby being written in all the memory blocks constituting the source memory bank. Any of the data can be invalid data. Therefore, the power supply of the memory bank can be controlled to be turned off, and the off-leakage current can be further reduced.

  In addition, when the power supply control circuit controls the power supply of the memory bank having the memory block in which valid data is written to ON, when the memory bank is not accessed, the data written in the memory is stored. It is also a preferable aspect that the control is performed to the first voltage that can be held, the memory access request is received, and the second voltage that is higher than the first voltage is controlled.

  As described above, when only the memory bank that has received the memory access request is controlled to the second voltage higher than the first voltage capable of holding the data written in the memory, the high speed of the memory is maintained while keeping the off-leakage current small. Can be achieved.

  According to the memory of the present invention, the off-leakage current can be suppressed by simple control while keeping the circuit area small.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of a memory according to an embodiment of the present invention.

  A memory 1 shown in FIG. 1 is a memory which receives designation of an address ADR, input of data DATA, and a control signal CNT, and writes the inputted data DATA to a designated address ADR so as to be overwritten.

  The memory 1 includes a memory block control unit 2 having a memory management function unit 2a and an address conversion function unit 2b described later. The memory block control unit 2 converts and outputs the input address ADR as necessary, and moves data in the memory block as necessary. The memory block control unit 2 generates and outputs a memory control signal MCNT and a power supply control signal PCNT based on the input control signal CNT.

  The memory 1 includes a power supply circuit 3, power control circuits 4, 5, and 6, and memory banks 110, 120, and 130. Actually, the memory 1 is provided with a large number of power supply control circuits and a large number of memory banks, but here, for example, three power supply control circuits 4, 5, 6 and three memory banks 110 are provided. , 120, 130.

  The power supply circuit 3 receives a control signal PCNT from the memory block control unit 2 and supplies a voltage V1 described later in detail or a voltage V2 higher than the voltage V1 to supply the power control circuits 4, 5, and 6 Generate.

  The power control circuits 4, 5, and 6 correspond to an example of the power control circuit according to the present invention, and the power control circuits 4, 5, and 6 are provided corresponding to the memory banks 110, 120, and 130, respectively. . The power supply control circuits 4, 5, and 6 are supplied with the voltage V1 or the voltage V2 from the power supply circuit 3. Each power control circuit 4, 5, 6 turns on / off the power of each memory bank 110, 120, 130.

  The memory bank 110 is composed of four memory blocks (here, two memory blocks 10 and 13 are shown as an example). Each memory block has a valid bit (corresponding to an example of a flag in the present invention, which indicates whether the data written in each memory block is valid data or invalid data. The effective bits 10a and 13a are exemplarily shown).

  The memory bank 120 is also composed of four memory blocks (two memory blocks 14 and 17 are exemplarily shown). In each memory block, the data written in each memory block is valid data. A valid bit (corresponding to an example of a flag according to the present invention, which shows valid bits 14a and 17a is shown here) indicating whether the data is valid or invalid data is provided.

  Further, the memory bank 130 is also composed of four memory blocks (two memory blocks 18 and 21 are shown as examples). In each memory block, the data written in each memory block is valid data. A valid bit (corresponding to an example of the flag according to the present invention, and here, the valid bits 18a and 21a are exemplarily shown) indicating whether the data is valid or invalid data is provided.

  Here, the power supply control circuit 4 determines that the memory bank 110 is valid when at least one of the data written in the memory blocks 10 to 13 constituting the memory bank 110 corresponding to the power supply control circuit 4 is valid. The power of the memory bank 110 is turned off when all the data written in all the memory blocks 10 to 13 constituting the memory bank 110 are invalid data.

  Similarly, when the power supply control circuit 5 is valid data even when one of the data written in the memory blocks 14 to 17 constituting the memory bank 120 corresponding to the power supply control circuit 5 is valid. The power supply of the memory bank 120 is controlled to be turned on, and the power supply of the memory bank 120 is controlled to be turned off when any of the data written in all the memory blocks 14 to 17 constituting the memory bank 120 is invalid data To do.

  Further, the power supply control circuit 6 determines that the data stored in the memory bank 130 is valid when at least one of the data written in the memory blocks 18 to 21 constituting the memory bank 130 corresponding to the power supply control circuit 6 is valid. The power supply is controlled to be turned on, and the power supply to the memory bank 130 is controlled to be turned off when all the data written in all the memory blocks 18 to 21 constituting the memory bank 130 are invalid data.

  As described above, each of the power supply control circuits 4, 5, 6 has any of the data written in all the memory blocks 10-13, 14-17, 18-21 constituting each memory bank 110, 120, 130. When the data is invalid data, the power supply of each memory bank 110, 120, 130 is controlled to be turned off. Therefore, in order to reduce the off-leak current in the memory 1, the power supply may be turned off for each memory bank. The circuit configuration is simplified and the control is simple. Therefore, the off-leakage current in the memory 1 can be reduced by simple control while keeping the circuit area small.

  In addition, when the power supply control circuits 4, 5 and 6 control the power supply of a memory bank having a memory block in which valid data is written to ON, when the memory bank is not accessed, data is written into the memory. In response to a memory access request, a voltage V2 higher than the voltage V1 (corresponding to the second voltage according to the present invention) is controlled. ) To control. As described above, in the memory 1 of the present embodiment, the voltage of the memory bank that is not accessed is controlled to the voltage V1, so that the off-leak current of the transistors that constitute the memory block in which valid data is written is reduced. can do. Further, by controlling only the memory bank that has received the memory access request to the voltage V2, the memory 1 can be accessed at high speed while keeping the off-leakage current small.

  FIG. 2 shows a configuration of power supply control circuit 4 and memory bank 110 shown in FIG.

  The configurations of the remaining power control circuit 5 and memory bank 120 and the configurations of power supply control circuit 6 and memory bank 130 are the same as the configurations of power control circuit 4 and memory bank 110 shown in FIG.

  The power supply control circuit 4 shown in FIG. 2 includes a NOR gate 4a and PMOS transistors 4b, 4c, 4d, and 4e. The output of the NOR gate 4a is commonly connected to the gates of the PMOS transistors 4b, 4c, 4d, and 4e. The voltage V1 (or voltage V2) is supplied to the sources of the PMOS transistors 4b, 4c, 4d, and 4e.

  On the other hand, valid bits 10a, 11a, 12a, and 13a are provided in the memory blocks 10, 11, 12, and 13 constituting the memory bank 110. Here, these valid bits 10a, 11a, 12a, and 13a are logical 0 indicating that the data written in the memory blocks 10, 11, 12, and 13 are invalid data. Since these logic 0s are input to the NOR gate 4a, a logic 1 is output from the NOR gate 4a. Since this logic 1 is input to the gates of the PMOS transistors 4b, 4c, 4d, and 4e, the PMOS transistors 4b, 4c, 4d, and 4e are turned off, and the memory block 10, 11, 12, and 13 have the voltage V1 ( Alternatively, the voltage V2) is not supplied, and therefore the off-leakage current of the transistors constituting the memory blocks 10, 11, 12, and 13 can be reduced.

  FIG. 3 is a diagram showing a state in which valid data is written in the memory block 11 and power is supplied to the memory bank in the power control circuit 4 and the memory bank 110 shown in FIG.

  When valid data is written in the memory block 11 constituting the memory bank 110, the valid bit 11a changes to valid (logic 1). This logic 1 is input to the NOR gate 4a, whereby a logic 0 is output from the NOR gate 4a. Since this logic 0 is input to the gates of the PMOS transistors 4b, 4c, 4d, and 4e, the PMOS transistors 4b, 4c, 4d, and 4e are turned on. In this way, the voltage V1 (or V2) is supplied to the memory blocks 10, 11, 12, and 13.

  By the way, when data is written in the memory 1, it can be determined that the data in the memory block is valid, but it is difficult to determine when the data has become invalid. Therefore, a control signal CNT for notifying that data in the memory block has become invalid is input to the memory block control unit 2 of the memory 1. The memory management function unit 2a constituting the memory block control unit 2 has a block purge function (block invalid function) that operates in response to the control signal CNT. Hereinafter, a description will be given with reference to FIG.

  FIG. 4 is a diagram for explaining a block purge function in power supply control circuit 4 and memory bank 110 shown in FIG.

  When only the memory block 11 constituting the memory bank 110 shown in FIG. 4 is a valid block, the memory block 11 is purged (invalidated) by the block purge function. As a result, the valid bit 11a is invalidated, and therefore all the memory blocks 10 to 13 constituting the memory bank 110 are invalidated, so that the power supply control circuit 4 can control the power supply to be turned off. As a result, the voltage V1 (or voltage V2) is not supplied to the memory blocks 10, 11, 12, and 13, and therefore the off-leak current of the transistors that constitute the memory blocks 10, 11, 12, and 13 can be reduced. This function is highly compatible with a memory management function (garbage collection) such as basic software, and the load on the memory management function unit 2a can be relatively small.

  Further, as a feature of memory access, access is often made with continuous addresses. That is, it is often accessed in units of data of a certain size. By managing the effective bits in units of memory blocks, the validity of the data can be managed as a unit, so that the management load is efficient and the management load is reduced. However, considering access in units of memory blocks, the block access cannot be said to be continuous, and effective memory blocks are scattered on the memory 1, and there are memory banks that can be controlled to turn off the power. Therefore, the effect of reducing the off-leakage current is reduced. Therefore, in the present embodiment, the memory block control unit 2 includes the address conversion function unit 2b, so that effective memory blocks can be prevented from being scattered regardless of the block at the time of writing.

  FIG. 5 is a diagram for explaining a state in which effective memory blocks are not scattered in the memory shown in FIG.

  In FIG. 5, when writing (access) to the memory blocks 11, 15, 13, 18 is in the order of the memory blocks 11, 15, 13, 18, the memory banks 110, 120, However, by using the address conversion function unit 2b, access to the memory block 11 is accessed to the memory block 10, access to the block 15 is to block 11, and access to the block 13 is block. 12, the access of the block 18 can be converted into the access of the block 13, respectively. The data is collected in the memory bank 110, and the power of the memory banks 120 and 130 can be controlled to be turned off. Therefore, the effect of reducing off-leakage current can be maximized.

  As an example, it is assumed that a memory block has 256 words (equivalent to 8 bits of address), one memory bank is configured by four memory blocks, and a memory having a three memory bank configuration. There are 12 memory blocks in the memory. Therefore, the memory space becomes necessary and sufficient with 12 bits of address. Since the address compiled by the address translation function unit 2b is a block address, it is 4 bits on the MSB side in the 12-bit address. The address conversion table in the memory can be realized by a memory of 12 words × 4 bits (hereinafter referred to as an address conversion memory). As described with reference to FIG. 5, the memory blocks 11, 15, 13, When writing is performed in the order of 18, since access to the memory block 11 is converted to the memory block 10, the conversion destination block address 10 is written to the address 11 of the address conversion memory. Since the address of the address must be converted from the address conversion memory data to the block 10, the MSB side 4 bits are converted to 0 out of all 12-bit addresses, and the LSB side 8 bits are used as they are without conversion. Next, the access to the memory block 15 is converted to the memory block 11. Therefore, 11 which is the conversion destination address is written to the address 15 of the address conversion memory, so that access to the memory block 13 is converted to the memory block 12 and access to the memory block 18 is converted to the memory block 13 in the same manner. 12 is written in the address 13 of the address conversion memory and 13 is written in the address 18. In the present embodiment, it is assumed that there is no valid data in the memory block of the conversion destination. Since there may be data, the valid bit must be scanned and the block for which no valid data exists must be designated as the destination block for conversion. Since it is only necessary to scan, it is difficult to restrict memory access.

  Even if such an address translation table is used, valid memory blocks are scattered by the block purge function when the memory is used for a long period of time. (Banks) will decrease. This can be solved by providing a memory management function inside the memory. Regarding the scattered effective memory blocks, when there is no access to the memory from outside, the effective memory blocks are moved to increase the number of memory banks that can be turned off. Hereinafter, a description will be given with reference to FIG.

  FIG. 6 is a diagram for explaining how the memory shown in FIG. 1 increases the number of memory banks that can be turned off by moving an effective memory block.

  The memory management function unit 2a illustrated in FIG. 6 has a function of moving data across a plurality of memory banks so that a memory bank including only memory blocks in which written data is invalid data is formed.

  The memory bank 120 shown in FIG. 6 has only one effective memory block (memory block 16). On the other hand, there is one invalid memory block in the memory bank 110 (memory block 12). In this case, the power of the memory bank 120 can be turned off by moving the data in the memory block 16 to the memory block 12 by the memory management function unit 2a. Details will be described below.

  Since data is moved from the memory block 16 to the memory block 12, the valid bit of the memory block 12 is validated. In this way, when new memory data is written during block movement, the movement of the block is interrupted, but writing to the memory block 12 is not performed. When there is no access to the memory from the outside, the block movement can be resumed. When the movement of all data is completed, the address conversion registration is changed. For example, if the data of the block 16 is originally the data of the block 19, “block 19 → block 16” is registered, but since the data of the block 16 is moved to the block 12 this time, “block 19 → Change registration to "Block 12". After the registration change, the valid bit of block 16 is invalidated. In this embodiment, the valid bit of the block 12 that is the block move destination is made valid before the block move, but this may be any time before the address translation registration is changed. When writing to the block movement destination block 12 is performed by memory access from the outside during the block movement, it is only necessary to discard the interrupted block movement.

  In this embodiment, the power supply control circuit controls the power supply to be turned off to reduce the off-leakage current. However, the power supply voltage may be reduced to reduce the off-leakage current.

  Next, the case where the speed is increased will be described with reference to FIG.

  FIG. 7 is a diagram for explaining how to increase the speed of memory access while suppressing an increase in off-leakage current in the memory shown in FIG.

  When the memory block 11 shown in FIG. 7 is accessed (1) via the memory block control unit 2, the memory block control unit 2 outputs access information (2) to the power supply circuit 3. In response to this, the power supply circuit 3 issues a voltage boost instruction (3) to the power supply control circuit 4. Specifically, the voltage V2 is output from the power supply control circuit 4. In this way, by increasing the power supply voltage of the memory bank 110 including the memory block 11, it is possible to increase the speed of memory access while suppressing an increase in off-leakage current.

  In this embodiment, the power supply voltage of the memory bank 110 is raised or lowered by the voltage supplied to the power supply control circuit 4, but a booster circuit or a step-down circuit may be provided in the power supply control circuit 4. Alternatively, a plurality of power supply wirings are provided on the semiconductor chip on which the memory 1 is formed and connected to the power supply control circuit 4, and connection of the power supply wiring is controlled by a power supply control circuit replacing the power supply circuit 3. The power supply voltage may be adjusted.

  Next, the area reduction effect in the memory to which the present invention is applied will be described.

  FIG. 8 is a diagram showing a configuration for explaining the area reduction effect of the memory to which the present invention is applied.

  The memory shown in FIG. 8 is a memory having a size of 256K words × 64 bits (16 Mbits). One block is composed of 256 words, and one memory bank is composed of 8 blocks. ... 327. In addition, power supply control circuits 400,..., 527 corresponding to the memory banks 200,. The power supply control circuits 400,... 527 have a configuration in which PMOS transistors are arranged in a line. Conventionally, a power supply control circuit and a valid bit are added for each word. Here, in the prior art, it is considered that one power supply control circuit is shared by two words.

  FIG. 9 is a diagram showing a circuit configuration of a memory sharing one power supply control circuit with two words.

  The memory 600 shown in FIG. 9 includes memory words 610 and 611 each having 64 bits. The memory words 610 and 611 have valid bits 610a and 611a. Further, the memory 600 is provided with a power supply control circuit 900. The power supply control circuit 900 includes 64 PMOS transistors 701, 702,..., 864 corresponding to the memory word 610, and 64 PMOS transistors 801, 802,. . In this way, the power supply control circuit 900 is assumed to be shared by two words in terms of occupied area. The size of the power supply control circuit 900 is the same size as one word in width and the height is 1/3 of 1 bit. Assume that Then, in terms of area, the area of the memory can be reduced as a whole, although the area is increased by 17% compared with the memory without the power supply control circuit 900 added. Here, since the memory shown in FIG. 8 has one power supply control circuit in one memory bank, the memory shown in FIG. 9 is compared with the technique devised to share the power supply control circuit 900 with two words. , The area can be kept small.

  Incidentally, it is difficult to configure a standard memory as shown in FIG. This is because the configuration shown in FIG. 10 is used to reduce the number of bit line drivers and sense amplifiers having a relatively large area and large power consumption among the circuits constituting the memory due to the reduction in area and the reduction in power consumption. It is because it is common.

  FIG. 10 is a diagram showing a configuration of a conventional memory.

  The memory shown in FIG. 10 is a memory having a size having 64 8K memory cells × 32 memory cells, and is composed of a total of 128 banks in which one block is composed of 256 words and one bank is composed of 8 blocks. It is. It is difficult to apply the prior art to the memory having the configuration shown in FIG. On the other hand, in the present embodiment, since one power supply control circuit is provided for each bank (2k words), it can be easily applied to the general memory shown in FIG. If the control circuit is installed, the area will increase by 1.5%. However, in this embodiment, the memory block control unit 2 (memory and a little logic) having the address conversion function unit 2b is required, and in this embodiment, a memory of 1 k words × 10 bits (10 k bits) is required. However, since this is less than 0.1% of the original memory, it is not necessary to consider in terms of area. In addition, when a booster circuit or a step-down circuit is included in the power supply control circuit, the area of the power supply control circuit itself inevitably increases. For example, if it is doubled, the area is increased by 33% in the prior art, and is only increased by 3% in the present embodiment. Further, when the power supply control circuit has an area three times larger, the disparity widens, such as 50% increase in the conventional technology and 4.5% increase in the present embodiment.

It is a figure which shows the structure of the memory of one Embodiment of this invention. FIG. 2 is a diagram showing a configuration of a power supply control circuit 4 and a memory bank 110 shown in FIG. FIG. 3 is a diagram illustrating a state in which valid data is written in a memory block 11 and power is supplied to the memory bank in the power supply control circuit 4 and the memory bank 110 illustrated in FIG. 2. FIG. 3 is a diagram for explaining a block purge function in the power supply control circuit 4 and the memory bank 110 shown in FIG. 2. FIG. 2 is a diagram for explaining a state in which effective memory blocks are not scattered in the memory shown in FIG. 1. In the memory shown in FIG. 1, it is a figure for demonstrating a mode that the memory bank which can move an effective memory block and can turn off a power supply is increased. FIG. 2 is a diagram for explaining how to increase the speed of memory access while suppressing an increase in off-leakage current in the memory shown in FIG. 1. It is a figure which shows the structure for demonstrating the area reduction effect of the memory to which this invention is applied. It is a figure which shows the circuit structure of the memory which shares one power supply control circuit by 2 words. It is a figure which shows the structure of the conventional memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,600 Memory 2 Memory block control part 2a Memory management function part 2b Address conversion function part 3 Power supply circuit 4, 5, 6, 400, ..., 527,900 Power supply control circuit 4a NOR gate 4b, 4c, 4d, 4e, 701 , 702,..., 764, 801, 802,..., 864 PMOS transistor 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 Memory block 10a, 11a, 12a, 13a, 14a , 15a, 16a, 17a, 18a, 19a, 20a, 21a, 610a, 611a Effective bits 110, 120, 130, 200,..., 327 Memory bank 610, 611 Memory word

Claims (3)

In the memory that writes the data entered in response to the address specification to the specified address in a freely overwriteable manner,
A flag that is provided for each memory block constituting a predetermined memory capacity and indicates whether the data written in the memory block is valid data or invalid data;
A power control circuit that is provided for each memory bank including a plurality of predetermined number of memory blocks, and that controls power on and off of the memory bank;
The power supply control circuit controls the power supply of the memory bank to be ON when at least one of the data written in the memory blocks constituting the memory bank corresponding to the power supply control circuit is valid data; A memory characterized in that when any of data written in all memory blocks constituting the memory bank is invalid data, the power of the memory bank is controlled to be turned off.   2. A memory management circuit for moving data across a plurality of memory banks so as to form a memory bank composed only of memory blocks in which written data is invalid data. Memory.   The power supply control circuit can hold the data written in the memory when the memory bank is not accessed when the power of the memory bank having the memory block in which valid data is written is turned on. 3. The control circuit according to claim 1, wherein the first voltage is controlled to a second voltage that is higher than the first voltage upon receiving a memory access request. Memory.

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