JP2009230205A - Memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory system effectively using relaxation effect when using a flash memory to allow construction of a high-reliability system. <P>SOLUTION: The memory system has: a RAM 13 and a NAND memory 11 wherein an erasure unit and a write/read unit vary; and control circuits 12, 14, 15 controlling them. In the memory system, the NAND memory has a cache area and a main storage area wherein use of data to be stored is different. The control circuit has a function of managing: a first list 21 storing data showing a block area during use among the erasure units in the NAND memory; a second list 22 storing data showing an unused or already used block area; a third list 23 prepared for securing an erasure interval to the NAND memory, storing data showing the already used block area in response to the main storage area and the cache area; and a fourth list 24. The number of data entries of the third list 23 is smaller than the number of data entries of the fourth list 24. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a memory system using a flash EEPROM type nonvolatile memory, and more particularly to a memory system using a NAND type flash memory whose retention characteristics (data retention characteristics) deteriorate when the write / erase time interval is shortened. For example, it is used as a substitute for a hard disk drive.

  Currently, semiconductor memories are used everywhere from the main memory of large computers to personal computers, home appliances, mobile phones and the like. The market that has grown significantly is Flash EEPROM type non-volatile memory (hereinafter referred to as flash memory). This is used for many information devices such as mobile phones and digital cameras because the data does not disappear even when the power is turned off and the structure is suitable for high integration. That is, various memory cards (SD cards, SD cards, MP3 and other music devices, storage media such as mobile PCs, digital TVs, etc.) are used as media for storing information such as images, videos, sounds, and games. MMC card, MS card, CF card, etc.), USB memory (USB memory) as a storage medium for personal computers, mobile phone memory, etc.

Flash memory mainly includes NOR-type memory (NOR memory) and NAND-type memory (NAND memory). NOR memory has the characteristics of high-speed reading and the number of ^{readings of} about 10 ¹³ and is used as an instruction code storage for portable devices, but it is not suitable for file recording because its effective writing bandwidth is small.

  On the other hand, NAND memory can be highly integrated compared to NOR memory, and the read characteristics are slow, with an access time of about 25 us, but burst reading is possible and the effective bandwidth is high. As for the write characteristics, although the program time is as slow as 200us and the erase time is about 1ms, the number of bits that can be programmed and erased at one time is large, the write data is captured by burst operation, and a large number of bits are paged at a time. Because it can be programmed, the effective bandwidth is high.

In addition, since the NAND memory can be increased in capacity by high integration, it has recently been considered as a replacement of a hard disk, but there are some restrictions in use. First, since there is data deterioration due to the number of read / write (& erase) times, there is a write number limit (program / erase number limit). That is, the NAND memory program injects electrons into the floating gate by applying a high voltage to the gate of the memory cell transistor with respect to the substrate. If this operation is performed many times, the oxide film around the floating gate of the memory cell transistor deteriorates and the data is destroyed. Currently, the reading and writing of the NAND memory (and erase) possible number of times is about 10 ⁵ times, very low compared to other non-volatile memory, along with the multi-level of miniaturization and cell of the future of the process, writing the number of times Is expected to decrease further. When using NAND memory with a memory card or USB memory, it takes a considerable amount of time to access about 10 ⁵ times, so NAND memory can be used practically. However, considering that NAND memory is installed in a hard disk replacement system, it will be accessed about 10 ⁵ times in a very short time.

  In addition, NAND memory has a large erasure unit, so there is little trouble when handling large amounts of data such as image data and music files. However, in a normal PC environment, not only large amounts of data are handled. It will accelerate fatigue.

  One solution that can deal with such problems is to use RAM, such as DRAM or FeRAM, as the storage medium. Since RAM can be read / written at high speed and can be overwritten, the use of RAM as a flash memory write buffer or cache (Cache) can only cover fatigue of NAND memory. In addition, the effective read / write bandwidth can be increased.

  However, recently, it has become difficult to secure enough RAM capacity to cover the fatigue of NAND memory, but the increase in capacity of NAND memory is remarkable, and not only in RAM but also in NAND memory as a cache. It is possible to further suppress the fatigue of the NAND memory. In this case, the cache capacity in the NAND memory is preferably large, but the user usable area is reduced.

  In addition, NAND memory has the property that the retention characteristic (data retention characteristic) deteriorates as the erase time interval is shorter, and recently, a system that increases the erase time interval is required.

The integrated memory and controller of Patent Document 1 receives the first address from the first bus, maps the first address to the second address in the NAND memory device, and stores the first address in the NAND memory device. Means are provided for operating the volatile RAM memory device as a cache for data to or from the second address. Further disclosed is a means for maintaining consistency between the data stored at the second address in the NAND memory device and the data stored in the volatile RAM memory device functioning as a cache. .
JP 2007-183962 A

  The present invention has been made to solve the above-described conventional problems, and provides a memory system capable of effectively utilizing the relaxation effect and constructing a highly reliable system when a flash memory is used. For the purpose.

  The present invention provides a flash EEPROM memory and RAM having different read / write units and erase units, and a memory system having a control circuit for controlling the flash EEPROM memory and RAM. A first list for storing data indicating a block area in use among erase units in the flash EEPROM memory, and an unused or used memory. A second list for storing data indicating the block area and a data for indicating a used block area corresponding to the two storage areas are prepared to secure an erasure interval for the flash EEPROM memory. A third list and a fourth list to manage the third list and the third list Preparative and fourth list, each of the number of data entry is different from each other.

  According to the present invention, in a memory system using a flash memory, a relaxation effect can be achieved by appropriately using a cache area with a short write interval and a short data retention period and a main storage area with a long write interval and a long data retention period. Can be used effectively and a highly reliable system can be constructed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, common parts are denoted by common reference numerals throughout the drawings.

<First Embodiment>
FIG. 1 shows an example of a hardware configuration of a memory system according to the first embodiment of the present invention. In this memory system 10, a flash memory (NAND memory in this example) 11, a controller (NAND control circuit) 12 that controls the NAND memory 11, a random access memory (RAM) 13, and a RAM 13 are controlled. And a controller (RAM control circuit) 14. Here, the NAND memory 11 has at least a first storage area and a second storage area that are different in data usage. In this example, the NAND memory 11 is a main storage area (user data area) 111 that mainly stores large amounts of data (large data) and a cache area that handles small amounts of data (small data) (hereinafter referred to as NAND cache). 112). The RAM 13 is assumed to have a save area at the time of data erasure of the NAND memory 11, a cache area for data reading / writing of the NAND memory 11, and the like.

  In addition, the memory system 10 includes a micro control unit (MPU) 15 that performs processing such as management of the used block area and management of the unused block area of the NAND memory 11 based on a control program, Interface circuit (IF) 16 connected to a host (not shown, for example, a personal computer; PC).

  When reading / writing from / to the memory system 10 from a PC connected to the memory system, not only large-capacity data but also small-capacity data are frequently accessed. When writing of small-capacity data is repeated in the NAND memory 11, the amount of erasure increases with respect to the amount of writing, so the deterioration of the NAND memory 11 is accelerated. Therefore, although deterioration is suppressed by using the RAM 13 as a write cache, by providing the NAND cache 112 in the NAND memory 11, the deterioration can be further reduced. Since the NAND cache 112 mainly performs additional writing, the management unit may be arbitrary. However, the smaller the management unit, the easier it is to manage small-capacity data, so that deterioration can be suppressed, and the larger the capacity, the smaller. Since capacity data can be stored, it is effective in reducing deterioration.

  2 and 3 show an example of a data management list (table) used for erasure management in the memory system. As shown in FIG. 2, the NAND control circuit 12 is an AB list 21 which is a first list for storing data indicating a block (hereinafter referred to as Active Block; AB) area in use among the erase units in the NAND memory 11. And a function of managing an FB list 22 which is a second list for storing data indicating an unused block area or a used and invalid block (hereinafter referred to as Free Block; FB) area.

  Furthermore, the NAND control circuit 12 has a function of managing a correspondence list 20 of addresses (hereinafter referred to as L_adr) managed by the PC and addresses (hereinafter referred to as P_adr) indicating write positions in the NAND memory 11.

  Further, as shown in FIGS. 6 and 7, which will be described later, the NAND control circuit 12 is arranged in the cache area and the main storage area in order to secure erase time intervals corresponding to the cache area and the main storage area, respectively. Correspondingly, it has a function of managing an FB list (1-1) 23 which is a third list for storing data indicating used block areas and an FB list (1-2) 24 which is a fourth list. In this case, the FB list (1-1) 23 and the FB list (1-2) 24 have different data entry numbers. In this example, the number of entries in the FB list (1-2) 24 for the main storage area is cached. Less than the number of data entries in the area FB list (1-1) 23.

  Hereinafter, an operation example of the memory system will be described with reference to FIG. When data is written to the memory system from the PC and writing to the NAND memory 11 occurs, the previous data is overwritten. At this time, the block area (erase unit area) where the previously written data is stored in the NAND memory 11 may be erased and written, but the number of times of erasure may be reduced by writing to the block area which is not currently used. it can. At that time, it is necessary to manage the correspondence list 20 of L_adr and P_adr.

  Also, in such a memory system, the AB list 21 that manages the currently used (used) block area in the NAND memory 11 and the unused block area or the used and invalid block area are managed. Use FB list (2) 22 etc.

  When writing to the NAND memory 11 occurs, writing to the current FB area occurs (in a write-once area such as a cache area, writing is possible without acquiring a new FB area). When data is written to the NAND memory 11, the contents of the correspondence list 20 of L_adr and P_adr are updated, and the newly written block area is deleted from the FB list and registered in the AB list 21, and the invalid block The area is deleted from the AB list 21 and registered in the FB list. At this time, the block area goes back and forth between the AB list 21 and the FB list 22 unless it becomes unusable due to a write / erase error or the like.

  By the way, when writing to the NAND memory 11 occurs, the invalid block area may be registered in the FB list 22 and used immediately in the next writing or the like. However, the recent large-capacity NAND memory 11 has a relationship between an Erase interval (time) and a retention time (data retention guarantee time) as shown in FIG. 4, and has a retention characteristic when the erase interval is short. Since it gets worse, it is better not to use the block area registered in the FB list 22 for a while.

  In view of such circumstances, in the present invention, as shown in FIG. 5, in order to secure an erasing time interval, the FB list 22 is divided and a FB list (1) having a low priority of a block area to be newly written is provided. . The remaining divided FB list (2) is hereinafter referred to as a normal FB list 22.

  In the present invention, as shown in FIG. 6, the FB list (1) is divided according to the write frequency, and the FB list (1-1) 23 is provided corresponding to the block area data used in the cache area. An FB list (1-2) 24 is provided corresponding to the data of the block area used in the storage area.

  In the block area used in the cache area, the data writing frequency is generally high, and the interval from being registered in the AB list 21 to being deleted is short. On the other hand, the block area used in the main storage area shows a tendency opposite to the block area used in the cache area (the interval from being registered in the AB list 21 to being deleted is long). Therefore, set a larger number of data entries in the FB list (1-1) 23 corresponding to the block area used in the cache area, and set the FB list (1-2) corresponding to the block area used in the main storage area. The number of 24 data entries may be set to a small value. In other words, the number of data entries in the FB list (1-2) 24 corresponding to the block area used in the main storage area is changed to the number of data entries in the FB list (1-1) 23 corresponding to the block area used in the cache area. It may be less than the number of data entries.

  In addition, the trigger to drive data from the FB list (1-1) 23 and FB list (1-2) 24 to the normal FB list 22 may be when the list is full, or after a certain period of time management. Even when left alone.

  Here, if a trigger is used when left unattended for a certain period, there is no block registered in the normal FB list 22, especially when the number of FB blocks is almost reduced due to user data. In some cases.

  In that case, the AB list 21 will obtain data from the FB list (1-1) 23 and FB list (1-2) 24, but if the usage of the data to be used is a cache area, the data will be Since it is not necessary to hold for a long time, data is acquired from the FB list (1-1) 23 for the cache area having relatively poor retention characteristics. On the other hand, if the purpose of the data to be used is the main storage area, it is necessary to keep the data for a long time, so the data is obtained from the main storage area FB list (1-2) 24 .

  The RAM 13 of the above embodiment can be a volatile or non-volatile memory that is faster than the NAND memory 11, such as DRAM, SRAM, FeRAM, MRAM, PRAM, or the like. In the above embodiment, the NAND memory 11 is divided into a large data area and a small data area. However, a medium data area for storing medium-capacity data is provided, and the NAND memory 11 may be implemented according to the above embodiment. Is possible.

1 is a block diagram showing a hardware configuration according to a first embodiment of a memory system of the present invention. FIG. The figure which shows an example of the data management list | wrist used for deletion management in the memory system of FIG. 1 is a diagram showing an operation example of the memory system. The characteristic view which shows the relationship between the erase interval and retention time in a large-capacity NAND memory. The figure which shows an example of the remaining FB list (2) which divided | segmented the FB list | wrist in the memory system of FIG. FIG. 2 is a diagram showing an example of an erase interval management list divided according to write frequency for main storage area and cache area in the memory system of FIG. 1. The figure which shows an example of the relationship of the timing which drives out from the FB list for erasure | elimination space reservation to the normal FB list in the memory system of FIG.

Explanation of symbols

10 ... Memory system, 11 ... NAND memory, 111 ... Main memory area, 112 ... Cache area, 12 ... NAND control circuit, 13 ... RAM, 14 ... RAM control circuit, 15 ... MCU, 16 ... IF, 20 ... L_adr and P_adr Correspondence list, 21 ... used block area list, 22 ... unused / used block area list, 23 ... cache area FB list, 24 ... main memory area FB list.

Claims (6)

In a memory system having a flash EEPROM memory and RAM having different read / write units and erase units, and a control circuit for controlling the flash EEPROM memory and RAM,
The flash EEPROM memory has at least a first storage area and a second storage area that have different uses for data to be stored;
The control circuit includes: a first list for storing data indicating a block area in use among erase units in the flash EEPROM memory; and a second list for storing data indicating a block area that is not used or used; A third list for storing data indicating a used block area corresponding to the first storage area and the second storage area, and a fourth list prepared for securing an erasing interval with respect to the flash EEPROM memory; A memory system, wherein the third list and the fourth list have different numbers of data entries.   The first storage area is a main storage area, the second storage area is a cache area, and the number of data entries in the third list is smaller than the number of data entries in the fourth list for the cache area. The memory system according to claim 1, wherein:   When the stored data of the third list or the fourth list becomes full, the control circuit gives priority to the data of the block area of the erase unit allocated the oldest in the list. 2. The memory system according to claim 1, further comprising a function of registering in a list.   2. The control circuit according to claim 1, wherein the control circuit has a function of preferentially registering data that has passed for a certain period of time in the data stored in the third list or the fourth list in the second list. Memory system.   When there is no candidate to be registered in the first list preferentially in the data in the second list, the control circuit uses the data to be registered in the first list as the main storage area. A function of selecting data from the third list and selecting the data to be registered in the first list by selecting data from the fourth list when using the data to be registered in the first list as the cache area; The memory system according to claim 2.   The control circuit, when selecting data from the third list or the fourth list, has a function of sequentially selecting data from the block area of the erasing unit that has been allocated the oldest according to the order of data stored in the list. 6. The memory system according to claim 5, further comprising:

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