JP2006126938A - Data transfer system and its data transfer method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize multi-dimensional addressing by connecting a plurality of DMA controllers, each having high reusability, simple specifications and small circuit scale. <P>SOLUTION: In this data transfer method of a data transfer system including a first DMA controller for supporting multi-dimensional addressing, a second DMA controller exclusive for memory write and a third DMA controller exclusive for memory read, the third DMA controller reads information showing an address to start data transfer and the length of transfer from a predetermined memory, and transfers it to the second DMA controller, and the second DMA controller writes information transferred from the third DMA controller in the first DMA controller, and executes the data transfer based on the information written by the first DMA controller. Then, the predetermined memory is made to store a plurality of information showing the address to start the data transfer and the length of transfer, and the data transfer for any discontinuous memory region is made possible. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for realizing multidimensional addressing by reducing software intervention as much as possible.

  In a conventional direct memory access (DMA) controller, several methods are used to realize addressing of data transfer to a discontinuous memory area. Three types of methods are listed below.

  As the simplest method, there is a method of performing DMA transfer once in a range where addresses are continuous, and resetting and restarting DMA again when it is necessary to skip to discontinuous addresses. This method does not have a great influence when the request for the transfer rate is not so high or the area where the addresses are continuous has a certain size, but the performance decreases when the CPU intervention increases too much.

  Therefore, as a method of reducing CPU intervention, a plurality of offset address registers are prepared in the DMA controller (hereinafter referred to as DMAC), and when the set transfer length is reached, addresses are automatically set by the amount set in the offset address register. A method is often used in which jumping is performed, and when the DMA reaches a set transfer length again, the address is jumped by the value of another offset address register.

  According to the above-described method, since the address can be jumped to a region where the DMAC itself is discontinuous, the intervention of the CPU is reduced and the performance can be improved to the maximum. However, in this method, if the number of offset registers is prepared in one DMAC, the number of dimensions required by the IP image processing block or communication processing block (the number of times the address jumps to a discontinuous area) can be satisfied. There is a problem that it is very difficult to determine.

  For example, in the image processing to be installed in the application specific integrated circuit (ASIC), a four-dimensional addressing-compatible DMAC is designed because four-dimensional is sufficient. In the next ASIC, an image processing module that requires six-dimensional addressing is required. When it is adopted, a DMAC corresponding to this must be newly designed. It seems to be difficult to design and verify this during a limited development period.

  As a DMAC that is not affected by the change in the number of dimensions (the number of times the address jumps to a discontinuous area), when jumping to a discontinuous address, the DMA parameter, especially the offset address value, is read from the memory area. Some can rewrite the DMA parameters themselves. This can be realized by placing the DMA parameter to be updated in a memory area in advance.

  According to this method, even if the number of dimensions (the number of times the address jumps to a discontinuous area) increases, discontinuous addressing is possible without software intervention, and it can be used without changing the specifications of the DMAC itself. The usability is also considered high.

For example, Patent Documents 1 to 5 have been proposed as prior arts related to addressing data transfer by DMAC.
Japanese Patent Laid-Open No. 05-120205 Japanese Unexamined Patent Publication No. 07-306825 Japanese Patent Laid-Open No. 05-108548 Japanese Unexamined Patent Publication No. 07-210496 Japanese Patent Laid-Open No. 05-120205

  However, in general, it can be said that the DMAC design of the addressing method as in the conventional example has a high degree of difficulty and has a specification that causes bugs. In addition, although the reusability is high, there is a problem that the circuit scale becomes large by using the DMAC having the redundant function for a normal device that does not require multidimensional addressing.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to realize multidimensional addressing by connecting a plurality of DMA controllers having a simple reusability and a small circuit scale. .

  The present invention provides a data transfer system including a first DMA controller that supports multidimensional addressing, a second DMA controller dedicated to memory write, and a third DMA controller dedicated to memory read. The second and third DMA controllers have a first interface for connecting to the system bus, a second interface for transferring data between peripheral devices, a head address register and a transfer length register. And a means for generating a transfer end signal to the outside after the transfer is completed and a means for starting data transfer by an external trigger in addition to the start by software, and the transfer end signal of the first DMA controller is sent to the first DMA controller. The second and third DMA controllers connected to the external trigger input of the second DMA controller A means for connecting via the second interface directly or via a selection means; when connected via the selection means, the connection with the peripheral device is enabled by software, or the second And enabling the connection between the third DMA controller and the third DMA controller.

  The present invention also provides a data transfer method for a data transfer system including a first DMA controller supporting multidimensional addressing, a second DMA controller dedicated to memory write, and a third DMA controller dedicated to memory read. The third DMA controller reads information indicating an address and transfer length at which data transfer starts from a predetermined memory and transfers the information to the second DMA controller, and the second DMA controller transfers the information to the second DMA controller. And writing the information transferred from the third DMA controller to the first DMA controller and executing the data transfer based on the information written by the first DMA controller. Store multiple pieces of information indicating the address and transfer length at which data transfer starts. Place, characterized in that to enable data transfer to a discontinuous memory areas.

  According to the present invention, it is possible to realize multidimensional addressing by connecting a plurality of DMA controllers having a simple specification with high reusability and a small circuit scale.

  The best mode for carrying out the invention will be described below in detail with reference to the drawings. In this embodiment, the configuration and operation of a single direct memory access (DMA) controller (hereinafter referred to as DMAC) will be described in detail, and then the configuration and operation of a system that uses a plurality of DMACs will be described.

  There are two types of DMACs in the present embodiment: write DMAC and read DMAC. This write DMAC is a dedicated DMAC that receives data from the IO device via the DMA bus and writes it to the memory space or the IO space via the system bus. On the other hand, the read DMAC performs the reverse operation, and is a dedicated DMAC that receives data from the memory space or the IO space via the system bus and transmits it to the IO device via the DMA bus.

  FIG. 1 is a schematic diagram showing an example of the internal configuration of the DMAC in the present embodiment. Here, only the write DMAC is shown as a representative. As shown in FIG. 1, the write DMAC 100 includes a bus master I / F 102, a DMA bus I / F 103, a DMA control block 106, a control register block (having a bus slave I / F) 105, and a data FIFO 104.

  The DMA control block 106 starts DMA in response to a DMA activation request (Start 116) by register access of a CPU or the like (not shown) or a DMA activation request by an external trigger (Start 113), and when the DMA ends, a transfer end signal (End 114). And an interrupt signal (Int115).

  FIG. 2 is a diagram showing the relationship between the signals shown in FIG. 1 and DMA execution. As shown in FIG. 2, when a DMA start request (Start 116) or an external trigger (Start 113) is input in one cycle, a DMA operation is executed. Thereafter, when the DMA operation is completed, the transfer end signal (End 114) is asserted for one cycle. The interrupt signal (Int115) is asserted at the same time as the transfer end signal, but keeps “1” until the interrupt factor is cleared.

  Here, referring back to FIG. 1, the control register block 105 includes a bus slave I / F inside and a control register (details will be described later) for which access control is performed from the bus master. The data FIFO 104 is a FIFO for storing data received from the IO device via the DMA bus.

  The bus master I / F 102 is a block that monitors an empty state of the data FIFO 104, an address alignment, a remaining transfer length, and the like, and outputs an optimal bus command request to the system bus 101. The bus master I / F 102 also receives an address generation block 107 having a counter for generating a bus address to be issued, a bus request issue control block 108 for issuing a bus request to the system bus 101, and data to be output to the system bus 101 from the data FIFO 104. It consists of a data control block 109 that extracts and transmits.

  The DMA bus I / F 103 is a block that controls “valid110”, “data111”, and “busy112” signals, which are DMA bus protocols, and writes “data111” to the data FIFO 104.

  FIG. 3 is a diagram for explaining protocol specifications in the DMA bus. Since the data transmission source outputs valid data data when valid is “1”, the receiving side must receive this data. However, if data cannot be received due to circumstances on the receiving side, the receiving side can refuse data reception by setting the busy signal to “1”. In the meantime, the transmission source keeps valid and valid data.

  Although the internal configuration of the read DMAC is not shown, it is the same as the internal configuration of the write DMAC. In the read DMAC, since the data flow is reversed, the control of the DMA bus I / F, the bus master I / F, etc. is slightly different.

  Next, the specifications of the control register in the control register block 105 in the DMAC will be described.

  FIG. 4 is a diagram illustrating a configuration example of a control register in the control register block 105. As shown in FIG. 4, there are two types of control registers, both of which are composed of 32 bits. It is common to the write DMAC and the read DMAC.

  Reference numeral 401 denotes a DMA head address register for designating a head address (SA) for starting DMA in a 32-bit width address space. The initial value is “0x0000_0000”. Reference numeral 402 denotes a DMA control register, which is composed of four fields. The initial value is “0x0000_0000”.

  In the DMA control register 402, the 0th bit is a DMA start bit (S). When “1” is written, the DMA can be started, and when “0” is written during DMA execution, the DMA can be forcibly terminated. The first bit is an interrupt enable bit (IE). When "1" is written, an interrupt is notified to an interrupt controller (not shown) after DMA is completed. When “0” is written, the interrupt is not asserted.

  The second bit is an interrupt status bit (IS), which corresponds to an interrupt signal output to an interrupt controller (not shown). When DMA is completed in the interrupt enable state, this bit is set to “1”, cleared by writing “0” in this bit, and the interrupt signal also becomes “0”. In the interrupt disabled state, this bit is always “0”.

  The upper 28 bits from the 4th bit to the 31st bit are a DMA transfer length field (LEN), and the unit is a byte. Other empty bits are reserved areas.

  The initial value of each of the DMA head address register 401 and the DMA control register 402 is “0x0000_0000”, and the DMA head address register 401 and the DMA control register 402 are sequentially arranged in the IO address space.

  The above is the specification of the DMAC alone, and it can be seen that a very simple and small circuit configuration is possible.

  Next, a DMAC system using a plurality of write DMACs and read DMACs will be described with reference to FIG.

  FIG. 5 is a block diagram showing an example of the DMAC system in the present embodiment. As shown in FIG. 5, there are four bus masters connected to the system (address, data) bus 1, which are CPU 21, DMAC 5, DMAC 6, and DMAC 7.

  On the other hand, there are an arbiter 4, a memory controller 2, an interrupt controller INTC23, a device selection block 11, and IO devices 8, 9, and 10 as bus slaves.

  All of the DMACs 5 to 7 operate as bus slaves in addition to being a bus master. The DMACs 5 to 7 are DMACs having the same specifications as the write DMAC (read DMAC) described above. The DMAC 5 is directly connected to the IO device 8 via the DMA bus 19, and is defined as a DMAC that should perform multidimensional addressing, which is the subject of the present invention.

  In FIG. 5, the DMAC 5 is a write DMAC. However, there is no restriction on whether a DMAC is to be a write DMAC or a read DMAC, and the configuration shown in FIG. It will not change.

  The DMAC 6 is a write DMAC and is connected to the DMA bus 14. Here, the DMA bus 14 is one in which either the DMA bus 16 of the IO device 9 or the DMA bus 17 that is the output of the selector (demultiplexer) 13 is selected by the selector (multiplexer) 12. The DMA bus 17 corresponds to the DMA bus 15 connected to the DMAC 7 which is a read DMAC.

  The select signals of the selectors 12 and 13 are generated by the device selection block 11, and the CPU 21 is switched by register setting. The timing for switching must be in a state where the DMA bus is not active.

  The DMAC 7 is a read DMAC and is connected to the IO device 10 via the selector 13. The selector 12 is a multiplexer that outputs only the selected input of the two inputs, and the selector 13 is a demultiplexer that passes the input only to the selected output number and passes the inactive level to the other output. is there. Further, the DMA bus arrows in FIG. 5 merely indicate the flow of data, and not all bus signals are directed in the direction of the arrows.

  The DMA transfer end signal (End) of the multi-dimensional addressing DMAC 5, that is, the signal 20 in FIG. 5 is connected to the DMA external trigger (Start) of the DMAC 6 that is the write DMAC.

  The IO devices 8, 9, and 10 are dedicated modules for performing image processing, or modules for controlling communication with external devices. This IO device incorporates a DMA bus interface circuit to support the DMA bus protocol.

  The INTC 22 is an interrupt controller, and notifies the CPU 21 of only the interrupt factor selected from the interrupt signals 23, 24 and 25 from the DMACs 5, 6 and 7 as the final interrupt signal 26.

  The memory controller 2 is a block that handles data transfer between each bus master and the DRAM 3. The arbiter 4 is a module that arbitrates bus requests from a plurality of masters.

  The above is the minimum system configuration in which the DMAC 5 can execute the multidimensional addressing DMA.

  If the DMAC 5 is used as multidimensional addressing, it is necessary to set the select signal of the selector 12 and the selector 13 so that the DMA bus 15 of the DMAC 7 and the DMA bus 14 of the DMAC 6 are connected. That is, in this case, the DMA bus 15, the DMA bus 17, and the DMA bus 14 are connected, and the IO devices 9 and 10 are disabled. DMAC 6 and DMAC 7 cooperate to enable the multidimensional addressing function of DMAC 5.

  A simple operation in which the DMAC 5 performs the multidimensional addressing DMA in the DMAC system described above will be described below.

  The DMAC 5 that wants to perform multidimensional addressing can execute only one-dimensional addressing DMA by itself. Therefore, the multi-dimensional addressing of DMAC 5 is realized by dynamically rewriting the transfer parameters (DMA start address register 401 and DMA control register 402) that DMAC 5 has in the other two DMACs 6 and 7. Here, it is assumed that the register data to be rewritten is arranged in advance in the memory area.

  The DMAC 7 that is the read DMAC reads the transfer parameters in the memory in order and sends them to the DMAC 6 that is the write DMAC via the DMA bus 15 (same DMA bus 14). As a result, the DMAC 6 writes this data group to the control register of the DMAC 5. Here, the DMA head address set in the DMAC 6 must point to the IO address of the control register of the DMAC 5. The update of the parameters of the DMAC 5 occurs every time the one-dimensional DMA of the DMAC 5 is finished. At this time, the connection relationship between the DMA transfer end signal (End) of the DMAC 5 and the external trigger signal (Start) of the DMAC 6 enables a DMA parameter update loop.

  In the case where the DMAC 5 does not require multidimensional addressing, the selectors 12 and 13 may be selected so that the DMAC 6 and the IO device 9 are connected to the DMAC 7 and the IO device 10. In this case, the DMAC 6 and the DMAC 7 can perform DMA transfer with a normal IO device.

  Next, assuming a specific discontinuous transfer area, what kind of register setting should enable addressing of the assumed discontinuous area, and what kind of procedure should start DMA? An explanation will be given of whether or not the assumed discontinuous area can be addressed.

FIG. 6 is a diagram illustrating an example when a discontinuous region is assumed in the present embodiment. As shown in FIG. 6, all DMA transfer areas are divided into five discontinuous areas (area 0, area 1, area 2, area 3, and area 4). Within the area, all addresses are continuous. In each area, SA _x (x = 0 to 4) is used as a head address, and addressing is performed to the right in the figure, and when reaching the end, a jump is made to the head address of the next area. That is, this jump to the discontinuous address is performed four times in this embodiment. The transfer range (number of transfer bytes) of each area is represented by LEN _x .

  In order to perform the transfer in the area as described above, it is necessary to store the transfer parameter in the memory (DRAM 3) in advance as shown in FIG. The transfer parameters are arranged for all the areas without a gap with the address “0x0001 — 0000” in the memory as the base address (BA). The order of arrangement is the order of the areas and the order of the registers, such as the DMA start address register in the area 0, the DMA control register, the DMA start address register in the area 1, the DMA control register, and so on.

Here, the start address (SA _{0 to} SA ₄ ) of each area is designated in the DMA start address register (SA). The transfer length (LEN _{0 to} LEN ₄ ) of each area is designated in the transfer length field (LEN) of the DMA control register. The start bit (S) is set to “1” in all areas, the interrupt enable bit (IE) is set to “0” except for the last area (area 4), and “1” is set only in the last area. This is because the interrupt of only the last area is made valid in order to detect only the interrupt when the DMA transfer ends the transfer in all areas.

  If it is desired to detect an intermediate interrupt depending on the application, the interrupt enable field may be set to “1” as appropriate. Since the interrupt status field is only “0” clear when the field is “1”, it is safe to set “0” only when it is desired to clear the interrupt factor, and to set “1” in all other cases.

  These parameters are read one by one by the read DMAC 7 and sent to the write DMAC 6, and the write DMAC 6 writes the parameters into the control register of the multidimensional addressing support DMAC 5.

  FIG. 8 is a diagram showing values to be set in the control register of each DMAC. First, since all the register values of the DMAC 5 are placed in a memory having BA as a base address, there is no need to set anything.

  Next, “0xF000_0000” which is the register base address of DMAC5 is set in the DMA start base address register (SA) of DMAC6, and “0x8” corresponding to two 32-bit registers is set in the transfer length field (LEN) of the DMA control register. To do. That is, the setting is such that writing is performed to two registers of the DMAC 5 by one DMA. The addresses assigned to each register are shown in the figure.

  It is necessary to set the start bit (S) to “1” and activate only the first one DMA by software. As can be seen from FIG. 5, the external start (Start) of the DMAC 6 is connected to the DMA transfer end signal (End) of the DMAC 5 and is started by the DMA end of the DMAC 5, but the transfer start of the first DMAC 5 is set. Since it is the DMAC 6 that performs, the first activation of the DMAC 6 must be software. The interrupt enable field may be “0”.

  The DMA start address register (SA) of the DMAC 7 stores the value of the base address (BA) of the memory area in which the transfer area parameter of the DMAC 5 is stored. In this case, “0x0001_0000”.

  The transfer length field (LEN) of the DMA control register is “0x28” because the number of parameters in the memory is converted into bytes. Set the start bit to “1”. The interrupt enable field may be “0”. This DMAC 7 is activated only once in one multidimensional DMAC.

  FIG. 9 is a diagram showing the relationship between transition and activation of DMA transfer in time series when DMA transfer is performed with the setting of FIG. Although not shown in FIG. 9, before the DMA transfer is performed, it is necessary for the CPU 21 to arrange the transfer parameters of the DMAC 5 in an arbitrary memory area of the DRAM 3.

  First, the CPU 21 sets DMAC6 and DMAC7 transfer parameters and starts DMA. The first DMAC that operates is DMAC7, which reads parameter information of DMAC7 from the memory area. Here, the read data is sent to the DMAC 6 via the DMA buses 15 and 14. When the DMAC 6 receives 8 bytes of data from the DMAC 7, it issues a bus request and performs DMA for 8 bytes. Here, the target is the register address of DMAC5.

Next, 8 bytes of DMAC6, that is, writing of the start address register and control register of DMAC5 is completed, and at the same time, DMA of DMAC5 is started and data transfer for the transfer length (LEN ₀ ) of the first area is performed. . During this time, the DMAC 6 continues to receive data from the DMA bus 14, but the data transfer to the system bus 1 is completely stopped. The DMAC 7 continues DMA for the set transfer length including this period, but since the DMAC 6 DMA is stopped, the DMAC 7 DMA itself may also stop. This state is likely to occur particularly when the DMAC 6 has a FIFO with a small number of stages. Conversely, if a multi-stage FIFO is provided, the DMA transfer of the DMAC 7 may be completed at an earlier stage than that shown in FIG.

Thereafter, when the DMAC 5 finishes the DMA in the area 0, an external trigger is applied to the DMAC 6, and the DMAC 6 performs re-DMA in response thereto. This sequence is repeatedly executed until the DMA of the last area (LEN ₄ ) of DMAC 5 is completed.

  Since the DMAC5 DMA transfer end signal (End) is used as the start trigger (Start) of the DMAC6, the last DMA of the DMAC6 is started excessively. Therefore, it is necessary to forcibly terminate the DMAC 6 DMA after detecting the DMAC 5 transfer end interrupt. At this time, the DMAC 7 has already finished the DMA transfer, and there is no extra data in the DMAC 6, so the DMAC 6 does not activate the DMAC 5 excessively.

  As described above, a multidimensional DMAC can be easily realized by combining at least one write DMAC, one read DMAC, and a write DMAC (or read DMAC) to be subjected to multidimensional addressing.

  The DMAC specification in this embodiment is a very simple one-dimensional DMAC, although there is naturally a difference between read-only and write-only. The greatest advantage is that a multidimensional DMAC can be realized using only the DMAC which is a common simple specification.

  Therefore, in a situation where multidimensional addressing is not used, the DMAC 6 and DMAC 7 can be disconnected by the selectors 12 and 13 of the DMA system shown in FIG. 5, and the DMAC can be used for a normal IO device. In this case, the timing of switching the selectors 12 and 13 is completely static and must be performed after confirming that the DMA has been completed.

  In this embodiment, as shown in FIG. 5, a DMAC that is one multidimensional addressing target and a write DMAC and a read DMAC necessary to realize the DMAC are prepared. The device can be switched by placing a selector on the DMA bus so that it can also be used as a device DMA.

  If this is expanded, it is possible to configure a system as shown in FIG. FIG. 10 is a diagram illustrating an example of a configuration in which an arbitrary DMAC is set as a multidimensional addressing target DMAC. As shown in FIG. 10, all DMAC DMA buses existing in this system are connected to a DMA bus selector 205, and a device selection signal 200 is controlled and switched by a device selection module 202.

  At the same time, since it is necessary to connect an external activation trigger and an end signal between the DMAC to which multi-dimensional addressing is to be performed and the write DMAC, as in the case of the DMA bus selector 205, a trigger transfer end selector 204 is provided to select a trigger. The module 203 controls the trigger selection signal 201 to perform switching.

  By controlling in this way, it becomes possible to switch a DMAC channel that is not used at that time to a support application for multidimensional DMAC with respect to a DMA channel to be subjected to multidimensional addressing, thereby increasing flexibility. .

  Alternatively, one set of write DMAC and read DMAC can be prepared and used as support DMAC for multidimensional DMAC from the beginning.

  As described above, according to the present embodiment, multi-dimensional addressing can be performed by using a plurality of DMACs that support only very simple one-dimensional addressing. Further, by using only the DMAC having the same specification, it can be used as a DMAC for other IO devices, and the design and verification period can be further shortened.

  Even if the present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), it is applied to an apparatus (for example, a copier, a facsimile machine, etc.) composed of a single device. It may be applied.

  Another object of the present invention is to supply a recording medium in which a program code of software realizing the functions of the above-described embodiments is recorded to a system or apparatus, and the computer (CPU or MPU) of the system or apparatus stores it in the recording medium. Needless to say, this can also be achieved by reading and executing the programmed program code.

  In this case, the program code itself read from the recording medium realizes the functions of the above-described embodiment, and the recording medium storing the program code constitutes the present invention.

  As a recording medium for supplying the program code, for example, a floppy (registered trademark) disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like is used. be able to.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (operating system) operating on the computer based on the instruction of the program code. It goes without saying that a case where the function of the above-described embodiment is realized by performing part or all of the actual processing and the processing is included.

  Further, after the program code read from the recording medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. It goes without saying that the CPU or the like provided in the board or the function expansion unit performs part or all of the actual processing and the functions of the above-described embodiments are realized by the processing.

It is the schematic which shows an example of the internal structure of DMAC in this embodiment. It is a figure which shows the relationship regarding the signal shown in FIG. 1, and DMA execution. It is a figure for demonstrating the specification of the protocol in a DMA bus. 3 is a diagram illustrating a configuration example of a control register in a control register block 105. FIG. It is a block diagram which shows an example of the DMAC system in this embodiment. It is a figure which shows an example at the time of assuming the discontinuous area | region in this embodiment. It is a figure for demonstrating arrangement | positioning of a memory area. It is a figure which shows the value which should be set to the control register of each DMAC. FIG. 9 is a diagram illustrating a relationship between transition and activation of DMA transfer in a time series when DMA transfer is performed with the setting of FIG. 8. It is a figure which shows an example of the structure which makes arbitrary DMAC DMAC of multidimensional addressing object.

Explanation of symbols

1 System bus (address bus, data bus)
2 Memory controller 3 DRAM
4 Bus Arbiter 5 Light DMAC
6 Light DMAC
7 Lead DMAC
8 IO device (sending only)
9 IO device (sending only)
10 IO device (receive only)
11 Device selection block 12 DMA bus selector (multiplexer)
13 DMA bus selector (demultiplexer)
14 DMAC6 DMA bus 15 DMAC7 DMA bus 16 IO device 9 DMA bus 17 DMAC connection DMA bus 18 IO device 10 DMA bus 19 IO device 8 DMA bus (DMAC5 DMA bus)
20 DMAC5 DMA transfer end signal 21 CPU
22 Interrupt controller (INTC)
23 Interrupt signal of DMAC5 24 Interrupt signal of DMAC6 25 Interrupt signal of DMAC7 100 Write DMAC
101 System bus 102 Bus master interface 103 DMA bus interface 104 Data FIFO
105 control register block 106 DMA control block 107 address generation circuit 108 bus request issue control block 109 data control block 110 valid signal 111 data signal 112 busy signal 113 external trigger signal Start
114 DMA transfer end signal End
115 Interrupt signal Int
116 Internal trigger signal Start
200 Device selection signal 201 Trigger selection signal 202 Device selection module 203 Trigger selection module 204 Trigger transfer end selector 205 DMA bus selector

Claims (5)

A data transfer system including a first DMA controller supporting multidimensional addressing, a second DMA controller dedicated to memory write, and a third DMA controller dedicated to memory read,
The first, second, and third DMA controllers include a first interface for connecting to a system bus, a second interface for transferring data between peripheral devices, a head address register, and a transfer length register. And means for generating a transfer end signal to the outside after the transfer is completed, and means for starting data transfer by an external trigger in addition to the start by software,
The transfer end signal of the first DMA controller is connected to an external trigger input of the second DMA controller, and the second and third DMA controllers are connected directly via the second interface or selection means. Having means for connecting via
When the connection is made via the selection means, it is possible to select whether the connection with the peripheral device is enabled by software or the connection between the second and third DMA controllers is enabled. And data transfer system.   Selection means capable of inputting the transfer end signals from a plurality of DMA controllers and selecting the transfer end signals as output candidates of all external trigger signals; and generating means for generating selection signals of the selection means The data transfer system according to claim 1. A data transfer method for a data transfer system, comprising: a first DMA controller supporting multidimensional addressing; a second DMA controller dedicated to memory write; and a third DMA controller dedicated to memory read,
Reading information indicating an address and transfer length at which the third DMA controller starts data transfer from a predetermined memory, and transferring the information to the second DMA controller;
The second DMA controller writing information transferred from the third DMA controller to the first DMA controller, and executing data transfer based on the information written by the first DMA controller; Have
A data transfer method for a data transfer system, wherein a plurality of pieces of information indicating an address for starting the data transfer and a transfer length are stored in the predetermined memory to enable data transfer to a discontinuous memory area .   A program for causing a computer to execute the data transfer method of the data transfer system according to claim 3.   A computer-readable recording medium on which the program according to claim 4 is recorded.

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