JP2006086179A - Distorted silicon wafer and its manufacturing method - Google Patents

Distorted silicon wafer and its manufacturing method Download PDF

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JP2006086179A
JP2006086179A JP2004266626A JP2004266626A JP2006086179A JP 2006086179 A JP2006086179 A JP 2006086179A JP 2004266626 A JP2004266626 A JP 2004266626A JP 2004266626 A JP2004266626 A JP 2004266626A JP 2006086179 A JP2006086179 A JP 2006086179A
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layer
strained
silicon wafer
nitride film
epitaxially grown
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Takeshi Senda
剛士 仙田
Kazuhiko Kajima
一日児 鹿島
Koji Sensai
宏治 泉妻
Masato Igarashi
昌人 五十嵐
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Coorstek KK
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Toshiba Ceramics Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To obtain a distorted silicon wafer with an SiGe layer where a through-dislocation density is reduced and a distortion is relaxed, and a manufacturing method for the distorted silicon wafer. <P>SOLUTION: The distorted silicon wafer has an epitaxial SiGe layer having lattice mismatching properties, a nitride-film layer having a nitrogen concentration of 1×10<SP>19</SP>atoms/cc or more, and a distorted Si layer on a single-crystal silicon substrate. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、歪みシリコンウェーハおよびその製造方法に関し、より詳細には、従来よりも貫通転位密度が低減された歪みシリコンウェーハおよびその製造方法に関する。   The present invention relates to a strained silicon wafer and a method for manufacturing the same, and more particularly to a strained silicon wafer having a threading dislocation density reduced as compared with the conventional method and a method for manufacturing the same.

近年、高速かつ低消費電力の半導体デバイスに対する要望が益々強くなってきているが、デバイスの大幅なスケールレダクション、即ち、素子寸法の大幅縮小化、微細化によるデバイス性能の更なる向上は、限界が見え始めてきている。   In recent years, there has been an increasing demand for high-speed and low-power consumption semiconductor devices. However, significant scale reduction of devices, that is, further improvement of device performance due to drastic reduction of element dimensions and miniaturization is the limit. Is beginning to be visible.

このため、高速かつ低消費電力の半導体デバイスを形成するための基板として、歪みシリコン層を有する半導体基板が注目されるようになっている。特に、単結晶シリコン基板上に、シリコン・ゲルマニウム層(以下、SiGe層という)を介して、シリコンをエピタキシャル成長させた歪みシリコン層(以下、歪みSi層という)をチャンネル領域に用いた高速デバイスが注目されている。   For this reason, a semiconductor substrate having a strained silicon layer has attracted attention as a substrate for forming a semiconductor device with high speed and low power consumption. In particular, high-speed devices using a strained silicon layer (hereinafter referred to as a strained Si layer) obtained by epitaxially growing silicon on a single crystal silicon substrate via a silicon-germanium layer (hereinafter referred to as a SiGe layer) are attracting attention. Has been.

この歪みSi層は、シリコンに比べ格子定数が大きいSiGe層により引っ張り歪みが生じている。この歪みによりSiのバンド構造が変化し、縮退が解けてキャリア移動度が高まる。   This strained Si layer is tensilely strained by the SiGe layer having a larger lattice constant than silicon. This strain changes the band structure of Si, degenerates and increases the carrier mobility.

従って、この歪みSi層をチャンネル領域に用いることにより、バルクシリコンを用いた際の1.5倍以上のキャリア高速化が可能となる。   Therefore, by using this strained Si layer for the channel region, it is possible to increase the carrier speed by 1.5 times or more when using bulk silicon.

良質な歪みSi層を得るためにはシリコン基板上に良質なSiGe層、即ち貫通転位や欠陥密度が低く歪み緩和され、平滑な表面を有するSiGe層をエピタキシャル成長させることが必要である。   In order to obtain a high-quality strained Si layer, it is necessary to epitaxially grow a high-quality SiGe layer on a silicon substrate, that is, a SiGe layer having a smooth surface with threading dislocations and defect density reduced and relaxed.

しかし、SiとGeの間には格子定数に約4.2%の差異があるため、通常状態でそのままエピタキシャル成長させた場合は、勿論、例えエピタキシャル成長前にSi表面を酸化させ、更に高温アニールしても、エピタキシャル成長中に貫通転位や積層欠陥が多発し、良好なエピタキシャル成長膜を得ることは困難である。   However, since there is a difference of about 4.2% in lattice constant between Si and Ge, when the epitaxial growth is performed as it is in the normal state, of course, the Si surface is oxidized before the epitaxial growth and further annealed at a high temperature. However, threading dislocations and stacking faults frequently occur during epitaxial growth, and it is difficult to obtain a good epitaxial growth film.

この問題を改善する試みも提案されており、例えば、SiGe層における厚さ方向にGe濃度の勾配をつけてエピタキシャル成長させ、格子定数差異による歪みの大きさを転位発生の許容限度内に緩和させることが提案されている。   Attempts have also been made to improve this problem. For example, epitaxial growth is performed with a Ge concentration gradient in the thickness direction of the SiGe layer, and the strain due to the difference in lattice constant is reduced within the allowable limit of dislocation generation. Has been proposed.

また、同様な発想からの提案として、SiGe層を多段層に形成し、各段層のGe濃度を段階的に変化させ、格子不整合による転位の多発を抑制する発明が開示されている(例えば、特許文献1及び2参照。)。   Further, as a proposal from a similar idea, an invention is disclosed in which SiGe layers are formed in multiple stages, the Ge concentration of each stage layer is changed stepwise, and the occurrence of dislocations due to lattice mismatch is suppressed (for example, Patent Documents 1 and 2).

しかしながら、これら提案によっても貫通転位の発生を充分に満足する程度には抑制できていない。更に、貫通転位の発生を回避するために形成したSiGe層の厚さは数μmにも達し、生産効率が悪かった。
特開2003−78116号公報(第5頁第7欄) 特開2003−78118号公報(第4頁第5欄20行〜第6欄第28行)
However, these proposals have not been able to suppress the occurrence of threading dislocations to the extent that they are sufficiently satisfied. Further, the thickness of the SiGe layer formed to avoid the occurrence of threading dislocations reached several μm, and the production efficiency was poor.
JP 2003-78116 A (page 5, column 7) JP 2003-78118 A (page 4, column 5, line 20 to column 6, line 28)

上述したとおり、従来の技術では、シリコン基板表面にGe濃度を増加しながら傾斜させてSiGe層をエピタキシャル成長させても、シリコン基板との界面からミスフィット転位が発生する。そして、上記ミスフィット転位に起因する貫通転位が高密度で歪みSi層の表面にまで達し、存在することとなる。上記歪みSi層の貫通転位の存在は、デバイス素子の成形時において、接合リーク電流の増加の大きな原因となる。   As described above, in the conventional technique, misfit dislocations are generated from the interface with the silicon substrate even when the SiGe layer is epitaxially grown by increasing the Ge concentration on the surface of the silicon substrate. The threading dislocations resulting from the misfit dislocations reach the surface of the strained Si layer at a high density and exist. The presence of threading dislocations in the strained Si layer is a major cause of an increase in junction leakage current during device element molding.

更に、貫通転位と残留歪みエネルギーにより、クロスハッチ模様の凹凸が形成されてしまい、その上に成長させる歪みSi層の表面粗さRmsが大きくなってしまうという問題が生じていた。   Further, the threading dislocations and the residual strain energy cause the formation of cross-hatch pattern irregularities, and the problem arises that the surface roughness Rms of the strained Si layer to be grown thereon increases.

そのため、組成傾斜SiGe層をエピタキシャル成長する際の貫通転位密度の発生・伸長を極力防ぐ有効な手段の出現が強く求められている。   Therefore, the emergence of an effective means for preventing the generation and elongation of threading dislocation density during epitaxial growth of the composition gradient SiGe layer is strongly demanded.

そこで本発明者は、窒素の存在により貫通転位が捕獲され、移動が妨げられ、その結果歪みSi層表面の転位密度が低下することを見出した。   Therefore, the present inventors have found that the presence of nitrogen captures threading dislocations and hinders movement, resulting in a decrease in dislocation density on the surface of the strained Si layer.

すなわち、本発明は、上記事情に鑑みてなされたものであり、従来よりも貫通転位密度が低い歪みシリコンウェーハおよびその製造方法を提供することを目的とする。   That is, the present invention has been made in view of the above circumstances, and an object thereof is to provide a strained silicon wafer having a threading dislocation density lower than the conventional one and a method for manufacturing the same.

上記目的を達成するために、本発明にかかる歪みシリコンウェーハは、単結晶シリコン基板上に格子不整合性のあるエピタキシャルSiGe層と、窒素濃度が1×1019atoms/cc以上の窒化膜層と、歪みSi層とを備えることを特徴としている。 In order to achieve the above object, a strained silicon wafer according to the present invention includes an epitaxial SiGe layer having lattice mismatch on a single crystal silicon substrate, a nitride film layer having a nitrogen concentration of 1 × 10 19 atoms / cc or more, and And a strained Si layer.

また、本発明にかかる歪みシリコンウェーハにおいて、格子不整合性のあるエピタキシャルSiGe層は、単結晶シリコン基板上にGe濃度を順次上げてエピタキシャル成長させた組成傾斜Si1-xGex層と、残留歪みを緩和させるために組成傾斜Si1-xGex層の上にエピタキシャル成長させた歪み緩和Si1-xGex層と、この歪み緩和Si1-xGex層の上にエピタキシャル成長させた歪みSi層であることを特徴としている。 Further, in the strained silicon wafer according to the present invention, the lattice-mismatched epitaxial SiGe layer includes a compositionally graded Si 1-x Ge x layer epitaxially grown by sequentially increasing the Ge concentration on the single crystal silicon substrate, and a residual strain. Strain relaxed Si 1-x Ge x layer epitaxially grown on a compositionally-graded Si 1-x Ge x layer and strained Si layer epitaxially grown on the strain relaxed Si 1-x Ge x layer It is characterized by being.

さらに、本発明の一態様によれば、単結晶シリコン基板上に、Ge濃度を順次上げて組成傾斜Si1-xGex層をエピタキシャル成長させ、前記組成傾斜Si1-xGex層の上に少なくとも窒素を含む約800℃以上の高温ガス雰囲気下で窒化膜層を形成させ、この窒化膜層上に歪み緩和Si1-xGex層をエピタキシャル成長させ、歪み緩和Si1-xGex層の上に歪みSi層を形成することを特徴とする歪みシリコンウェーハの製造方法が提供される。 Furthermore, according to one aspect of the present invention, a composition-graded Si 1-x Ge x layer is epitaxially grown on a single crystal silicon substrate by sequentially increasing the Ge concentration, and the composition-graded Si 1-x Ge x layer is formed on the composition-graded Si 1-x Ge x layer. least nitrogen to form a nitride layer in a high-temperature gas atmosphere at above about 800 ° C. containing, a strain-relaxed Si 1-x Ge x layer on the nitride layer is epitaxially grown, the strain relaxed Si 1-x Ge x layer There is provided a method for producing a strained silicon wafer, wherein a strained Si layer is formed thereon.

また、本発明の別の一態様によれば、単結晶シリコン基板上に、Ge濃度を順次上げて組成傾斜Si1-xGex層をエピタキシャル成長させ、前記組成傾斜Si1-xGex層の上に歪み緩和Si1-xGex層をエピタキシャル成長させ、この歪み緩和Si1-xGex層の上に少なくとも窒素を含む約800℃以上の高温ガス雰囲気下で窒化膜層を形成させ、この窒化膜層の上に歪みSi層を形成することを特徴とする歪みシリコンウェーハの製造方法が提供される。 Further, according to another aspect of the present invention, a composition gradient Si 1-x Ge x layer is epitaxially grown on a single crystal silicon substrate by sequentially increasing a Ge concentration, and the composition gradient Si 1-x Ge x layer is formed. A strain-relaxed Si 1-x Ge x layer is epitaxially grown thereon, and a nitride film layer is formed on the strain-relaxed Si 1-x Ge x layer in a high-temperature gas atmosphere of at least about 800 ° C. containing nitrogen. A strained silicon wafer manufacturing method is provided, wherein a strained Si layer is formed on a nitride film layer.

更に、本発明の別の一態様によれば、単結晶シリコン基板上に、格子不整合性のあるSiGe層をエピタキシャル成長させ、前記格子不整合性のあるSiGe層の上に第1の歪みSi層をエピタキシャル成長させ、前記第1の歪みSi層の上に少なくとも窒素を含む約800℃以上の高温ガス雰囲気下で窒化膜層を形成させ、この窒化膜層の上に第2の歪みSi層を形成することを特徴とする歪みシリコンウェーハの製造方法が提供される。   Further, according to another aspect of the present invention, a lattice mismatched SiGe layer is epitaxially grown on a single crystal silicon substrate, and a first strained Si layer is formed on the lattice mismatched SiGe layer. Is epitaxially grown, and a nitride film layer is formed on the first strained Si layer in a high-temperature gas atmosphere at least about 800 ° C. containing nitrogen, and a second strained Si layer is formed on the nitride film layer. A method of manufacturing a strained silicon wafer is provided.

本発明によれば、貫通転位密度が低減されたことによる、表面に凹凸の少ない歪みシリコンウェーハおよびその製造方法を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the distortion silicon wafer with few unevenness | corrugations on the surface by the reduced threading dislocation density, and its manufacturing method can be provided.

以下に、本発明の実施の形態について、図面を参照しながら説明する。図1は、本発明の実施の形態にかかる歪みシリコンウェーハの概略断面図である。   Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic cross-sectional view of a strained silicon wafer according to an embodiment of the present invention.

本発明の実施の形態では、例えば表面が鏡面研磨された単結晶シリコン基板1上に、Ge濃度を次第に増やした組成傾斜SiGe層2を形成している。この組成傾斜SiGe層2は、例えばGe濃度を0%から30%まで増加させたものである。Geの濃度傾斜としては、例えば20%/μm以下に設定すると好適である。組成傾斜SiGe層2の上に窒化膜層3を形成している。例えば、窒化膜層3の窒素濃度は1×1019atoms/cc以上あることが好適である。この窒化膜層3の上には、歪み緩和Si70Ge30層4をエピタキシャル成長させている。尚、SiGe層2,4は格子不整合性のあるものである。さらに、歪み緩和SiGe層4の上には、歪みSi層5を形成している。 In the embodiment of the present invention, for example, a compositionally graded SiGe layer 2 with a gradually increasing Ge concentration is formed on a single crystal silicon substrate 1 whose surface is mirror-polished. This composition gradient SiGe layer 2 has a Ge concentration increased from 0% to 30%, for example. For example, the Ge concentration gradient is preferably set to 20% / μm or less. A nitride film layer 3 is formed on the composition gradient SiGe layer 2. For example, the nitrogen concentration of the nitride film layer 3 is preferably 1 × 10 19 atoms / cc or more. A strain relaxation Si 70 Ge 30 layer 4 is epitaxially grown on the nitride film layer 3. The SiGe layers 2 and 4 have lattice mismatch. Further, a strained Si layer 5 is formed on the strain relaxation SiGe layer 4.

本実施の形態に係るシリコンウェーハによれば、Ge濃度を順次上げた組成傾斜SiGe層2とGe濃度の最終組成の緩和SiGe層4との間に、窒化膜層3を介在させることによって、組成傾斜SiGe層2で生じた貫通転位がその直上の窒素により捕獲されるため、本来であれば更に上に伸びるべき貫通転位が緩和SiGe層4および歪みSi層5に及ばなくなる。   According to the silicon wafer according to the present embodiment, the composition is obtained by interposing the nitride film layer 3 between the composition-graded SiGe layer 2 in which the Ge concentration is sequentially increased and the relaxed SiGe layer 4 in the final composition having the Ge concentration. Since the threading dislocation generated in the tilted SiGe layer 2 is captured by the nitrogen immediately above the threading dislocation, the threading dislocation that should originally extend further does not reach the relaxed SiGe layer 4 and the strained Si layer 5.

次に、本発明の別の実施の形態について説明する。図2は、本発明の実施の形態にかかる歪みシリコンウェーハの概略断面図である。図2に示すように、例えば表面が鏡面研磨された単結晶シリコン基板11上に、Ge濃度を次第に増やした組成傾斜SiGe層12を形成している。この組成傾斜SiGe層12は、例えばGe濃度を0%から30%まで増加させたものである。Geの濃度傾斜としては、例えば20%/μm以下に設定すると好適である。組成傾斜SiGe層12の上に、歪み緩和Si70Ge30層13をエピタキシャル成長させている。尚、SiGe層12,13は格子不整合性のあるものである。さらに、歪み緩和Si70Ge30層13の上に窒化膜層14を形成している。例えば、窒化膜層14の窒素濃度は1×1019atoms/cc以上あることが好適である。窒化膜層14の上には、歪みSi層15を形成している。本実施の形態に係るシリコンウェーハによれば、歪みSi層15と歪み緩和Si70Ge30層13との界面に窒化膜層14が存在するので、単結晶シリコン基板11と組成傾斜SiGe層12の界面から発生・伸長するミスフット転位および貫通転位が抑制される。 Next, another embodiment of the present invention will be described. FIG. 2 is a schematic cross-sectional view of a strained silicon wafer according to an embodiment of the present invention. As shown in FIG. 2, for example, a composition gradient SiGe layer 12 with a gradually increasing Ge concentration is formed on a single crystal silicon substrate 11 whose surface is mirror-polished. This composition gradient SiGe layer 12 has a Ge concentration increased from 0% to 30%, for example. For example, the Ge concentration gradient is preferably set to 20% / μm or less. A strain relaxation Si 70 Ge 30 layer 13 is epitaxially grown on the composition gradient SiGe layer 12. The SiGe layers 12 and 13 have lattice mismatch. Further, a nitride film layer 14 is formed on the strain relaxation Si 70 Ge 30 layer 13. For example, the nitrogen concentration of the nitride film layer 14 is preferably 1 × 10 19 atoms / cc or more. A strained Si layer 15 is formed on the nitride film layer 14. In the silicon wafer according to the present embodiment, since the nitride film layer 14 is present at the interface between the strained Si layer 15 and the strain relaxation Si 70 Ge 30 layer 13, the single crystal silicon substrate 11 and the composition gradient SiGe layer 12 are formed. Misfoot dislocations and threading dislocations generated and extended from the interface are suppressed.

次に、本発明の別の実施の形態について説明する。図3は、本発明の実施の形態にかかる歪みシリコンウェーハの概略断面図である。図3に示すように、例えば表面が鏡面研磨された単結晶シリコン基板21上に、Ge濃度20%のSi80Ge20層22を形成している。この格子不整合性のあるSi80Ge20層22の上に第1歪みSi層23をエピタキシャル成長させている。この第1歪みSi層23の上に窒化膜層24を形成している。例えば、窒化膜層24の窒素濃度は1×1019atoms/cc以上あることが好適である。更に、窒化膜層24の上には第2歪みSi層25を形成している。本実施の形態に係るシリコンウェーハによれば、Si80Ge20層22と第1歪みSi層23の界面で生じた貫通転位がその直上の窒素により捕獲されるため、本来であれば更に上に伸びるべき貫通転位が第2歪みSi層25に及ばなくなる。 Next, another embodiment of the present invention will be described. FIG. 3 is a schematic cross-sectional view of a strained silicon wafer according to an embodiment of the present invention. As shown in FIG. 3, for example, a Si 80 Ge 20 layer 22 having a Ge concentration of 20% is formed on a single crystal silicon substrate 21 whose surface is mirror-polished. A first strained Si layer 23 is epitaxially grown on the lattice mismatched Si 80 Ge 20 layer 22. A nitride film layer 24 is formed on the first strained Si layer 23. For example, the nitrogen concentration of the nitride film layer 24 is preferably 1 × 10 19 atoms / cc or more. Further, a second strained Si layer 25 is formed on the nitride film layer 24. According to the silicon wafer according to the present embodiment, threading dislocations generated at the interface between the Si 80 Ge 20 layer 22 and the first strained Si layer 23 are trapped by the nitrogen immediately above, so that if it is originally, further above The threading dislocation to be extended does not reach the second strained Si layer 25.

次に、上記した歪みシリコンウェーハの製法について概説する。   Next, an outline of a method for producing the above-described strained silicon wafer will be described.

まず、表面が鏡面研磨されたシリコン基板1上に形成していくSiGe層2,4のエピタキシャル成長は、例えば、ランプ加熱によるCVD法、超高真空中でのCVD法(UHV−CVD)等の気相エピタキシャル成長法や分子線エピタキシャル成長法(MBE)等で行うことができる。   First, the epitaxial growth of the SiGe layers 2 and 4 formed on the mirror-polished silicon substrate 1 is performed by, for example, a CVD method using lamp heating or a CVD method (UHV-CVD) in an ultrahigh vacuum. It can be performed by a phase epitaxial growth method, a molecular beam epitaxial growth method (MBE), or the like.

成長条件は、成長させるべきSiGe層のSi:Ge組成比や膜厚を、用いる成長方法、装置等により夫々異なり適宜設定される。   The growth conditions are appropriately set depending on the Si: Ge composition ratio and film thickness of the SiGe layer to be grown, depending on the growth method and apparatus used.

例えば、ランプ加熱によるCVD法の場合の一例を示すと、組成がGe=0.3の場合、次のようになる。   For example, an example in the case of a CVD method by lamp heating is as follows when the composition is Ge = 0.3.

キャリアガス:H2、原料ガス:SiH4、GeH4、チャンバ圧:10〜100Torr、温度:650〜680℃、成長速度10〜50nm/分。 Carrier gas: H 2 , source gas: SiH 4 , GeH 4 , chamber pressure: 10-100 Torr, temperature: 650-680 ° C., growth rate 10-50 nm / min.

なお、組成傾斜SiGe層2の表面部の上に窒素を含むガスで800℃以上の高温熱処理し、窒化膜層3を形成させる。その上に緩和SiGe層4を形成する。   The nitride film layer 3 is formed on the surface portion of the composition gradient SiGe layer 2 by high-temperature heat treatment at 800 ° C. or higher with a gas containing nitrogen. A relaxed SiGe layer 4 is formed thereon.

このようにして得られたSiGe層の表面上に、例えば、CVD法等により単結晶Si層5を成長させる。形成された単結晶Si層5は、その下層のSiGe層と格子定数が異なるため歪みSi層5となる。この歪みSi層はデバイス活性領域となるので、例えば5〜30nmの厚さに形成するのが好ましい。   On the surface of the SiGe layer thus obtained, the single crystal Si layer 5 is grown by, for example, the CVD method. The formed single crystal Si layer 5 becomes a strained Si layer 5 because the lattice constant is different from that of the underlying SiGe layer. Since this strained Si layer becomes a device active region, it is preferably formed to a thickness of 5 to 30 nm, for example.

さらに、CVD法による単結晶Siの成長条件の一例を示すと次のようになる。   Furthermore, an example of the growth conditions of single crystal Si by the CVD method is as follows.

キャリアガス:H2、原料ガス:SiH2Cl2又はSiH4、チャンバ圧:10〜760Torr、温度:650〜1000℃。 Carrier gas: H 2 , source gas: SiH 2 Cl 2 or SiH 4 , chamber pressure: 10 to 760 Torr, temperature: 650 to 1000 ° C.

「実施例1」
表面を鏡面研磨した単結晶シリコン基板の表面に、Ge濃度を0%から20%まで増加させた組成傾斜Si80Ge20層を成膜温度900℃で厚さ500nmにエピタキシャル成長させた。さらに、前記組成傾斜Si80Ge20層の上にシリコン窒化膜(Si)層をCVD法により生成温度1000℃で厚さ2nmに成長させた。さらに、前記シリコン窒化膜層の上に緩和Si80Ge20層を成膜温度900℃で厚さ200nmにエピタキシャル成長させた。最後に、歪みSi層を生成温度700℃で厚さ10nmに成長させた。
"Example 1"
A compositionally-graded Si 80 Ge 20 layer having a Ge concentration increased from 0% to 20% was epitaxially grown to a thickness of 500 nm at a film forming temperature of 900 ° C. on the surface of a single crystal silicon substrate whose surface was mirror-polished. Further, a silicon nitride film (Si 3 N 4 ) layer was grown on the composition graded Si 80 Ge 20 layer by a CVD method at a generation temperature of 1000 ° C. to a thickness of 2 nm. Further, a relaxed Si 80 Ge 20 layer was epitaxially grown on the silicon nitride film layer at a film forming temperature of 900 ° C. to a thickness of 200 nm. Finally, a strained Si layer was grown at a production temperature of 700 ° C. to a thickness of 10 nm.

「実施例2」
表面を鏡面研磨した単結晶シリコン基板の表面に、Ge濃度を0%から20%まで増加させた組成傾斜Si80Ge20層を成膜温度900℃で厚さ500nmにエピタキシャル成長させた。さらに、前記組成傾斜Si80Ge20層の上にアルゴンガス95%および窒素ガス5%を含む気体で1200℃の高温熱処理し窒素をSiGe層表面に拡散させた。さらに、前記シリコン窒化膜層の上に緩和Si80Ge20層を成膜温度900℃で厚さ200nmにエピタキシャル成長させた。最後に、歪みSi層を生成温度700℃で厚さ10nmに成長させた。
"Example 2"
A compositionally-graded Si 80 Ge 20 layer having a Ge concentration increased from 0% to 20% was epitaxially grown to a thickness of 500 nm at a film forming temperature of 900 ° C. on the surface of a single crystal silicon substrate whose surface was mirror-polished. Further, high-temperature heat treatment at 1200 ° C. was performed on the composition-gradient Si 80 Ge 20 layer with a gas containing 95% argon gas and 5% nitrogen gas to diffuse nitrogen on the surface of the SiGe layer. Further, a relaxed Si 80 Ge 20 layer was epitaxially grown on the silicon nitride film layer at a film forming temperature of 900 ° C. to a thickness of 200 nm. Finally, a strained Si layer was grown at a production temperature of 700 ° C. to a thickness of 10 nm.

「実施例3」
表面を鏡面研磨した単結晶シリコン基板の表面に、Ge濃度を0%から30%まで増加させた組成傾斜Si70Ge30層を成膜温度900℃で厚さ2μmにエピタキシャル成長させた。さらに、前記組成傾斜SiGe層の上に緩和Si70Ge30層を成膜温度900℃で厚さ1μmにエピタキシャル成長させた。さらに、前記緩和SiGe層の上に窒素ガスを10秒拡散させた。最後に、歪みSi層を生成温度700℃で厚さ20nmに成長させた。
"Example 3"
A compositionally graded Si 70 Ge 30 layer having a Ge concentration increased from 0% to 30% was epitaxially grown to a thickness of 2 μm at a film forming temperature of 900 ° C. on the surface of a single crystal silicon substrate whose surface was mirror-polished. Further, a relaxed Si 70 Ge 30 layer was epitaxially grown on the composition gradient SiGe layer to a thickness of 1 μm at a film forming temperature of 900 ° C. Further, nitrogen gas was diffused on the relaxed SiGe layer for 10 seconds. Finally, a strained Si layer was grown at a production temperature of 700 ° C. to a thickness of 20 nm.

「実施例4」
表面を鏡面研磨した単結晶シリコン基板の表面に、Ge濃度20%のSi80Ge20層を成膜温度900℃で厚さ500nmにエピタキシャル成長させた。さらに、前記SiGe層の上に第1歪みSi層を成膜温度700℃で厚さ10nmにエピタキシャル成長させ、その上に、シリコン窒化膜をCVD法により成膜温度1000℃で厚さ2nmに成膜した。さらに、前記シリコン窒化膜の上に第2歪みSi層を生成温度700℃で厚さ10nmに成長させた。
Example 4
A Si 80 Ge 20 layer having a Ge concentration of 20% was epitaxially grown at a film forming temperature of 900 ° C. to a thickness of 500 nm on the surface of a single crystal silicon substrate whose surface was mirror-polished. Further, a first strained Si layer is epitaxially grown on the SiGe layer to a thickness of 10 nm at a film formation temperature of 700 ° C., and a silicon nitride film is formed thereon to a thickness of 2 nm at a film formation temperature of 1000 ° C. by CVD. did. Further, a second strained Si layer was grown on the silicon nitride film at a generation temperature of 700 ° C. to a thickness of 10 nm.

「実施例5」
表面を鏡面研磨した単結晶シリコン基板の表面に、Ge濃度20%のSi80Ge20層を成膜温度900℃で厚さ500nmにエピタキシャル成長させた。さらに、前記SiGe層の上に第1歪みSi層を成膜温度700℃で厚さ5nmにエピタキシャル成長させ、その上に、アルゴンガス95%および窒素ガス5%を含む気体で1200℃の高温熱処理し窒素をSiGe層表面に拡散させた。さらに、前記窒化膜の上に第2歪みSi層を生成温度700℃で厚さ10nmに成長させた。
"Example 5"
A Si 80 Ge 20 layer having a Ge concentration of 20% was epitaxially grown at a film forming temperature of 900 ° C. to a thickness of 500 nm on the surface of a single crystal silicon substrate whose surface was mirror-polished. Further, a first strained Si layer is epitaxially grown on the SiGe layer to a thickness of 5 nm at a film forming temperature of 700 ° C., and then subjected to a high temperature heat treatment at 1200 ° C. with a gas containing 95% argon gas and 5% nitrogen gas. Nitrogen was diffused on the surface of the SiGe layer. Further, a second strained Si layer was grown on the nitride film at a generation temperature of 700 ° C. to a thickness of 10 nm.

「比較例1」
表面を鏡面研磨した単結晶シリコン基板の表面に、Ge濃度を0%から20%まで増加させた組成傾斜Si80Ge20層を成膜温度900℃で厚さ500nmにエピタキシャル成長させた。さらに、その上に緩和Si80Ge20層を成膜温度900℃で厚さ200nmにエピタキシャル成長させた。最後に、歪みSi層を生成温度700℃で厚さ10nmに成長させた。
“Comparative Example 1”
A compositionally-graded Si 80 Ge 20 layer having a Ge concentration increased from 0% to 20% was epitaxially grown to a thickness of 500 nm at a film forming temperature of 900 ° C. on the surface of a single crystal silicon substrate whose surface was mirror-polished. Further, a relaxed Si 80 Ge 20 layer was epitaxially grown to a thickness of 200 nm at a film forming temperature of 900 ° C. Finally, a strained Si layer was grown at a production temperature of 700 ° C. to a thickness of 10 nm.

表1に実施例1〜5と比較例1の各ウェーハをSecco液による各々の貫通転位密度を示す。

Figure 2006086179
Table 1 shows the threading dislocation density of each of the wafers of Examples 1 to 5 and Comparative Example 1 using the Secco solution.
Figure 2006086179

表1から明らかなように、窒化膜があると歪みシリコンウェーハ表面に存在する貫通転位濃度は10 /cm2未満であり、窒化膜が存在しないと貫通転位濃度は10 /cmと高い値となってしまう。 As is apparent from Table 1, the threading dislocation concentration existing on the strained silicon wafer surface is less than 10 3 / cm 2 when the nitride film is present, and the threading dislocation concentration is as high as 10 5 / cm when the nitride film is not present. End up.

図4に窒素濃度と歪みSi層の貫通転位密度の関係を示す。図4から明らかなように、窒素濃度が1×1019atoms/cc以上では、貫通転位密度が10 /cm2未満と低くなる傾向があり、一方、窒素濃度が1×1018atoms/cc以下では、貫通転位密度が高くなる傾向であることがわかる。 FIG. 4 shows the relationship between the nitrogen concentration and the threading dislocation density of the strained Si layer. As apparent from FIG. 4, when the nitrogen concentration is 1 × 10 19 atoms / cc or more, the threading dislocation density tends to be as low as less than 10 3 / cm 2 , while the nitrogen concentration is 1 × 10 18 atoms / cc. In the following, it can be seen that the threading dislocation density tends to increase.

以上詳述した通り、本発明にかかる歪みシリコンウェーハは、歪み緩和層中に貫通転位等の転位密度が極めて低く、充分に歪み緩和されているためその上に形成された歪みシリコン層も良質である。   As described above in detail, the strained silicon wafer according to the present invention has a very low dislocation density such as threading dislocations in the strain relaxation layer and is sufficiently strain relaxed, so that the strained silicon layer formed thereon is of good quality. is there.

なお、本発明は上記実施形態そのままに限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で構成要素を変形して具体化できる。また、上記実施形態に開示されている複数の構成要素の適宜な組み合わせにより、種々の発明を形成できる。   Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment.

本発明の実施の形態に係る歪みシリコン基板ウェーハの概略断面図である。1 is a schematic cross-sectional view of a strained silicon substrate wafer according to an embodiment of the present invention. 本発明の別な実施の形態に係る歪みシリコンウェーハの概略断面図である。It is a schematic sectional drawing of the distortion | strained silicon wafer which concerns on another embodiment of this invention. 本発明の別な実施の形態に係る歪みシリコンウェーハの概略断面図である。It is a schematic sectional drawing of the distortion | strained silicon wafer which concerns on another embodiment of this invention. 窒素濃度と歪みSi層の貫通転位密度の関係を示す線図である。It is a diagram which shows the relationship between a nitrogen concentration and the threading dislocation density of a strained Si layer.

符号の説明Explanation of symbols

1,11,21:単結晶シリコン基板、 2,12:組成傾斜SiGe層、
3,14,24:窒化膜層、 4,13:緩和SiGe層、
5,15,23,25:歪みSi層。
1, 11, 21: single crystal silicon substrate, 2, 12: composition gradient SiGe layer,
3, 14, 24: nitride film layer, 4, 13: relaxed SiGe layer,
5, 15, 23, 25: strained Si layer.

Claims (4)

単結晶シリコン基板上に格子不整合性のあるエピタキシャルSiGe層と、
窒素濃度が1×1019atoms/cc以上の窒化膜層と、
歪みSi層とを備えることを特徴とする歪みシリコンウェーハ。
An epitaxial SiGe layer having lattice mismatch on a single crystal silicon substrate;
A nitride film layer having a nitrogen concentration of 1 × 10 19 atoms / cc or more;
A strained silicon wafer comprising a strained Si layer.
単結晶シリコン基板上に、Ge濃度を順次上げて組成傾斜Si1-xGex層をエピタキシャル成長させ、前記組成傾斜Si1-xGex層の上に少なくとも窒素を含む約800℃以上の高温ガス雰囲気下で窒化膜層を形成させ、この窒化膜層上に歪み緩和Si1-xGex層をエピタキシャル成長させ、歪み緩和Si1-xGex層の上に歪みSi層を形成することを特徴とする歪みシリコンウェーハの製造方法。 A compositionally graded Si 1-x Ge x layer is epitaxially grown on a single crystal silicon substrate by sequentially increasing the Ge concentration, and a high-temperature gas at least about 800 ° C. containing at least nitrogen on the composition graded Si 1-x Ge x layer. characterized in that to form a nitride layer in an atmosphere, by epitaxially growing a strained relaxed Si 1-x Ge x layer on the nitride layer, forming a strained Si layer on the strained relaxed Si 1-x Ge x layer A method for producing a strained silicon wafer. 単結晶シリコン基板上に、Ge濃度を順次上げて組成傾斜Si1-xGex層をエピタキシャル成長させ、前記組成傾斜Si1-xGex層の上に歪み緩和Si1-xGex層をエピタキシャル成長させ、この歪み緩和Si1-xGex層の上に少なくとも窒素を含む約800℃以上の高温ガス雰囲気下で窒化膜層を形成させ、この窒化膜層の上に歪みSi層を形成することを特徴とする歪みシリコンウェーハの製造方法。 A compositionally graded Si 1-x Ge x layer is epitaxially grown on a single crystal silicon substrate by sequentially increasing the Ge concentration, and a strain-relaxed Si 1-x Ge x layer is epitaxially grown on the composition graded Si 1-x Ge x layer. Forming a nitride film layer on the strain-relaxed Si 1-x Ge x layer in a high-temperature gas atmosphere containing at least nitrogen and at least about 800 ° C., and forming a strained Si layer on the nitride film layer A method for producing a strained silicon wafer characterized by 単結晶シリコン基板上に、格子不整合性のあるSiGe層をエピタキシャル成長させ、前記格子不整合性のあるSiGe層の上に第1の歪みSi層をエピタキシャル成長させ、前記第1の歪みSi層の上に少なくとも窒素を含む約800℃以上の高温ガス雰囲気下で窒化膜層を形成させ、この窒化膜層の上に第2の歪みSi層を形成することを特徴とする歪みシリコンウェーハの製造方法。   A lattice mismatched SiGe layer is epitaxially grown on the single crystal silicon substrate, and a first strained Si layer is epitaxially grown on the lattice mismatched SiGe layer. A method for producing a strained silicon wafer comprising: forming a nitride film layer in a high-temperature gas atmosphere containing at least nitrogen containing at least about 800 ° C .; and forming a second strained Si layer on the nitride film layer.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2418676A1 (en) 2010-08-09 2012-02-15 Siltronic AG Silicon wafer and production method thereof
JP2018060959A (en) * 2016-10-07 2018-04-12 株式会社Sumco Epitaxial silicon wafer and method for manufacturing epitaxial silicon wafer

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2418676A1 (en) 2010-08-09 2012-02-15 Siltronic AG Silicon wafer and production method thereof
JP2018060959A (en) * 2016-10-07 2018-04-12 株式会社Sumco Epitaxial silicon wafer and method for manufacturing epitaxial silicon wafer
WO2018066322A1 (en) * 2016-10-07 2018-04-12 株式会社Sumco Epitaxial silicon wafer and method for manufacturing epitaxial silicon wafer
KR20190047095A (en) * 2016-10-07 2019-05-07 가부시키가이샤 사무코 Epitaxial silicon wafer and epitaxial silicon wafer manufacturing method
KR102183254B1 (en) * 2016-10-07 2020-11-25 가부시키가이샤 사무코 Epitaxial silicon wafer and method of manufacturing epitaxial silicon wafer
US11888036B2 (en) 2016-10-07 2024-01-30 Sumco Corporation Method for setting a nitrogen concentration of a silicon epitaxial film in manufacturing an epitaxial silicon wafer

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