JP2006084682A - Pixel circuit and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pixel circuit and a display device, wherein a current of a desired value can be stably and accurately supplied to a light emitting element in each pixel independently of the variance in threshold of active elements in pixels to prevent a gradient of luminance in a display image and an image of high quality can be displayed as a result. <P>SOLUTION: A first scan driver 104 and a second scan driver 105 set a drive signal VDRL of drive lines DRL101 to DRL10m, a drive signal VSCNL of scan lines SCNL101 to SCNL10m, and a drive signal VAZL of auto-zero lines AZL101 to AZL10m so as to satisfy a relation Von1>Von2, whereby a diving voltage and a switch resistance are optimized. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a pixel circuit having an electro-optical element whose luminance is controlled by a signal line including an active matrix display device such as an organic EL (Electroluminescence) display device and an LCD (Liquid Crystal Display device), and the pixel circuit in a matrix form. The present invention relates to a wiring structure, an arrangement, and a circuit in an arranged image display device.

In an active matrix display device, an electro-optical element such as a liquid crystal cell or an organic EL element is used as a display element of a pixel.
Among them, the organic EL element has a structure in which a layer made of an organic material, that is, an organic layer is sandwiched between electrodes.
In this organic EL element, by applying a voltage to the element, electrons from the cathode and holes from the anode are injected into the organic layer. As a result, the electrons and holes are recombined to generate light. This organic EL element has the following features.

(1) Since a luminance of several hundreds to several 10000 cd / m ² can be obtained by driving at a low voltage of 10 V or less, power consumption can be reduced.
(2) Since it is a self-luminous element, it has a high image contrast and a high response speed, so that it has good visibility and is suitable for displaying moving images.
(3) It is an all solid state element having a simple structure, and the element can be made highly reliable and thin.

  An organic EL display device using an organic EL element having these features as a pixel display element (hereinafter referred to as an organic EL display) is considered promising as a next-generation flat panel display.

  By the way, as a driving method of the organic EL display, there are a simple matrix method and an active matrix method. Among these methods, the active matrix method has the following features.

(1) An active matrix system that can hold light emission of an organic EL element in each pixel for one frame period is suitable for high definition and high luminance of an organic EL display.
(2) Since a peripheral circuit using a thin film transistor can be formed on a substrate (panel), the interface with the outside of the panel can be simplified and the function of the panel can be enhanced.

In this active matrix organic EL display, a polysilicon thin film transistor (TFT) having polysilicon as an active layer is generally used as a transistor as an active element.
This is because the polysilicon TFT has a high driving capability and can be designed to have a small pixel size, which is advantageous for high definition.

By the way, it is well known that the polysilicon TFT has the above-mentioned features, but has a large variation in characteristics.
Therefore, in the case of using a polysilicon TFT, it is a big problem in an active matrix type organic EL display using a polysilicon TFT to suppress the characteristic variation and to compensate for the TFT characteristic variation in a circuit. This is due to the following reason.

  That is, in a liquid crystal display using a liquid crystal cell as a pixel display element, the luminance data of each pixel is controlled by a voltage value, whereas in an organic EL display, the luminance data of each pixel is controlled by a current value. It is because the structure to control is taken.

Here, an outline of the active matrix organic EL display will be described.
FIG. 1 is a diagram illustrating an outline of a configuration of a general active matrix organic EL display, and FIG. 2 is a circuit diagram illustrating a configuration example of a pixel circuit of an active matrix organic EL display (for example, Patent Documents). 1 and 2).

  The active matrix organic EL display 1 includes m × n pixel circuits 10 arranged in a matrix, and signal lines SGL1 for n columns driven by a data driver (DDRV) 2 with respect to the matrix arrangement of the pixels PX. ... SGLn is wired for each pixel column, and m rows of scanning lines SCNL1 to SCNLm driven by the scan driver (SDRV) 3 are wired for each pixel row.

Further, as shown in FIG. 2, the pixel circuit 10 includes a p-channel TFT 11, an n-channel TFT 12, a capacitor C11, and a light emitting element 13 including an organic EL element (OLED).
The TFT 11 of each pixel circuit 10 has a source connected to the power supply potential line VCCL and a gate connected to the drain of the TFT 12. The organic EL light emitting element 13 has an anode connected to the drain of the TFT 11 and a cathode connected to a reference potential (for example, ground potential) GND.
The TFT 12 of each pixel circuit 10 is connected to the signal lines SGL1 to SGLn of the column corresponding to the source, and to the scanning lines SCNL1 to SCNLm of the row corresponding to the gate.
The capacitor C11 has one end connected to the power supply potential line VCCL and the other end connected to the drain of the TFT 12.

  Since organic EL elements often have rectifying properties, they are sometimes referred to as OLEDs (Organic Light Emitting Diodes). In FIG. 2 and other figures, diode symbols are used as light-emitting elements. However, it does not necessarily require rectification.

In the pixel circuit 10 having such a configuration, in a pixel to which luminance data is written, a pixel row including the pixel is selected by the scan driver 3 via the scanning line SCNL, so that the TFT 12 of the pixel in the row can be selected. Turn on.
At this time, the luminance data is supplied as a voltage from the data driver 2 through the signal line SGL, and is written into the capacitor C11 that holds the data voltage through the TFT 12.
The luminance data written in the capacitor C11 is held for one field period. The held data voltage is applied to the gate of the TFT 11.
Thereby, TFT11 drives the organic EL element 13 with an electric current according to holding | maintenance data. At this time, gradation expression of the organic EL light emitting element 13 is performed by modulating the gate-source voltage Vdata (<0) of the TFT 11 held by the capacitor C11.

  In general, the luminance Loled of the organic EL element is proportional to the current Ioled flowing through the element. Therefore, the following equation (1) is established between the luminance Loled of the organic EL light emitting element 13 and the current Ioled.

(Equation 1)
Loled∝Ioled = k (Vdata−Vth) ² (1)

In Equation (1), k = 1/2 · μ · Cox · W / L. Here, μ is the carrier mobility of the TFT 11, Cox is the gate capacitance per unit area of the TFT 11, W is the gate width of the TFT 11, and L is the gate length of the TFT 11.
Therefore, it can be seen that the variation in mobility μ and threshold voltage Vth (<0) of the TFT 11 directly affects the luminance variation of the organic EL light emitting element 13.

  In this case, for example, even when the same potential Vdata is written to different pixels, the threshold voltage Vth of the TFT 11 varies from pixel to pixel. As a result, the current Ioled flowing through the light emitting element (OLED) 13 varies greatly from pixel to pixel and is completely different from the desired value. As a result, the display cannot be expected to have high image quality.

  A number of pixel circuits have been proposed in order to improve this problem. A typical example is shown in FIG. 3 (see, for example, Patent Document 3 or Patent Document 4).

The pixel circuit 20 in FIG. 3 includes a p-channel TFT 21, n-channel TFTs 22 to 24, capacitors C21 and C22, and an organic EL light emitting element 25 that is a light emitting element. In FIG. 3, SGL indicates a signal line, SCNL indicates a scanning line, AZL indicates an auto-zero line, and DRVL indicates a drive line.
The operation of the pixel circuit 20 will be described below with reference to the timing chart shown in FIG.

  As shown in FIGS. 4A and 4B, the drive line DRVL and the auto-zero line AZL are set to high level, and the TFTs 22 and 23 are turned on. At this time, since the TFT 21 is connected to the light emitting element (OLED) 25 in a diode-connected state, a current flows through the TFT 21.

  Next, as shown in FIG. 4A, the drive line DRVL is set to low level, and the TFT 22 is turned off. At this time, the scanning line SCNL is at a high level as shown in FIG. 4C, and the TFT 24 is in a conductive state, and the reference potential Vref is applied to the signal line SGL as shown in FIG. 4D. Since the current flowing through the TFT 21 is cut off, the gate potential Vg of the TFT 21 rises as shown in FIG. 4E. However, when the potential rises to VDD− | Vth | Potential stabilizes. Hereinafter, this operation may be referred to as “auto-zero operation”.

  As shown in FIGS. 4B and 4D, the auto zero line AZL is set to a low level to turn off the TFT 23, and the potential of the signal line SGL is set to a potential that is lower than Vref by ΔVdata. This change in the signal line potential lowers the gate potential of the TFT 21 by ΔVg through the capacitor C21, as shown in FIG.

  As shown in FIGS. 4A and 4C, when the TFT 24 is turned off by setting the scanning line SCNL to the low level and the TFT 22 is turned on by setting the drive line DRVL to the high level, the TFT 21 and the light emitting element (OLED) 25 are turned on. Current flows, and the light emitting element 25 starts to emit light.

  If the parasitic capacitance can be ignored, ΔVg and the gate potential Vg of the TFT 21 are as follows.

(Equation 2)
ΔVg = ΔVdata × C1 / (C1 + C2) (2)

(Equation 3)
Vg = V _CC − | Vth | −ΔVdata × C1 / (C1 + C2) (3)

  Here, C1 indicates the capacitance value of the capacitor C21, and C2 indicates the capacitance value of the capacitor C22.

  On the other hand, if the current flowing through the light emitting element (OLED) 25 during light emission is Ioled, the current value is controlled by the TFT 21 connected in series with the light emitting element 25. Assuming that the TFT 21 operates in the saturation region, the following relationship is obtained using the well-known MOS transistor equation and the above equation (3).

(Equation 4)
Ioled = μCoxW / L / 2 (V _CC −Vg− | Vth |) ²
= ΜCoxW / L / 2 (ΔVdata × C1 / (C1 + C2)) ²
(4)

  Here, μ represents carrier mobility, Cox represents gate capacitance per unit area, W represents gate width, and L represents gate length.

  According to the equation (4), Ioled is controlled by ΔVdata given from the outside regardless of the threshold value Vth of the TFT 21. In other words, if the pixel circuit 20 of FIG. 3 is used, it is possible to realize a display device that is relatively unaffected by the threshold value Vth that varies from pixel to pixel and that has a relatively high current uniformity and, consequently, luminance uniformity.

USP 5,684,365 JP-A-8-234683 USP 6,229,506 Fig. 1 of JP-T-2002-514320. 3

As described above, when the pixel circuit 10 as shown in FIG. 2 is used, the luminance uniformity between the pixels is impaired due to variations in the threshold voltage Vth of the transistor, and a high-quality display device is configured. It is difficult.
Here, in FIG. 2, it should be noted that not only the characteristic variation of the transistor 11 but also the characteristic variation of the transistor 12 impairs the luminance uniformity between the pixels. What happens is that after the luminance data is written from the data line through the transistor 12, when the transistor 12 becomes non-conductive, part of its channel charge flows into the gate node of the transistor 11, but the amount of the transistor is the amount of the transistor This is because it depends on the characteristics of the transistor 11 and the change speed of the gate control signal of the transistor 11.

  On the other hand, if the pixel circuit of FIG. 3 is used, a display device with relatively high luminance uniformity can be realized, but this has the following problems.

The second problem is that the above description of the operation relating to the pixel circuit 20 of FIG. 3 is ideal, and in practice, the influence of the variation in Vth of the TFT 21 that drives the light emitting element (OLED) 25 is not eliminated. .
This is because the auto zero line AZL and the gate node of the TFT 21 are coupled by the gate capacitance of the TFT 23, and the channel charge of the TFT 23 becomes the gate of the TFT 21 in the process in which the auto zero line AZL transitions to a high level and the TFT 23 becomes non-conductive. This is because it flows into the node. The reason for this will be described next.

That is, the gate potential of the TFT 21 should ideally be VDD− | Vth | after the completion of the auto-zero operation, but actually becomes a slightly higher potential due to the inflow of the charge, and the inflow amount of the charge is It varies depending on the value of Vth. This is because the gate potential of the TFT 21 immediately before the end of the auto-zero operation is approximately VDD− | Vth |. Therefore, this potential is higher as | Vth | is smaller, for example.
On the other hand, when the auto zero line ends, the potential of the auto zero line AZL rises and the TFT 23 switches to non-conduction, so that the higher the source potential, that is, the gate potential of the TFT 21, the more delayed the timing at which the TFT 23 becomes non-conduction, Will flow into the gate of the TFT 21. As a result, the gate potential of the TFT 21 after completion of the auto-zero operation is influenced by | Vth |, and thus the above-described equations (3) and (4) are not strictly established and are affected by Vth which varies from pixel to pixel. become.

  Therefore, the inventors of the present application have proposed a pixel circuit that is not easily affected by noise due to the switch transistor as shown in FIG. 3, but the influence of switching noise is not completely eliminated.

When attention is paid to the pixel circuit of FIG. 3, there is one drive transistor (TFT 21) and three or four switching transistors in one pixel circuit.
The gates of these three or switching transistors are connected to a number of control lines such as scanning lines.
Among these three or four switching transistors, the TFT 22 turns on / off a current path (path) flowing through the organic EL light emitting element (OLED) 25.
Therefore, the resistance (ON resistance) when this switch is turned on is preferably as small as possible.
When this resistance is large, the gate-source voltage Vgs and the drain-source voltage Vds of the TFT 21, which is a drive transistor that determines the current flowing through the light emitting element 25, vary due to a voltage drop due to the resistance of the switch.
As a result, the current flowing through the light emitting element 25 cannot be determined accurately, and problems such as in-plane brightness variation due to the distribution of the voltage drop in the surface occur.

On the other hand, since the TFTs 23 and 24 as switching transistors form a transmission path for data signals and node voltages, when the gate voltage of the switching transistor fluctuates greatly, it is held in the pixel by the gate capacitance and the parasitic capacitance. The voltage fluctuates.
Therefore, it is not preferable to change the gate potential to be larger than the voltage that becomes the resistance necessary for charging and discharging the switch transistor.

  If these switching transistors TFT22, TFT23, and TFT24 are all n-channel, it is preferable that the on-potential of the TFT 21 is as high as possible, and the on-potential of the TFT 23 and TFT24 is excessively high. That is not preferable.

  The present invention has been made in view of such circumstances, and an object of the present invention is to stably and accurately supply a current of a desired value to a light emitting element of each pixel regardless of variations in threshold values of active elements inside the pixel. An object of the present invention is to provide a pixel circuit and a display device that can be supplied and can prevent unevenness in luminance of a display image, and as a result, can display a high-quality image.

  In order to achieve the above object, a first aspect of the present invention is a pixel circuit that drives an electro-optical element whose luminance changes according to a flowing current, and at least a signal line to which a signal corresponding to luminance information is supplied; A drive transistor for controlling a current flowing through the current supply line in accordance with a potential of the control terminal, at least a first and a second control line, at least a first and a second switching transistor, and a first and a second reference; The electro-optic element, the drive transistor, and at least one first switching transistor as a current path of a current flowing through the electro-optic element between the first reference potential and the second reference potential Are connected in series, the control terminal of the first switch transistor is connected to the first control line, and the second switch transistor is The second switching transistor is disposed outside the current path of the current flowing through the electro-optic element, the control terminal of the second switching transistor is connected to the second control line, and the first switching transistor and the second switching transistor are the same. The on-potential of the first control line and the on-potential of the second control line are such that the resistance value when the first switching transistor is on is the on-state of the second switching transistor. The value is set to be smaller than the resistance value at the time.

  Preferably, the first switching transistor and the second switching transistor are n-channel transistors, and the ON potential of the first control line is set higher than the second ON potential.

  Preferably, the first switching transistor and the second switching transistor are p-channel transistors, and the ON potential of the first control line is set lower than the second ON potential.

  Preferably, the electro-optical element is an organic EL element, and the driving transistor and the first and second switching transistors are thin film transistors.

  According to a second aspect of the present invention, there is provided a pixel circuit for driving an electro-optical element whose luminance is changed by a flowing current, a signal line to which a signal corresponding to at least luminance information is supplied, and at least first and second A control line is connected between the control line, the first and second reference potentials, a predetermined precharge potential, a field effect transistor, a node, the source of the field effect transistor and the first reference potential, and a control terminal Is connected to the first control line to be conductively controlled, a second switching transistor connected between the source of the field effect transistor and the node, and the field effect transistor A third switching transistor connected between a gate and the precharge potential; and a third switching transistor connected between the signal line and the node. And a coupling capacitor connected between the node and the gate of the field effect transistor, and the electro-optic element is connected between the drain of the transistor and a second reference potential. The control terminal of at least one switching transistor of the second, third, and fourth switching transistors is connected to the second control line for conduction control, and the first switching transistor and the control terminal are connected to the first switching transistor. At least one of the second, third, and fourth switching transistors connected to the second control line is a transistor of the same conductivity type, and the ON potential of the first control line and the second The on-potential of the control line has the second and third resistance values when the first switching transistor is on. Is set to the fourth least one smaller becomes such a value than the resistance value at the on-state of the switching transistor of the switching transistor.

  According to a third aspect of the present invention, there is provided a pixel circuit for driving an electro-optical element whose luminance is changed by a flowing current, a signal line to which a signal corresponding to at least luminance information is supplied, and at least first and second A control line; a first reference potential; a second reference potential; a predetermined precharge potential; a field effect transistor; a node; a source of the field effect transistor; and the electro-optic element; A first switching transistor connected to the first control line and controlled in conduction; a second switching transistor connected between a source of the field effect transistor and the node; and a gate of the field effect transistor. And a third switching transistor connected between the signal line and the node, and a third switching transistor connected between the signal line and the node. 4 and a coupling capacitor connected between the node and the gate of the field effect transistor, the drain of the field effect transistor is connected to a first reference potential, and the electro-optic element Is connected between the first switching transistor and the second reference potential, and the control terminal of at least one switching transistor of the second, third, and fourth switching transistors is connected to the second control line. The first switching transistor and the at least one switching transistor of the second, third, and fourth switching transistors whose control terminals are connected to the second control line have the same conductivity. Of the first control line and the second control line. Is set to a value such that the on-resistance value of the first switching transistor is smaller than the on-resistance value of at least one of the second, third, and fourth switching transistors. .

  According to a fourth aspect of the present invention, there is provided a pixel circuit for driving an electro-optical element whose luminance is changed by a flowing current, a signal line to which a signal corresponding to at least luminance information is supplied, and at least first and second A control line; a first reference potential; a second reference potential; a predetermined precharge potential; a field effect transistor; a node; a drain of the field effect transistor; and the electro-optic element; A first switch connected to the first control line and controlled in conduction; a second switch connected between a drain and a gate of the field effect transistor; and the node and the precharge potential. A third switch connected in between, a fourth switch connected between the signal line and the node, and between the node and the gate of the field effect transistor; A coupling capacitor connected, wherein the source of the field effect transistor is connected to a first reference potential, the electro-optic element is connected between the first switch and a second reference potential, The control terminal of at least one switching transistor of the second, third, and fourth switching transistors is connected to the second control line to control conduction, and the first switching transistor and the control terminal are connected to the second control line. At least one of the second, third, and fourth switching transistors connected to the control line is a transistor of the same conductivity type, and the on-potential of the first control line and the second switching transistor The second ON potential of the control line is such that the resistance value when the first switching transistor is ON is the second, third, or fourth switching transistor. Is set to at least one of the smaller becomes such a value than the resistance value at the on-state of the switching transistor in register.

  Preferably, at least one of the first switching transistor and the second, third, and fourth switching transistors is an n-channel transistor, and the ON potential of the first control line is the second switching transistor. Is set higher than the ON potential.

  Preferably, at least one of the first switching transistor and the second, third, and fourth switching transistors is a p-channel transistor, and the ON potential of the first control line is the second switching transistor. Is set lower than the ON potential.

  Preferably, the electro-optical element is an organic EL element, and the driving transistor, the first, second, third, and fourth switching transistors are thin film transistors.

  According to a fifth aspect of the present invention, there are provided a plurality of pixel circuits arranged in a matrix, a signal line wired for each column to the matrix arrangement of the pixel circuits, and supplied with at least a data signal corresponding to luminance information , At least a first control line and a second control line wired for each row with respect to the matrix arrangement of the pixel circuit, a first drive circuit for setting the potential of the first control line, and the first A second driving circuit for setting a potential of the two control lines, and each of the pixel circuits includes a driving transistor for controlling a current flowing through the current supply line in accordance with the potential of the control terminal, and at least a first driving circuit. And a second switching transistor, and a first reference potential and a second reference potential, and a current path of a current flowing through the electro-optic element between the first reference potential and the second reference potential, Electro-optic element A drive transistor, at least one first switching transistor connected in series, a control terminal of the first switch transistor connected to the first control line, and the second switch transistor connected to the electro-optic element The control terminal of the second switching transistor is connected to the second control line, and the first switching transistor and the second switching transistor are of the same conductivity type. The first and second driving circuits have an on-potential of the first control line and an on-potential of the second control line, and a resistance value when the first switching transistor is on is The value is set to be smaller than the resistance value when the second switching transistor is on.

  According to a sixth aspect of the present invention, there are provided a plurality of pixel circuits arranged in a matrix, a signal line wired for each column to the matrix arrangement of the pixel circuits, and supplied with at least a data signal corresponding to luminance information , At least a first control line and a second control line wired for each row with respect to the matrix arrangement of the pixel circuit, a first drive circuit for setting the potential of the first control line, and the first Each of the pixel circuits includes a first reference potential, a second reference potential, a predetermined precharge potential, a field effect transistor, a node, A first switching transistor connected between the source of the field effect transistor and a first reference potential, the control terminal of which is connected to the first control line and controlled in conduction, and the source of the field effect transistor A second switching transistor connected between the node, a third switching transistor connected between the gate of the field effect transistor and the precharge potential, and between the signal line and the node; And a coupling capacitor connected between the node and the gate of the field effect transistor, wherein the electro-optic element has a drain and a second reference potential of the transistor. And a control terminal of at least one switching transistor of the second, third, and fourth switching transistors is connected to the second control line to be conductively controlled, and the first switching transistor The second, third, and fourth switching transistors having control terminals connected to the second control line. The at least one switching transistor of the register is a transistor of the same conductivity type, and the first and second drive circuits have an on-potential of the first control line and an on-potential of the second control line. The resistance value when the first switching transistor is on is set to a value that is smaller than the resistance value when at least one of the second, third, and fourth switching transistors is on.

  According to a seventh aspect of the present invention, there are provided a plurality of pixel circuits arranged in a matrix, a signal line wired for each column to the matrix arrangement of the pixel circuits, and supplied with at least a data signal corresponding to luminance information , At least a first control line and a second control line wired for each row with respect to the matrix arrangement of the pixel circuit, a first drive circuit for setting the potential of the first control line, and the first Each of the pixel circuits includes a first reference potential, a second reference potential, a predetermined precharge potential, a field effect transistor, a node, A first switching transistor connected between the source of the field effect transistor and the electro-optic element, the control terminal of which is connected to the first control line to control conduction, and the source of the field effect transistor A second switching transistor connected between the gate and the node, a third switching transistor connected between the gate of the field effect transistor and the precharge potential, and the signal line and the node. A fourth switching transistor connected in between, and a coupling capacitor connected between the node and the gate of the field effect transistor, wherein the electro-optic element includes the first switching transistor and the second switching transistor. The control terminal of at least one switching transistor of the second, third, and fourth switching transistors is connected to the second control line for conduction control, and is connected to the first reference potential. The switching transistor and the second, third, and fourth switches having a control terminal connected to the second control line. At least one of the switching transistors is a transistor of the same conductivity type, and the first and second drive circuits include an on-potential of the first control line and an on-potential of the second control line. Is set to a value such that the on-resistance value of the first switching transistor is smaller than the on-resistance value of at least one of the second, third, and fourth switching transistors.

  According to an eighth aspect of the present invention, there are provided a plurality of pixel circuits arranged in a matrix, a signal line wired for each column to the matrix arrangement of the pixel circuits, and supplied with at least a data signal corresponding to luminance information , At least a first control line and a second control line wired for each row with respect to the matrix arrangement of the pixel circuit, a first drive circuit for setting the potential of the first control line, and the first Each of the pixel circuits includes a first reference potential, a second reference potential, a predetermined precharge potential, a field effect transistor, a node, A first switch connected between the drain of the field effect transistor and the electro-optic element, the control terminal of which is connected to the first control line to control conduction, and the drain and gate of the field effect transistor When A second switch connected in between; a third switch connected between the node and the precharge potential; a fourth switch connected between the signal line and the node; A coupling capacitor connected between the node and the gate of the field effect transistor, the source of the field effect transistor is connected to a first reference potential, and the electro-optic element is connected to the first switch And a second reference potential, and a control terminal of at least one of the second, third, and fourth switching transistors is connected to the second control line for conduction control, and A first switching transistor and at least one of the second, third, and fourth switching transistors having a control terminal connected to the second control line. And the first and second drive circuits are configured to set the first control line on-potential and the second control line on-potential to the first control line. The resistance value when the switching transistor is on is set to a value that is smaller than the resistance value when at least one of the second, third, and fourth switching transistors is on.

According to the present invention, for example, the first switching transistor, the second switching transistor, and the third switching transistor are turned on by the first control line, the second control line, and the like.
At this time, the control terminal of the driving transistor, for example, the gate is set to the precharge potential Vpc by the third switching transistor, and the input side potential (node potential) of the coupling capacitor is that the first and second switching transistors are in the conductive state. , Rise to the first reference potential (power supply potential V _CC ) or the vicinity thereof.
Then, the first switching transistor is turned off by the first control line. As a result, the current flowing through the drive transistor is cut off, so that the potential of the second terminal (for example, drain) of the drive transistor drops, but when the potential drops to Vpc + | Vth |, the drive transistor becomes non-conductive. To stabilize the potential.
At this time, the input side potential (node potential) of the capacitor is also Vpc + | Vth | because the second switching transistor is in a conductive state. Here, | Vth | is the absolute value of the threshold value of the driving transistor.
Next, the second and third switching transistors are turned off by the second control line or the like. Alternatively, after the second switching transistor is turned off by the second control line or the like, the third switching transistor is turned off. The potential of the input node of the capacitor is Vpc + | Vth |, and the gate potential of the driving transistor is Vpc. That is, the potential difference between the capacitor terminals is | Vth |.
Next, the fourth switching transistor is turned on, and the potential Vdata corresponding to the luminance data is supplied from the signal line to the input side node of the capacitor.
Since the potential difference between the capacitor terminals is maintained as | Vth |, the gate potential of the driving transistor is Vdata− | Vth |.
Next, when the fourth switching transistor is turned off and the first switching transistor is turned on by the first control line, a current flows through the driving transistor and the electro-optical element, and light emission is started.
In such a control operation, the on-potential of the first control line and the on-potential of the second, third, and / or fourth control line have a resistance value when the first switching transistor is on. The value is set to be smaller than the resistance value when the second, third, and fourth switching transistors are turned on.
As described above, the pixel circuit according to the present invention can supply current to the electro-optical element regardless of the threshold value of the driving transistor that varies from pixel to pixel, and thus can prevent unevenness in the luminance of the display image. A display device that displays high-quality images can be realized. In particular, when compared with the conventional technique, the configuration is less affected by noise from the control line to the drive transistor, and therefore, more accurate threshold variation correction can be performed.

  According to the present invention, a current of a desired value can be supplied to a light emitting element of each pixel stably and accurately regardless of variations in threshold values of active elements within the pixel, and unevenness in luminance of a display image can be prevented. As a result, a high-quality image can be displayed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 6 is a circuit diagram showing a first embodiment of an active matrix organic EL display (display device) according to the present invention.
FIG. 7 is a diagram showing a wiring arrangement related to the power supply line of the active matrix organic EL display according to the first embodiment.

As shown in FIG. 6, the organic EL display 100 includes a pixel array unit 102 in which pixel circuits 101 are arranged in an m × n matrix, a data driver (DDRV) 103, and a first drive circuit as a first drive circuit. It has a scan driver (SDRV1) 104 and a second scan driver (SDRV2) 105 as a second drive circuit.
The signal lines SGL1 to SGLn for n columns driven by the data driver (DDRV) 103 with respect to the matrix arrangement of the pixel circuit 101 are selectively driven by the first scan driver (SDRV1) 104 for each pixel column. Drive lines DRL101 to DRL10m for m rows, scan lines SCNL101 to SCNL10m for m rows selectively driven by the first scan driver (SDRV2) 105, and auto-zero lines AZL101 to AZL10m for each pixel row, respectively. Wired.
The drive lines DRL101 to DRL10m correspond to the first control line of the present invention, and the scan lines SCNL101 to SCNL10m and / or the auto zero lines AZL101 to AZL10m correspond to the second control line of the present invention.

  Further, in the present embodiment, n columns of power supply potential lines VCCL101 to VCCL10n for supplying the power supply voltage Vcc and n columns of precharge potential lines VPCL101 for supplying the reference voltage Vpc for performing offset cancellation. The VPCL 10n is wired for each pixel column in the same direction so as to be parallel to the signal lines SGL101 to SGL10n.

  Further, in the present embodiment, the power supply potential line VCCL is a pixel that is a display region in order to prevent luminance unevenness due to a potential difference in the length direction generated above and below the power supply potential line VCCL as shown in FIG. The upper and lower portions of the array unit 102 in the drawing are made common, that is, both ends of the plurality of power supply potential lines VCCL101 to VCCL10n are connected in common to achieve the same potential.

In the pixel array unit 102, the pixel circuits 101 are arranged in a matrix of m × n. However, in FIG. 6, a matrix of 2 (= m) × 2 (= n) is shown for simplification of the drawing. The example arranged in the shape is shown.
In FIG. 6, each of the 2 × 2 pixel circuits is also expressed as Pixel (M, N), Pixel (M, N + 1), Pixel (M + 1, N), and Pixel (M + 1, N + 1).

  Next, a specific configuration of each pixel circuit 101 will be described.

As shown in FIG. 6, the pixel circuit 101 includes one p-channel TFT 111, four n-channel TFTs 112 to 115, an organic EL light emitting element 116, capacitors C111 and C112, and nodes ND111 to ND113.
In this embodiment, the TFT 111 corresponds to the driving transistor of the present invention, the TFT 112 corresponds to the first switching transistor of the present invention, the TFT 113 corresponds to the second switching transistor of the present invention, and the TFT 115 corresponds to the main switching transistor. This corresponds to the third switching transistor of the invention, and the TFT 114 corresponds to the fourth switching transistor of the present invention.
The power supply potential VCC corresponds to the first reference potential of the present invention, and the ground potential GND corresponds to the second reference potential.

In the pixel circuit Pixel (M, N) arranged in the first row and first column in FIG. 6, the source of the TFT 111 as the drive transistor is connected to the power supply potential line VCCL101 wired in the first column, and the drain is connected to the node ND113. The gates are connected to the node ND111.
The drain of the TFT 112 is connected to the node ND113 (the drain of the TFT 111), the source is connected to the anode side of the organic EL light emitting element 116, the gate is connected to the drive line DRL101 wired in the first row, The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 113 is connected to the node ND113 (the drain of the TFT 111), the drain is connected to the node ND111 (the gate of the TFT 111), and the gate is connected to the auto zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND111, and a second electrode is connected to the node ND112. The first electrode of the capacitor C112 is connected to the node ND111, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 114 is connected to the node ND112, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 115 is connected to the node ND112, and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M + 1, N) arranged in the second row and first column in FIG. 6, the source of the TFT 111 as the drive transistor is connected to the power supply potential line VCCL101 wired in the first column, and the drain is connected to the node ND113. The gates are connected to the node ND111.
The drain of the TFT 112 is connected to the node ND113 (the drain of the TFT 111), the source is connected to the anode side of the organic EL light emitting element 116, the gate is connected to the drive line DRL102 wired in the second row, The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 113 is connected to the node ND113 (the drain of the TFT 111), the drain is connected to the node ND111 (the gate of the TFT 111), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND111, and a second electrode is connected to the node ND112. The first electrode of the capacitor C112 is connected to the node ND111, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 114 is connected to the node ND112, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 115 is connected to the node ND112, and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M, N + 1) arranged in the first row and the second column in FIG. 6, the source of the TFT 111 as the drive transistor is connected to the power supply potential line VCCL102 wired in the second column, and the drain is connected to the node ND113. The gates are connected to the node ND111.
The drain of the TFT 112 is connected to the node ND113 (the drain of the TFT 111), the source is connected to the anode side of the organic EL light emitting element 116, the gate is connected to the drive line DRL101 wired in the first row, The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 113 is connected to the node ND113 (the drain of the TFT 111), the drain is connected to the node ND111 (the gate of the TFT 111), and the gate is connected to the auto zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND111, and a second electrode is connected to the node ND112. The first electrode of the capacitor C112 is connected to the node ND111, and the second electrode is connected to the power supply potential line VCCL102 wired in the second column.
The source of the TFT 114 is connected to the node ND112, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 115 is connected to the node ND112, and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In the pixel circuit Pixel (M + 1, N + 1) arranged in the second row and the second column in FIG. 6, the source of the TFT 111 as the drive transistor is connected to the power supply potential line VCCL102 wired in the second column, and the drain is connected to the node ND113. The gates are connected to the node ND111.
The drain of the TFT 112 is connected to the node ND113 (the drain of the TFT 111), the source is connected to the anode side of the organic EL light emitting element 116, the gate is connected to the drive line DRL102 wired in the second row, The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 113 is connected to the node ND113 (the drain of the TFT 111), the drain is connected to the node ND111 (the gate of the TFT 111), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND111, and a second electrode is connected to the node ND112. The first electrode of the capacitor C112 is connected to the node ND111, and the second electrode is connected to the power supply potential line VCCL102 wired in the second column.
The source of the TFT 114 is connected to the node ND112, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 115 is connected to the node ND112, and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In the first embodiment, the TFTs 112 to 115 as the first to fourth switching transistors have the same conductivity type (n-channel), and the first scan driver 104 as the first drive circuit and the second The second scan driver 105 serving as the drive circuit includes the on potential Von1 of the drive lines DRL101 to DRL10m as the first control lines, the scan lines SCNL101 to SCNL10m and the auto zero lines AZL101 to AZL10m as the second control lines. The on-potential Von2 is set so that the on-resistance value of the TFT 112 as the first switching transistor is smaller than the on-resistance values of the TFTs 113 to 115 as the second, third, and fourth switching transistors. Set.
That is, as shown in FIGS. 8A and 8B, the first scan driver 104 and the second scan driver 105 drive the drive lines DRL101 to DRL10m so as to satisfy the relationship Von1> Von2. The signal VDRL and drive signals VSCNL and VAZL for the scanning lines SCNL101 to SCNL10m and the auto zero lines AZL101 to AZL10m are set.
The drive signal VDRL has an amplitude of (VDD−VSS), and the drive signals VSCNL and VAZL have an amplitude of [VDD2 (<VDD) −VSS].

FIG. 9 is a circuit diagram illustrating a configuration example of the generation circuit of the drive signal VDRL in the first scan driver 104 as the first drive circuit. In FIG. 9, for simplification of the drawing, a three-stage configuration is shown, and only one stage of the signal output system is shown. In practice, m shift registers and a signal output system are provided for each shift register.
As illustrated in FIG. 9, the first scan driver 104 includes a plurality of shift registers 1041 to 1043 and an output buffer 1044.
In order to drive the corresponding drive line DRL, for example, in response to the output of the shift register 1042, a drive signal VDRL having a high level of VDD level and a low level of VSS level is output from the output buffer 1044. Each n-channel TFT 112 is turned on (conducted) by a drive signal VDRL at the VDD level.

FIG. 10 is a circuit diagram showing a configuration example of a generation circuit of the drive signals VSCNL and VAZL in the second scan driver 105 as the second drive circuit. In FIG. 10, for simplification of the drawing, a three-stage configuration is shown, and only one stage of the signal output system is shown. In practice, m shift registers and a signal output system are provided for each shift register.
As illustrated in FIG. 10, the second scan driver 105 includes a plurality of shift registers 1051 to 1053 and an output buffer 1054.
In order to drive the corresponding scan line SCNL and auto-zero line AZL, in response to the output of the shift register 1052, for example, the drive signal VDRL of the VDD2 (<VDD) level at the high level and the VSS level at the low level is output from the output buffer 1054. Is output. Each of the n-channel TFTs 113 to 115 is turned on (conducted) by the drive signals VAZL and VSCNL at the VDD2 level.

FIG. 11 is a circuit diagram showing a configuration example of a circuit for generating the voltage VDD2 in the second scan driver 105 as the second drive circuit.
This generation circuit generates a voltage VDD2 through a voltage follower 1055 by dividing a voltage divided by resistance elements R101 and R102 connected in series between a supply line of the voltage VDD and a reference potential VSS.

  As described above, in the second embodiment, the first scan driver 104 and the second scan driver 105 satisfy the drive signal VDRL of the drive lines DRL101 to DRL10m so that the relationship Von1> Von2 is satisfied. By setting the drive signals VSCNL and VAZL of the scanning lines SCNL101 to SCNL10m and the auto zero lines AZL101 to AZL10m, the jump voltage and the switch resistance are optimized to prevent unevenness in the brightness of the display image, thereby achieving high quality. It is possible to display a simple image.

  Next, the operation of the pixel circuit 101 will be described using Pixel (M, N) in FIG. 6 as an example.

The drive line DRL101 is set to the high level (VDD, Von1), the auto zero line AZL101 is set to the high level (VDD2, Von2), and the TFTs 112, 113, and 115 are turned on. At this time, since the TFT 111 is connected to the light emitting element (OLED) 116 in a diode-connected state, a constant current Iref flows through the TFT 111.
Further, the fixed reference voltage Vpc supplied to the precharge potential line VPCL101 is supplied to the node ND112 on one end (second electrode side) of the coupling capacitor C111 through the TFT 115.
Then, at both ends of the coupling capacitor C111, the same voltage as the gate-source potential is generated when the current Iref flows through the TFT 111 as the driving transistor. This potential Vref is expressed by the following equation, with the gate side of the TFT 111 as the driving transistor being a plus direction.

(Equation 5)
Iref = β (Vref−Vth) ² (5)

  Here, β is a proportional coefficient of the driving transistor (the mobility of the driving transistor), and Vth is a threshold voltage of the driving transistor. That is, the gate-source potential Vref of the TFT 111 as the driving transistor is as follows.

(Equation 6)
Vref = Vth + (Iref / β) ^1/2 (6)

  Next, the drive line DRL101 is set to a low level (VSS), and the TFT 112 is turned off. At this time, the scanning line SCNL101 is at a high level (VDD2, Von2), and the TFT 114 is turned on, and the reference potential Vref is applied to the signal line SGL101. Since the current flowing through the TFT 111 is cut off, the gate potential Vg of the TFT 111 rises, but when the potential rises to Vcc− | Vth |, the TFT 111 becomes non-conductive and the potential is stabilized. That is, an auto zero operation is performed.

  The auto zero line AZL101 is set to the low level (VSS) to turn off the TFT 113, and the data voltage Vdata is written to the other end side (node ND111 side) of the coupling capacitor C111 through the signal line SGL101. Therefore, the gate-source potential of the driving transistor at this time is expressed as Vgs as follows.

(Equation 7)
Vgs = Vdata + Vref−Vsource
= Vdata + Vth + (Iref / β) ^1/2 −Vsource (7)

  Therefore, the current Ids flowing through the driving transistor is as follows.

(Equation 8)
Ids = β (Vdata + (Iref / β) ^1/2 −Vsource) ² (8)

  That is, the current Ids flowing through the driving transistor does not depend on the threshold voltage Vth, that is, threshold voltage correction is performed.

  Note that after the data voltage is taken in order for the light emitting element 116 to start light emission, the scanning line SCNL101 is set to the low level, the TFT 114 is turned off, the driving line DRL101 is set to the high level (VDD, von1), and the TFT 112 is turned on. The operation is performed.

Here, the timing of offset cancellation will be considered.
In the present embodiment, a pre-jersey potential line VPCL is wired in parallel with the signal line SGL. At this time, the number of pixels that are connected to one of the pre-jersey potential lines VPCL parallel to the signal line SGL and simultaneously cancel the offset is K pixels.
Usually, K is an offset cancellation period, which is a time required for sufficient offset, but usually 1 to several tens or less, which is smaller than the number of pixels subjected to offset cancellation simultaneously in the conventional example. Also, K does not change even if the panel resolution increases. Therefore, it becomes easy to keep the precharge potential at a stable potential.

As described above, according to the first embodiment, the drive lines DRL101 to DRL10m are driven so that the first scan driver 104 and the second scan driver 105 satisfy the relationship Von1> Von2. By setting the signal VDRL and the drive signals VSCNL and VAZL of the scanning lines SCNL101 to SCNL10m and the auto zero lines AZL101 to AZL10m, the jump voltage and the switch resistance are optimized, and the power supply for n columns supplying the power supply voltage Vcc The potential lines VCCL101 to VCCL10n and n columns of precharge potential lines VPCL101 to VPCL10n for supplying the reference voltage Vpc for performing offset cancellation are arranged in the same direction for each pixel column so that the signal lines SGL101 to SGL10n are parallel to each other. Wired to From the above, it is assumed that a current of a desired value can be supplied to the light emitting element of each pixel stably and accurately regardless of variations in the threshold value of the active element in the pixel, and an offset cancel function using a precharge potential line is provided. In addition, the reference potential can be stably maintained, and a gradient (unevenness) in the luminance of the display image can be prevented.
As a result, a high-quality image can be displayed.

  In the present embodiment, the power supply potential line VCCL is common to the upper and lower sides of the pixel array unit 102 in the drawing, that is, the power supply potential lines VCCL101 to VCCL10n are connected in common. We are trying to increase the potential. Therefore, luminance unevenness due to a potential difference in the length direction occurring at the top and bottom of the power supply potential line VCCL in the drawing can be reliably prevented.

  Note that the auto-zero line AZL is commonly used as a control line for turning on / off the TFT 125, but it is also possible to perform on / off control using another control line.

Second Embodiment
FIG. 12 is a circuit diagram showing a second embodiment of an active matrix organic EL display (display device) according to the present invention.

The second embodiment is different from the first embodiment of FIG. 6 described above in the configuration of the pixel circuit 101A.
That is, in the pixel circuit 101 of FIG. 6, the TFTs 112 to 115 as the switching transistors are configured by n-channel transistors, but in the pixel circuit 101A of the second embodiment, the TFTs 112 to 115 as the switching transistors are p-channel transistors. It is constituted by.

  In this case, the drive signal VDRL of the drive lines DRL101 to DRL10m driven by the first scan driver 104A and the second scan driver 105A, and the levels of the drive signals VSCNL and VAZL of the scan lines SCNL101 to SCNL10m and the auto zero lines AZL101 to AZL10m However, the levels of the drive signals VDRL of the drive lines DRL101 to DRL10m and the drive signals VSCNL and VAZL of the scan lines SCNL101 to SCNL10m and the auto-zero lines AZL101 to AZL10m are Von1 < It is set so as to satisfy the relationship of Von2.

In the second embodiment, the TFTs 112 to 115 as the first to fourth switching transistors have the same conductivity type (p channel), and the first scan driver 104A as the first drive circuit and the second The second scan driver 105A serving as the drive circuit includes the on-potential Von1 of the drive lines DRL101 to DRL10m as the first control lines, the scan lines SCNL101 to SCNL10m and the auto zero lines AZL101 to AZL10m as the second control lines. The on-potential Von2 is set so that the on-resistance value of the TFT 112 as the first switching transistor is smaller than the on-resistance values of the TFTs 113 to 115 as the second, third, and fourth switching transistors. Set.
That is, as shown in FIGS. 13A and 13B, the first scan driver 104A and the second scan driver 105A drive the drive lines DRL101 to DRL10m so as to satisfy the relationship Von1 <Von2. The signal VDRL and drive signals VSCNL and VAZL for the scanning lines SCNL101 to SCNL10m and the auto zero lines AZL101 to AZL10m are set.
The drive signal VDRL has an amplitude of (VDD−VSS), and the drive signals VSCNL and VAZL have an amplitude of [VDD−VSS2 (> VSS)].

FIG. 14 is a circuit diagram illustrating a configuration example of the generation circuit of the drive signal VDRL in the first scan driver 104A as the first drive circuit. In FIG. 14, for simplification of the drawing, a three-stage configuration is shown, and only one stage of the signal output system is shown. In practice, m shift registers and a signal output system are provided for each shift register.
As shown in FIG. 14, the first scan driver 104A includes a plurality of shift registers 1041A to 1043A and an output buffer 1044A.
In order to drive the corresponding drive line DRL, for example, in response to the output of the shift register 1042A, the output signal 1044A outputs the drive signal VDRL whose high level is VDD level and low level is VSS level. Each of the p-channel TFTs 112 is turned on (conducted) in response to a VSS level drive signal VDRL.

FIG. 15 is a circuit diagram showing a configuration example of a generation circuit of the drive signals VSCNL and VAZL in the second scan driver 105A as the second drive circuit. In FIG. 15, for simplification of the drawing, a three-stage configuration is shown, and only one stage of the signal output system is shown. In practice, m shift registers and a signal output system are provided for each shift register.
As shown in FIG. 15, the second scan driver 105A includes a plurality of shift registers 1051A to 1053A and an output buffer 1054A.
In order to drive the corresponding scan line SCNL and auto-zero line AZL, for example, in response to the output of the shift register 1052A, the drive signal VDRL of the VDD level at the high level and the VSS2 (> VSS) level at the low level is output from the output buffer 1054A. Is output. Each of the p-channel TFTs 113 to 115 is turned on (conductive) in response to the VSS2 level drive signals VAZL and VSCNL.

FIG. 16 is a circuit diagram illustrating a configuration example of a circuit for generating the voltage VDD2 in the second scan driver 105A as the second drive circuit.
This generation circuit generates a voltage VSS2 through a voltage follower 1055A obtained by dividing a voltage divided by the resistance elements R103 and R104 connected in series between the supply line of the voltage VDD and the reference potential VSS2.

  As described above, in the second embodiment, the drive signals VDRL of the drive lines DRL101 to DRL10m are set so that the first scan driver 104A and the second scan driver 105A satisfy the relationship of Von1 <Von2. By setting the drive signals VSCNL and VAZL of the scanning lines SCNL101 to SCNL10m and the auto zero lines AZL101 to AZL10m, the jump voltage and the switch resistance are optimized to prevent unevenness in the brightness of the display image, thereby achieving high quality. It is possible to display a simple image.

  The operation in FIG. 12 is performed in the same manner as in the first embodiment except that the active level of the drive signal is opposite to that in the case of FIG. 6, and thus detailed description thereof is omitted here.

  According to the second embodiment, the same effect as that of the first embodiment described above can be obtained.

<Third Embodiment>
FIG. 17 is a circuit diagram showing a third embodiment of an active matrix organic EL display (display device) according to the present invention.

The difference between the third embodiment and the first embodiment described above is the configuration of the pixel circuit 101B.
Hereinafter, the configuration and operation of the pixel circuit 101B according to the third embodiment will be described in order.

As shown in FIG. 17, each pixel circuit 101B according to the third embodiment includes a light-emitting element 126 including a p-channel TFT 121, n-channel TFTs 122 to 125, capacitors C121 and C122, and an organic EL element OLED (electro-optical element). And nodes ND121 to ND123.
Among these components, the TFT 121 constitutes a field effect transistor according to the present invention, the TFT 122 constitutes a first switching transistor, the TFT 123 constitutes a second switching transistor, and the TFT 125 constitutes a third switching transistor. The TFT 124 constitutes a fourth switching transistor, and the capacitor C121 constitutes a capacitor according to the present invention.
Note that the auto-zero line AZL is commonly used as a control line for turning on / off the TFT 125, but it is also possible to perform on / off control using another control line.
Further, the supply line (power supply potential) of the power supply voltage V _CC corresponds to the first reference potential, and the potential of the cathode line CSL (for example, the ground potential GND) corresponds to the second reference potential.

In the pixel array unit 102B, the pixel circuits 101B are arranged in an m × n matrix. However, in FIG. 17 as well, a 2 (= m) × 2 (= n) matrix is used for simplification of the drawing. The example arranged in the shape is shown.
In FIG. 17, each of the 2 × 2 pixel circuits is also expressed as Pixel (M, N), Pixel (M, N + 1), Pixel (M + 1, N), and Pixel (M + 1, N + 1).

  Next, a specific configuration of each pixel circuit 101B will be described.

In the pixel circuit Pixel (M, N) arranged in the first row and the first column in FIG. 17, the source of the TFT 121 as a drive transistor is connected to the node ND123 (the connection point between the source of the TFT 122 and the drain of the TFT TFT 123). The organic EL light emitting element 116 is connected to the anode side, and the cathode of the light emitting element 126 is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 122 is connected to the node ND123 (source of the TFT 121), the drain is connected to the power supply potential line VCCL101 wired in the first column, and the gate is connected to the drive line DRL101 wired in the first row. Yes.
The drain of the TFT 123 is connected to the node ND123 (source of the TFT 121), the source is connected to the node ND122 (source of the TFT 124), and the gate is connected to the auto-zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND121, and a second electrode is connected to the node ND122. The first electrode of the capacitor C122 is connected to the node ND122, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 124 is connected to the node ND122, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 125 is connected to the node ND121 (the gate of the TFT 121), and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M + 1, N) arranged in the second row and the first column in FIG. 17, the source of the TFT 121 as a drive transistor is connected to a node ND123 (a connection point between the source of the TFT 122 and the drain of the TFT TFT 123). The organic EL light emitting element 116 is connected to the anode side, and the cathode of the light emitting element 126 is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 122 is connected to the node ND123 (source of the TFT 121), the drain is connected to the power supply potential line VCCL101 wired in the first column, and the gate is connected to the drive line DRL102 wired in the second row. Yes.
The drain of the TFT 123 is connected to the node ND123 (source of the TFT 121), the source is connected to the node ND122 (source of the TFT 124), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND121, and a second electrode is connected to the node ND122. The first electrode of the capacitor C122 is connected to the node ND122, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 124 is connected to the node ND122, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 125 is connected to the node ND121 (the gate of the TFT 121), and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M, N + 1) arranged in the first row and the second column in FIG. 17, the source of the TFT 121 as a drive transistor is connected to the node ND123 (the connection point between the source of the TFT 122 and the drain of the TFT TFT 123). The organic EL light emitting element 116 is connected to the anode side, and the cathode of the light emitting element 126 is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 122 is connected to the node ND123 (source of the TFT 121), the drain is connected to the power supply potential line VCCL102 wired in the second column, and the gate is connected to the drive line DRL101 wired in the first row. Yes.
The drain of the TFT 123 is connected to the node ND123 (source of the TFT 121), the source is connected to the node ND122 (source of the TFT 124), and the gate is connected to the auto-zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND121, and a second electrode is connected to the node ND122. The first electrode of the capacitor C122 is connected to the node ND122, and the second electrode is connected to the power supply potential line VCCL102 wired in the second column.
The source of the TFT 124 is connected to the node ND122, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 125 is connected to the node ND121 (the gate of the TFT 121), and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In the pixel circuit Pixel (M + 1, N + 1) arranged in the second row and the second column in FIG. 17, the source of the TFT 121 as a drive transistor is connected to the node ND123 (the connection point between the source of the TFT 122 and the drain of the TFT TFT 123), and the drain is The organic EL light emitting element 116 is connected to the anode side, and the cathode of the light emitting element 126 is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 122 is connected to the node ND123 (source of the TFT 121), the drain is connected to the power supply potential line VCCL102 wired in the second column, and the gate is connected to the drive line DRL102 wired in the second row. Yes.
The drain of the TFT 123 is connected to the node ND123 (source of the TFT 121), the source is connected to the node ND122 (source of the TFT 124), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND121, and a second electrode is connected to the node ND122. The first electrode of the capacitor C122 is connected to the node ND122, and the second electrode is connected to the power supply potential line VCCL102 wired in the second column.
The source of the TFT 124 is connected to the node ND122, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 125 is connected to the node ND121 (the gate of the TFT 121), and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In the third embodiment, the TFTs 122 to 125 as the first to fourth switching transistors have the same conductivity type (n channel), and the first scan driver 104B as the first drive circuit and the second The second scan driver 105B serving as the drive circuit includes the ON potential Von1 of the drive lines DRL101 to DRL10m as the first control lines, the scan lines SCNL101 to SCNL10m and the auto zero lines AZL101 to AZL10m as the second control lines. The on-potential Von2 is set so that the on-resistance value of the TFT 122 as the first switching transistor is smaller than the on-resistance values of the TFTs 123 to 125 as the second, third, and fourth switching transistors. Set.
That is, as shown in FIGS. 18A, 18B, and 18C, the first scan driver 104B and the second scan driver 105B have the drive line DRL101 so as to satisfy the relationship Von1> Von2. Drive signal VDRL for .about.DRL10m and drive signals VSCNL and VAZL for scan lines SCNL101 to SCNL10m and auto-zero lines AZL101 to AZL10m are set.
The drive signal VDRL has an amplitude of (VDD−VSS), and the drive signals VSCNL and VAZL have an amplitude of [VDD2 (<VDD) −VSS].

  The drive signal generation circuits of the first scan driver 104B and the second scan driver 105B have the same configuration as the circuit configurations of FIGS.

  As described above, in the third embodiment, the drive signals VDRL of the drive lines DRL101 to DRL10m are set so that the first scan driver 104B and the second scan driver 105B satisfy the relationship of Von1> Von2. By setting the drive signals VSCNL and VAZL of the scanning lines SCNL101 to SCNL10m and the auto zero lines AZL101 to AZL10m, the jump voltage and the switch resistance are optimized to prevent unevenness in the brightness of the display image, thereby achieving high quality. It is possible to display a simple image.

  Next, the operation of the pixel circuit 101B will be described with reference to timing charts shown in FIGS. 18A to 18F, taking Pixel (M, N) in FIG. 17 as an example.

Step ST11 :
First, as shown in FIGS. 18A and 18B, the drive line DRL101 is set to the high level (VDD, Von1), the auto-zero line AZL101 is set to the high level (VDD2, Von2), and the TFT122, TFT123, and TFT125 are turned on. To do.
At this time, the gate of the TFT 121 becomes a precharge potential Vpc by the TFT 125 as shown in FIG. 18F, and the input side potential VC121 of the capacitor C121 is shown in FIG. 18E because the TFT 122 and the TFT 123 are in a conductive state. Thus, it rises to the power supply potential V _CC or the vicinity thereof.

Step ST12:
As shown in FIG. 18A, the drive line DRL101 is set to a low level (VSS), and the TFT 122 is turned off. Since the current flowing through the TFT 121 is cut off, the drain potential of the TFT 121 decreases. However, when the potential decreases to Vpc + | Vth |, the TFT 121 becomes non-conductive and the potential is stabilized.
At this time, the input side potential VC121 of the capacitor C121 is also Vpc + | Vth | as shown in FIG. 18E because the TFT 123 is in a conductive state. Here, | Vth | is the absolute value of the threshold value of the TFT 121.

Step ST13 :
As shown in FIG. 18B, the auto-zero line AZL101 is set to a low level to turn off the TFT 123 and the TFT 125. The potential VC121 of the input side node of the capacitor C121 is Vpc + | Vth | as shown in FIG. 18E, and the gate potential Vg121 of the TFT 121 is Vpc as shown in FIG. 18F. That is, the potential difference between the terminals of the capacitor C121 is | Vth |.

Step ST14 :
As shown in FIGS. 18C and 18D, the scanning line SCNL101 is set to the high level to make the TFT 124 conductive, and the potential Vdata corresponding to the luminance data is supplied from the signal line SGL101 to the input side node ND121 of the capacitor C121.
Since the potential difference between the terminals of the capacitor C121 is maintained as | Vth |, the gate potential Vg121 of the TFT 121 becomes Vdata− | Vth | as shown in FIG.

Step ST15 :
As shown in FIGS. 18A and 18C, when the scanning line SCNL101 is set to the high level (VDD2, Von2) and the TFT 124 is turned off, and the driving line DRL101 is set to the high level (VDD and Von1) and the TFT 122 is turned on. A current flows through the TFT 121 and the light emitting element (OLED) 126, and the OLED starts to emit light.

  In the operations of steps ST11 and ST12, it is necessary to set the value of Vpc so that Vpc + | Vth | <VDD. However, as long as this value is satisfied, the value of Vpc is arbitrary.

  When the current Ioled flowing through the light emitting element (OLED) 126 is calculated after the above operation is performed, if the TFT 121 is operating in the saturation region, the following is obtained.

(Equation 9)
Ioled = μCoxW / L / 2 (Vgs−Vth) ²
= ΜCoxW / L / 2 (V _CC −Vg− | Vth |) ²
= ΜCoxW / L / 2 (V _CC −Vdata + | Vth | − | Vth |) ²
= ΜCoxW / L / 2 (V _CC −Vdata) ²
... (9)

Here, μ represents carrier mobility, Cox represents gate capacitance per unit area, W represents gate width, and L represents gate length.
According to the equation (9), the current Ioled does not depend on the threshold value Vth of the TFT 121 (regardless of Vth) and is controlled by Vdata supplied from the outside.
In other words, when the pixel circuit 101B in FIG. 11 is used, it is possible to realize a display device that is relatively free from the influence of Vth, which varies from pixel to pixel, and that has relatively high current uniformity and luminance uniformity.

  Even when the TFT 121 is operating in the linear region, the current Ioled flowing through the light emitting element (OLED) 126 is as follows and is not dependent on Vth.

(Equation 10)
Ioled = μCoxW / L {(Vgs -Vth) Vds-Vds 2/2}
= ΜCoxW / L {(V _CC −Vg− | Vth |) (V _CC −Vd) − (V _CC
-Vd) ^2/2}
= ΜCoxW / L {(V _CC −Vdata + | Vth | − | Vth |) (V _CC −
_{Vd) - (V CC -Vd)} 2/2}
_{= ΜCoxW / L {(V CC} -Vdata) (V CC -Vd) - (V CC -Vd) 2/2}
(10)

  Here, Vd represents the drain potential of the TFT 121.

As described above, the pixel circuit 101B of the third embodiment is superior to the conventional example of FIG. 1 in that the influence of variations in the threshold value Vth can be canceled.
3 is superior to the conventional example of FIG. 3 in the following points.
First, the conventional example of FIG. 3 has a problem that the gate amplitude ΔVg of the driving transistor decreases according to the equation (2) with respect to the data amplitude ΔVdata driven from the outside. Accordingly, the pixel circuit can be driven with a smaller signal line amplitude.
As a result, it is possible to drive with lower power consumption and lower noise.
Second, regarding the capacitive coupling between the auto-zero line and the TFT gate, which is a problem in the conventional example of FIG. 3, the TFT 123 is not directly connected to the gate of the TFT 121 in the pixel circuit 101B of FIG. Less is.
On the other hand, the TFT 125 is connected to the gate of the TFT 121, but the source of the TFT 125 is connected to the constant potential Vpc. Therefore, even if the gate potential changes at the end of the auto-zero operation, the gate potential of the TFT 121 is approximately Vpc. Kept at potential.
As described above, in the pixel circuit 101B of FIG. 17, the influence of the coupling between the auto zero line AZL31 and the gate of the TFT 121 is small, and as a result, the Vth variation is corrected more accurately than the pixel circuit of FIG.
That is, according to the present embodiment, a current having a desired value is accurately supplied to the light emitting element of the pixel circuit regardless of variations in the threshold value of the transistor, and as a result, a high-quality image with high luminance uniformity. An organic EL pixel circuit capable of displaying the above can be realized. As a result, the threshold value can be corrected with higher accuracy than the conventional similar circuit.

Also consider the timing of offset cancellation.
Also in the third embodiment, the pre-jersey potential line VPCL is wired in parallel with the signal line SGL. At this time, the number of pixels that are connected to one of the pre-jersey potential lines VPCL parallel to the signal line SGL and simultaneously cancel the offset is K pixels.
Usually, K is an offset cancellation period, which is a time required for sufficient offset, but usually 1 to several tens or less, which is smaller than the number of pixels subjected to offset cancellation simultaneously in the conventional example. Also, K does not change even if the panel resolution increases. Therefore, it becomes easy to keep the precharge potential at a stable potential.

  According to the third embodiment, an effect similar to that of the first embodiment described above, that is, a desired light emitting element of each pixel can be stably and accurately regardless of variations in threshold values of active elements inside the pixel. Can be supplied, and even if the offset cancel function using the precharge potential line is provided, the reference potential can be stably maintained, and a gradient in the brightness of the display image can be prevented. As a result, there is an advantage that a high-quality image can be displayed.

  Also in the third embodiment, the power supply potential line VCCL is common to the upper and lower sides of the pixel array unit 102 as a display region, that is, both ends of the plurality of power supply potential lines VCCL101 to VCCL10n are connected in common. Therefore, the same potential is achieved. Accordingly, luminance unevenness due to a potential difference in the length direction occurring at the top and bottom of the power supply potential line VCCL in the drawing can be prevented.

<Fourth embodiment>
FIG. 19 is a circuit diagram showing a fourth embodiment of an active matrix organic EL display (display device) according to the present invention.

The fourth embodiment is different from the above-described third embodiment of FIG. 17 in the configuration of the pixel circuit 101C.
That is, in the pixel circuit 101B of FIG. 17, the TFTs 122 to TFT125 as switching transistors are configured by n-channel transistors, but in the pixel circuit 101C of the fourth embodiment, the TFTs 122 to TFT125 as switching transistors are replaced by p-channel transistors. It is constituted by.

  In this case, the drive signal VDRL of the drive lines DRL101 to DRL10m driven by the first scan driver 104C and the second scan driver 105C, and the levels of the drive signals VSCNL and VAZL of the scan lines SCNL101 to SCNL10m and the auto zero lines AZL101 to AZL10m However, the levels of the drive signals VDRL of the drive lines DRL101 to DRL10m and the drive signals VSCNL and VAZL of the scan lines SCNL101 to SCNL10m and the auto-zero lines AZL101 to AZL10m are Von1 < It is set so as to satisfy the relationship of Von2.

In the fourth embodiment, the TFTs 122 to 125 as the first to fourth switching transistors have the same conductivity type (p channel), and the first scan driver 104C as the first drive circuit and the second The second scan driver 105C as a drive circuit of the second control circuit includes an ON potential Von1 of drive lines DRL101 to DRL10m as first control lines, and scan lines SCNL101 to SCNL10m and auto zero lines AZL101 to AZL10m as second control lines. The on-potential Von2 is set so that the on-resistance value of the TFT 122 as the first switching transistor is smaller than the on-resistance values of the TFTs 123 to 125 as the second, third, and fourth switching transistors. Set.
That is, as shown in FIGS. 20A, 20B, and 20C, the first scan driver 104C and the second scan driver 105C have the drive line DRL101 so that the relationship Von1 <Von2 is satisfied. Drive signal VDRL for .about.DRL10m and drive signals VSCNL and VAZL for scan lines SCNL101 to SCNL10m and auto-zero lines AZL101 to AZL10m are set.
The drive signal VDRL has an amplitude of (VDD−VSS), and the drive signals VSCNL and VAZL have an amplitude of [VDD−VSS2 (> VSS)].

  The drive signal generation circuits of the first scan driver 104C and the second scan driver 105C have the same configuration as the circuit configurations of FIGS. 14, 15, and 16.

  As described above, in the fourth embodiment, the drive signals VDRL of the drive lines DRL101 to DRL10m are set so that the first scan driver 104C and the second scan driver 105C satisfy the relationship Von1 <Von2. By setting the drive signals VSCNL and VAZL of the scanning lines SCNL101 to SCNL10m and the auto zero lines AZL101 to AZL10m, the jump voltage and the switch resistance are optimized to prevent unevenness in the brightness of the display image, thereby achieving high quality. It is possible to display a simple image.

  The operation in FIG. 19 is performed in the same manner as in the third embodiment except that the active level of the drive signal is opposite to that in the case of FIG. 17, and thus detailed description thereof is omitted here.

  According to the fourth embodiment, the same effects as those of the third embodiment described above can be obtained.

<Fifth Embodiment>
FIG. 21 is a circuit diagram showing a fifth embodiment of an active matrix organic EL display (display device) according to the present invention.

The fifth embodiment is different from the third embodiment described above in the configuration of the pixel circuit 101D.
Hereinafter, the configuration and operation of the pixel circuit 101D according to the fifth embodiment will be described in order.

As shown in FIG. 21, each pixel circuit 101D according to the fifth embodiment includes n-channel TFTs 131 to 135, capacitors C131 and C132, a light-emitting element 136 including an organic EL element OLED (electro-optical element), and a node ND131. ~ ND133.
Of these components, the TFT 131 constitutes a field effect transistor according to the present invention, the TFT 132 constitutes a first switching transistor, the TFT 133 constitutes a second switching transistor, and the TFT 135 constitutes a third switching transistor. The TFT 134 constitutes a fourth switching transistor, and the capacitor C131 constitutes a capacitor according to the present invention.
Note that the auto-zero line AZL is commonly used as a control line for turning on / off the TFT 135, but it is also possible to perform on / off control using another control line.
Further, the supply line (power supply potential) of the power supply voltage V _CC corresponds to the first reference potential, and the potential of the cathode line CSL (for example, the ground potential GND) corresponds to the second reference potential.

In the present pixel array unit 102D, the pixel circuits 101D are arranged in an m × n matrix. However, in FIG. 21 as well, a 2 (= m) × 2 (= n) matrix is used for simplification of the drawing. The example arranged in the shape is shown.
In FIG. 21, each of the 2 × 2 pixel circuits is also expressed as Pixel (M, N), Pixel (M, N + 1), Pixel (M + 1, N), and Pixel (M + 1, N + 1).

  Next, a specific configuration of each pixel circuit 101D will be described.

In the pixel circuit Pixel (M, N) arranged in the first row and first column in FIG. 21, the drain of the TFT 131 as a drive transistor is connected to the power supply potential line VCCL101 wired in the first column, and the source is connected to the node ND133. The gates are connected to the node ND131.
The drain of the TFT 132 is connected to the node ND133 (source of the TFT 131), the source is connected to the anode side of the organic EL light emitting element 136, the gate is connected to the drive line DRL101 wired in the first row, and the light emitting element 116 The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 133 is connected to the node ND133 (source of the TFT 131), the drain is connected to the node ND131 (gate of the TFT 131), and the gate is connected to the auto-zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND131, and a second electrode is connected to the node ND132. The first electrode of the capacitor C132 is connected to the node ND131, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 134 is connected to the node ND132, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 135 is connected to the node ND132, and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M + 1, N) arranged in the second row and the first column in FIG. 21, the drain of the TFT 131 as the drive transistor is connected to the power supply potential line VCCL101 wired in the first column, and the source is connected to the node ND133. The gates are connected to the node ND131.
The drain of the TFT 132 is connected to the node ND133 (the source of the TFT 131), the source is connected to the anode side of the organic EL light emitting device 136, the gate is connected to the drive line DRL102 wired in the second row, and the light emitting device 116 The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 133 is connected to the node ND133 (source of the TFT 131), the drain is connected to the node ND131 (gate of the TFT 131), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND131, and a second electrode is connected to the node ND132. The first electrode of the capacitor C132 is connected to the node ND131, and the second electrode is connected to the power supply potential line VCCL101 wired in the first column.
The source of the TFT 134 is connected to the node ND132, the drain is connected to the signal line SGL101 wired in the first column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 135 is connected to the node ND132, and the drain is connected to the precharge potential line VPCL101 wired in the first column.

In the pixel circuit Pixel (M, N + 1) arranged in the first row and the second column in FIG. The gates are connected to the node ND131.
The drain of the TFT 132 is connected to the node ND133 (source of the TFT 131), the source is connected to the anode side of the organic EL light emitting element 136, the gate is connected to the drive line DRL101 wired in the first row, and the light emitting element 116 The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 133 is connected to the node ND133 (source of the TFT 131), the drain is connected to the node ND131 (gate of the TFT 131), and the gate is connected to the auto-zero line AZL101 wired in the first row.
A first electrode of the capacitor C101 is connected to the node ND131, and a second electrode is connected to the node ND132. The first electrode of the capacitor C132 is connected to the node ND131, and the second electrode is connected to the power supply potential line VCCL102 wired in the second column.
The source of the TFT 134 is connected to the node ND132, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL101 wired in the first row.
The source of the TFT 135 is connected to the node ND132, and the drain is connected to the precharge potential line VPCL102 wired in the second column.

In the pixel circuit Pixel (M + 1, N + 1) arranged in the second row and the second column in FIG. The gates are connected to the node ND131.
The drain of the TFT 132 is connected to the node ND133 (the source of the TFT 131), the source is connected to the anode side of the organic EL light emitting device 136, the gate is connected to the drive line DRL102 wired in the second row, and the light emitting device 116 The cathode is connected to a cathode line CSL having a predetermined potential (for example, ground potential).
The source of the TFT 133 is connected to the node ND133 (source of the TFT 131), the drain is connected to the node ND131 (gate of the TFT 131), and the gate is connected to the auto zero line AZL102 wired in the second row.
A first electrode of the capacitor C101 is connected to the node ND131, and a second electrode is connected to the node ND132. The first electrode of the capacitor C132 is connected to the node ND131, and the second electrode is connected to the power supply potential line VCCL102 wired in the second column.
The source of the TFT 134 is connected to the node ND132, the drain is connected to the signal line SGL102 wired in the second column, and the gate is connected to the scanning line SCNL102 wired in the second row.
The source of the TFT 135 is connected to the node ND132, and the drain is connected to the precharge potential line VPCL102 wired in the second column.

  The biggest difference between the pixel circuit 101D in FIG. 21 and the pixel circuit 101B in FIG. 17 is that the TFT 131 is an n-channel as a drive transistor for controlling the current flowing in the light emitting element (OLED) 136, and the source and the organic EL light emitting element ( OLED) and a TFT 132 as a switch.

In the fifth embodiment, the TFTs 132 to 135 as the first to fourth switching transistors have the same conductivity type (n-channel), and the first scan driver 104D as the first drive circuit and the second The second scan driver 105D serving as the drive circuit includes the ON potential Von1 of the drive lines DRL101 to DRL10m as the first control lines, the scan lines SCNL101 to SCNL10m and the auto zero lines AZL101 to AZL10m as the second control lines. The on-potential Von2 is set so that the on-resistance value of the TFT 132 as the first switching transistor is smaller than the on-resistance values of the TFTs 133 to 135 as the second, third, and fourth switching transistors. Set.
That is, as shown in FIGS. 22A, 22B, and 22C, the first scan driver 104B and the second scan driver 105D drive line DRL101 so as to satisfy the relationship Von1> Von2. Drive signal VDRL for .about.DRL10m and drive signals VSCNL and VAZL for scan lines SCNL101 to SCNL10m and auto-zero lines AZL101 to AZL10m are set.
The drive signal VDRL has an amplitude of (VDD−VSS), and the drive signals VSCNL and VAZL have an amplitude of [VDD2 (<VDD) −VSS].

  The drive signal generation circuits of the first scan driver 104D and the second scan driver 105D have the same configuration as the circuit configurations of FIGS.

  As described above, in the fifth embodiment, the drive signal VDRL of the drive lines DRL101 to DRL10m is set so that the first scan driver 104D and the second scan driver 105D satisfy the relationship of Von1> Von2. By setting the drive signals VSCNL and VAZL of the scanning lines SCNL101 to SCNL10m and the auto zero lines AZL101 to AZL10m, the jump voltage and the switch resistance are optimized to prevent unevenness in the brightness of the display image, thereby achieving high quality. It is possible to display a simple image.

  Next, the operation of the pixel circuit 101D will be described with reference to timing charts shown in FIGS. 22A to 22F, taking Pixel (M, N) in FIG. 21 as an example.

Step ST21 :
As shown in FIGS. 22A and 22B, the drive line DRL101 is set to a high level (VDD, Von1), the auto-zero line AZL101 is set to a high level (VDD2, Von2), and the TFTs 132, 133, and 135 are turned on. At this time, the gate potential Vg131 of the TFT 131 becomes a precharge potential Vpc by the TFT 135 as shown in FIG. When Vpc is set to a sufficiently high potential, the TFT 131 becomes conductive, and a current flows through the TFT 131 and the light emitting element (OLED) 136.

Step ST22 :
As shown in FIG. 22A, the drive line DRL101 is set to a low level (VSS), and the TFT 132 is turned off. Since the current flowing through the TFT 131 is cut off, the source potential of the TFT 131 rises, but when the potential rises to (Vpc−Vth), the TFT 131 becomes nonconductive and the potential is stabilized.
At this time, the input side potential VC131 of the capacitor C131 is also (Vpc−Vth) as shown in FIG. 22E because the TFT 133 is in a conductive state. Here, Vth is a threshold value of the TFT 131.

Step ST23 :
As shown in FIG. 22B, the auto zero line AZL101 is set to a low level (VSS), so that the TFT 133 and the TFT 135 are turned off. The potential VC131 of the input side node ND131 of the capacitor C131 is (Vpc−Vth) as shown in FIG. 22E, and the gate potential Vg131 of the TFT 131 is Vpc as shown in FIG. That is, the potential difference between the terminals of the capacitor C131 is Vth.

Step ST24 :
As shown in FIGS. 22C and 22D, the scanning line SCNL101 is set to the high level (VDD2, Von2), the TFT 134 is turned on, and the potential Vdata corresponding to the luminance data is supplied from the signal line SGL101 to the input side node of the capacitor C131. To ND131. Since the potential difference between the terminals of the capacitor C131 is held at Vth, the gate potential Vg131 of the TFT 131 is (Vdata + Vth) as shown in FIG.

Step ST25 :
As shown in FIGS. 22A and 22C, when the scanning line SCNL101 is at a low level and the TFT 134 is turned off, and the driving line DRL101 is at a high level (VDD, Von1) and the TFT 132 is turned on, the TFT 131 and the light emission. A current flows through the element (OLED) 136, and the light emitting element (OLED) 136 starts to emit light.

  In the operations of steps ST21 and ST22, it is necessary to set the value of Vpc so that Vpc_Vth> Vth_el when Vth_el is the threshold value of OLED. The value of is arbitrary.

  When the current Ioled flowing through the light emitting element (OLED) 136 is calculated after the above operation is performed, if the TFT 131 operates in the saturation region, the following is obtained.

(Equation 11)
Ioled = μCoxW / L / 2 (Vgs−Vth) ²
= ΜCoxW / L / 2 (V _CC −Vs−Vth) ²
= ΜCoxW / L / 2 (Vdata + Vth−Vs−Vth) ²
= ΜCoxW / L / 2 (Vdata−Vs) ²
... (11)

Here, μ represents carrier mobility, Cox represents gate capacitance per unit area, W represents gate width, and L represents gate length.
According to the equation (11), the current Ioled flowing through the light emitting element (OLED) 136 is controlled by Vdata applied from the outside regardless of the threshold value Vth of the TFT 131.
In other words, when the pixel circuit 101D in FIG. 21 is used, it is possible to realize a display device that is relatively unaffected by Vth that varies from pixel to pixel and that has relatively high current uniformity and thus luminance uniformity. The same applies to the case where the TFT 131 operates in the linear region.

  According to the fifth embodiment, the same effects as those of the first and third embodiments described above, that is, the light emission of each pixel stably and accurately regardless of variations in threshold values of active elements inside the pixel. Even if a current having a desired value can be supplied to the element and an offset cancel function using a precharge potential line is provided, the reference potential can be stably maintained, and a gradient in display image luminance can be prevented. As a result, there is an advantage that a high-quality image can be displayed.

  Also in the fifth embodiment, the power supply potential line VCCL is common to the upper and lower sides of the pixel array unit 102 as a display region, that is, both ends of the plurality of power supply potential lines VCCL101 to VCCL10n are connected in common. Therefore, the same potential is achieved. Accordingly, luminance unevenness due to a potential difference in the length direction occurring at the top and bottom of the power supply potential line VCCL in the drawing can be prevented.

<Sixth Embodiment>
FIG. 23 is a circuit diagram showing a sixth embodiment of an active matrix organic EL display (display device) according to the present invention.

The sixth embodiment is different from the above-described fifth embodiment of FIG. 21 in the configuration of the pixel circuit 101E.
That is, in the pixel circuit 101D of FIG. 21, the TFTs 132 to 135 as switching transistors are configured by n-channel transistors. However, in the pixel circuit 101E of the sixth embodiment, the TFTs 132 to 135 as switching transistors are p-channel transistors. It consists of.

  In this case, the drive signal VDRL of the drive lines DRL101 to DRL10m driven by the first scan driver 104E and the second scan driver 105E, and the levels of the drive signals VSCNL and VAZL of the scan lines SCNL101 to SCNL10m and the auto zero lines AZL101 to AZL10m However, the levels of the drive signals VDRL of the drive lines DRL101 to DRL10m and the drive signals VSCNL and VAZL of the scan lines SCNL101 to SCNL10m and the auto-zero lines AZL101 to AZL10m are Von1 < It is set so as to satisfy the relationship of Von2.

In the sixth embodiment, the TFTs 132 to 135 as the first to fourth switching transistors have the same conductivity type (p channel), and the first scan driver 104E as the first drive circuit and the second The second scan driver 105E serving as the drive circuit includes the ON potential Von1 of the drive lines DRL101 to DRL10m as the first control lines, the scan lines SCNL101 to SCNL10m and the auto zero lines AZL101 to AZL10m as the second control lines. The on-potential Von2 is set so that the on-resistance value of the TFT 122 as the first switching transistor is smaller than the on-resistance values of the TFTs 123 to 125 as the second, third, and fourth switching transistors. Set.
That is, as shown in FIGS. 24A, 24B, and 24C, the first scan driver 104E and the second scan driver 105E drive line DRL101 so as to satisfy the relationship Von1 <Von2. Drive signal VDRL for .about.DRL10m and drive signals VSCNL and VAZL for scan lines SCNL101 to SCNL10m and auto-zero lines AZL101 to AZL10m are set.
The drive signal VDRL has an amplitude of (VDD−VSS), and the drive signals VSCNL and VAZL have an amplitude of [VDD−VSS2 (> VSS)].

  The drive signal generation circuits of the first scan driver 104E and the second scan driver 105E have the same configuration as the circuit configurations of FIGS.

  As described above, in the sixth embodiment, the drive signal VDRL of the drive lines DRL101 to DRL10m is set so that the first scan driver 104E and the second scan driver 105E satisfy the relationship of Von1 <Von2. By setting the drive signals VSCNL and VAZL of the scanning lines SCNL101 to SCNL10m and the auto zero lines AZL101 to AZL10m, the jump voltage and the switch resistance are optimized to prevent unevenness in the brightness of the display image, thereby achieving high quality. It is possible to display a simple image.

  The operation in FIG. 23 is performed in the same manner as in the third embodiment except that the active level of the drive signal is opposite to that in the case of FIG. 21, and therefore detailed description thereof is omitted here.

  According to the sixth embodiment, the same effects as those of the fifth embodiment described above can be obtained.

<Seventh embodiment>
FIG. 25 is a circuit diagram showing a seventh embodiment of an active matrix organic EL display (display device) according to the present invention.

The seventh embodiment is different from the above-described third embodiment of FIG. 19 in the configuration of the pixel circuit 101F.
That is, the pixel circuit 101C in FIG. 19 has a precharge function and an auto-zero function, whereas the pixel circuit 101F according to the seventh embodiment has a TFT 124 as a first switching transistor, 2 includes a TFT 122 as a switching transistor and a capacitor C122 connected between the gate of the TFT 121 and the power supply potential line VCCL.

  In this case, the levels of the drive signal VDRL of the drive lines DRL101 to DRL10m driven by the first scan driver 104F and the second scan driver 105F and the level of the drive signal VSCNL of the scan lines SCNL101 to SCNL10m are the same as in the fourth embodiment. The drive signal VDRL of the drive lines DRL101 to DRL10m and the levels of the drive signals VSCNL and VAZL of the scan lines SCNL101 to SCNL10m are set so as to satisfy the relationship of Von1 <Von2.

In the seventh embodiment, the TFT 123 and the TFT 122 as the first and second switching transistors have the same conductivity type (p channel), and the first scan driver 104F as the first driving circuit and the second switching transistor The second scan driver 105F serving as the drive circuit of the second drive driver includes the ON potential Von1 of the drive lines DRL101 to DRL10m as the first control line and the ON potential Von2 of the scan lines SCNL101 to SCNL10m as the second control line. The on-resistance value of the TFT 122 as the second switching transistor is set to be smaller than the on-resistance value of the TFT 124 as the first switching transistor.
That is, as shown in FIGS. 13A and 13B, the first scan driver 104F and the second scan driver 105F drive the drive lines DRL101 to DRL10m so as to satisfy the relationship Von1 <Von2. The signal VDRL and the drive signal VSCNL for the scanning lines SCNL101 to SCNL10m are set.
The drive signal VDRL has an amplitude of (VDD−VSS), and the drive signals VSCNL and VAZL have an amplitude of [VDD−VSS2 (> VSS)].

  The drive signal generation circuits of the first scan driver 104F and the second scan driver 105F have the same configuration as the circuit configurations of FIGS. 14, 15, and 16.

  As described above, in the seventh embodiment, the drive signal VDRL of the drive lines DRL101 to DRL10m is set so that the first scan driver 104F and the second scan driver 105F satisfy the relationship of Von1 <Von2. By setting the drive signal VSCNL of the scanning lines SCNL101 to SCNL10m, the jumping voltage and the switch resistance are optimized to prevent unevenness in the brightness of the display image, thereby realizing a high-quality image display. is doing.

  The operation in FIG. 25 is a simple operation in which the active level of the drive signal is opposite to that in FIG. 17 and there is no precharge and auto-zero operation.

  According to the seventh embodiment, there is an advantage that a current having a desired value can be supplied to the light emitting element of each pixel stably and accurately, and that the brightness of the display image can be prevented from being gradient.

It is a block diagram showing a general active matrix type organic EL display (display device). It is a circuit diagram which shows the 1st structural example of the conventional pixel circuit. It is a circuit diagram which shows the 2nd structural example of the conventional pixel circuit. 4 is a timing chart for explaining a method of driving the circuit of FIG. 3. It is a figure which shows the example of a timing of offset cancellation. 1 is a circuit diagram showing a first embodiment of an active matrix organic EL display (display device) according to the present invention. It is a figure which shows the wiring arrangement | positioning regarding the power source line of the active matrix type organic EL display which concerns on 1st Embodiment. In the first embodiment, it is a diagram for explaining the setting condition of the drive signal level of the drive line and the drive signal level of the scanning line and auto-zero line. FIG. 3 is a circuit diagram illustrating a configuration example of a drive signal generation circuit in a first scan driver serving as a first drive circuit in the first embodiment. FIG. 3 is a circuit diagram illustrating a configuration example of a drive signal generation circuit in a second scan driver as a second drive circuit in the first embodiment. FIG. 3 is a circuit diagram illustrating a configuration example of a circuit for generating a voltage VDD2 in a second scan driver as a second drive circuit in the first embodiment. It is a circuit diagram which shows 2nd Embodiment of the active matrix type organic electroluminescent display (display apparatus) based on this invention. In the second embodiment, it is a diagram for explaining the setting condition of the drive signal level of the drive line and the drive signal level of the scanning line and auto-zero line. FIG. 10 is a circuit diagram illustrating a configuration example of a drive signal generation circuit in a first scan driver as a first drive circuit in the second embodiment. FIG. 10 is a circuit diagram illustrating a configuration example of a drive signal generation circuit in a second scan driver as a second drive circuit in the second embodiment. FIG. 10 is a circuit diagram illustrating a configuration example of a generation circuit of a voltage VSS2 in a second scan driver as a second drive circuit in the second embodiment. It is a circuit diagram which shows 3rd Embodiment of the active matrix type organic electroluminescent display (display apparatus) which concerns on this invention. 18 is a timing chart for explaining the level and operation of a drive signal of the pixel circuit of FIG. It is a circuit diagram which shows 4th Embodiment of the active matrix type organic electroluminescent display (display apparatus) based on this invention. FIG. 20 is a timing chart for explaining the level and operation of a drive signal of the pixel circuit of FIG. 19. FIG. FIG. 6 is a circuit diagram showing a fifth embodiment of an active matrix organic EL display (display device) according to the present invention. FIG. 22 is a timing chart for explaining the level and operation of a drive signal of the pixel circuit of FIG. 21. It is a circuit diagram which shows 6th Embodiment of the active matrix type organic electroluminescent display (display apparatus) based on this invention. 24 is a timing chart for explaining the level and operation of a drive signal of the pixel circuit of FIG. It is a circuit diagram which shows 7th Embodiment of the active matrix type organic electroluminescent display (display apparatus) based on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100,100A-100F ... Active matrix type organic EL display (display device), 101, 101A-101F ... Pixel circuit, 102, 102A-102F ... Pixel array part, 103 ... Data driver (DDRV), 104, 104A-104F ... Scan driver (SDRV1, first drive circuit), 105, 105A to 105F... Scan driver (SDRV2, second drive circuit), 111, 121, 131, 141... TFT as drive transistor, 112 to 115, 122 to 125, 132 to 135 ... TFT as a switch, C111, C112, C121, C122, C131, C132 ... Capacitor, ND111 to ND113, ND121 to ND123, ND131 to ND133 ... Node, VCCL ... Power supply potential line, VP L ... the pre-charge potential line

Claims (20)

A pixel circuit that drives an electro-optic element whose luminance changes according to a flowing current,
A signal line to which a signal corresponding to at least luminance information is supplied;
A drive transistor for controlling the current flowing through the current supply line in accordance with the potential of the control terminal;
At least first and second control lines;
At least first and second switching transistors;
First and second reference potentials,
The electro-optic element, the drive transistor, and at least one first switching transistor are connected in series as a current path of the current flowing through the electro-optic element between the first reference potential and the second reference potential.
A control terminal of the first switch transistor is connected to the first control line;
The second switch transistor is disposed outside a current path of a current flowing through the electro-optical element, a control terminal of the second switching transistor is connected to the second control line,
The first switching transistor and the second switching transistor are transistors of the same conductivity type, and the ON potential of the first control line and the ON potential of the second control line are the first switching transistor. A pixel circuit in which a resistance value when ON is smaller than a resistance value when ON of the second switching transistor is set. The pixel circuit according to claim 1, wherein the first switching transistor and the second switching transistor are n-channel transistors, and an ON potential of the first control line is set higher than the second ON potential. 2. The pixel circuit according to claim 1, wherein the first switching transistor and the second switching transistor are p-channel transistors, and an ON potential of the first control line is set lower than the second ON potential. The electro-optical element is an organic EL element,
The pixel circuit according to claim 1, wherein the driving transistor and the first and second switching transistors are thin film transistors. A pixel circuit that drives an electro-optic element whose luminance changes according to a flowing current,
A signal line to which a signal corresponding to at least luminance information is supplied;
At least first and second control lines;
First and second reference potentials;
A predetermined precharge potential;
A field effect transistor;
Nodes,
A first switching transistor connected between the source of the field effect transistor and a first reference potential and connected to the first control line and controlled in conduction by a control terminal;
A second switching transistor connected between the source of the field effect transistor and the node;
A third switching transistor connected between the gate of the field effect transistor and the precharge potential;
A fourth switching transistor connected between the signal line and the node;
A coupling capacitor connected between the node and the gate of the field effect transistor;
The electro-optical element is connected between a drain of the transistor and a second reference potential, and a control terminal of at least one switching transistor of the second, third, and fourth switching transistors is the second control line. Connected to the
The first switching transistor and at least one of the second, third, and fourth switching transistors whose control terminals are connected to the second control line are transistors of the same conductivity type, The on potential of the first control line and the on potential of the second control line are such that the resistance value when the first switching transistor is on is at least one of the second, third, and fourth switching transistors. A pixel circuit that is set to a value that is smaller than the resistance value when the switching transistor is on. At least one of the first switching transistor and the second, third, and fourth switching transistors is an n-channel transistor, and the ON potential of the first control line is higher than the second ON potential. The pixel circuit according to claim 5, wherein the pixel circuit is set high. At least one of the first switching transistor and the second, third, and fourth switching transistors is a p-channel transistor, and the ON potential of the first control line is higher than the second ON potential. The pixel circuit according to claim 5, wherein the pixel circuit is set low. The electro-optical element is an organic EL element,
The pixel circuit according to claim 5, wherein the drive transistor, the first, second, third, and fourth switching transistors are thin film transistors. A pixel circuit that drives an electro-optic element whose luminance changes according to a flowing current,
A signal line to which a signal corresponding to at least luminance information is supplied;
At least first and second control lines;
First and second reference potentials;
A predetermined precharge potential;
A field effect transistor;
Nodes,
A first switching transistor connected between a source of the field effect transistor and the electro-optic element, and connected to the first control line and controlled to be connected to the control terminal;
A second switching transistor connected between the source of the field effect transistor and the node;
A third switching transistor connected between the gate of the field effect transistor and the precharge potential;
A fourth switching transistor connected between the signal line and the node;
A coupling capacitor connected between the node and the gate of the field effect transistor;
The drain of the field effect transistor is connected to a first reference potential, the electro-optic element is connected between the first switching transistor and a second reference potential,
The control terminal of at least one switching transistor of the second, third, and fourth switching transistors is connected to the second control line, and conduction control is performed.
The first switching transistor and at least one of the second, third, and fourth switching transistors whose control terminals are connected to the second control line are transistors of the same conductivity type, The on potential of the first control line and the on potential of the second control line are such that the resistance value when the first switching transistor is on is at least one of the second, third, and fourth switching transistors. A pixel circuit that is set to a value that is smaller than the resistance value when the switching transistor is on. At least one of the first switching transistor and the second, third, and fourth switching transistors is an n-channel transistor, and the ON potential of the first control line is higher than the second ON potential. The pixel circuit according to claim 9, wherein the pixel circuit is set high. At least one of the first switching transistor and the second, third, and fourth switching transistors is a p-channel transistor, and the ON potential of the first control line is higher than the second ON potential. The pixel circuit according to claim 9, wherein the pixel circuit is set low. The electro-optical element is an organic EL element,
The pixel circuit according to claim 9, wherein the driving transistor, the first, second, third, and fourth switching transistors are thin film transistors. A pixel circuit that drives an electro-optic element whose luminance changes according to a flowing current,
A signal line to which a signal corresponding to at least luminance information is supplied;
At least first and second control lines;
First and second reference potentials;
A predetermined precharge potential;
A field effect transistor;
Nodes,
A first switch connected between the drain of the field-effect transistor and the electro-optic element, the control terminal of which is connected to the first control line and conduction controlled;
A second switch connected between the drain and gate of the field effect transistor;
A third switch connected between the node and the precharge potential;
A fourth switch connected between the signal line and the node;
A coupling capacitor connected between the node and the gate of the field effect transistor;
A source of the field effect transistor is connected to a first reference potential; the electro-optic element is connected between the first switch and a second reference potential;
The control terminal of at least one switching transistor of the second, third, and fourth switching transistors is connected to the second control line, and conduction control is performed.
The first switching transistor and at least one of the second, third, and fourth switching transistors whose control terminals are connected to the second control line are transistors of the same conductivity type, The on potential of the first control line and the on potential of the second control line are such that the resistance value when the first switching transistor is on is at least one of the second, third, and fourth switching transistors. A pixel circuit that is set to a value that is smaller than the resistance value when the switching transistor is on. At least one of the first switching transistor and the second, third, and fourth switching transistors is an n-channel transistor, and the ON potential of the first control line is higher than the second ON potential. The pixel circuit according to claim 13, wherein the pixel circuit is set high. At least one of the first switching transistor and the second, third, and fourth switching transistors is a p-channel transistor, and the ON potential of the first control line is higher than the second ON potential. The pixel circuit according to claim 13, wherein the pixel circuit is set low. The electro-optical element is an organic EL element,
The pixel circuit according to claim 13, wherein the driving transistor, the first, second, third, and fourth switching transistors are thin film transistors. A plurality of pixel circuits arranged in a matrix;
A signal line that is wired for each column with respect to the matrix arrangement of the pixel circuit, and that is supplied with a data signal corresponding to at least luminance information;
At least a first control line and a second control line wired for each row with respect to the matrix arrangement of the pixel circuit;
A first drive circuit for setting a potential of the first control line;
A second drive circuit for setting the potential of the second control line,
Each pixel circuit is
A drive transistor for controlling the current flowing through the current supply line in accordance with the potential of the control terminal;
At least first and second switching transistors;
First and second reference potentials,
The electro-optic element, the drive transistor, and at least one first switching transistor are connected in series as a current path of the current flowing through the electro-optic element between the first reference potential and the second reference potential.
A control terminal of the first switch transistor is connected to the first control line;
The second switch transistor is disposed outside a current path of a current flowing through the electro-optical element, a control terminal of the second switching transistor is connected to the second control line,
The first switching transistor and the second switching transistor are transistors of the same conductivity type,
The first and second drive circuits have an ON potential of the first control line and an ON potential of the second control line, and a resistance value when the first switching transistor is ON is the second potential. A display device that is set to a value that is smaller than the resistance value when the switching transistor is on. A plurality of pixel circuits arranged in a matrix;
A signal line that is wired for each column with respect to the matrix arrangement of the pixel circuit, and that is supplied with a data signal corresponding to at least luminance information;
At least a first control line and a second control line wired for each row with respect to the matrix arrangement of the pixel circuit;
A first drive circuit for setting a potential of the first control line;
A second drive circuit for setting the potential of the second control line,
Each pixel circuit is
First and second reference potentials;
A predetermined precharge potential;
A field effect transistor;
Nodes,
A first switching transistor connected between the source of the field effect transistor and a first reference potential and connected to the first control line and controlled in conduction by a control terminal;
A second switching transistor connected between the source of the field effect transistor and the node;
A third switching transistor connected between the gate of the field effect transistor and the precharge potential;
A fourth switching transistor connected between the signal line and the node;
A coupling capacitor connected between the node and the gate of the field effect transistor;
The electro-optic element is connected between the drain of the transistor and a second reference potential;
The control terminal of at least one switching transistor of the second, third, and fourth switching transistors is connected to the second control line, and conduction control is performed.
The first switching transistor and at least one of the second, third, and fourth switching transistors having a control terminal connected to the second control line are transistors of the same conductivity type,
The first and second drive circuits have an ON potential of the first control line and an ON potential of the second control line, and a resistance value when the first switching transistor is ON is the second, A display device that is set to a value that is smaller than a resistance value when at least one of the third and fourth switching transistors is on. A plurality of pixel circuits arranged in a matrix;
A signal line that is wired for each column with respect to the matrix arrangement of the pixel circuit, and that is supplied with a data signal corresponding to at least luminance information;
At least a first control line and a second control line wired for each row with respect to the matrix arrangement of the pixel circuit;
A first drive circuit for setting a potential of the first control line;
A second drive circuit for setting the potential of the second control line,
Each pixel circuit is
First and second reference potentials;
A predetermined precharge potential;
A field effect transistor;
Nodes,
A first switching transistor connected between a source of the field effect transistor and the electro-optic element, and connected to the first control line and controlled to be connected to the control terminal;
A second switching transistor connected between the source of the field effect transistor and the node;
A third switching transistor connected between the gate of the field effect transistor and the precharge potential;
A fourth switching transistor connected between the signal line and the node;
A coupling capacitor connected between the node and the gate of the field effect transistor;
The electro-optic element is connected between the first switching transistor and a second reference potential;
The control terminal of at least one switching transistor of the second, third, and fourth switching transistors is connected to the second control line, and conduction control is performed.
The first switching transistor and at least one of the second, third, and fourth switching transistors having a control terminal connected to the second control line are transistors of the same conductivity type,
The first and second drive circuits have an ON potential of the first control line and an ON potential of the second control line, and a resistance value when the first switching transistor is ON is the second, A display device that is set to a value that is smaller than a resistance value when at least one of the third and fourth switching transistors is on. A plurality of pixel circuits arranged in a matrix;
A signal line that is wired for each column with respect to the matrix arrangement of the pixel circuit, and that is supplied with a data signal corresponding to at least luminance information;
At least a first control line and a second control line wired for each row with respect to the matrix arrangement of the pixel circuit;
A first drive circuit for setting a potential of the first control line;
A second drive circuit for setting the potential of the second control line,
Each pixel circuit is
First and second reference potentials;
A predetermined precharge potential;
A field effect transistor;
Nodes,
A first switch connected between the drain of the field-effect transistor and the electro-optic element, the control terminal of which is connected to the first control line and conduction controlled;
A second switch connected between the drain and gate of the field effect transistor;
A third switch connected between the node and the precharge potential;
A fourth switch connected between the signal line and the node;
A coupling capacitor connected between the node and the gate of the field effect transistor;
A source of the field effect transistor is connected to a first reference potential; the electro-optic element is connected between the first switch and a second reference potential;
The control terminal of at least one switching transistor of the second, third, and fourth switching transistors is connected to the second control line, and conduction control is performed.
The first switching transistor and at least one of the second, third, and fourth switching transistors having a control terminal connected to the second control line are transistors of the same conductivity type,
The first and second drive circuits have an ON potential of the first control line and an ON potential of the second control line, and a resistance value when the first switching transistor is ON is the second, A display device that is set to a value that is smaller than a resistance value when at least one of the third and fourth switching transistors is on.

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