JP2006060606A - Inverting amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inverting amplifier capable of performing stable amplification action with low voltage. <P>SOLUTION: A bias power supply 5 as a gate bias generating means is connected between the source Sp and the gate Gp of a P channel MOS transistor 1 of a CMOS type circuit through a bias resistor Rb, and the bias power supply 5 at this time is a direct current voltage source of (VTP+αp(≥βp))≤power supply voltage VDD. In such a case, VTP is threshold voltage of the P channel MOS transistor 1, αp is operating voltage of the P channel MOS transistor 1, and βp is drain voltage needed to saturate drain current Idp when bias voltage (VTP+αp) is applied between the gate Gp and the source Sp of the P channel MOS transistor 1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an inverting amplifier, and is particularly useful when applied to an AC inverting amplifier of a CMOS circuit.

  FIG. 7 is a circuit diagram showing an inverting amplifier of a CMOS type circuit according to the prior art. As shown in the figure, a P-channel MOS transistor 1 and an N-channel MOS transistor 2 are connected in series, an input terminal 3 is connected to both gates Gp and Gn, and an output is provided between both drains Dp and Dn. Terminals 4 are connected to each other. A feedback resistor Rf is connected between the input terminal 3 and the output terminal 4 to constitute a self-bias circuit.

  FIG. 8 is a characteristic diagram showing the relationship between the input voltage of the inverting amplifier shown in FIG. 7 and the drain currents Idp and Idn of the P-channel MOS transistor 1 and the N-channel MOS transistor 2. In the figure, VTP, αp, and Idp (solid lines) indicate the threshold voltage of the P-channel MOS transistor 1, the voltage difference between the gate-source voltage of the P-channel MOS transistor 1 and the VTP at the operating point of the inverting amplifier, and the drain current. Respectively. In addition, VTN, αn, and Idn (one-dot chain line) indicate the threshold voltage of the N channel MOS transistor 2, the gate-source voltage of the N channel MOS transistor 2 at the operating point of the inverting amplifier, the voltage difference between the VTN, and the drain current. Each is shown.

The inverting amplifier amplifies a signal input to the input terminal 3 with an intersection of the drain currents Idp and Idn as an operating point, and takes out the signal via the output terminal 4. When the minimum values of αp and αn necessary for the inverting amplifier to perform a desired amplification operation are each 0.2 V, the minimum voltage of the power supply voltage VDD, that is, the minimum operating voltage VDDmin is:
VDD = VTN + αn + VTP + αp
Than,
VDDmin = VTN + 0.2 + VTP + 0.2 (V)
It is.

  The following patent documents can be listed as known techniques related to the present invention.

JP-A-5-145341

  In recent years, for example, in an inverting amplifier applied to a crystal oscillator, there has been a demand for reducing the minimum operating voltage without impairing the amplification characteristic. Specifically, the appearance of an inverting amplifier having a minimum operating voltage VDDmin of 1.0 V or less is expected.

  In the inverting amplifier of the above prior art, in order to reduce the minimum operating voltage VDDmin, it is necessary to reduce both the threshold voltage VTP of the P-channel MOS transistor 1 and the threshold voltage VTN of the N-channel MOS transistor 2.

  In a commonly used CMOS transistor using n-type polysilicon as a gate electrode material, when the threshold voltage VTP of the P-channel MOS transistor becomes 0.4 V or less, the off-leakage of the P-channel MOS transistor increases rapidly. In general, in an IC that requires low-voltage operation, the demand for current consumption is severe, and the use of elements with a large off-leakage current is avoided. On the other hand, the threshold voltage VTN of the N-channel MOS transistor can be reduced to about 0.35V.

Therefore, assuming that the P-channel MOS transistor 1 having a threshold voltage VTP of 0.4 V can be used, the threshold voltage VTN of the N-channel MOS transistor 2 is set to 0.35 V, and αp = αn = 0.2 V, the lowest value of the inverting amplifier. The operating voltage VDDmin is
VDDmin = 0.4 + 0.2 + 0.35 + 0.2 = 1.15 (V)
Even in this case, the minimum operating voltage VDDmin cannot be reduced to 1.0 V or less.

  The threshold voltage VTP is reduced to about 0.35 when the dual gate technology is employed in which the gate of the P-channel MOS transistor of the CMOS transistor is formed of P-type polysilicon and the gate of the N-channel MOS transistor is formed of N-type polysilicon. Can do. However, even in this case, it is still difficult to set the minimum operating voltage VDDmin of the inverting amplifier to 1.0 V or less.

  On the other hand, in order to realize the minimum operating voltage VDDmin of 1.0 V or less, the values of αp and αn may be reduced to about 0.1 V. In this case, the inversion is performed unless the size of the CMOS transistor is considerably increased. Not only is it difficult to secure the current drive capability necessary for the amplifier, but there is a problem that the manufacturing margin is small and stable production cannot be expected in consideration of variations in the IC process.

  The present invention has been made in view of the above problems of the prior art, and an object thereof is to provide an inverting amplifier having a stable amplification characteristic at a low voltage without lowering the threshold voltage of a MOS transistor constituting the inverting amplifier to the limit. .

  The configuration of the present invention that achieves the above object is characterized by the following points.

1) In an inverting amplifier of a CMOS circuit having a P-channel MOS transistor and an N-channel MOS transistor connected in series,
The gates of the N-channel MOS transistor and the P-channel MOS transistor are connected via a capacitor so that a bias voltage can be independently applied to the gate of the N-channel MOS transistor and the gate of the P-channel MOS transistor. Alternatively, in either MOS transistor of the N channel MOS transistor, the gate and drain of the MOS transistor are connected via a feedback resistor, and either the gate of the P channel MOS transistor or the N channel MOS transistor or both of them are connected. The gate was used as an input terminal.
2) In the inverting amplifier described in 1) above,
A bias voltage is applied to the gate of the P-channel MOS transistor via a bias resistor, and the gate and drain of the N-channel MOS transistor are connected via a feedback resistor.
3) In the inverting amplifier described in 2) above,
A voltage higher by about 0.1V to 0.3V than the threshold voltage VTP of the P channel MOS transistor is applied as a bias voltage of the gate of the P channel MOS transistor.
4) In the inverting amplifier described in 3) above,
The bias voltage is made of a combination of a P-channel MOS transistor and a constant current source.
5) In the inverting amplifier described in 2) above,
An inverting amplifier using a power supply voltage VDD of an inverting amplifier as a bias voltage of a gate of a P-channel MOS transistor.
6) In the inverting amplifier described in 1) above,
A bias voltage is applied to the gate of the N-channel MOS transistor via a first resistor, and the gate and drain of the P-channel MOS transistor are connected via a second resistor.
7) In the inverting amplifier described in 6) above,
As the gate bias voltage of the N channel MOS transistor, a voltage about 0.1V to 0.3V higher than the threshold voltage VTN of the N channel MOS transistor is used.
8) In the inverting amplifier described in 7) above,
The bias voltage is made of a combination of an N-channel MOS transistor and a constant current source.
9) In the inverting amplifier described in 6) above,
The power supply voltage VDD of the inverting amplifier is used as the gate bias voltage of the N channel MOS transistor.
10) In the inverting amplifier described in 2) to 9) above,
The power supply voltage VDD of the inverting amplifier is obtained from a constant voltage source.
11) In the inverting amplifier described in 4) to 9) above,
A part or all of the bias resistor and the feedback resistor is replaced with a MOS transistor having a source and a drain as terminals.

  According to the present invention as described above, an inverting amplifier operating at a low voltage can be easily realized without lowering the threshold voltage of the MOS transistor constituting the CMOS inverting amplifier. Further, by reducing these threshold voltages somewhat, it is possible to produce a crystal oscillator that operates at a voltage of 1 V or less at an oscillation frequency of several tens of MHz and that has a low current consumption. In addition, when the effect of reducing the operating voltage is utilized, it is possible to easily reduce the excitation current that is substantially proportional to the power supply voltage of the crystal oscillation circuit in the crystal oscillation circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same number is attached | subjected to the same part in the same part thru | or each embodiment as FIG. 7, and the overlapping description is abbreviate | omitted.

<Embodiment 1>
FIG. 1 is a circuit diagram showing an inverting amplifier according to Embodiment 1 of the present invention. As shown in the figure, in the inverting amplifier according to this embodiment, a bias power source 5 as a gate bias generating means is connected between a gate Gp of a P-channel MOS transistor 1 and a power source VDD via a bias resistor Rb. The bias power source 5 is a DC voltage source having a voltage that is about 0.1 V to 0.3 V higher than the threshold voltage VTP of the P-channel MOS transistor 1 and lower than the power source voltage VDD. Hereinafter, this bias voltage is expressed as VTP + αp.

  In the inverting amplifier, a capacitor Cg is inserted between the gate Gp and the gate Gn so that different bias voltages can be applied to the respective gates. Further, the configuration of the N channel MOS transistor 2 is the same as that of the inverting amplifier according to the prior art shown in FIG. 7, and the gate and drain of the N channel MOS transistor 2 are connected via a feedback resistor Rf.

The input signal may be supplied to both the input terminals 3-1 and 3-2, but may be supplied to either one. When signals are input to both input terminals, the capacitor Cg can be omitted. When a signal is input to one of the input terminals, the value of the capacitor Cg, bias resistor Rb, and feedback resistor Rf must satisfy the following conditions in order to transmit the input signal to the other input terminal without being attenuated. Must be set to
1) The value of the bias resistor Rb is set to a value sufficiently larger than 1 / ωCg (Cg is a capacitor value).
2) The value of the feedback resistor Rf should be sufficiently larger than A / ωCg. Here, A is the gain of the inverting amplifier.

  FIG. 2 is a characteristic diagram showing the relationship between the input voltage of the inverting amplifier according to the present embodiment and the drain currents Idp and Idn of the PMOS transistor 1 and the NMOS transistor 2. As shown in the figure, the PMOS transistor 1 can flow a predetermined drain current when a bias voltage of VTP + αp is applied to the gate Gp. At this time, if the power supply voltage VDD is larger than the threshold voltage of the NMOS transistor 2, the current from the P-channel MOS transistor 1 flows through the N-channel MOS transistor 2 having a self-bias configuration.

In the conventional inverting amplifier, both the P-channel MOS transistor 1 and the N-channel MOS transistor 2 operate in the saturation region at the DC operating point. Therefore, both the P-channel MOS transistor 1 and the N-channel MOS transistor 2 operate in the saturation region in order to have the same level of amplification factor as the conventional inverting amplifier even in the inverting amplifier according to this embodiment. Need to be. The N-channel MOS transistor 2 in which the gate-source voltage and the drain-source voltage are the same and the threshold voltage VTN is positive always operates in the saturation region. On the other hand, in order for the P-channel MOS transistor 1 to operate in the saturation region, as shown in FIG. 3, the drain-source voltage VDSP of the P-channel MOS transistor 1 must be larger than βp. Here, βp is a drain voltage necessary for saturating the drain current Idp when a bias voltage (VTP + αp) is applied between the gate and source of the P-channel MOS transistor 1, and generally a relationship of βp ≦ αp is established. Yes. When the drain-source voltage of the N-channel MOS transistor 2 is expressed as (VTN + αn) when the saturation drain current Idps flows through the P-channel MOS transistor 1, the drain-source voltage VDSP of the P-channel MOS transistor 1 VDSP = VDD− (VTN + αn)
The power supply voltage VDD that allows the inverting amplifier to perform sufficient amplification operation is
From VDSP ≧ βp VDD ≧ VTN + αn + βp
It becomes.

  The minimum operating voltage VDDmin is defined by the larger value of both (VTP + αp) and (VTN + αn + βp). That is, the minimum operating voltage VDDmin = MAX (VTP + αp, VTN + αn + βp). In a normal CMOS, VTP and VTN are substantially equal, so that the minimum operating voltage VDDmin = VTN + αn + βp. Here, with the relationship of βp ≦ αp in mind, when comparing the minimum operating voltage of the inverting amplifier of this embodiment and the minimum operating voltage of the conventional inverting amplifier, the minimum operating voltage in this embodiment is at least that of the P-channel MOS transistor 1. It can be seen that the voltage corresponding to the threshold voltage VTP can be reduced.

Here, a specific example of the minimum operating voltage in the inverting amplifier according to this embodiment will be shown. When VTP = 0.5V, VTN = 0.5V, αp = αn = βp = 0.2V, the minimum operating voltage VDDmin is
VDDmin = MAX (0.5 + 0.2, 0.5 + 0.2 + 0.2)
= 0.9 (V)
Thus, the minimum operating voltage VDDmin of 1 V or less can be realized without using limit values for VTP and VTN.

<Embodiment 2>
FIG. 4 is a circuit diagram showing an inverting amplifier according to Embodiment 2 of the present invention. As shown in the figure, in the inverting amplifier according to the present embodiment, the power supply 5 for the gate bias in the first embodiment is omitted, and the power supply voltage VDD of the inverting amplifier is used as the bias voltage.

  Here, when βp = αp (= VDD−VTP), in order for both the P-channel MOS transistor 1 and the N-channel MOS transistor 2 to operate in the saturation region at the operating point of the inverting amplifier, VDD ≧ VTN + αn + VDD−VTP, That is, it is only necessary that the threshold voltages VTP and VTN can be set so that VTP ≧ VTN + αn. Such threshold voltages VTP and VTN can be easily set.

  Therefore, in the inverting amplifier according to the present embodiment, as long as the condition of VTP ≧ VTN + αn is satisfied, the same low voltage operation as that of the first embodiment can be realized even if the bias power supply 5 is omitted.

<Embodiment 3>
FIG. 5 is a circuit diagram showing an inverting amplifier according to Embodiment 3 of the present invention. As shown in the figure, in the inverting amplifier according to this embodiment, the gate bias generating means of the P-channel MOS transistor 1 is formed by a constant current source 6 and a P-channel MOS transistor 7.

  In the gate bias generating means, a voltage (VTP + αp) obtained by adding a certain voltage αp to the threshold voltage VTP of the P-channel MOS transistor 7 can be produced, and the voltage has a characteristic that does not depend on the power supply voltage. A circuit equivalent to the first embodiment is realized.

  In the inverting amplifiers according to the first to third embodiments, the fluctuation of the power supply voltage VDD becomes apparent as the fluctuation of the operating point, and when the operating point fluctuates, for example, when used as an amplifier of a crystal oscillator, the fluctuation of the oscillation frequency Will occur. Therefore, it is desirable to use a constant voltage power supply as a power supply for supplying the power supply voltage VDD.

  The constant current source 6 can be realized by an NMOS transistor or the like in which a bias voltage is applied to the gate, but can be replaced by a resistor.

  FIG. 6 is a circuit diagram showing a crystal oscillator to which the inverting amplifier shown in FIG. 5 is applied. As shown in the figure, the crystal oscillator 8 vibrates the crystal resonator 8a with the oscillation signal amplified by the inverting amplifier, and takes out a signal having a predetermined oscillation frequency from the output terminal 4. At this time, the low voltage operation of the inverting amplifier is realized, and as a result, the excitation current of the crystal oscillator 8 can be reduced.

  The present invention can be used in an industrial field in which a power source of an electronic device such as a crystal oscillator is manufactured and sold.

1 is a circuit diagram illustrating an inverting amplifier according to a first embodiment of the present invention. FIG. 2 is a characteristic diagram showing a relationship between an input voltage of the inverting amplifier shown in FIG. 1 and drain currents Idp and Idn of the PMOS transistor and the NMOS transistor. FIG. 2 is a characteristic diagram showing a relationship between an output voltage Vout of the inverting amplifier shown in FIG. 1 and drain currents Idp and Idn of the PMOS transistor and NMOS transistor. It is a circuit diagram which shows the inverting amplifier which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the inverting amplifier which concerns on Embodiment 3 of this invention. FIG. 6 is a circuit diagram showing a state where the inverting amplifier shown in FIG. 5 is applied to a crystal oscillator. It is a circuit which shows the inverting amplifier of the CMOS type circuit which concerns on a prior art. FIG. 8 is a characteristic diagram illustrating a relationship between an input voltage of the inverting amplifier illustrated in FIG. 7 and drain currents Idp and Idn of the PMOS transistor and the NMOS transistor.

Explanation of symbols

1, 7 P-channel MOS transistor 2 N-channel MOS transistor 3 Input terminal 4 Output terminal 5 Bias power supply 6 Constant current source 8 Crystal oscillator 8a Crystal oscillator Rf Feedback resistor Rb Bias resistor VDD Power supply voltage VDDmin Minimum operating voltage

Claims (12)

In an inverting amplifier of a CMOS circuit having a P-channel MOS transistor and an N-channel MOS transistor connected in series,
The gate of the N-channel MOS transistor and the P-channel MOS transistor are connected via a capacitor, and the gate and drain of either the P-channel MOS transistor or the N-channel MOS transistor are connected via a feedback resistor. While applying a bias voltage to the gate of the other MOS transistor,
An inverting amplifier characterized in that one or both of the P channel MOS transistor and the N channel MOS transistor are used as input terminals. The inverting amplifier according to claim 1.
An inverting amplifier, wherein a bias voltage is applied to the gate of the P-channel MOS transistor via a bias resistor, and the gate and drain of the N-channel MOS transistor are connected via a feedback resistor. An inverting amplifier according to claim 2,
An inverting amplifier characterized by applying a voltage about 0.1 V to 0.3 V higher than a threshold voltage VTP of the P channel MOS transistor as a bias voltage of the gate of the P channel MOS transistor. The inverting amplifier according to claim 3,
An inverting amplifier, wherein the bias voltage is made of a combination of a P-channel MOS transistor and a constant current source. An inverting amplifier according to claim 2,
An inverting amplifier using a power supply voltage VDD of an inverting amplifier as a bias voltage of a gate of a P-channel MOS transistor. The inverting amplifier according to claim 1.
An inverting amplifier, wherein a bias voltage is applied to a gate of the N-channel MOS transistor via a bias resistor, and the gate and drain of the P-channel MOS transistor are connected via a feedback resistor. The inverting amplifier according to claim 6,
An inverting amplifier characterized in that a voltage higher by about 0.1V to 0.3V than the threshold voltage VTN of the N channel MOS transistor is used as the gate bias voltage of the N channel MOS transistor. The inverting amplifier according to claim 7,
An inverting amplifier, wherein the bias voltage is made of a combination of an N-channel MOS transistor and a constant current source. The inverting amplifier according to claim 6,
An inverting amplifier using a power supply voltage VDD of an inverting amplifier as a gate bias voltage of an N-channel MOS transistor. In the inverting amplifier according to claim 2 to 9,
An inverting amplifier characterized in that the power supply voltage VDD of the inverting amplifier is obtained from a constant voltage source. In an inverting amplifier according to claim 4 and claim 9,
An inverting amplifier using a resistor instead of a constant current source. The inverting amplifier according to any one of claims 1 to 10,
An inverting amplifier in which a part or all of the bias resistor and the feedback resistor are replaced with a MOS transistor having a source and a drain as terminals.

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