JP2006032930A - Doping device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing device of a semiconductor device having a device for uniformly doping impurity elements by using a large scale substrate where multiple chamfering is realized in mass production. <P>SOLUTION: A cross-section of ion flow is set to be linear or rectangular. The large area substrate is moved to a direction vertical to a longitudinal direction of an ion flow while the large area substrate is kept in a state where it is inclined to ion flow by a prescribed inclination angle θ. An incident angle of an ion beam is controlled by changing the inclination angle θ. Width of the longitudinal direction of ion flow can be made shorter than length of one side of the substrate by making the large area substrate in the inclined state with respect to a horizontal face. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a doping apparatus used when manufacturing a semiconductor device having a circuit formed of a thin film transistor (hereinafter referred to as TFT). In particular, the present invention relates to an ion doping apparatus having a preferable configuration for the purpose of processing a large area substrate.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  In manufacturing a semiconductor integrated circuit using a silicon wafer, a method is known in which an impurity formation region is formed by doping an n-type or p-type impurity element into a semiconductor. A doping method that separates the mass and charge ratio of ions is called an ion implantation method, and is widely used in manufacturing semiconductor integrated circuits. Also, a doping method in which a plasma having an impurity element is generated, impurity ions in the plasma are accelerated by a high voltage, and injected into a semiconductor as an ion flow (ion shower) is called an ion doping method or a plasma doping method. It is widely used in the manufacturing process of liquid crystal displays using glass substrates.

  In the manufacture of electronic devices having semiconductor circuits, in order to efficiently perform mass production, a mother glass substrate is used instead of a wafer substrate, and multiple chamfering that cuts out a plurality of devices from a single mother glass substrate is often performed. The size of the mother glass substrate was increased from 300 x 400 mm of the first generation in early 1990 to the fourth generation in 2000 and increased to 680 x 880 mm or 730 x 920 mm. Typically, production technology has progressed so that display panels can be removed.

  In a conventional doping apparatus, a substrate (or wafer) is rotated in order to make the ion implantation distribution uniform. If the substrate is further increased in size in the future, the conventional doping apparatus is considered disadvantageous in mass production in that the mechanism for rotating the large substrate becomes large.

  Further, in the conventional doping apparatus, since the substrate is rotated around the tilt axis, the ion implantation distribution becomes concentric. Further, in the conventional doping apparatus, since the size of the substrate is limited to a size that can be accommodated within the outer periphery of the ion flow, there is a problem that the ion shower is wasted and the efficiency is poor.

  Therefore, the present applicant has shown a linear doping apparatus in Patent Document 1 that moves a substrate without rotating it.

The present applicant also discloses a doping apparatus in which a substrate is relatively moved using laser light in Patent Document 2.
JP-A-10-162770 JP 2001-210605 A

  The present invention provides an apparatus for manufacturing a semiconductor device including an apparatus for uniformly doping an impurity element using a large-area substrate capable of multi-cavity in mass production.

  In the present invention, the cross section of the ion flow is linear or rectangular, and the large area substrate is maintained in a state where the large area substrate is inclined by a predetermined inclination angle θ with respect to the ion flow. It is one of the features that it is moved in the direction perpendicular to. As the large-area substrate, a substrate having a size of 600 mm × 720 mm, 680 mm × 880 mm, 1000 mm × 1200 mm, 1100 mm × 1250 mm, 1150 mm × 1300 mm, or larger is used. In the present invention, the incident angle of the ion beam is adjusted by changing the tilt angle θ. By making the large area substrate inclined with respect to the horizontal plane, the width in the longitudinal direction of the ion flow can be made shorter than the length of one side of the substrate.

One of the configurations of the invention disclosed in this specification is:
A means for generating an ion flow having a linear or rectangular cross section, a means for irradiating the ion flow, and a substrate position for moving the substrate to be processed in one direction while keeping the substrate surface inclined with respect to the perpendicular. And a control means for irradiating the ion flow to the substrate to be processed in a tilted position.

  The doping apparatus is connected to a substrate carry-in chamber and a substrate carry-out chamber, and the substrate carry-in chamber and the substrate carry-out chamber are provided opposite to each other with the doping apparatus interposed therebetween. The substrate stage in the doping chamber preferably has an angle adjustment function and a substrate transfer function. In addition, a means for heating the substrate may be provided in the doping chamber.

One of the configurations of the invention disclosed in this specification is as follows:
A substrate loading chamber, a doping chamber, and a substrate unloading chamber are arranged in series, wherein the doping chamber has a means for generating an ion flow having a linear or rectangular cross section, and a substrate with respect to a vertical line. A substrate position control means for moving the substrate to be processed in one direction while holding the surface in an inclined posture, and the substrate to be processed moves in one direction from the substrate carry-in chamber to the substrate carry-out chamber through the doping chamber The doping apparatus is characterized in that the ion stream is irradiated.

  The substrate loading chamber or the doping apparatus is provided with a substrate transport robot, and has a mechanism for freely switching the posture of the holding unit of the robot between a posture for holding the substrate in a horizontal state and a posture for holding the substrate in an inclined state. It may be allowed.

Further, when the large-area substrate is transported in an inclined state, the occupied floor area (footprint) can be made smaller than the conventional apparatuses shown in Patent Document 1 and Patent Document 2.

  Further, by supporting the large area substrate in an inclined state, distortion due to its own weight can be suppressed. Conventionally, when a large-area substrate is supported in a horizontal state, there is a problem that the central portion of the substrate is bent by its own weight and distortion is increased.

  In the present invention, since the large area substrate is not rotated, an excessive force is not applied and the substrate is not broken.

  Further, when the doping apparatus of the present invention is used, doping is performed from one direction in an oblique direction, and only one side of a mask or a member serving as a mask is introduced and doped. For example, when forming an LDD region of a TFT with a gate electrode as a mask by doping from an oblique direction, an LDD region overlapping with the gate electrode on one side is formed.

  Further, the substrate inclination angle θ is an angle between the normal of the large-area substrate surface and the ion beam. It can also be said that the substrate surface is transported with the substrate surface set to an angle α with respect to the ion beam (angle α = 90 ° −θ formed by the substrate surface and the ion beam irradiation direction).

In addition, when doping is performed obliquely, the tilt angle θ formed by the plane perpendicular to the tilted substrate surface and the direction of ion irradiation is 0 ° <θ <90 ° or −90 ° <θ <0 °. Of the range, 30 ° to 60 ° (or −30 ° to −60 °) is preferable. When doping is performed obliquely with respect to the substrate surface, a simulation was performed to investigate the optimum angle θ formed by the ion irradiation direction and a surface perpendicular to the substrate surface. FIG. 4B and FIG. The simulation results shown in Fig. 5 were derived. Assuming the model diagram shown in FIG. 4A, simulation was performed using software called TRIM (Transport of Ion in Matter). TRIM is software for simulating the ion implantation process by the Monte Carlo method. The numerical values used in the simulation in FIG. 4B are a phosphorus (P) dose of 3 × 10 ¹⁵ / cm ² , an acceleration voltage of 80 keV, and a gate insulating film thickness of 150 nm. Further, in the numerical values used in the simulation in FIG. 5, the boron (B) dose is 2 × 10 ¹⁶ / cm ² , the acceleration voltage is 80 keV, and the thickness of the gate insulating film is 150 nm. 4B and 5, the vertical axis represents the wraparound amount L (Lateral length), which is the distance from the mask end face shown in FIG. 4A, and the horizontal axis represents a plane perpendicular to the substrate surface. Is a tilt angle (angle θ shown in FIG. 4A), which is an angle formed by the ion irradiation direction.

Alternatively, a plurality of ion sources may be prepared and a plurality of different doping processes may be sequentially performed on the substrate being transferred.
A doping apparatus in which a substrate loading chamber, a doping chamber, and a substrate unloading chamber are arranged in series. The doping chamber has a first means for generating a linear or rectangular ion flow in cross section, and a cross section A second means for generating a linear or rectangular ion flow; and a substrate position control means for moving the substrate to be processed in one direction, in one direction from the substrate carry-in chamber to the substrate carry-out chamber through the doping chamber. A doping apparatus characterized by irradiating a substrate to be processed with a plurality of ion flows.

  By preparing a plurality of ion sources, a plurality of different doping processes can be performed in a short time.

In each of the above structures, the means for generating the ion flow includes high frequency energy or microwaves and a magnetic field. When a plurality of ion sources are used, ion sources having different configurations can be combined.

  Further, the present invention is not limited to the apparatus configuration that irradiates the ion beam in the direction of gravity, and may be an apparatus configuration that irradiates the ion beam in the horizontal direction to a substrate in an inclined state close to a vertically standing state.

  Moreover, the axis | shaft which inclines a board | substrate is not specifically limited to the axis | shaft (axis parallel to one side of a board | substrate) which passes along the center of a board | substrate, It can be set as arbitrary axes | shafts or arbitrary several axes | shafts. For example, the substrate may be tilted about the diagonal line of the substrate. In this case, the irradiation direction of the laser light in the TFT manufacturing process and the diagonal line of the substrate may be matched. In addition, it is preferable to arrange the TFTs appropriately according to the diagonal line of the substrate.

Further, in each of the above structures, it is also one of the features that the substrate inclined to the substrate posture is moved in a direction orthogonal to the substrate posture direction. Further, the irradiation direction of the laser light in the TFT manufacturing process may be matched with the transport direction of the substrate. In addition, it is preferable to arrange the TFTs as appropriate in accordance with the substrate transport direction.

The laser oscillator used in the present invention is not particularly limited, and either a pulse oscillation or a continuous oscillation (CW) laser oscillator can be used. As a pulsed laser oscillator, an excimer laser, a YAG laser, a YVO ₄ laser, or the like can be used. As a CW laser oscillator, a YAG laser, a YVO ₄ laser, a GdVO ₄ laser, a YLF laser, or an Ar laser can be used. By using a CW solid-state laser and irradiating laser light of the second to fourth harmonics of the fundamental wave, a crystal having a large particle size extending long along the irradiation direction of the laser light can be obtained. For example, typically, it is desirable to use the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm). Specifically, laser light emitted from a continuous wave YVO ₄ laser is converted into a harmonic by a non-linear optical element to obtain laser light having an output number of W or more. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system and irradiated onto the semiconductor film. At this time, the energy density of about 0.001~100MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 0.5 to 2000 cm / sec (preferably 10 to 200 cm / sec).

  Further, the laser crystallization may be performed using a frequency band significantly higher than a frequency band of several tens to several hundreds Hz that is usually used with an oscillation frequency of pulsed laser light of 0.5 MHz or more. It is said that the time from irradiating a semiconductor film with laser light by pulse oscillation until the semiconductor film is completely solidified is several tens to several hundreds nsec. Therefore, by using the above frequency band, it is possible to irradiate the next pulse of laser light from when the semiconductor film is melted by the laser light to solidification. Accordingly, since the solid-liquid interface can be continuously moved in the semiconductor film, a semiconductor film having crystal grains continuously grown in the scanning direction is formed. Specifically, a set of crystal grains having a width of 10 to 30 μm in the scanning direction and a width of about 1 to 5 μm in a direction perpendicular to the scanning direction can be formed. By forming single crystal grains extending long along the scanning direction, a semiconductor film having almost no crystal grain boundary at least in the channel direction of the thin film transistor can be formed.

  In addition, all the processing units constituting the in-line system can be tilted by connecting the substrate to a processing unit that processes the substrate in an inclined state.

  According to the present invention, a semiconductor device manufacturing apparatus including a device capable of uniformly doping an impurity element using a large area substrate without rotating can be realized.

  Embodiments of the present invention will be described below.

(Embodiment 1)
FIG. 1A is a perspective view showing an example of the doping apparatus of the present invention. FIG. 2 is a top view showing an example of the structure of the entire doping apparatus of the present invention. In FIG. 2, the same reference numerals are used for the same portions as in FIG.

The ion source 12 includes a thermionic emission filament provided in a chamber that is a plasma chamber, and ring-shaped permanent magnets that are arranged around the chamber in a plurality of alternating polarities.

The accelerating electrode section 13 includes an ion confining electrode that is maintained at the same potential as the anode chamber, an extraction electrode that is maintained at a potential several kV lower than the ion confinement electrode, and an extraction electrode. The acceleration electrode is maintained at a low potential of several tens of kV. The ion confinement electrode, the extraction electrode, and the acceleration electrode are grid electrodes.

Alternatively, irradiation on / off may be controlled by opening and closing a shutter for blocking the ion beam.

A plasma is generated by causing electrons emitted from the filament to act on the working gas (hydrogen, phosphine, diborane, etc.) introduced into the chamber from the gas inlet, and this is confined in the chamber by the magnetic field of the permanent magnet. By applying an electric field by the extraction electrode, ions in the plasma are extracted through the ion confinement electrode, and this is accelerated by the electric field of the acceleration electrode to generate the ion beam 14.

Then, the ion beam 14 is irradiated into the doping chamber 11 and ions are implanted into the substrate 10 in an inclined state. The substrate 10 is tilted about the tilt axis 16 and held. The doping process on the entire surface of the substrate is performed by making the cross section of the ion beam 14 linear or rectangular and moving the substrate in a direction perpendicular to the longitudinal direction of the ion beam 14.

  As shown in FIG. 2, the substrate 10 is moved in the scanning direction 15 so as to pass under the ion source 12. The doping chamber 11 is connected to the substrate carry-in chamber 20 through the gate valve 23. A transfer robot 22 is provided in the substrate carry-in chamber 20, and the substrate 10 is transferred from the substrate cassette 21 in which a plurality of substrates are stored to the substrate stage 30 in the doping chamber.

  When changing the tilt of the substrate between the horizontal state and the tilted state, the tilt angle of the substrate is changed by the substrate stage 30 or the transfer robot 22.

  When changing the tilt angle of the substrate on the substrate stage 30, the substrate control mechanism 32 moves the substrate in the scanning direction and adjusts the angle of the stage as shown in FIG. If the substrate control mechanism 32 shown in FIG. 3 is used, doping can be performed from the horizontal direction, and θ can be set to 60 ° or more and less than 120 °, and can also be applied to a substrate vertical placement apparatus. The movement of the substrate in the scanning direction is not limited to the robot, and a rail and a drive geared motor may be used. The angle of the stage is adjusted by angle adjusting means such as a goniometer. A stage provided with a goniometer is also called a goniometer stage, which has a center of rotation above the stage, rotates about that as a fulcrum, and the stage surface tilts. Further, the angle formed between the surface including the perpendicular extending from the base 33 and the main surface of the substrate 10 is an angle α, and the angle between the surface perpendicular to the substrate surface and the surface including the normal extending from the base 33 is an inclination angle. θ. The substrate 10 is held by the clamper 31 on the substrate stage 30.

  FIG. 7 shows another example of changing the tilt angle of the substrate. The substrate control mechanism 83 moves the substrate in the scanning direction 84 to scan the substrate 87 fixed to the substrate stage 88. If two goniometers 85a and 85b whose axes are orthogonal to each other are used, a complicated tilt state can be maintained. For example, it is possible to maintain a tilted substrate having the tilt axis 82 as a diagonal line of the substrate. In this case, the tilt axis 82 and the substrate scanning direction 84 are not orthogonal. The first goniometer 85a changes the angle between the X direction of the substrate and the horizontal plane, and the second goniometer 85b changes the angle between the Y direction of the substrate and the horizontal plane. The inclination (angle with respect to the horizontal plane) of the semiconductor film provided on the substrate can be freely adjusted. The personal computer 86 is connected to the first goniometer 85a, the second goniometer 85b, and the board control mechanism 83, and controls each of them.

  In addition, when the tilt angle is changed by the transfer robot 22, the holding unit of the transfer robot 22 can suck the substrate, and the holding unit can be rotated around a predetermined axis by a driving unit. To do. By rotating the holding unit of the transfer robot 22, the posture of the holding unit can be changed, and the posture of the substrate adsorbed by the holding unit can be changed.

Further, the substrate cassette 21 may have a structure in which the substrate is stocked in an inclined state. In this case, the substrate transfer and the doping process can be performed with almost no change in the inclined state of the substrate.

  Similarly, the doping chamber 11 is connected to the substrate carry-out chamber 25 via the gate valve 24. A transfer robot 27 is also provided in the substrate carry-out chamber 25, and the transfer robot 27 stores the substrate subjected to the doping process in the substrate cassette 26.

  Since the doping apparatus of the present invention performs the doping process by moving the substrate while maintaining the tilted state by the substrate stage, it is possible to process a large-area substrate. Further, since the cross-sectional shape of the ion beam is a quadrangle, all the ion beams are irradiated onto the substrate, so that ion irradiation can be performed efficiently. Further, since the substrate is not rotated, the width of the ion beam in the longitudinal direction can be reduced.

  Further, the present invention is not particularly limited to the above-described apparatus configuration, and since there is a problem of particles, the apparatus may be configured to irradiate the ion beam in the horizontal direction in an inclined state close to a vertically standing state.

  FIG. 30 shows an example of an apparatus configuration in which a substrate is vertically set. Since there is a problem of particles, it is preferable that the substrate 601 be configured to irradiate the ion beam 602 in the horizontal direction with the substrate 601 standing vertically. Further, it is preferable that the substrate cassette is placed vertically and is carried into the chamber by a mechanism for carrying the substrate while standing. Note that FIG. 30A shows a diagram in which the ion beam irradiated from the ion beam irradiation means 603 is linear, but there is no particular limitation. Further, there are two ways of moving a substrate stage (for example, the mechanism shown in FIG. 3) that holds and moves the substrate. One is a method of tilting the substrate by an angle β as shown in FIG. 30B, and the other is a method of tilting the substrate by an angle β as shown in FIG. Further, while the ion beam is irradiated, the substrate stage may be fixed at a certain angle β, or the angle β may be constantly changed within a certain angle range.

  Further, in order to dope obliquely and form an impurity region below the gate electrode, it is necessary to consider the arrangement of TFTs. As shown in FIGS. 30B and 30C, it is preferable to design a circuit including TFTs by combining the movement of the substrate stage for tilting the substrate and the channel length directions 600a and 600b.

The present invention is not particularly limited to the above-described apparatus configuration, and a substrate transport roller may be used instead of the substrate stage to hold and transport the tilted substrate. In this case, the lower surface of the substrate is held by a holding member such as a transport roller, and the lower end of the slope is held by the side guide. The side guide plays a role of suppressing the downward movement of the substrate by tilting the lower end support roller in contact with the lower end of the substrate and holding it from the side.

Moreover, it is not specifically limited to the apparatus structure mentioned above, You may add the ion focusing apparatus and ion mass separation apparatus well-known in the conventional ion doping technique to the doping apparatus of this invention.

In addition, in order to perform doping while holding the substrate obliquely and form an impurity region below the gate electrode, it is necessary to consider the arrangement of TFTs. FIG. 1B is a schematic diagram simply showing the state of the substrate in the doping chamber 11. As shown in FIG. 1B, it is preferable to design a circuit including TFTs by combining the movement of the substrate stage for inclining the substrate and the channel length direction 17.

(Embodiment 2)
In order to efficiently perform a plurality of doping processes, a plurality of ion sources may be provided in one doping chamber.

  FIG. 6 shows an example of a top view of the entire doping apparatus of the present invention.

  As shown in FIG. 6, an apparatus is provided in which a first ion source 52a and a second ion source 52b are provided in parallel and can irradiate a first ion beam 54a and a second ion beam 54b, respectively. It has become.

  The substrate 50 is carried from the substrate cassette 61 into the doping chamber 51 through the gate valve 63 from the substrate carry-in chamber 60 by the transfer robot 62. The substrate 50 is disposed on the substrate stage 70, and when the substrate 50 moves in the doping chamber 51 in the scanning direction 55 and passes below the two ion sources, the ion doping process is performed twice. The substrate after the doping process is stored in the substrate cassette 66 in the substrate carry-out chamber 65 by the transfer robot 67 through the gate valve 64.

For example, the first ion treatment for forming the high-concentration impurity region and the second doping for forming the low-concentration impurity region can be continuously performed under the conditions of different acceleration voltages in the two ion sources. it can.

  Moreover, it is not limited to two ion sources, You may provide three or more ion sources.

  Further, this embodiment mode can be freely combined with Embodiment Mode 1. In this embodiment, an example is shown in which the substrate is moved while being held horizontally, but even if the substrate is moved while being tilted using a stage having an angle adjustment function as in the first embodiment, the substrate is moved. Good.

(Embodiment 3)
A method for manufacturing a thin film transistor using the doping apparatus described in this embodiment will be described in detail with reference to FIGS.

A silicon nitride oxide film (SiNO) is formed as a base film on the substrate 100 having an insulating surface by a CVD method (Chemical Vapor Deposition) such as a sputtering method, a PVD method, a low pressure CVD method (LPCVD method), or a plasma CVD method. The base film 101a is formed to a thickness of 10 to 200 nm (preferably 50 to 100 nm), and the base film 101b is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm) using a silicon oxynitride film (SiON). In this embodiment, the base film 101a and the base film 101b are formed by a plasma CVD method. As the substrate 100, a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used, or a flexible substrate such as a film may be used. In addition, a two-layer structure may be used as the base film, or a single-layer film or a structure in which two or more layers are stacked may be used.

    Next, a semiconductor film is formed over the base film. The semiconductor film may be formed by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) with a thickness of 25 to 200 nm (preferably 30 to 150 nm). In this embodiment mode, it is preferable to use a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film by laser crystallization.

    As a material for forming the semiconductor film, an amorphous semiconductor (hereinafter also referred to as “amorphous semiconductor: AS”) manufactured by a vapor deposition method or a sputtering method using a semiconductor material gas typified by silane or germane is used. A polycrystalline semiconductor obtained by crystallizing a crystalline semiconductor using light energy or thermal energy, or a semi-amorphous (also referred to as microcrystal or microcrystal; hereinafter, also referred to as “SAS”) semiconductor can be used.

SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state that is stable in terms of free energy and has a short-range order and a lattice. It includes a crystalline region with strain. A crystal region of 0.5 to 20 nm can be observed in at least a part of the film, and when silicon is the main component, the Raman spectrum shifts to a lower wave number side than 520 cm ^−1. Yes. In X-ray diffraction, diffraction peaks of (111) and (220) that are derived from the silicon crystal lattice are observed. In order to terminate dangling bonds (dangling bonds), hydrogen or halogen is contained at least 1 atomic% or more. The SAS is formed by glow discharge decomposition (plasma CVD) of a silicide gas. As the silicide gas, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _{4, and the} like can be used. Further, F ₂ and GeF ₄ may be mixed. This silicide gas may be diluted with H ₂ , or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. The dilution rate is in the range of 2 to 1000 times, the pressure is in the range of approximately 0.1 Pa to 133 Pa, and the power supply frequency is 1 MHz to 120 MHz, preferably 13 MHz to 60 MHz. The substrate heating temperature is preferably 300 ° C. or lower, and can be formed even at a substrate heating temperature of 100 to 200 ° C. Here, as an impurity element mainly taken in at the time of film formation, it is desirable that impurities derived from atmospheric components such as oxygen, nitrogen, and carbon be 1 × 10 ²⁰ cm ⁻³ or less, and in particular, the oxygen concentration is 5 × 10 5. It is preferable to be ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less. Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability is improved and a favorable SAS can be obtained. In addition, a SAS layer formed of a hydrogen-based gas may be stacked on a SAS layer formed of a fluorine-based gas as a semiconductor film.

    A typical example of an amorphous semiconductor is hydrogenated amorphous silicon, and a typical example of a crystalline semiconductor is polysilicon. Polysilicon (polycrystalline silicon) is mainly made of so-called high-temperature polysilicon using polysilicon formed through a process temperature of 800 ° C. or higher as a main material, or polysilicon formed at a process temperature of 600 ° C. or lower. And so-called low-temperature polysilicon, and polysilicon crystallized by adding an element that promotes crystallization. Needless to say, as described above, a semi-amorphous semiconductor or a semiconductor containing a crystal phase in part of a semiconductor film can also be used.

In the case where a crystalline semiconductor film is used as the semiconductor film, a method for manufacturing the crystalline semiconductor film can be a known method (laser crystallization method, thermal crystallization method, or heat using an element that promotes crystallization such as nickel. A crystallization method or the like may be used. In addition, a microcrystalline semiconductor that is a SAS can be crystallized by laser irradiation to improve crystallinity. In the case where an element for promoting crystallization is not introduced, the concentration of hydrogen contained in the amorphous semiconductor film is set to 1 × by heating at 500 ° C. for 1 hour in a nitrogen atmosphere before irradiating the amorphous semiconductor film with laser light. Release to 10 ²⁰ atoms / cm ³ or less. This is because the film is destroyed when an amorphous semiconductor film containing a large amount of hydrogen is irradiated with laser light.

    The method of introducing the metal element into the amorphous semiconductor film is not particularly limited as long as the metal element can be present on the surface of the amorphous semiconductor film or inside the amorphous semiconductor film. For example, sputtering, CVD, A plasma treatment method (including a plasma CVD method), an adsorption method, or a method of applying a metal salt solution can be used. Among these, the method using a solution is simple and useful in that the concentration of the metal element can be easily adjusted. At this time, in order to improve the wettability of the surface of the amorphous semiconductor film and to spread the aqueous solution over the entire surface of the amorphous semiconductor film, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, hydroxy radical It is desirable to form an oxide film by treatment with ozone water or hydrogen peroxide.

By using a solid-state laser capable of continuous oscillation and irradiating laser light of the second to fourth harmonics of the fundamental wave, a crystal having a large grain size can be obtained. For example, typically, it is desirable to use the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm). Specifically, laser light emitted from a continuous wave YVO ₄ laser is converted into a harmonic by a non-linear optical element to obtain laser light having an output number of W or more. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system and irradiated onto the semiconductor film. At this time, the energy density of about 0.001~100MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 0.5 to 2000 cm / sec (preferably 10 to 200 cm / sec).

As the laser, a known continuous wave gas laser or solid-state laser can be used. Examples of gas lasers include Ar laser and Kr laser, and solid-state lasers include YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, Y ₂ O ₃ laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser. Etc.

  Further, the laser crystallization may be performed using a frequency band significantly higher than a frequency band of several tens to several hundreds Hz that is usually used with an oscillation frequency of pulsed laser light of 0.5 MHz or more. It is said that the time from irradiating a semiconductor film with laser light by pulse oscillation until the semiconductor film is completely solidified is several tens to several hundreds nsec. Therefore, by using the above frequency band, it is possible to irradiate the next pulse of laser light from when the semiconductor film is melted by the laser light to solidification. Accordingly, since the solid-liquid interface can be continuously moved in the semiconductor film, a semiconductor film having crystal grains continuously grown in the scanning direction is formed. Specifically, a set of crystal grains having a width of 10 to 30 μm in the scanning direction and a width of about 1 to 5 μm in a direction perpendicular to the scanning direction can be formed. By forming single crystal grains extending long along the scanning direction, a semiconductor film having almost no crystal grain boundary at least in the channel direction of the thin film transistor can be formed.

  Further, laser light may be irradiated in an inert gas atmosphere such as a rare gas or nitrogen. Accordingly, the surface roughness of the semiconductor can be suppressed by laser light irradiation, and variations in threshold values caused by variations in interface state density can be suppressed.

Crystallization of the amorphous semiconductor film may be a combination of heat treatment and crystallization by laser light irradiation, or may be performed multiple times by heat treatment or laser light irradiation alone.

    In this embodiment, the amorphous semiconductor film 115 is formed using amorphous silicon over the base film 101b. By irradiating the amorphous semiconductor film 115 with laser light 170 while scanning in the direction of the arrow 171, the amorphous semiconductor film 115 is crystallized to form a crystalline semiconductor film 116 (see FIGS. 8A and 8B). ). FIG. 8B is a schematic perspective view at the time of irradiation, and scanning is performed so as to coincide with the channel length direction of the TFT having the active layer in the portion surrounded by the dotted line.

    In order to control the threshold voltage of the thin film transistor, the semiconductor film obtained in this manner may be doped with a small amount of impurity element (boron or phosphorus). An n-channel thin film transistor is manufactured so as to have a p-type impurity region, and a threshold voltage of the thin film transistor is controlled. Therefore, when the present invention is used, the doping process for controlling the threshold voltage is not necessarily performed, and thus the process is simplified.

    Next, the crystalline semiconductor film 116 is patterned using a mask. In this embodiment, a photomask is manufactured, and the semiconductor layer 102 is formed by a patterning process using a photolithography method.

As the etching process at the time of patterning, either plasma etching (dry etching) or wet etching may be employed, but plasma etching is suitable for processing a large area substrate. As an etching gas, a fluorine-based or chlorine-based gas such as CF ₄ , NF ₃ , Cl ₂ , or BCl ₃ may be used, and an inert gas such as He or Ar may be appropriately added. Further, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

    In the present invention, a conductive layer for forming a wiring layer or an electrode layer, a mask layer for forming a predetermined pattern, or the like may be formed by a method capable of selectively forming a pattern such as a droplet discharge method. . A droplet discharge (ejection) method (also called an ink-jet method depending on the method) is a method in which a droplet of a composition prepared for a specific purpose is selectively ejected (ejection) to form a predetermined pattern (such as a conductive layer or a conductive layer). An insulating layer or the like can be formed. At this time, pretreatment for forming a titanium oxide film or the like in the formation region may be performed. In addition, a method by which a pattern can be transferred or drawn, for example, a printing method (a method for forming a pattern such as screen printing or offset printing) can be used.

  In this embodiment mode, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin is used as a mask to be used. Also, organic materials such as benzocyclobutene, parylene, flare, permeable polyimide, compound materials made by polymerization of siloxane polymers, composition materials containing water-soluble homopolymers and water-soluble copolymers, etc. are used. You can also Alternatively, a commercially available resist material containing a photosensitizer may be used. For example, a novolak resin that is a typical positive resist and a naphthoquinonediazide compound that is a photosensitizer, a base resin that is a negative resist, diphenylsilanediol, and An acid generator or the like may be used. When using the droplet discharge method, regardless of which material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

    A gate insulating layer 105 is formed to cover the semiconductor layer 102. The gate insulating layer 105 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. The gate insulating layer 105 may be formed of a known material such as a silicon oxide material or a nitride material, and may be a stacked layer or a single layer. In this embodiment, the gate insulating layer has a stacked structure. A thin silicon oxide film having a thickness of 1 to 100 nm, preferably 1 to 10 nm, and more preferably 2 to 5 nm is formed over the semiconductor layer 102 as the first insulating film. As a method of forming the first insulating layer, the surface of the semiconductor region is oxidized using a GRTA (Gas Rapid Thermal Anneal) method, an LRTA (Lamp Rapid Thermal Anneal) method, etc., and a thermal oxide film is formed. A thin first insulating layer can be formed. In this embodiment, a stacked layer of a silicon nitride film, a silicon oxide film, and a silicon nitride film is used on the first insulating film. Alternatively, a single layer or a double layer of silicon oxynitride film may be used. A silicon nitride film having a dense film quality is preferably used. Note that in order to form a dense insulating film with low gate leakage current at a low deposition temperature, a rare gas element such as argon is preferably contained in the reaction gas and mixed into the formed insulating film.

    Next, a first conductive film 106 with a thickness of 20 to 100 nm and a second conductive film 107 with a thickness of 100 to 400 nm used as a gate electrode layer are stacked over the gate insulating layer 105 (FIG. 8 ( C)). The first conductive film 106 and the second conductive film 107 can be formed by a known method such as a sputtering method, an evaporation method, or a CVD method. The first conductive film and the second conductive film are tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), neodymium (Nd ), Or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used as the first conductive film and the second conductive film. Further, the present invention is not limited to the two-layer structure. For example, a three-layer structure in which a tungsten film with a thickness of 50 nm, an aluminum-silicon alloy film with a thickness of 500 nm (Al-Si), and a titanium nitride film with a thickness of 30 nm are sequentially stacked. Also good. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum instead of the aluminum and silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. Moreover, a single layer structure may be sufficient. In this embodiment mode, tantalum nitride (TaN) is used for the first conductive film 106 and tungsten (W) is used for the second conductive film 107.

Next, a resist mask is formed by photolithography, the second conductive film 107 is patterned, and the first gate electrode layer 205 is formed. Using ICP (Inductively Coupled Plasma) etching method, etching conditions (amount of power applied to coil-type electrode layer, amount of power applied to electrode layer on substrate side, electrode temperature on substrate side, etc.) By appropriately adjusting, the first conductive film can be etched into a desired taper shape. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl _4, CCl _4, etc., a fluorine-based gas typified by CF ₄ , SF _6, NF _3, etc., or O ₂ is appropriately used. be able to.

    A thin film transistor capable of high-speed operation can be formed by reducing the width D1 of the gate electrode layer. Two methods for forming the first gate electrode layer 205 with a narrow width in the channel direction are shown in FIGS. FIG. 11A corresponds to FIG. 8C, and the second conductive film 107 is formed over the substrate 100.

    First, the first method will be described with reference to FIGS. 11B, 11C, and 11F. A mask 220 made of resist is formed over the second conductive film 107. The mask 220 is formed using a photolithography method, a droplet discharge method, or the like. As shown in FIG. 11B, the second conductive film 107 is etched using a mask 220 to form a first gate electrode layer 210. Thereafter, the mask 220 is not removed, and the first gate electrode layer 210 is further etched in the direction of the arrow 255. The width of the first gate electrode layer 210 is reduced to the first gate electrode layer 205, so that the first gate electrode layer 205 is formed (see FIG. 11C). The mask 220 is removed, and as shown in FIG. 11F, the first gate electrode layer 205 having a gate electrode width D1 of 200 nm to 1500 nm, preferably 200 nm to 700 nm, can be completed.

    Next, a second method will be described with reference to FIGS. 11D, 11E, and 11F. A mask 220 made of resist is formed over the second conductive film 107. The mask 220 is formed using a photolithography method, a droplet discharge method, or the like. The mask 220 is further slimmed in the direction of the arrow 256 by etching, ashing, or the like to form a mask 221 having a narrower width (see FIG. 11E). The second conductive film 107 is patterned using the mask 221 formed with a very small line width, and the mask 221 is removed, so that the first gate electrode layer 205 whose gate electrode layer width D1 is narrow is similarly reduced. Can be formed. By setting the width D1 of the gate electrode layer within the range, a thin film transistor having a short channel length can be formed later, and a semiconductor device capable of high-speed operation can be manufactured.

Next, an impurity element 251 imparting p-type conductivity is added using the first gate electrode layer 205 as a mask. Here, the doping apparatus shown in FIG. 1 is used, an impurity element imparting p-type is added at less than 60 degrees, preferably 5 to 45 degrees with respect to the surface of the semiconductor layer 102, and the first p-type impurity region is added. 103a and a first p-type impurity region 103b are formed (see FIG. 8D). Since the impurity element imparting p-type conductivity is doped obliquely toward the surface of the semiconductor layer, the impurity element is also added to the region of the semiconductor layer 102 covered with the first gate electrode layer 205, and the first p-type impurity region 103b is added. Form. On the other hand, part of the impurity element imparting p-type conductivity is shielded by the first gate electrode layer 205, and thus the first p-type impurity region 103 a includes a semiconductor region covered with the gate electrode layer 205. Not. Here, the first p-type impurity region 103a and the first p-type impurity region 103b include the impurity element imparting p-type at a concentration of about 5 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ^3. Added. Further, the impurity element imparting p-type conductivity may be added so as to be contained at a concentration of about 5 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity.

  FIG. 9 shows the state of the substrate during doping. 9A is a top view, FIG. 9B is a cross-sectional view taken along the dotted line IJ in FIG. 9A, and FIG. 9C is cut along the dotted line GH in FIG. 9A. Cross-sectional views are shown respectively. Further, FIG. 9C and FIG. 8D are the same. In FIG. 9, the same reference numerals are used for the same portions as in FIG.

Further, when it is cut along a plane parallel to the axis of rotation of the substrate, it appears to be doped vertically as shown in FIG. 9B, but there is no particular limitation. For example, using a stage shown in FIG. If the substrate is inclined with respect to a plurality of axes, it can be doped obliquely regardless of which plane is cut.

In this embodiment mode, a region where the impurity region overlaps with the gate electrode layer through the gate insulating layer is referred to as a Lov region, and a region where the impurity region does not overlap with the gate electrode layer through the gate insulating layer is referred to as a Loff region. The regions overlapping with the gate electrode layer 205 in the first p-type impurity regions 103a and 103b are indicated by hatching and white background, which indicates that boron is not added to the white background portion. Instead, as described above, it is possible to intuitively understand that the boron concentration distribution in this region reflects the film thickness of the tapered portion of the gate electrode layer 205. This also applies to other drawings in this specification.

Again, an impurity element 252 imparting n-type conductivity is added using the first gate electrode layer 205 as a mask. An impurity element 252 imparting n-type conductivity is added perpendicular to the surface of the semiconductor layer 102, so that the first n-type impurity region 104a and the first n-type impurity region 104b are formed (see FIG. 10A). . In the first n-type impurity region 104a and the first n-type impurity region 104b, since the impurity element imparting p-type is already added, the first p-type is inverted to invert from p-type to n-type. An impurity element imparting n-type having a higher concentration than the impurity element concentration imparting p-type conductivity of the impurity region 103a and the first p-type impurity region 103b is added. The first n-type impurity region 104a and the first n-type impurity region 104b typically contain an impurity element imparting n-type at a concentration of 1 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ^3. To form. In this embodiment mode, phosphorus (P) is used as the impurity element imparting n-type conductivity.

    Here, since the impurity element 252 imparting n-type is added in a self-aligning manner using the first gate electrode layer 205, the first p-type impurity region 103b overlaps with the first gate electrode layer 205. In this case, the impurity element 252 imparting n-type is not added and remains as a p-type impurity region. Therefore, the second p-type impurity region 208 is formed in the semiconductor layer 102, and the second p-type impurity region 208 is a Lov region. On the other hand, the first n-type impurity region 104 a and the first n-type impurity region 104 b are Loff regions because they are not covered with the gate electrode layer 205.

    Next, after an insulating layer covering the first conductive film 106, the gate electrode layer 205, and the like is formed, the insulating layer is processed by anisotropic etching by a RIE (Reactive ion etching) method. Sidewalls (sidewall spacers) 201 are formed on the side walls of the layer 205 in a self-aligning manner (see FIG. 10B). Here, there is no particular limitation on the insulating layer, and the insulating layer may be silicon oxide with good step coverage formed by reacting TEOS (Tetra-Ethyl-Orso-Silicate) or silane with oxygen or nitrous oxide. preferable. The insulating layer can be formed by a method such as thermal CVD, plasma CVD, atmospheric pressure CVD, bias ECRCVD, or sputtering.

In this embodiment mode, since the gate electrode layer has a stacked structure, the first conductive film 106 functions as an etching stopper. Next, the first conductive film 106 is etched using the first gate electrode layer 205 and the sidewall 201 as a mask, so that the second gate electrode layer 202 is formed. In this embodiment mode, the first conductive film 106 and the second conductive film 107 are formed using a material with a high etching selection ratio; therefore, the first gate electrode layer 205 is etched from the first conductive film 106. It can be used as a mask when In the case where the etching selectivity between the first conductive film 106 and the second conductive film 107 is not so high, an insulating layer is formed over the first gate electrode layer 205 when the sidewall 201 is formed. Alternatively, a resist mask may be formed over the first gate electrode layer 205. By protecting the first gate electrode layer 205 in this manner, the first gate electrode layer 205 can be prevented from being reduced when the first conductive film 106 is etched. The etching method may be a dry etching method or a wet etching method, and a known etching method can be used. In this embodiment mode, a dry etching method is used. As the etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , SF ₆ or NF _3, or O ₂ is appropriately used. it can.

Next, using the sidewall 201 and the first gate electrode layer 205 as a mask, an impurity element 253 imparting n-type conductivity is added to the semiconductor layer 102 so as to be perpendicular to the surface of the semiconductor layer 102, so that a second n-type impurity is added. A region 203a and a second n-type impurity region 203b are formed (see FIG. 10C). Here, the second n-type impurity region 203a and the second n-type impurity region 203b include an impurity element imparting n-type at a concentration of about 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ^3. Added. In this embodiment mode, phosphorus (P) is used as the impurity element imparting p-type conductivity. The regions where the sidewall 201 serves as a mask and the impurity element imparting n-type conductivity is not added are a third n-type impurity region 206a and a third n-type impurity region 206b. The third n-type impurity region 206 a and the third n-type impurity region 206 b are Lov regions because they are covered with the second gate electrode layer 202. Note that a channel formation region 207 is formed in the semiconductor layer 102 (see FIG. 10C).

    The second n-type impurity region 203a and the second n-type impurity region 203b are high-concentration impurity regions in which the concentration of an impurity element imparting n-type is high, and function as a source region and a drain region. On the other hand, the third n-type impurity region 206a and the third n-type impurity region 206b, which are low-concentration impurity regions, are covered with the second gate electrode layer 202. It is possible to suppress the deterioration of the on-current due to. As a result, a semiconductor device capable of high speed operation can be formed.

    In order to activate the impurity element, heat treatment, intense light irradiation, or laser light irradiation may be performed. Simultaneously with activation, plasma damage to the gate insulating layer and plasma damage to the interface between the gate insulating layer and the semiconductor layer can be recovered.

    Next, an insulating film 108 containing hydrogen is formed as a passivation film. The insulating film 108 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm using a plasma CVD method or a sputtering method. The insulating film 108 is not limited to a silicon nitride film, and may be a silicon nitride oxide (SiNO) film using plasma CVD, or an insulating film containing other silicon may be used as a single layer or a laminated structure.

    Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in a nitrogen atmosphere to perform a step of hydrogenating the semiconductor layer. Preferably, it carries out at 400-500 degreeC. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the insulating film 108.

    The insulating film 108 includes silicon nitride, silicon oxide, silicon oxynitride (SiON), silicon nitride oxide (SiNO), aluminum nitride (AlN), aluminum oxynitride (AlON), and aluminum nitride oxide having a nitrogen content higher than the oxygen content. (AlNO) or aluminum oxide, diamond-like carbon (DLC), and a material selected from substances including a nitrogen-containing carbon film (CN). In addition, a skeleton structure is formed by a bond of silicon (Si) and oxygen (O), and an organic group containing at least hydrogen as a substituent (for example, an alkyl group or aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  Next, an insulating layer 109 to be an interlayer insulating film is formed (see FIG. 10D). In the present invention, an interlayer insulating film provided for planarization is required to have high heat resistance and insulation and a high planarization rate. As a method for forming such an insulating layer, a coating method typified by a spin coating method is preferably used.

  In this embodiment mode, the material of the insulating layer 109 is an organic group (for example, an alkyl group or aromatic carbonization) in which a skeleton structure is formed by a bond of silicon (Si) and oxygen (O), and the substituent includes at least hydrogen. A coating film using hydrogen is used. The film after baking can be called a silicon oxide film (SiOx) containing an alkyl group. This silicon oxide (SiOx) film containing an alkyl group can withstand heat treatment at 300 ° C. or higher.

  The insulating layer 109 can employ dipping, spray coating, doctor knife, roll coater, curtain coater, knife coater, CVD method, vapor deposition method, or the like. The insulating layer 109 may be formed by a droplet discharge method. When the droplet discharge method is used, the material liquid can be saved. Further, a method capable of transferring or drawing a pattern, such as a droplet discharge method, for example, a printing method (a method for forming a pattern such as screen printing or offset printing) or the like can be used. Spin coating or an inorganic material may be used. In that case, silicon oxide, silicon nitride, silicon oxynitride, or the like can be used.

  The insulating layer 109 can be an inorganic material (silicon oxide) as long as it has high heat resistance and good planarity in addition to an insulating film having a skeleton structure formed of a bond of silicon (Si) and oxygen (O). , Silicon nitride, silicon oxynitride, silicon nitride oxide PSG (phosphorus glass), BPSG (phosphorus boron glass), alumina film, etc.), photosensitive or non-photosensitive organic material (organic resin material) (polyimide, acrylic, polyamide, (Polyimide amide, benzocyclobutene, etc.), a resist, a low dielectric constant Low-k material, or a film made of a plurality of kinds, or a stack of these films can be used.

    Next, contact holes (openings) reaching the semiconductor layer 102 are formed in the insulating layer 109, the insulating film 108, and the gate insulating layer 105 using a resist mask. Etching may be performed once or a plurality of times depending on the selection ratio of the material to be used. In this embodiment, the first etching is performed under conditions where the selection ratio between the insulating layer 109 and the insulating film 108 and the gate insulating layer 105 is high, so that the insulating layer 109 and the insulating film 108 are removed. Next, the gate insulating layer 105 is removed by second etching, and openings reaching the second n-type impurity region 203a and the second n-type impurity region 203b which are source regions or drain regions are formed.

First etching is performed to remove the insulating layer 109 and the insulating film 108. Etching (wet etching or dry etching) is performed. An inert gas may be added to the etching gas used. As the inert element to be added, one or more elements selected from He, Ne, Ar, Kr, and Xe can be used. Among them, it is preferable to use argon which has a relatively large atomic radius and is inexpensive. In this embodiment mode, CF ₄ , O ₂ , He, and Ar are used. The etching conditions for dry etching are CF ₄ flow rate of 380 sccm, O ₂ flow rate of 290 sccm, He flow rate of 500 sccm, Ar flow rate of 500 sccm, RF power of 3000 W, and pressure of 25 Pa. Etching residues can be reduced under the above conditions.

Note that in order to perform etching without leaving a residue on the gate insulating layer 105, it is preferable to increase the etching time at a rate of about 10 to 20% and perform over-etching. A taper shape may be formed by one etching, or a taper shape may be formed by a plurality of etchings. Further, using CF ₄ , O ₂ , and He, the second dry etching is performed with a CF ₄ flow rate of 550 sccm, an O ₂ flow rate of 450 sccm, a He flow rate of 350 sccm, an RF power of 3000 W, and a pressure of 25 Pa. It may be a tapered shape.

Next, as the second etching, the gate insulating layer 105 is etched to form openings reaching the source region and the drain region. The opening may be formed by etching the insulating layer 109 and then forming a mask again, or by etching the insulating film 108 and the gate insulating layer 105 using the etched insulating layer 109 as a mask. The gate insulating layer 105 is etched using CHF ₃ and Ar as etching gases. By etching under the above conditions, an etching residue can be reduced and a contact hole with high flatness with less unevenness can be formed. In order to perform etching without leaving a residue on the semiconductor layer, it is preferable to increase the etching time at a rate of about 10 to 20%.

    A conductive film is formed, and the conductive film is etched to form a source electrode layer or a drain electrode layer 112 that is electrically connected to part of each source region or drain region. The source or drain electrode layer 112 is a wiring that is in contact with a wiring or the like to be formed later and connects the thin film transistor and the wiring. The source or drain electrode layer 112 can be formed by forming a conductive film by a PVD method, a CVD method, an evaporation method, or the like, and then etching it into a desired shape. Further, the conductive layer can be selectively formed at a predetermined place by a droplet discharge method, a printing method, an electroplating method, or the like. Furthermore, a reflow method or a damascene method may be used. The material of the source or drain electrode layer 112 is Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, It is formed using a metal such as Ba or an alloy thereof, or a metal nitride thereof. Moreover, it is good also as these laminated structures. In this embodiment mode, Ti, Al, and Ti are stacked and then patterned into a desired shape to form the source or drain electrode layer 112.

    Through the above steps, the second n-type impurity region 203a, which is a high-concentration impurity region, the second n-type impurity region 203b, the third n-type impurity region 206a, which is a low-concentration impurity region, and the third layer are formed in the semiconductor layer. A thin film transistor 150 including the n-type impurity region 206b, the second p-type impurity region 208, and the channel formation region 207 can be formed (see FIG. 10E). The width D2 of the second p-type impurity region 208 shown in FIG. 10E is preferably 5 to 200 nm, and the widths of the third n-type impurity region 206a and the third n-type impurity region 206b are 10 to 200 nm. preferable. By setting the width D2 of the second p-type impurity region and the width D1 of the third n-type impurity region within the above ranges, the threshold value can be shifted and the cut-off current can be reduced. A channel thin film transistor can be manufactured.

  In this embodiment mode, a low-concentration p-type impurity region is formed in an n-channel thin film transistor; however, a low-concentration n-type impurity region can be formed in a p-channel thin film transistor in the same manner.

Further, the thin film transistor 150 from the substrate 100 illustrated in FIG. 10 can be peeled by the following method. As a peeling method, (1) a substrate having a heat resistance of about 300 to 500 degrees is used as the substrate 100, a metal oxide film is provided between the substrate 100 and the thin film transistor 150, and the metal oxide film is weakened by crystallization. (2) An amorphous silicon film containing hydrogen is provided between the substrate 100 and the thin film transistor 150, and the amorphous silicon film is formed by laser irradiation or etching with a gas / solution. A method of removing the thin film transistor 150 by removing, (3) A method of separating the thin film transistor 150 by mechanically removing the substrate 100 on which the thin film transistor 150 is formed, or removing the substrate 100 by etching with a gas such as a solution or CF _3. Etc. In addition, the peeled thin film transistor 150 can be attached to a variety of materials or properties depending on the intended use. For example, a commercially available adhesive may be used for attachment to the flexible substrate, and an adhesive such as an epoxy resin adhesive or a resin additive may be used.

  As described above, when the peeled thin film transistor 150 is attached to a flexible substrate, it is possible to provide a semiconductor device that is thin, light, and difficult to break even when dropped. In addition, since the flexible substrate has flexibility, it can be bonded on a curved surface or an irregular shape, and a wide variety of uses can be realized. Further, if the substrate 100 is reused, an inexpensive semiconductor device can be provided. Further, since the thin film transistor formed in this embodiment has a sidewall structure, an LDD region can be formed even in a thin film transistor having a submicron structure.

  When the present invention is used, an impurity region having an impurity element imparting a different conductivity type can be formed in a semiconductor layer; thus, fine characteristics of a thin film transistor can be controlled. Accordingly, a thin film transistor having a required function can be formed through a simple process, and a semiconductor device with high reliability and electrical characteristics can be manufactured at low cost. Since the thin film transistor in this embodiment is an n-channel thin film transistor having a low-concentration p-type impurity region, a semiconductor device capable of high-speed operation and reduced power consumption can be formed.

  Further, since the semiconductor device formed in this embodiment can be formed using a crystalline semiconductor film, the semiconductor device can be manufactured without using an expensive single crystal semiconductor substrate. For this reason, cost reduction is possible. Further, a thin semiconductor device can be manufactured by peeling the thin film transistor 150 manufactured in this embodiment and bonding the thin film transistor 150 to a flexible substrate.

  This embodiment mode can be freely combined with Embodiment Mode 1 or Embodiment Mode 2.

(Embodiment 4)
In the third embodiment, an example in which a TFT having the second p-type impurity region 208 is formed using the doping shown in FIG. 1 is described, but the present invention is not particularly limited, and includes the structure shown in the third embodiment. A kind of structure can be obtained. 4 types of n-channel thin film transistors (structure B, structure C, structure D, structure E), p-channel thin film transistors (structure F), low-concentration n-type There are four types of p-channel thin film transistors having an impurity region (structure G, structure H, structure I, structure J), that is, a total of eight types. 12B, 13B, 14B, and 15B illustrate structures of thin film transistors.

    Simulation results of current-voltage (IV) characteristics of an n-channel thin film transistor having a low-concentration p-type impurity region will be described with reference to FIGS. 12A assumes a model diagram shown in FIG. 12B, and an n-channel in which a standard n-channel thin film transistor and a low-concentration p-type impurity region (hereinafter referred to as p−) are provided on the drain side. The IV characteristic of a thin film transistor is shown.

FIG. 12B illustrates the structure of each thin film transistor. Structure A is a standard n-channel thin film transistor having Loff, structure B is an n-channel thin film transistor with a p ⁻ width of 100 nm, and structure C is an n-channel thin film transistor with a p ⁻ width of 300 nm. In addition, L / W of each thin film transistor is 1000/20000 nm, the width of the Loff region is 300 nm, the thickness of the gate insulating layer is 20 nm, and the impurity concentration of the source region and the drain region (denoted as n ⁺ ) is 1 × 10 ^20. The IV characteristics were simulated by setting the impurity concentration of cm ⁻³ , the Loff region to 1 × 10 ¹⁸ cm ⁻³ , ^and the impurity concentration of p ⁻ to 1 × 10 ¹⁸ cm ⁻³ .

In FIG. 12A, the solid line indicates the IV characteristics of the structure A, and the broken lines indicate the IV characteristics of the structures B and C each having p ⁻ . It can be seen that by having p ⁻ , the threshold value of the thin film transistor is shifted to the positive side. It can also be seen that the shift amount of the threshold value increases as the width of p− increases (that is, in the structure C than in the structure B).

FIG. 13 shows a simulation result of IV characteristics of a thin film transistor having p ⁻ on the source side. FIG. 13A assumes a model diagram shown in FIG. 13B, and an n-channel type having a standard n-channel thin film transistor and a second p-type impurity region (hereinafter referred to as p-) on the source side. The IV characteristic of a thin-film transistor is shown.

FIG. 13B illustrates the structure of each thin film transistor. Structure A is the same as the standard n-channel thin film transistor shown in FIG. 12B, structure D is an n-channel thin film transistor with a p ⁻ width of 100 nm, and structure E has a p ⁻ width of 300 nm. It is an n-channel thin film transistor. In addition, L / W, Loff region width, gate insulating layer thickness, and n ⁺ concentration of each thin film transistor were the same as those used in FIG.

In FIG. 13A, the solid line indicates the IV characteristics of the structure A, and the broken line indicates the IV characteristics of the structures D and E each having p ⁻ . By having p ⁻ , the threshold value of the thin film transistor is shifted to the positive side. Further, the threshold shift amount increases as the width of p− increases (that is, in the structure E than in the structure D). Furthermore, the cut-off current (Icut) is lower than that of a standard n-channel thin film transistor. The cut-off current (Icut) is the value of the drain current Id when the gate voltage Vg is 0 V in the Id-Vg characteristic.

  As described above, by using an n-channel thin film transistor that is covered with a gate electrode and has a low concentration p-type impurity region in one of a channel formation region and a source region or a drain region, the threshold value is shifted and cut off. The current is reduced. Conventionally, thin film transistors such as CPUs, DRAMs, image processing circuits, and audio processing circuits that require high-speed operation have a short channel structure. However, when the channel length is short, the threshold value decreases and the cut-off current decreases. There was a problem of increasing. However, the thin film transistor of this embodiment can reduce the cut-off current with a short channel structure. By using such a thin film transistor at a key point, the power consumption of the entire semiconductor device can be reduced. For example, it is possible to reduce power consumption during standby by connecting such a thin film transistor between a thin film transistor for logic and a power source and turning it on during operation and turning it off during non-operation. It becomes. Alternatively, power consumption can be reduced by forming logic with the thin film transistors in a block that does not particularly require high-speed operation.

    Simulation results of current-voltage (IV) characteristics of a p-channel thin film transistor having a low-concentration n-type impurity region will be described with reference to FIGS. 14A assumes a model diagram shown in FIG. 14B, and a p-channel in which a standard p-channel thin film transistor and a low-concentration n-type impurity region (hereinafter referred to as n−) are provided on the drain side. The IV characteristic of a thin film transistor is shown.

FIG. 14B illustrates the structure of each thin film transistor. The structure F is a standard p-channel thin film transistor having Loff, the structure G is a p-channel thin film transistor with an n ⁻ width of 100 nm, and the structure H is a p-channel thin film transistor with an n ⁻ width of 300 nm. In addition, L / W of each thin film transistor is 1000/20000 nm, the width of the Loff region is 300 nm, the thickness of the gate insulating layer is 20 nm, and the impurity concentration of the source region and the drain region (denoted as p ⁺ ) is 1 × 10 ^20. The IV characteristics were simulated by setting the impurity concentration of cm ⁻³ , the Loff region to 1 × 10 ¹⁸ cm ⁻³ , ^and the impurity concentration of p ⁻ to 1 × 10 ¹⁸ cm ⁻³ .

In FIG. 14A, the solid line indicates the IV characteristics of the structure F, and the broken line indicates the IV characteristics of the structures G and H each having p ⁻ . It can be seen that by having n ⁻ , the threshold value of the thin film transistor is shifted to the negative side. It can also be seen that the shift amount of the threshold value increases as the width of n− increases (that is, in the structure H than in the structure G).

FIG. 15 shows simulation results of IV characteristics of a p-channel thin film transistor having n ⁻ on the source side. FIG. 15A assumes a model diagram shown in FIG. 15B and is a p-channel transistor having a standard p-channel thin film transistor and a second n-type impurity region (hereinafter referred to as n−) on the source side. The IV characteristic of a thin-film transistor is shown.

FIG. 15B illustrates the structure of each thin film transistor. The structure F is the same as the standard p-channel thin film transistor shown in FIG. 15B, the structure I is a p-channel thin film transistor with an n ⁻ width of 100 nm, and the structure J has an n ⁻ width of 300 nm. This is a p-channel thin film transistor. Further, the L / W, Loff region width, gate insulating layer thickness, and p ⁺ concentration of each thin film transistor were the same as those used in FIG.

In FIG. 15A, the solid line indicates the IV characteristics of the structure F, and the broken line indicates the IV characteristics of the structure I and the structure J each having n ⁻ . By having n ⁻ , the threshold value of the thin film transistor is shifted to the negative side. In addition, the threshold shift amount increases as the width of n− increases (that is, in the structure J than in the structure I). Further, the cut-off current (Icut) is lower than that of a standard p-channel thin film transistor. That is, like an n-channel thin film transistor, high-speed operation is possible and power consumption can be reduced.

  This embodiment mode can be freely combined with any one of Embodiment Modes 1 to 3.

(Embodiment 5)
An embodiment of the present invention will be described with reference to FIGS. This embodiment shows an example in which a semiconductor nonvolatile memory element (hereinafter referred to as a memory transistor) is formed in the semiconductor device including the thin film transistor manufactured in Embodiment 3. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    As in Embodiment 3, a base film 401 a and a base film 401 b are stacked over the substrate 400 as base films to form a semiconductor layer 402, a semiconductor layer 403, a semiconductor layer 404, and a semiconductor layer 405. The semiconductor layer 402, the semiconductor layer 403, the semiconductor layer 404, and the semiconductor layer 405 are formed by crystallizing an amorphous semiconductor film by laser irradiation and patterning the formed crystalline semiconductor film. In this embodiment mode, silicon is used as a material for the semiconductor layer, and the amorphous silicon film is irradiated with laser light to form a crystalline silicon film having continuously grown crystal grains. Note that the semiconductor layer 402, the semiconductor layer 403, the semiconductor layer 404, and the semiconductor layer 405 are formed so that a channel formation region of a thin film transistor to be formed later is parallel to the scanning direction of the laser light. In this embodiment mode, laser light having a pulsed laser light oscillation frequency of 80 MHz is used as the laser light. By forming single crystal grains that extend long along the scanning direction of the laser light, it is possible to form a semiconductor film in which at least crystal grain boundaries that hinder the movement of carriers in the thin film transistor do not exist.

  An insulating film 480, an insulating film 481, an insulating film 482, and an insulating film 483 are formed over the semiconductor layer 402, the semiconductor layer 403, the semiconductor layer 404, the semiconductor layer 405, and the substrate 400, and the insulating film 406 is formed over them. To do. The insulating film 480, the insulating film 481, the insulating film 482, the insulating film 483, and the insulating film 406 formed over them have a thickness of 1 to 100 nm, preferably 1 to 10 nm, and more preferably 2 to 5 nm. It is desirable. The insulating film 480, the insulating film 481, the insulating film 482, the insulating film 483, and the insulating film 406 formed thereon function later as a tunnel oxide film in the memory transistor and as a part of the gate insulating layer in the thin film transistor. Therefore, the thinner the insulating film 480, the insulating film 481, the insulating film 482, the insulating film 483 and the insulating film 406 formed thereover, the thinner the tunnel current, the higher the speed of operation, which is preferable. Further, as the insulating film 480, the insulating film 481, the insulating film 482, the insulating film 483, and the insulating film 406 formed thereon are thinner, charges can be accumulated in the floating gate electrode at a lower voltage. is there. As a result, power consumption of a semiconductor device formed later can be reduced.

  As a method for forming the insulating film 480, the insulating film 481, the insulating film 482, and the insulating film 483, the surface of the semiconductor region is oxidized using a GRTA method, an LRTA method, or the like, and a thermal oxide film is formed. An insulating film can be formed. In addition to this method, a CVD method, a coating method, or the like may be used. The insulating film 406 can be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. Alternatively, a stacked structure such as a stacked layer of a silicon oxide film and a silicon nitride film or a stacked layer of a silicon oxide film, a silicon nitride film, and a silicon oxide film may be employed from the substrate 400 side.

  In this embodiment, a silicon oxide film is formed as the insulating film 480, the insulating film 481, the insulating film 482, and the insulating film 483, and a silicon nitride film is formed as the insulating film 406. After removing the natural oxide film formed on the surfaces of the semiconductor layer 402, the semiconductor layer 403, the semiconductor layer 404, and the semiconductor layer 405, the semiconductor layer 402, the semiconductor are exposed to ozone water containing hydroxy radicals for several tens of seconds to several minutes. Silicon oxide films are formed on the surfaces of the layer 403, the semiconductor layer 404, and the semiconductor layer 405. After that, the silicon oxide film is further densified by a GRTA method, and an insulating film 480, an insulating film 481, an insulating film 482, and an insulating film 483 having a thickness of 1 to 2 nm are formed. By this method, processing can be performed in a short time and at a high temperature, so that a dense and thin insulating film can be formed without stretching the substrate. Next, a silicon nitride oxide film with a thickness of 1 to 5 nm is formed as the insulating film 406 over the silicon oxide film.

  Conductive particles or semiconductor particles (hereinafter referred to as dispersed particles) 407 dispersed over the insulating film 406 are formed (see FIG. 16A). As a method for manufacturing the dispersed particles, a known method such as a sputtering method, a plasma CVD method, an LPCVD method, a vapor deposition method, or a droplet discharge method can be used. When dispersed particles are formed by a plasma CVD method, an LPCVD method, a vapor deposition method, a droplet discharge method, or the like, the impact on the insulating film 406 at the time of film formation can be reduced. It is possible to suppress. As a result, a highly reliable semiconductor device can be manufactured. Further, after forming a conductive film or a semiconductor film by the above method, the dispersed particles can be formed by etching into a desired shape. The size of the dispersed particles is 0.1 to 10 nm, preferably 2 to 5 nm. Moreover, as a material of the conductive particles, gold, silver, copper, palladium, platinum, cobalt, tungsten, nickel, or the like can be used. As a material of the semiconductor particles, silicon (Si), germanium (Ge), a silicon germanium alloy, or the like can be used. In this embodiment, here, silicon microcrystals are formed as the dispersed particles 407 by a plasma CVD method (see FIG. 16A).

  An insulating film is formed over the dispersed particles 407 and the insulating film 406. As the insulating film, a silicon nitride film or a silicon nitride oxide film with a thickness of 10 to 20 nm is formed by a plasma CVD method.

  Next, a mask is formed over the dispersed particles 407 over the semiconductor layer 402 to be a memory transistor later.

A part of the dispersed particles 407 is etched using a mask to form the insulating layer 408 having the floating gate electrode 410. As a method for removing the insulating film and the dispersed particles 407, a known etching method such as a dry etching method or a wet etching method can be used. In this embodiment mode, the insulating film is removed by dry etching so that the dispersed particles 407 are exposed. Note that if dry etching is used when the insulating film 406 over which the dispersed particles 407 are formed is thin, defects may occur in the insulating film 406 due to plasma bombardment. For this reason, it is preferable to remove by wet etching. Here, silicon microcrystals that are dispersed particles are removed by a wet etching method using an NMD ₃ solution (an aqueous solution containing 0.2 to 0.5% tetramethylammonium hydroxide) or the like.

  The floating gate electrode is formed of dispersed particles. For this reason, when the insulating film 406 functioning as a tunnel oxide film has a defect, it is possible to prevent all charges accumulated in the floating gate electrode from flowing into the semiconductor region from the defect. As a result, a highly reliable semiconductor memory transistor can be formed.

  Next, after the mask is removed, an insulating film 409 is formed over the insulating layer 408 and the insulating film 406 having the floating gate electrode 410 (see FIG. 16B). The insulating film 409 has a thickness of 1 to 100 nm, preferably 10 to 70 nm, and more preferably 10 to 30 nm. The insulating film 409 needs to maintain insulation between the floating gate electrode 410 and a gate electrode layer formed later in the memory transistor. For this reason, it is preferable to set the film thickness so that the leakage current does not increase between them. The insulating film 409 can be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film, similarly to the insulating film 406. Note that it is preferable to form a silicon oxide film in contact with the semiconductor layer because an interface state between the gate insulating film and the semiconductor region is lowered. Here, the insulating film 409 is formed to have a stacked structure of a silicon oxide film with a thickness of 10 nm and a silicon nitride film with a thickness of 20 nm.

  Thereafter, after forming the insulating film 409, the dispersed particles and a mask pattern covering them may be formed to form the second floating gate electrode. Furthermore, the same process may be repeated to form a plurality of stacked floating gate electrodes.

    Over the insulating film 409, a conductive film is formed using W. In this embodiment mode, W is used for the gate electrode layer. The conductive film is etched to be a thin line, so that the gate electrode layer 411, the gate electrode layer 412, the gate electrode layer 413, and the gate electrode layer 414 are formed (see FIG. 16C). A mask 461 made of a resist is formed so as to cover the semiconductor layers 402 to 405.

Using the doping apparatus shown in FIG. 1, an impurity element 451 imparting p-type conductivity is added to the semiconductor layer 405 obliquely toward the surface of the semiconductor layer using the gate electrode layer 414 as a mask, so that a first p-type impurity region is formed. 415a and a first p-type impurity region 415b are formed (see FIG. 16D). Note that FIG. 16D shows a horizontal view of the substrate for simplification, but in actuality, doping is performed by tilting the substrate and moving it in one direction. Since the impurity element 451 imparting p-type conductivity is doped obliquely, the first p-type impurity region 415b is also formed in the semiconductor layer 405 covered with the gate electrode layer 414. On the other hand, since the gate electrode layer 414 serves as a mask to shield the impurity element 451 imparting p-type conductivity, the first p-type impurity region 415a is formed in the semiconductor layer 405 under which the gate electrode layer 414 is formed. Not formed. Here, the first p-type impurity region 415a and the first p-type impurity region 415b include the impurity element imparting p-type at a concentration of about 5 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ^3. Added. Further, the impurity element imparting p-type conductivity may be added so as to be contained at a concentration of about 5 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity.

Next, the mask 461 is removed, and a mask 462 made of a resist that covers the semiconductor layer 403 is formed. The mask 462 may be newly formed or may be formed by processing the mask 461. Using the gate electrode layer 411, the gate electrode layer 413, and the gate electrode layer 414 as a mask, an impurity element imparting n-type conductivity is added to the semiconductor layer 402, the semiconductor layer 404, and the semiconductor layer 405 perpendicular to the surface of the semiconductor layer. N-type impurity region 416a, first n-type impurity region 416b, first n-type impurity region 417a, first n-type impurity region 417b, first n-type impurity region 418a, first n-type impurity region 418b is formed (see FIG. 17A). An impurity element imparting p-type is added to the first p-type impurity region 415a and the first p-type impurity region 415b, and thus an impurity imparting n-type is inverted so as to be inverted to the n-type impurity region. Add elements. First n-type impurity region 416a, first n-type impurity region 416b, first n-type impurity region 417a, first n-type impurity region 417b, first n-type impurity region 418a, first n-type impurity region The impurity region 418b is typically formed to include an impurity element imparting n-type at a concentration of 1 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ . In this embodiment mode, phosphorus (P) is used as the impurity element imparting n-type conductivity. Since the impurity element 452 imparting n-type conductivity is added vertically, the n-type impurity element 452 is shielded by the gate electrode layer 411, the gate electrode layer 413, and the gate electrode layer 414, so that the gate electrode layer 411, the gate electrode layer 413, and the gate electrode layer 414 It is not added to the regions of the semiconductor layer 402, the semiconductor layer 404, and the semiconductor layer 405 that are covered. Therefore, a part of the first p-type impurity region formed in the semiconductor layer under the gate electrode layer 414 remains and becomes the second p-type impurity region 435. The second p-type impurity region 435 is formed as a Lov region.

The mask 462 is removed by etching or the like, so that a mask 463a and a mask 463b that cover the semiconductor layer 402, the semiconductor layer 404, and the semiconductor layer 405 are formed. Using the mask 463a, the mask 463b, and the gate electrode layer 412 as a mask, an impurity element 453 imparting p-type conductivity is added to the semiconductor layer 403 in a direction perpendicular to the surface of the semiconductor layer 403, so that the third p-type impurity region 420a, A third p-type impurity region 420b is formed (see FIG. 17B). Here, the third p-type impurity region 420a and the third p-type impurity region 420b include the impurity element imparting p-type at a concentration of about 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ^3. Added. In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity.

    The masks 463a and 463b are removed by etching or the like, an insulating layer is formed over the insulating film 409, the gate electrode layer 411, the gate electrode layer 412, the gate electrode layer 413, and the gate electrode layer 414, and anisotropic etching is performed. A sidewall 421, a sidewall 422, a sidewall 423, and a sidewall 424 are formed on side surfaces of the gate electrode layer 411, the gate electrode layer 412, the gate electrode layer 413, and the gate electrode layer 414 (see FIG. 17C). In this embodiment mode, silicon oxide is used as an insulating layer for forming the sidewall. When the sidewall 421, the sidewall 422, the sidewall 423, and the sidewall 424 are formed, an insulating layer is formed over the gate electrode layer 411, the gate electrode layer 412, the gate electrode layer 413, and the gate electrode layer 414. A protective film may be formed over the gate electrode layer.

A mask 464 made of a resist that covers the semiconductor layer 403 is formed. The side wall 421, the side wall 423, the side wall 424, the gate electrode layer 411, the gate electrode layer 413, and the gate electrode layer 414 are used as masks, and the semiconductor layer 402, the semiconductor layer 404, and the semiconductor layer 405 are n perpendicular to the surface of the semiconductor layer. An impurity element 454 imparting a type is added, and the second n-type impurity region 425a, the second n-type impurity region 425b, the second n-type impurity region 428a, the second n-type impurity region 428b, An n-type impurity region 431a and a second n-type impurity region 431b are formed (see FIG. 18A). Since the impurity element 454 imparting n-type conductivity is not added to the semiconductor layer covered with the sidewalls, the third n-type impurity region 426a, the third n-type impurity region 426b, which are low-concentration impurity regions, 3 n-type impurity regions 429a, third n-type impurity regions 429b, third n-type impurity regions 432a, and third n-type impurity regions 432b. Second n-type impurity region 425a, second n-type impurity region 425b, second n-type impurity region 428a, second n-type impurity region 428b, second n-type impurity region 431a, second n-type Since the impurity region 431b is a high-concentration impurity region, it functions as a source region or a drain region. Second n-type impurity region 425a, second n-type impurity region 425b, second n-type impurity region 428a, second n-type impurity region 428b, second n-type impurity region 431a, second n-type The impurity region 431b is added so that an impurity element imparting n-type conductivity is contained at a concentration of about 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ³ . In this embodiment mode, phosphorus (P) is used as the impurity element imparting n-type conductivity.

  Further, the third n-type impurity region 426a, the third n-type impurity region 426b, the third n-type impurity region 429a, the third n-type impurity region 429b, and the third n-type impurity which are low-concentration impurity regions. Since the region 432a and the third n-type impurity region 432b are formed using Loff regions that are not covered with the gate electrode layer 411, the gate electrode layer 413, and the gate electrode layer 414, the electric field in the vicinity of the drain is relaxed and hot carriers are formed. This has the effect of preventing deterioration due to injection and reducing off-current. As a result, a highly reliable semiconductor device with low power consumption can be manufactured. Note that a channel formation region 427, a channel formation region 430, and a channel formation region 434 are formed in the semiconductor layer 402, the semiconductor layer 404, and the semiconductor layer 405.

Masks 465 a and 465 b made of resist are formed to cover the semiconductor layer 402, the semiconductor layer 404, and the semiconductor layer 405. Using the mask 465a, the mask 465b, the sidewall 422, and the gate electrode layer 412 as masks, an impurity element 455 imparting p-type conductivity is added to the semiconductor layer 403 in a direction perpendicular to the surface of the semiconductor layer 403, so that a fourth p-type impurity is added. An impurity region 436a, a fourth p-type impurity region 436b, a fifth p-type impurity region 437a, and a fifth p-type impurity region 437b are formed (see FIG. 18B). Here, the fourth p-type impurity region 436a and the fourth p-type impurity region 436b include the impurity element imparting p-type at a concentration of about 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ^3. Added. Further, the fifth p-type impurity region 437a and the fifth p-type impurity region 437b are added so that the impurity element imparting p-type is contained at a concentration of about 5 × 10 ^{18 to} 5 × 10 ¹⁹ / cm ^3. To do. In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity. Note that a channel formation region 438 is formed in the semiconductor layer 403.

  The fourth p-type impurity region 436a and the fourth p-type impurity region 436b are high-concentration impurity regions and function as a source region or a drain region. The fifth p-type impurity region 437a and the fifth p-type impurity region 437b are low-concentration p-type impurity regions and are formed as Loff regions that are not covered with the gate electrode layer. Since the fifth p-type impurity region 437a and the fifth p-type impurity region 437b are not covered with the gate electrode layer, the electric field in the vicinity of the drain is relaxed to prevent deterioration due to hot carrier injection, and the off-current is reduced. effective. As a result, a highly reliable semiconductor device with low power consumption can be manufactured.

    An insulating film 443 for hydrogenation is formed as appropriate by performing heat treatment, laser irradiation, or the like for activating the impurity element. Hydrogenation is performed by heat treatment, so that the insulating layer 446 is formed. The heat treatment for activating the impurity element and the heat treatment for hydrogenation may be performed in the same process, and the process can be simplified. In this embodiment, a silicon nitride oxide film and a silicon oxynitride film are successively formed as the insulating layer 446 to have a stacked structure.

    Openings (contact holes) reaching the source region and the drain region are formed in the insulating layer 446, the insulating film 443, the insulating film 406, the insulating film 409, the insulating film 480, the insulating film 481, the insulating film 482, and the insulating film 483. A source or drain electrode layer 440a in contact with a source region or a drain region, a source or drain electrode layer 440b, a source or drain electrode layer 441a, a source or drain electrode layer 441b, a source electrode layer or The drain electrode layer 442a, the source or drain electrode layer 442b, the source or drain electrode layer 439a, and the source or drain electrode layer 439b are formed (see FIG. 19A). In this embodiment, a stack formed of Al, Ti, and Al in this order is used as the source electrode layer or the drain electrode layer.

    As shown in FIG. 19B, an insulating layer 444 having an opening reaching the source electrode layer or the drain electrode layer is formed over the source electrode layer or the drain electrode layer, and a wiring layer 445 is formed in the opening. It is good also as a structure to do. In this embodiment, an insulating layer containing a siloxane polymer is used as the insulating layer 444, and the wiring layer 445 is formed using a Ti stack formed of Ti and Al in this order.

    A semiconductor device including the memory transistor 470, the p-channel thin film transistor 471, the n-channel thin film transistor 472, and the n-channel thin film transistor 473 including the low-concentration p-type impurity region can be formed over the same substrate. Since the memory transistor and the thin film transistor in the semiconductor device of this embodiment are formed using a semiconductor region in which there is almost no crystal grain boundary in the channel direction, high-speed operation is possible. In addition, since the n-channel thin film transistor including the low-concentration p-type impurity region is included, a semiconductor device such as an ID chip that can operate at high speed and has low power consumption can be formed.

    In addition, the p-channel thin film transistor 471, the n-channel thin film transistor 472, and the n-channel thin film transistor 473 including a low-concentration p-type impurity region which are manufactured in this embodiment are each formed as a gate insulating layer on the surface of the semiconductor layer. The insulating film 481, the insulating film 482, the insulating film 483, and a stack including the insulating film 406 and the insulating film 409 formed thereon are used. Therefore, a thin film transistor having high withstand voltage and high withstand voltage characteristics can be obtained. Note that when the insulating film 409 is removed and the gate insulating layer is formed by stacking the insulating film 481, the insulating film 482, the insulating film 483, and the insulating film 406 formed thereon, a thin film transistor capable of high-speed operation is obtained. be able to. In this manner, a thin film transistor having characteristics that can cope with the required function can be manufactured, whereby a semiconductor device can be manufactured.

  When the present invention is used, an impurity region having an impurity element imparting a different conductivity type can be formed in a semiconductor layer; thus, fine characteristics of a thin film transistor can be controlled. Accordingly, a thin film transistor having a required function can be formed through a simple process, and a semiconductor device with high reliability and electrical characteristics can be manufactured at low cost. That is, a functional circuit that emphasizes high-speed operation such as a CPU, DRAM, an image processing circuit, and an audio processing circuit, and a drive circuit that emphasizes high breakdown voltage characteristics such as a buffer circuit, a shift register circuit, a level shifter circuit, and a sampling circuit. It can be formed on the same substrate. For this reason, semiconductor devices having elements having various functions and structures, such as a system LSI, can be manufactured on the same substrate.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 to 4.

(Embodiment 6)
One of semiconductor devices that can be formed using a method for manufacturing a semiconductor device using the doping apparatus of the present invention is an ID chip. An ID chip is a semiconductor device capable of transmitting and receiving data such as identification information wirelessly, and its practical use is being promoted in various fields. The ID chip is also called a wireless tag, an RFID (Radio frequency identification) tag, or an IC tag. In addition, an ID chip using a glass substrate can be called an IDG chip (Identification Glass Chip), and an ID chip using a flexible substrate can be called an IDF chip (Identification Flexible Chip). .

FIG. 20A is a perspective view illustrating one mode of an ID chip which is one of semiconductor devices. 1101 is an integrated circuit, 1102 is an antenna, and the antenna 1102 is connected to the integrated circuit 1101. Reference numeral 1103 denotes a support that also functions as a cover material, and 1104 corresponds to a cover material. The integrated circuit 1101 and the antenna 1102 are formed over the support 1103, and the cover material 1104 overlaps the support 1103 so as to cover the integrated circuit 1101 and the antenna 1102. Note that the cover material 1104 is not necessarily used, but the mechanical strength of the ID chip can be increased by covering the integrated circuit 1101 and the antenna 1102 with the cover material 1104.

  FIG. 20B is a perspective view showing one mode of an IC card which is one of semiconductor devices. Reference numeral 1105 denotes an integrated circuit, 1106 denotes an antenna, and the antenna 1106 is connected to the integrated circuit 1105. Reference numeral 1108 denotes a substrate that functions as an inlet sheet, and reference numerals 1107 and 1109 denote cover materials. The integrated circuit 1105 and the antenna 1106 are formed over a substrate 1108, and the substrate 1108 is sandwiched between two cover materials 1107 and 1109. Note that the IC card may include a display device connected to the integrated circuit 1105.

  In this embodiment mode, an example in which a stacked body including an integrated circuit and an antenna formed over an interlayer insulating film of the integrated circuit is bonded with different cover materials is described; however, the present invention is not limited thereto, and an antenna is formed. The cover material and the integrated circuit may be fixed with an adhesive. At this time, the integrated circuit and the antenna are connected by performing UV treatment or ultrasonic treatment using an anisotropic conductive adhesive or an anisotropic conductive film, but the present invention is not limited to this method, and various Can be used.

For the support 1103 and the cover material 1104, a flexible material such as plastic, organic resin, paper, fiber, or carbon graphite can be used. By using a biodegradable resin for the cover material, it is decomposed into bacteria and reduced to the soil. Furthermore, since the integrated circuit of this embodiment is formed using silicon, aluminum, oxygen, nitrogen, or the like, a pollution-free ID chip can be formed. Further, by using an incineration-free pollution material such as paper, fiber, carbon graphite, etc., the used ID chip can be incinerated or cut. In addition, ID chips using these materials are non-polluting because they do not generate toxic gas even when incinerated.

The thickness of the integrated circuit 1101 sandwiched between the support 1103 and the cover material 1104 may be 5 μm or less, preferably 0.1 μm to 3 μm. Further, when the thickness when the support 1103 and the cover material 1104 are overlapped is d, the thickness of the support 1103 and the cover material 1104 is preferably (d / 2) ± 30 μm, more preferably (d / 2) Set to ± 10 μm. The thickness of the support 1103 and the cover material 1104 is preferably 10 μm to 200 μm. Furthermore, the area of the integrated circuit 1101 is 5 mm square (25 mm ² ) or less, and desirably has an area of 0.3 mm square to 4 mm square (0.09 mm ^{2 to} 16 mm ² ).

  Since the support 1103 and the cover material 1104 are made of an organic resin material, they have a strong characteristic against bending. In addition, the integrated circuit 1101 itself formed by a separation process also has a strong characteristic against bending as compared with a single crystal semiconductor. Since the integrated circuit 1101, the support 1103, and the cover material 1104 can be in close contact with each other so that there is no gap, the completed ID chip itself has a strong characteristic against bending. The integrated circuit 1101 surrounded by the support 1103 and the cover material 1104 may be arranged on the surface or inside of another solid object, or may be embedded in paper.

  In this embodiment mode, an example in which a stacked body including an integrated circuit and an antenna formed over an interlayer insulating film of the integrated circuit is bonded with different cover materials is described; however, the present invention is not limited thereto, and an antenna is formed. The cover material and the integrated circuit may be fixed with an adhesive. At this time, the integrated circuit and the antenna are connected by performing UV treatment or ultrasonic treatment using an anisotropic conductive adhesive or an anisotropic conductive film, but the present invention is not limited to this method, and various Can be used. Further, the antenna is not necessarily equal to the size of the ID chip, and may be larger or smaller and may be set as appropriate. For signal transmission / reception, radio waves such as electromagnetic waves and light can be used.

  This embodiment mode can be freely combined with any of Embodiment Modes 1 to 5 described above.

(Embodiment 7)
In this embodiment, a block diagram of one chip of a processor such as a CPU which is a typical example of a semiconductor device will be described with reference to FIG.

  First, when the operation code is input to the data bus interface 1001, the analysis circuit 1003 (also referred to as instruction decoder) decodes the code, and the signal is input to the control signal generation circuit 1004 (CPU Timing Control). When a signal is input, a control signal is output from the control signal generation circuit 1004 to the arithmetic circuit 1009 (hereinafter referred to as ALU) and the storage circuit 1010 (hereinafter referred to as register).

  The control signal generation circuit 1004 includes an ALU controller 1005 (hereinafter referred to as ACON) that controls the ALU 1009, a circuit 1006 (hereinafter referred to as RCON) that controls the register 1010, and a timing controller 1007 (hereinafter referred to as RCON) that controls timing. And an interrupt controller 1008 (hereinafter referred to as ICON) for controlling interrupts.

  On the other hand, when an operand is input to the data bus interface 1001, it is output to the ALU 1009 and the register 1010. Then, processing based on the control signal input from the control signal generation circuit 1004 (for example, a memory read cycle, a memory write cycle, an I / O read cycle, an I / O write cycle, etc.) is performed.

  Note that the register 1010 includes a general-purpose register, a stack pointer (SP), a program counter (PC), and the like.

  The address controller 1011 (hereinafter referred to as ADRC) outputs a 16-bit address.

  Note that the configuration of the processor described in this embodiment is merely an example and is not limited. Therefore, a known processor configuration other than the configuration described in this embodiment can also be used.

  This embodiment mode can be used in combination with each of Embodiment Modes 1 to 6.

(Embodiment 8)
Here, a case where the present invention is applied to a system LSI which is an example of a semiconductor device will be described with reference to FIG.

  The system LSI is an LSI that is incorporated in a device that assumes a specific application and constitutes a system that controls the device and performs data processing. Applications are diverse and include, for example, mobile phones, PDAs, DSCs, televisions, printers, FAX machines, game machines, car navigation systems, DVD players, and the like.

  FIG. 22 shows an example of a system LSI. The system LSI typically includes a CPU core 1601, a nonvolatile memory (also referred to as NVM) 1604, a clock controller 1603, a main memory 1602, a memory controller 1605, an interrupt controller 1606, an I / O port 1607, and the like. Of course, the system LSI shown in FIG. 22 is a simplified example, and various circuit designs are performed on an actual system LSI depending on the application.

  The memory transistor manufactured in Embodiment 5 can be used for the NVM 1604.

  In addition, as a transistor constituting the CPU core 1601, the clock controller 1603, the main memory 1602, the memory controller 1605, the interrupt controller 1606, and the I / O port 1607, a transistor capable of high-speed operation manufactured using the present invention is used. Can do. Thus, various circuits can be manufactured on the same substrate.

  This embodiment mode can be used in combination with each of Embodiment Modes 1 to 7.

(Embodiment 9)
In this embodiment, an example in which steps are partly different from those in Embodiment 3 will be described with reference to FIGS.

    As in Embodiment 3, a base film 301 a and a base film 301 b are stacked over the substrate 300 as base films to form a semiconductor layer 302, a semiconductor layer 303, a semiconductor layer 304, and a semiconductor layer 370. The semiconductor layer 302, the semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370 are formed by crystallizing an amorphous semiconductor film by laser irradiation and patterning the formed crystalline semiconductor film. In this embodiment mode, silicon is used as a material for the semiconductor layer, and the amorphous silicon film is irradiated with laser light to form a crystalline silicon film having continuously grown crystal grains. Note that the semiconductor layer 302, the semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370 are formed so that a channel formation region of a thin film transistor to be formed later is parallel to the scanning direction of the laser light.

    A gate insulating layer 395 is formed over the semiconductor layer 302, the semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370, and a first conductive film 396 and a second conductive film 397 are formed (see FIG. 23A). . In this embodiment, a thin silicon oxide film with a thickness of 2 to 5 nm is formed as a first insulating film over the semiconductor layer 302, the semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370 with a GRTA (Gas Rapid A stacked layer of a silicon nitride film, a silicon oxide film, and a silicon nitride film 3 is used as the gate insulating layer 395 over the first insulating film. The first conductive film 396 is formed by sputtering using TaN, and the second conductive film 397 is formed by using W.

    The first conductive film 396 and the second conductive film 397 are etched to be thin lines, and the first gate electrode layer 305, the first gate electrode layer 306, the first gate electrode layer 307, and the first gate are etched. An electrode layer 371, a second gate electrode layer 380, a second gate electrode layer 381, a second gate electrode layer 382, and a second gate electrode layer 379 are formed. A mask 361 made of a resist is stacked to cover the semiconductor layer 302 and the semiconductor layer 303 to form a gate electrode layer.

With the first gate electrode layer 307, the second gate electrode layer 382, the first gate electrode layer 371, and the second gate electrode layer 379 as masks, the impurity element 351 imparting p-type is added to the doping apparatus of FIG. Use to dope diagonally. The first p-type impurity region 308a, the first p-type impurity region 308b, the first p-type impurity region 385a, and the first p-type impurity region 308a are added to the semiconductor layer 304 and the semiconductor layer 370 obliquely toward the surface of the semiconductor layer. A p-type impurity region 385b is formed (see FIG. 23B). Note that although FIG. 23B shows a diagram in which the substrate is horizontal for simplification, the doping is actually performed by tilting the substrate and moving it in one direction. Since the impurity element 351 imparting p-type conductivity is doped obliquely, the first p-type impurity region 308b and the first p-type impurity region 385b include the first gate electrode layer 307 and the first gate electrode layer. The semiconductor layer 304 and the semiconductor layer 370 covered with 371 are also formed. On the other hand, the first gate electrode layer 307 and the first gate electrode layer 371 are used as a mask to shield the impurity element 351 imparting p-type conductivity, so that the first p-type impurity region 308a and the first p-type impurity region 351 are shielded. The impurity region 385a is not formed in the first gate electrode layer 307, the semiconductor layer 304 under which the first gate electrode layer 371 is formed, and the semiconductor layer 370. Here, the first p-type impurity region 308a, the first p-type impurity region 308b, the first p-type impurity region 385a, and the first p-type impurity region 385b have an impurity element imparting p-type of 5 ×. It is added so as to be contained at a concentration of about 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ . Further, the impurity element imparting p-type conductivity may be added so as to be contained at a concentration of about 5 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity.

    In this embodiment, in a thin film transistor including the semiconductor layer 304 to be formed later, a region in which the first p-type impurity region 308b is formed serves as a drain region, and in the thin film transistor including the semiconductor layer 370, the first p-type impurity is formed. A region where the region 385b is formed is a source region. By aligning the channel formation region of the semiconductor layer in parallel with the scanning direction of the laser beam and adding an impurity element obliquely from one direction using the gate electrode layer as a mask, either the source region or the drain region is formed. Only one conductivity impurity region different from the conductivity of the thin film transistor can be formed. By using the present invention, both the thin film transistor having the different one conductive impurity region in the source region and the thin film transistor having the different one conductive impurity region in the drain region can be formed in the same step. Which is set as the source region or the drain region can be freely designed by wirings to be connected, and the present invention can sufficiently cope with such a circuit. Accordingly, characteristics of finer thin film transistors can be controlled and a variety of thin film transistors can be manufactured. Therefore, a highly accurate semiconductor device that requires a plurality of circuits having different functions can be manufactured with high reliability.

Next, the mask 361 is removed, and a mask 362 made of a resist that covers the semiconductor layer 302 is formed. The mask 362 may be newly formed or may be formed by processing the mask 361. Using the first gate electrode layer 306, the first gate electrode layer 307, and the first gate electrode layer 371 as a mask, n-type is imparted to the semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370 perpendicular to the surface of the semiconductor layer. The first n-type impurity region 309a, the first n-type impurity region 309b, the first n-type impurity region 310a, the first n-type impurity region 310b, and the first n-type impurity region are added. 372a and a first n-type impurity region 372b are formed (see FIG. 23C). An impurity element imparting p-type conductivity is added to the first p-type impurity region 308a, the first p-type impurity region 308b, the first p-type impurity region 385a, and the first p-type impurity region 385b. Therefore, an impurity element imparting n-type conductivity is added so as to invert to the n-type impurity region. First n-type impurity region 309a, first n-type impurity region 309b, first n-type impurity region 310a, first n-type impurity region 310b, first n-type impurity region 372a, first n-type impurity region The impurity region 372b is typically formed so as to contain an impurity element imparting n-type at a concentration of 1 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ . In this embodiment mode, phosphorus (P) is used as the impurity element imparting n-type conductivity. Since the impurity element 352 imparting n-type conductivity is added vertically, the impurity element 352 is shielded by the first gate electrode layer 306, the first gate electrode layer 307, and the first gate electrode layer 371, so that the first gate electrode layer 306, the first gate electrode layer 307, and the semiconductor layer 303 covered with the first gate electrode layer 371, the semiconductor layer 304, and the semiconductor layer 370 are not added. Accordingly, part of the first p-type impurity region formed in the semiconductor layer below the first gate electrode layer 307 and the first gate electrode layer 371 remains, and the second p-type impurity region 324, A second p-type impurity region 377 is formed. The second p-type impurity region 324 is formed as a Lov region on the drain side, and the second p-type impurity region 377 is formed as a Lov region on the source side.

The mask 362 is removed by etching or the like, and a mask 364 made of a resist that covers the semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370 is formed. With the mask 364 and the first gate electrode layer 305 as masks, an impurity element 354 imparting p-type conductivity is added to the semiconductor layer 302 in a direction perpendicular to the surface of the semiconductor layer 302, so that third p-type impurity regions 316a, A third p-type impurity region 316b is formed (see FIG. 24A). Here, the third p-type impurity region 316a and the third p-type impurity region 316b include the impurity element imparting p-type at a concentration of about 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ^3. Added. In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity.

    The mask 364 is removed by etching or the like, and the gate insulating layer 395, the first gate electrode layer 305, the first gate electrode layer 306, the first gate electrode layer 307, the first gate electrode layer 371, and the second gate An insulating layer is formed over the electrode layer 380, the second gate electrode layer 381, the second gate electrode layer 382, and the second gate electrode layer 379. Anisotropic etching is performed on the insulating layer, so that the first gate electrode layer 305, the second gate electrode layer 380, the first gate electrode layer 306, the second gate electrode layer 381, the first gate electrode layer 307, Sidewalls 311, 312, 313, and 373 are formed on side surfaces of the second gate electrode layer 382, the first gate electrode layer 371, and the second gate electrode layer 379. In this embodiment mode, silicon oxide is used as an insulating layer for forming the sidewall. In addition, when the sidewall 311, the sidewall 312, the sidewall 313, and the sidewall 373 are formed, the semiconductor layer 302, the semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370 are etched as etching stoppers, so that the semiconductor layer 302, the semiconductor The layer 303, the semiconductor layer 304, and the semiconductor layer 370 are exposed, and the insulating layer 721, the insulating layer 722, the insulating layer 723, and the insulating layer 724 are formed.

    In this embodiment, when the insulating layer is etched, the insulating layer is formed over the first gate electrode layer 305, the first gate electrode layer 306, the first gate electrode layer 307, and the first gate electrode layer 370. A sidewall 311, a sidewall 312, a sidewall 313, and a sidewall 373 are formed so as to remain (see FIG. 24B). In addition, after the insulating layer is etched until the first gate electrode layer 305, the first gate electrode layer 306, the first gate electrode layer 307, and the first gate electrode layer 370 are exposed to form sidewalls, A protective film may be formed over the first gate electrode layer 305, the first gate electrode layer 306, the first gate electrode layer 307, and the first gate electrode layer 370. In this manner, the first gate electrode layer 305, the first gate electrode layer 306, the first gate electrode layer 307, and the first gate electrode layer 370 are protected, so that the first gate electrode is etched. The film loss of the electrode layer 305, the first gate electrode layer 306, the first gate electrode layer 307, and the first gate electrode layer 370 can be prevented.

A mask 363 made of a resist that covers the semiconductor layer 302 is formed. The semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370 are formed using the sidewall 312, the sidewall 313, the sidewall 373, the first gate electrode layer 306, the first gate electrode layer 307, and the first gate electrode layer 371 as a mask. An impurity element 353 that imparts n-type conductivity is added to the surface of the semiconductor layer so that the second n-type impurity region 314a, the second n-type impurity region 314b, the second n-type impurity region 315a, and the second n-type impurity region 315a An n-type impurity region 315b, a second n-type impurity region 374a, and a second n-type impurity region 374b are formed (see FIG. 24C). Since the impurity element 353 imparting n-type is not added to the semiconductor layer covered with the sidewalls, the third n-type impurity region 320a, the third n-type impurity region 320b, which are low-concentration n-type regions, A third n-type impurity region 322a, a third n-type impurity region 322b, a third n-type impurity region 375a, and a third n-type impurity region 375b are formed. Note that a channel formation region 321, a channel formation region 323, and a channel formation region 376 are formed in the semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370. Second n-type impurity region 314a, second n-type impurity region 314b, second n-type impurity region 315a, second n-type impurity region 315b, second n-type impurity region 374a, second n-type impurity region Since the impurity region 374b is a high-concentration impurity region, it functions as a source region or a drain region. In this embodiment mode, the second n-type impurity region 315b on the side where the second p-type impurity region 324 is formed is used as a drain region, and the side on which the second p-type impurity region 377 is formed. A certain second n-type impurity region 374b is used as a source region. Therefore, the second n-type impurity region 315a functions as a source region, and the second n-type impurity region 374a functions as a drain region. In the second n-type impurity region 314a, the second n-type impurity region 314b, the second n-type impurity region 315a, and the second n-type impurity region 315b, an impurity element imparting n-type conductivity is 5 × 10 ¹⁹ to It is added so as to be contained at a concentration of about 5 × 10 ²⁰ / cm ³ . In this embodiment mode, phosphorus (P) is used as the impurity element imparting n-type conductivity.

  On the other hand, the third n-type impurity region 320a, the third n-type impurity region 320b, the third n-type impurity region 322a, the third n-type impurity region 322b, and the third n-type impurity, which are low-concentration impurity regions. Since the region 375a and the third n-type impurity region 375b are Loff regions that are not covered with the first gate electrode layer and the second gate electrode layer, the electric field in the vicinity of the drain is relaxed to prevent deterioration due to hot carrier injection. This has the effect of reducing the off current. As a result, a semiconductor device with high reliability and low power consumption can be manufactured while being capable of high-speed operation.

A mask 365 made of a resist that covers the semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370 is formed. The mask 365 may be used as it is without removing the mask 364, may be formed by processing the mask 364, or may be newly formed. Using the mask 365 and the first gate electrode layer 305 as a mask, an impurity element 355 imparting p-type conductivity is added to the semiconductor layer 302 in a direction perpendicular to the surface of the semiconductor layer 302, so that fourth p-type impurity regions 317a, A fourth p-type impurity region 317b, a fifth p-type impurity region 318a, and a fifth p-type impurity region 318b are formed (see FIG. 25A). Here, the fourth p-type impurity region 317a and the fourth p-type impurity region 317b include the impurity element imparting p-type at a concentration of about 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ^3. Added. Further, the fifth p-type impurity region 318a and the fifth p-type impurity region 318b are added so that the impurity element imparting p-type is contained at a concentration of about 5 × 10 ^{18 to} 5 × 10 ¹⁹ / cm ^3. To do. In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity. Note that a channel formation region 319 is formed in the semiconductor layer 302.

  The fourth p-type impurity region 317a and the fourth p-type impurity region 317b are high-concentration impurity regions and function as a source region or a drain region. The fifth p-type impurity region 318a and the fifth p-type impurity region 318b are low-concentration impurity regions and are formed as Loff regions that are not covered with the gate electrode layer. Since the fifth p-type impurity region 318a and the fifth p-type impurity region 318b are Loff regions not covered with the gate electrode layer, the electric field in the vicinity of the drain is relaxed to prevent deterioration due to hot carrier injection and There is an effect of reducing current. As a result, a highly reliable semiconductor device with low power consumption can be manufactured.

    A conductive film 714 is formed over the semiconductor layer 302, the semiconductor layer 303, the semiconductor layer 304, the semiconductor layer 370, the sidewall 311, the sidewall 312, the sidewall 313, and the sidewall 373 (see FIG. 25B). As a material for the conductive film 714, titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), zirconium (Zr), Hf (hafnium), tantalum (Ta), vanadium ( A film containing V), neodymium (Nb), chromium (Cr), platinum (Pt), palladium (Pd), or the like is formed. Here, a titanium film is formed by a sputtering method.

  Next, the silicon in the exposed semiconductor layer of the source region and the drain region is reacted with the conductive film 714 by heat treatment, a GRTA method, an LRTA method, or the like, thereby forming silicide 715a, silicide 715b, silicide 716a, silicide 716b, Silicide 717a and silicide 717b, silicide 725a and silicide 725b are formed. After that, the conductive film 714 that has not reacted with the semiconductor layer is removed (see FIG. 25C).

    An insulating film 325 for hydrogenation is appropriately formed by heat treatment, laser irradiation, or the like for activating the impurity element. Hydrogenation is performed by heat treatment, so that the insulating layer 326 is formed. The heat treatment for activating the impurity element and the heat treatment for hydrogenation may be performed in the same process, and the process can be simplified.

    Openings (contact holes) reaching the source region and the drain region are formed in the insulating layer 326 and the insulating film 325. A source or drain electrode layer 328a in contact with a source region or a drain region, a source or drain electrode layer 328b, a source or drain electrode layer 329a, a source or drain electrode layer 329b, a source electrode layer or A drain electrode layer 327a, a source or drain electrode layer 327b, a source or drain electrode layer 398a, and a source or drain electrode layer 398b are formed (see FIG. 26). In this embodiment, the source or drain electrode layer 327a serves as a source electrode layer, and the source or drain electrode layer 327b serves as a drain electrode layer. On the other hand, the source or drain electrode layer 398a serves as a drain electrode layer, and the source or drain electrode layer 398b serves as a source electrode layer. Therefore, the p-channel thin film transistor 330, the n-channel thin film transistor 331, the n-channel thin film transistor 332 having a low-concentration p-type impurity region on the drain region side, and the n-channel thin film transistor 332 having a low-concentration p-type impurity region on the source region side. A channel thin film transistor 378 is manufactured, and a semiconductor device using the channel thin film transistor 378 is manufactured. In this embodiment mode, a CPU in which a CMOS circuit and a thin film transistor whose characteristics are controlled is provided over the same substrate is manufactured.

  In this embodiment mode, the p-channel thin film transistor 330, the n-channel thin film transistor 331, the n-channel thin film transistor 332 having a low-concentration p-type impurity region on the drain region side, and the n-channel type having a low-concentration p-type impurity region on the source region side. Since the thin film transistor 378 has a silicide structure, the resistance of the source region and the drain region can be reduced, and the speed of the semiconductor device can be increased. Further, since operation at a low voltage is possible, power consumption can be reduced.

  This embodiment mode can be used in combination with each of Embodiment Modes 1 to 7.

(Embodiment 10)
In this embodiment, an example in which the steps of Embodiment 9 are partially changed will be described with reference to FIG. Since the steps are the same as those of the ninth embodiment except that the steps are partially different from those of the ninth embodiment, detailed description of the same steps is omitted here.

  In the step of FIG. 23B in Embodiment 9, an example in which doping is performed once obliquely with respect to the substrate is shown, but in this embodiment, doping at a different angle is performed twice.

  Instead of the step of FIG. 23B, masks 761a and 761b made of resist are formed as shown in FIG. 27A, and the first doping is performed. Since the impurity element 751 imparting p-type conductivity is doped obliquely, the first p-type impurity region 308b is formed in the semiconductor layer 304 covered with the first gate electrode layer 307. On the other hand, since the first gate electrode layer 307 is used as a mask to shield the impurity element 751 imparting p-type conductivity, the first p-type impurity region 308a is formed under the first gate electrode layer 307. The semiconductor layer 304 is not formed.

    Next, the masks 761a and 761b are removed, and a mask 766 made of resist is formed. The mask 766 may be newly formed, or may be formed by processing the masks 761a and 761b.

  Next, as shown in FIG. 27B, the second doping is performed obliquely at an angle different from the first. Since the impurity element 752 imparting p-type conductivity is doped obliquely, the first p-type impurity region 385a is formed in the semiconductor layer 370 covered with the first gate electrode layer 371. On the other hand, since the first gate electrode layer 371 is used as a mask to shield the impurity element 752 imparting p-type conductivity, the first gate electrode layer 371 is formed in the first p-type impurity region 385b. The semiconductor layer 370 is not formed.

Here, the first p-type impurity region 308a, the first p-type impurity region 308b, the first p-type impurity region 385a, and the first p-type impurity region 385b are added to the p-type by the above-described two dopings. Is added so that the impurity element imparting a concentration of 5 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ is contained. Further, the impurity element imparting p-type conductivity may be added so as to be contained at a concentration of about 5 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity.

  In the subsequent steps, according to Embodiment 9, the structure shown in the cross-sectional view of FIG. 27C is obtained. A p-channel thin film transistor 330, an n-channel thin film transistor 331, an n-channel thin film transistor 332 having a low-concentration p-type impurity region on the drain region side, and an n-channel thin film transistor 778 having a low-concentration p-type impurity region 777 on the drain region side. Can be formed.

  Further, this embodiment mode can be used in combination with each of Embodiment Modes 1 to 9.

(Embodiment 11)
A semiconductor device manufactured using the doping apparatus of the present invention has a wide range of uses. For example, an ID chip which is one form of a semiconductor device is used for banknotes, coins, securities, certificates, bearer bonds, and packaging. It can be used in containers, books, recording media, personal items, vehicles, foods, clothing, health supplies, daily necessities, medicines, electronic devices, and the like. A processor chip can be used instead of the ID chip.

  Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refer to checks, securities, promissory notes, and the like, and can be provided with an ID chip 1020 (see FIG. 28A). The certificate refers to a driver's license, a resident card, or the like, and an ID chip 1021 can be provided (see FIG. 28B). Bearer bonds refer to stamps, gift cards, and various gift certificates. Packaging containers refer to wrapping paper such as lunch boxes, plastic bottles, and the like, and can be provided with an ID chip 1023 (see FIG. 28D). Books refer to books, books, and the like, and can be provided with an ID chip 1024 (see FIG. 28E). A recording medium refers to DVD software, a video tape, or the like, and can be provided with an ID chip 1025 (see FIG. 28F). Personal belongings refer to bags, glasses, and the like, and can be provided with an ID chip 1027 (see FIG. 28H). The vehicles refer to vehicles such as bicycles, ships, and the like, and can be provided with an ID chip 1026 (see FIG. 28G). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

  Forgery can be prevented by providing ID chips on bills, coins, securities, certificates, bearer bonds, and the like. In addition, by providing ID chips for personal items such as packaging containers, books, recording media, food items, daily necessities, electronic devices, etc., the efficiency of inspection systems and rental store systems can be improved. it can. By providing ID chips on vehicles, health supplies, medicines, etc., counterfeiting and theft can be prevented, and medicines can prevent mistakes in taking medicines. The ID chip is provided by being stuck on the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin.

    The processor chip can also be used as an apparatus for measuring and evaluating a biological response of a living organism (biological signals (eg, electroencephalogram, electrocardiogram, electromyogram, blood pressure)), and can also be used in the medical field. FIG. 28C shows an example of measuring an electroencephalogram by attaching a plurality of processor chips to the human body. Information obtained from the plurality of processor chips 1022a, 1022b, and 1022c provided in the human body is analyzed, and an electroencephalogram is measured. The physical health and mental state can be known from information obtained from brain waves and processor chips. Moreover, since the processor chip is small and light, the burden on the subject can be reduced.

  Further, an example that can be applied to an object management and distribution system will be described with reference to FIG. Here, an example in which an ID chip (processor chip) is mounted on a product will be described. As shown in FIG. 29A, an ID chip 1402 is mounted on a beer bottle 1400 using a label 1401.

  In the ID chip 1402, basic items such as a manufacturing date, a manufacturing place, and a material used are recorded. Such basic matters do not need to be rewritten, and are preferably recorded using a non-rewritable memory such as a mask ROM or a memory transistor. In addition, the ID chip 1402 records individual items such as the delivery destination and delivery date and time of each beer bottle. For example, as shown in FIG. 29B, when the beer bottle 1400 flows through the belt conveyor 1412 and passes through the writer device 1413, each delivery destination and delivery date and time can be recorded. Such individual items may be recorded using a rewritable and erasable memory such as EEROM.

  When product information purchased from a delivery destination is transmitted to the distribution management center through the network, based on this product information, the writer device or a personal computer that controls the writer device calculates the delivery destination and delivery date and time. A system that records on a chip should be constructed.

  Since delivery is performed for each case, an ID chip can be mounted for each case or for each of a plurality of cases, and individual items can be recorded.

  By mounting an ID chip on such a product on which a plurality of delivery destinations can be recorded, it is possible to reduce the time required for manual input and to reduce input errors caused by the time. In addition, labor costs that are the most expensive in the field of logistics management can be reduced. Therefore, by mounting the ID chip, it is possible to carry out low-cost logistics management with few mistakes.

  Furthermore, application items such as foods suitable for beer and cooking methods using beer may be recorded at the delivery destination. As a result, it can serve as an advertisement for foods and the like, and the consumer's willingness to purchase can be enhanced. Such application items may be recorded using a rewritable and erasable memory such as EEROM. By mounting the ID chip in this way, information that can be provided to the consumer can be increased, so that the consumer can purchase the product with peace of mind.

  This embodiment mode can be freely combined with any of Embodiment Modes 1 to 10 described above.

According to the present invention, it is possible to realize an apparatus for uniformly doping an impurity element using a large-area substrate capable of multiple chamfering in mass production, and to reduce the processing time required for the doping process.

It is a perspective view of the doping apparatus of this invention. (Embodiment 1) It is a top view. (Embodiment 1) It is sectional drawing of a board | substrate control mechanism. (Embodiment 1) It is a figure which shows the model figure used for simulation, and a result. (Embodiment 1) It is a figure which shows a simulation result. It is a top view of the doping apparatus of this invention. (Embodiment 2) It is an example of sectional drawing of a board | substrate control mechanism. (Embodiment 1) It is an example of a cross-sectional view showing a manufacturing process of a TFT. (Embodiment 3) The top view and sectional drawing which show the mode of the board | substrate at the time of doping. (Embodiment 3) It is an example of a cross-sectional view showing a manufacturing process of a TFT. (Embodiment 3) It is an example of sectional drawing which shows the variation of the manufacturing process of TFT. (Embodiment 3) The model figure used for simulation and the figure which shows a result. Model diagram used for simulation and diagram showing results The model figure used for simulation and the figure which shows a result. The model figure used for simulation and the figure which shows a result. 8A and 8B illustrate a method for manufacturing a semiconductor device. (Embodiment 5) 8A and 8B illustrate a method for manufacturing a semiconductor device. (Embodiment 5) 8A and 8B illustrate a method for manufacturing a semiconductor device. (Embodiment 5) 8A and 8B illustrate a method for manufacturing a semiconductor device. (Embodiment 5) The perspective view which showed the semiconductor device. (Embodiment 6) FIG. 3 is a block diagram illustrating a configuration of a semiconductor device. (Embodiment 7) FIG. 3 is a block diagram illustrating a configuration of a semiconductor device. (Embodiment 8) 8A and 8B illustrate a method for manufacturing a semiconductor device. (Embodiment 9) 8A and 8B illustrate a method for manufacturing a semiconductor device. (Embodiment 9) 8A and 8B illustrate a method for manufacturing a semiconductor device. (Embodiment 9) 8A and 8B illustrate a method for manufacturing a semiconductor device. (Embodiment 9) 8A and 8B illustrate a method for manufacturing a semiconductor device. (Embodiment 10) FIG. 10 illustrates an application example using a semiconductor device. FIG. 10 illustrates an application example using a semiconductor device. It is an example of the perspective view of a doping apparatus. (Embodiment 1)

Explanation of symbols

10: Substrate 11: Doping chamber 12: Ion source 13: Acceleration electrode unit 14: Ion beam 15: Scanning direction 16: Tilt axis 17: Channel length direction 20: Substrate loading chamber 21, 26: Substrate cassette 22: Transfer robot 23, 24: gate valve 25: substrate carry-out chamber 30: substrate stage 31: clamper 32: substrate control mechanism 33: base 50: substrate 51: doping chamber 52a, 52b: ion source 53: acceleration electrode unit 54: ion beam 55: scanning direction 60: Substrate loading chamber 61, 26: Substrate cassette 62: Transfer robot 63, 64: Gate valve 65: Substrate unloading chamber 70: Substrate stage 82: Tilt axis 83: Substrate control mechanism 84: Scan direction 85a: X-axis goniometer 1 goniometer)
85b: Y-axis goniometer (second goniometer)
86: PC
87: Substrate 88: Substrate stage

Claims (8)

Means for generating an ion stream having a linear or rectangular cross section;
Means for irradiating the ion stream;
Substrate position control means for moving the substrate to be processed in one direction while holding the substrate surface in an inclined posture with respect to the vertical line,
A doping apparatus which irradiates the ion stream to a substrate to be processed which is in a tilted posture. A doping apparatus in which a substrate loading chamber, a doping chamber, and a substrate unloading chamber are arranged in series.
In the doping chamber, means for generating an ion flow having a linear or rectangular cross section, and a substrate position control means for moving the substrate to be processed in one direction while holding the substrate surface in an inclined posture with respect to the perpendicular. Have
A doping apparatus characterized by irradiating a substrate to be processed moving in one direction from a substrate carry-in chamber through a doping chamber to a substrate carry-out chamber. A doping apparatus in which a substrate loading chamber, a doping chamber, and a substrate unloading chamber are arranged in series.
In the doping chamber, a first means for generating an ion flow having a linear or rectangular cross section, a second means for generating an ion flow having a linear or rectangular cross section, and a substrate to be processed are moved in one direction. Substrate position control means
A doping apparatus characterized by irradiating a substrate to be processed moving in one direction from a substrate carry-in chamber through a doping chamber to a substrate carry-out chamber.   4. The doping apparatus according to claim 1, further comprising means for heating the substrate.   5. The doping apparatus according to claim 1, wherein the means for generating the ion flow includes high-frequency energy or microwave and magnetic field. 6. The doping apparatus according to claim 1, wherein the substrate inclined to the substrate posture is moved in a direction orthogonal to the substrate posture direction.   7. The doping apparatus according to claim 1, wherein the substrate tilted in the substrate posture is tilted about a line parallel to one side and passing through the center of the substrate surface. 6. The doping apparatus according to claim 1, wherein the substrate inclined to the substrate posture is inclined with respect to a plurality of axes.

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