JP2006032920A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a thin film transistor having requested characteristics without complicating a process and a device and to provide technology for manufacturing a semiconductor device having high reliability and superior electric characteristics with low cost and sufficient yield by precisely and freely controlling the characteristics of the thin film transistor. <P>SOLUTION: In the thin film transistor, a low concentration impurity region is formed on a source region side or a drain region side of a semiconductor layer covered with a gate electrode layer. The low concentration impurity region is formed on a surface of the semiconductor layer obliquely doping with the gate electrode layer as a mask. Thus, the detailed characteristic of the thin film transistor can be controlled. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

    Thin film transistors used in semiconductor devices have different required characteristics depending on the purpose and function of the semiconductor device. In order to satisfy this requirement, it is important to control the characteristics of the thin film transistor, and a technique for manufacturing the thin film transistor so as to have a characteristic suitable for the purpose of use has been studied (see, for example, Patent Document 1). .

In Patent Document 1, a sidewall is used to form a thin film transistor having an LDD (Lightly Doped Drain) structure impurity region, thereby reducing leakage current when the thin film transistor is OFF.
JP-A-9-27624

    An object of the present invention is to manufacture a thin film transistor having required characteristics without complicating a process and an apparatus. It is another object of the present invention to provide a technique capable of manufacturing a semiconductor device having high reliability and excellent electrical characteristics with low yield and high yield by precisely controlling characteristics of a thin film transistor.

    In the present invention, in a thin film transistor, a low concentration impurity region is formed on one of a source region side and a drain region side of a semiconductor layer covered with a gate electrode layer. The low concentration impurity region is formed by obliquely doping the surface of the semiconductor layer using the gate electrode layer as a mask. Therefore, when the semiconductor layer has an impurity region containing an impurity element imparting a conductivity type different from that of the thin film transistor, fine characteristics of the thin film transistor can be controlled. Also, by crystallizing the semiconductor film by laser irradiation and forming single crystal grains that extend long along the laser beam scanning direction, there are almost no crystal grain boundaries that prevent the movement of carriers in the thin film transistor. A semiconductor film that does not exist can be formed.

  Note that in this specification, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. A semiconductor device such as a multilayer wiring layer or an ID chip can be manufactured by using the present invention.

    In addition, a display device can be manufactured using the present invention. In a display device to which the present invention can be used, light emission in which an organic substance that emits light called electroluminescence (hereinafter also referred to as “EL”) or a layer containing a mixture of an organic substance and an inorganic substance is interposed between electrodes is used. There are a light-emitting display device in which an element and a TFT are connected, a liquid crystal display device in which a liquid crystal element having a liquid crystal material is used as a display element, and the like.

    One embodiment of the semiconductor device of the present invention includes a gate insulating layer over a semiconductor layer, and the semiconductor layer includes a channel formation region, a source region, a drain region, and an impurity region between the channel formation region and the source region. The channel formation region and the drain region are provided in contact with each other, and a gate electrode layer is provided over the channel formation region and the impurity region with the gate insulating layer interposed therebetween.

    One embodiment of the semiconductor device of the present invention includes a gate insulating layer over a semiconductor layer, the semiconductor layer includes a channel formation region, a source region, and a drain region, and an impurity region is provided between the channel formation region and the drain region. The channel formation region and the source region are provided in contact with each other, and a gate electrode layer is provided over the channel formation region and the impurity region with the gate insulating layer interposed therebetween.

    One embodiment of the semiconductor device of the present invention includes a gate insulating layer over a semiconductor layer, and the semiconductor layer includes a channel formation region, a source region, a drain region, and a first impurity between the channel formation region and the source region. A second impurity region between the source region and the first impurity region, and a third impurity region between the drain region and the channel formation region, the channel formation region, the third impurity region, Are provided in contact with each other and have a gate electrode layer over the channel formation region and the first impurity region with a gate insulating layer interposed therebetween, and the second impurity region, the third impurity region, the source region, and the drain region are integrated. The concentration of the element having an impurity element imparting conductivity type and imparting one conductivity type in the second impurity region and the third impurity region depends on the impurity element imparting one conductivity type in the source region and the drain region. Lower than the concentration.

    One embodiment of the semiconductor device of the present invention includes a gate insulating layer over a semiconductor layer, and the semiconductor layer includes a channel formation region, a source region, a drain region, and a first impurity between the channel formation region and the drain region. A second impurity region between the source region and the channel formation region, and a third impurity region between the drain region and the first impurity region, the channel formation region and the second impurity region Are provided in contact with each other and have a gate electrode layer over the channel formation region and the first impurity region with a gate insulating layer interposed therebetween, and the second impurity region, the third impurity region, the source region, and the drain region are integrated. The concentration of the element imparting one conductivity type in the second impurity region and the third impurity region has an impurity element imparting one conductivity type in the second impurity region and the third impurity region. Lower than the concentration of iodine.

    One embodiment of the semiconductor device of the present invention includes a gate insulating layer over a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer includes a first channel formation region, a first source region, , A first drain region and a first impurity region between the first channel formation region and the first source region, and the second semiconductor layer includes a second channel formation region, a second channel formation region, Source region, a second drain region, and a second impurity region between the second channel formation region and the second drain region, and the first channel formation region, the first drain region, Are provided in contact with each other, the second channel formation region and the second source region are provided in contact with each other, and the first gate is formed over the first channel formation region and the first impurity region with the gate insulating layer interposed therebetween. An electrode layer and a second channel formation region and a gate insulating layer through the gate insulating layer; A second gate electrode layer on the second impurity region.

According to one method for manufacturing a semiconductor device of the present invention, an amorphous semiconductor film is formed over an insulating surface, and the amorphous semiconductor film is irradiated with laser light to form a crystalline semiconductor film. To form a semiconductor layer, a gate insulating layer is formed on the semiconductor layer, a gate electrode layer is formed on the gate insulating layer, and the gate electrode layer is used as a mask to the semiconductor layer with respect to the surface of the semiconductor layer An impurity element imparting the first conductivity type is obliquely added from one direction to form a first impurity region, and a second perpendicular to the semiconductor layer surface is formed on the semiconductor layer using the gate electrode layer as a mask. An impurity element imparting one conductivity type is added to form a second impurity region, a source region, a drain region, and a channel formation region, and the second impurity region is a gate between the channel formation region and the source region. Semiconductor covered with electrode layer Formed in the drain region is formed in contact with the channel formation region.

    According to one method for manufacturing a semiconductor device of the present invention, an amorphous semiconductor film is formed over an insulating surface, and the amorphous semiconductor film is irradiated with laser light to form a crystalline semiconductor film. To form a semiconductor layer, a gate insulating layer is formed on the semiconductor layer, a gate electrode layer is formed on the gate insulating layer, and the gate electrode layer is used as a mask to the semiconductor layer with respect to the surface of the semiconductor layer An impurity element imparting the first conductivity type is obliquely added from one direction to form a first impurity region, and a second perpendicular to the semiconductor layer surface is formed on the semiconductor layer using the gate electrode layer as a mask. An impurity element imparting one conductivity type is added to form a second impurity region, a source region, a drain region, and a channel formation region, and the second impurity region is a gate between the channel formation region and the drain region. Semiconductor covered with electrode layer Formed in the layer, the source region is formed in contact with the channel formation region.

    According to one method for manufacturing a semiconductor device of the present invention, an amorphous semiconductor film is formed over an insulating surface, and the amorphous semiconductor film is irradiated with laser light to form a crystalline semiconductor film. To form a semiconductor layer, a gate insulating layer is formed on the semiconductor layer, a gate electrode layer is formed on the gate insulating layer, and the gate electrode layer is used as a mask to the semiconductor layer with respect to the surface of the semiconductor layer An impurity element imparting the first conductivity type is obliquely added from one direction to form a first impurity region, and a second perpendicular to the semiconductor layer surface is formed on the semiconductor layer using the gate electrode layer as a mask. An impurity element imparting one conductivity type is added to form a second impurity region, a third impurity region, a fourth impurity region, and a channel formation region, and an insulating layer is formed on a side surface of the gate electrode layer. Using the gate electrode layer and the insulating layer as a mask An impurity element imparting a third conductivity type is added to the semiconductor layer perpendicularly to the surface of the semiconductor layer to add a source region, a fifth impurity region in contact with the source region, a drain region, and a sixth in contact with the drain region. In the fifth impurity region and the sixth impurity region, the concentration of the impurity element having the second one conductivity type and the concentration of the impurity element imparting the third one conductivity type are the source region and the drain region. The second impurity region is lower than the concentration of the impurity element having the second one conductivity type and the impurity element imparting the third one conductivity type, and the second impurity region is a gate electrode between the channel formation region and the fifth impurity region. The sixth impurity region is formed in contact with the channel formation region and is formed in the semiconductor layer covered with the layer.

    According to one method for manufacturing a semiconductor device of the present invention, an amorphous semiconductor film is formed over an insulating surface, and the amorphous semiconductor film is irradiated with laser light to form a crystalline semiconductor film. To form a semiconductor layer, a gate insulating layer is formed on the semiconductor layer, a gate electrode layer is formed on the gate insulating layer, and the gate electrode layer is used as a mask to the semiconductor layer with respect to the surface of the semiconductor layer An impurity element imparting the first conductivity type is obliquely added from one direction to form a first impurity region, and a second perpendicular to the semiconductor layer surface is formed on the semiconductor layer using the gate electrode layer as a mask. An impurity element imparting one conductivity type is added to form a second impurity region, a third impurity region, a fourth impurity region, and a channel formation region, and an insulating layer is formed on a side surface of the gate electrode layer. Using the gate electrode layer and the insulating layer as a mask An impurity element imparting a third conductivity type is added to the semiconductor layer perpendicularly to the surface of the semiconductor layer to add a source region, a fifth impurity region in contact with the source region, a drain region, and a sixth in contact with the drain region. In the fifth impurity region and the sixth impurity region, the concentration of the impurity element having the second one conductivity type and the concentration of the impurity element imparting the third one conductivity type are the source region and the drain region. The second impurity region is lower than the concentration of the impurity element having the second one conductivity type and the impurity element imparting the third one conductivity type, and the second impurity region is a gate electrode between the channel formation region and the sixth impurity region. The fifth impurity region is formed in contact with the channel formation region and is formed in the semiconductor layer covered with the layer.

    According to one method for manufacturing a semiconductor device of the present invention, an amorphous semiconductor film is formed over an insulating surface, and the amorphous semiconductor film is irradiated with laser light to form a crystalline semiconductor film. Are patterned to form a first semiconductor layer and a second semiconductor layer, a gate insulating layer is formed on the first semiconductor layer and the second semiconductor layer, and a first gate electrode layer is formed on the gate insulating layer And the second gate electrode layer are formed, and the first gate electrode layer and the second gate electrode layer are used as a mask, and the first one conductivity is inclined with respect to the surfaces of the first semiconductor layer and the second semiconductor layer. An impurity element imparting a type is added from one direction to form a first impurity region in the first semiconductor layer, a second impurity region is formed in the second semiconductor layer, the first gate electrode layer, Using the second gate electrode layer as a mask, the surface of the first semiconductor layer and the second semiconductor layer An impurity element imparting a second conductivity type is added perpendicularly to the surface to form a third impurity region, a first source region, a first drain region, and a first channel in the first semiconductor layer Forming a region, forming a fourth impurity region, a second source region, a second drain region, and a second channel formation region in the second semiconductor layer, and the third impurity region is a first channel The fourth impurity region is formed in the first semiconductor layer covered with the first gate electrode layer between the formation region and the first source region, and the fourth impurity region includes the second channel formation region and the second drain region. The first drain region is formed in contact with the first channel formation region, and the second source region is formed in the second semiconductor layer covered with the second gate electrode layer. 2 in contact with the channel formation region.

    According to the present invention, a thin film transistor having required characteristics can be manufactured without complicating a process and an apparatus. In addition, by controlling the characteristics of the thin film transistor precisely and freely, a semiconductor device having high reliability and excellent electrical characteristics can be manufactured with low cost and high yield.

  Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
A method for manufacturing the thin film transistor in this embodiment will be described in detail with reference to FIGS.

    Silicon nitride oxide by a sputtering method, a PVD method (Physical Vapor Deposition), a low pressure CVD method (LPCVD method), or a CVD method (Chemical Vapor Deposition) such as a plasma CVD method as a base film on the substrate 100 having an insulating surface A base film 101a is formed to a thickness of 10 to 200 nm (preferably 50 to 100 nm) using a film (SiNO), and a base film 101b is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm) using a silicon oxynitride film (SiON). . In this embodiment, the base film 101a and the base film 101b are formed by a plasma CVD method. As the substrate 100, a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used, or a flexible substrate such as a film may be used. In addition, a two-layer structure may be used as the base film, or a single-layer film or a structure in which two or more layers are stacked may be used.

    Next, a semiconductor film is formed over the base film. The semiconductor film may be formed by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) with a thickness of 25 to 200 nm (preferably 30 to 150 nm). In this embodiment mode, it is preferable to use a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film by laser crystallization.

    As a material for forming the semiconductor film, an amorphous semiconductor (hereinafter also referred to as “amorphous semiconductor: AS”) manufactured by a vapor deposition method or a sputtering method using a semiconductor material gas typified by silane or germane is used. A polycrystalline semiconductor obtained by crystallizing a crystalline semiconductor using light energy or thermal energy, or a semi-amorphous (also referred to as microcrystal or microcrystal; hereinafter, also referred to as “SAS”) semiconductor can be used.

SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state that is stable in terms of free energy and has a short-range order and a lattice. It includes a crystalline region with strain. A crystal region of 0.5 to 20 nm can be observed in at least a part of the film, and when silicon is the main component, the Raman spectrum shifts to a lower wave number side than 520 cm ^−1. Yes. In X-ray diffraction, diffraction peaks of (111) and (220) that are derived from the silicon crystal lattice are observed. As a neutralizing agent for dangling bonds, hydrogen or halogen is contained at least 1 atomic% or more. The SAS is formed by glow discharge decomposition (plasma CVD) of a silicide gas. As the silicide gas, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _{4, and the} like can be used. Further, F ₂ and GeF ₄ may be mixed. This silicide gas may be diluted with H ₂ , or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. The dilution rate is in the range of 2 to 1000 times, the pressure is in the range of approximately 0.1 Pa to 133 Pa, and the power supply frequency is 1 MHz to 120 MHz, preferably 13 MHz to 60 MHz. The substrate heating temperature is preferably 300 ° C. or lower, and can be formed even at a substrate heating temperature of 100 to 200 ° C. Here, as an impurity element mainly taken in at the time of film formation, it is desirable that impurities derived from atmospheric components such as oxygen, nitrogen, and carbon be 1 × 10 ²⁰ cm ⁻³ or less, and in particular, the oxygen concentration is 5 × 10 5. It is preferable to be ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less. Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability is improved and a favorable SAS can be obtained. Alternatively, a SAS layer formed of a silicide gas containing hydrogen may be stacked on a SAS layer formed of a silicide gas containing fluorine as a semiconductor film.

    A typical example of an amorphous semiconductor is hydrogenated amorphous silicon, and a typical example of a crystalline semiconductor is polysilicon. Polysilicon (polycrystalline silicon) is mainly made of so-called high-temperature polysilicon using polysilicon formed through a process temperature of 800 ° C. or higher as a main material, or polysilicon formed at a process temperature of 600 ° C. or lower. And so-called low-temperature polysilicon, and polysilicon crystallized by adding an element that promotes crystallization. Needless to say, as described above, a semi-amorphous semiconductor or a semiconductor containing a crystal phase in part of a semiconductor film can also be used.

In the case where a crystalline semiconductor film is used as the semiconductor film, a method for manufacturing the crystalline semiconductor film can be a known method (laser crystallization method, thermal crystallization method, or heat using an element that promotes crystallization such as nickel. A crystallization method or the like may be used. In addition, a microcrystalline semiconductor that is a SAS can be crystallized by laser irradiation to improve crystallinity. In the case where an element for promoting crystallization is not introduced, the concentration of hydrogen contained in the amorphous semiconductor film is set to 1 × by heating at 500 ° C. for 1 hour in a nitrogen atmosphere before the amorphous semiconductor film is irradiated with laser light. Release to 10 ²⁰ atoms / cm ³ or less. This is because when an amorphous semiconductor film containing a large amount of hydrogen is irradiated with laser light, the amorphous semiconductor film is destroyed.

    The method of introducing the metal element into the amorphous semiconductor film is not particularly limited as long as the metal element can be present on the surface of the amorphous semiconductor film or inside the amorphous semiconductor film. For example, sputtering, CVD, A plasma treatment method (including a plasma CVD method), an adsorption method, or a method of applying a metal salt solution can be used. Among these, the method using a solution is simple and useful in that the concentration of the metal element can be easily adjusted. At this time, in order to improve the wettability of the surface of the amorphous semiconductor film and to spread the aqueous solution over the entire surface of the amorphous semiconductor film, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, hydroxy radical It is desirable to form an oxide film by treatment with ozone water or hydrogen peroxide.

By using a solid-state laser capable of continuous oscillation and irradiating laser light of the second to fourth harmonics of the fundamental wave, a crystal having a large grain size can be obtained. For example, typically, it is desirable to use the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm). Specifically, laser light emitted from a continuous wave YVO ₄ laser is converted into a harmonic by a non-linear optical element to obtain laser light having an output number of W or more. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system and irradiated onto the semiconductor film. At this time, the energy density of about 0.001~100MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 0.5 to 2000 cm / sec (preferably 10 to 200 cm / sec).

As the laser, a known continuous wave gas laser or solid-state laser can be used. Examples of gas lasers include Ar laser and Kr laser, and solid-state lasers include YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, Y ₂ O ₃ laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser. Etc.

  Further, the laser crystallization may be performed using a frequency band significantly higher than a frequency band of several tens to several hundreds Hz that is usually used with an oscillation frequency of pulsed laser light of 0.5 MHz or more. It is said that the time from irradiating a semiconductor film with laser light by pulse oscillation until the semiconductor film is completely solidified is several tens to several hundreds nsec. Therefore, by using the above frequency band, it is possible to irradiate the next pulse of laser light from when the semiconductor film is melted by the laser light to solidification. Accordingly, since the solid-liquid interface can be continuously moved in the semiconductor film, a semiconductor film having crystal grains continuously grown in the scanning direction is formed. Specifically, a set of crystal grains having a width of 10 to 30 μm in the scanning direction and a width of about 1 to 5 μm in a direction perpendicular to the scanning direction can be formed. By forming single crystal grains extending long along the scanning direction, a semiconductor film having almost no crystal grain boundary at least in the channel direction of the thin film transistor can be formed.

  Further, laser light may be irradiated in an inert gas atmosphere such as a rare gas or nitrogen. Accordingly, the surface roughness of the semiconductor can be suppressed by laser light irradiation, and variations in threshold values caused by variations in interface state density can be suppressed.

    Crystallization of the amorphous semiconductor film may be a combination of heat treatment and crystallization by laser light irradiation, or may be performed multiple times by heat treatment or laser light irradiation alone.

    As a semiconductor, an organic semiconductor material can be used and formed by a printing method, a spray method, a spin coating method, a droplet discharge method, or the like. In this case, the number of processes can be reduced because the etching process is not necessary. As the organic semiconductor, a low molecular material, a polymer material, or the like is used, and materials such as an organic dye or a conductive polymer material can also be used. The organic semiconductor material used in the present invention is preferably a π-electron conjugated polymer material whose skeleton is composed of conjugated double bonds. Typically, a soluble polymer material such as polythiophene, polyfluorene, poly (3-alkylthiophene), a polythiophene derivative, or pentacene can be used.

    In addition, as an organic semiconductor material that can be used in the present invention, there is a material that can form a semiconductor layer by processing after forming a soluble precursor. Examples of such an organic semiconductor material include polythienylene vinylene, poly (2,5-thienylene vinylene), polyacetylene, a polyacetylene derivative, and polyarylene vinylene.

    When converting the precursor into an organic semiconductor, a reaction catalyst such as hydrogen chloride gas is added as well as heat treatment. Typical solvents for dissolving these soluble organic semiconductor materials include toluene, xylene, chlorobenzene, dichlorobenzene, anisole, chloroform, dichloromethane, γ-butyllactone, butyl cellosolve, cyclohexane, NMP (N-methyl-2 -Pyrrolidone), cyclohexanone, 2-butanone, dioxane, dimethylformamide (DMF), THF (tetrahydrofuran), or the like can be applied.

    In this embodiment, the amorphous semiconductor film 115 is formed using amorphous silicon over the base film 101b. By irradiating the amorphous semiconductor film 115 with laser light 170 while scanning in the direction of an arrow 171, the amorphous semiconductor film 115 is crystallized to form a crystalline semiconductor film 116 (see FIG. 1A).

    In order to control the threshold voltage of the thin film transistor, the semiconductor film obtained in this manner may be doped with a small amount of impurity element (boron or phosphorus). An n-channel thin film transistor is manufactured so as to have a p-type impurity region, and a threshold voltage of the thin film transistor is controlled. Therefore, when the present invention is used, the doping process for controlling the threshold voltage is not necessarily performed, and thus the process is simplified.

    Next, the crystalline semiconductor film 116 is patterned using a mask. In this embodiment, a photomask is manufactured, and the semiconductor layer 102 is formed by a patterning process using a photolithography method.

Either plasma etching (dry etching) or wet etching may be employed for the etching process at the time of patterning, but plasma etching is suitable for processing a large area substrate. As an etching gas, a gas containing fluorine such as CF ₄ or NF ₃ or a gas containing chlorine such as Cl ₂ or BCl ₃ may be used, and an inert gas such as He or Ar may be added as appropriate. Further, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

    In the present invention, a conductive layer for forming a wiring layer or an electrode layer, a mask layer for forming a predetermined pattern, or the like may be formed by a method capable of selectively forming a pattern such as a droplet discharge method. . A droplet discharge (ejection) method (also called an ink-jet method depending on the method) is a method in which a droplet of a composition prepared for a specific purpose is selectively ejected (ejection) to form a predetermined pattern (such as a conductive layer or a conductive layer). An insulating layer or the like can be formed. At this time, a process for controlling wettability and adhesion may be performed on the formation region. In addition, a method by which a pattern can be transferred or drawn, for example, a printing method (a method for forming a pattern such as screen printing or offset printing) can be used.

  In this embodiment mode, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin is used as a mask to be used. Also, use organic materials such as benzocyclobutene, parylene, flare, permeable polyimide, compound materials made by polymerization of siloxane polymers, composition materials containing water-soluble homopolymers and water-soluble copolymers, etc. You can also. Alternatively, a commercially available resist material containing a photosensitizer may be used. For example, a novolak resin that is a typical positive resist and a naphthoquinonediazide compound that is a photosensitizer, a base resin that is a negative resist, diphenylsilanediol, and An acid generator or the like may be used. When using the droplet discharge method, regardless of which material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

    A gate insulating layer 105 is formed to cover the semiconductor layer 102. The gate insulating layer 105 is formed of an insulating film containing silicon with a thickness of 10 to 150 nm using a plasma CVD method, a sputtering method, or the like. The gate insulating layer 105 may be formed of a known material such as a silicon oxide material or a nitride material, and may be a stacked layer or a single layer. In this embodiment, the gate insulating layer has a stacked structure. A thin silicon oxide film having a thickness of 1 to 100 nm, preferably 1 to 10 nm, and more preferably 2 to 5 nm is formed over the semiconductor layer 102 as the first insulating film. As a method of forming the first insulating layer, the surface of the semiconductor region is oxidized using a GRTA (Gas Rapid Thermal Anneal) method, an LRTA (Lamp Rapid Thermal Anneal) method, etc., and a thermal oxide film is formed. A thin first insulating layer can be formed. In this embodiment, a stacked layer of a silicon nitride film, a silicon oxide film, and a silicon nitride film is used on the first insulating film. Alternatively, a single layer or a double layer of silicon oxynitride film may be used. A silicon nitride film having a dense film quality is preferably used. Note that in order to form a dense insulating film with low gate leakage current at a low deposition temperature, a rare gas element such as argon is preferably contained in a reaction gas and mixed into the formed insulating film.

    Next, a first conductive film 106 with a thickness of 20 to 100 nm and a second conductive film 107 with a thickness of 100 to 400 nm used as a gate electrode layer are stacked over the gate insulating layer 105 (FIG. 1). See B). The first conductive film 106 and the second conductive film 107 can be formed by a known method such as a sputtering method, an evaporation method, or a CVD method. The first conductive film and the second conductive film are tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), neodymium (Nd ), Or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used as the first conductive film and the second conductive film. Further, the present invention is not limited to the two-layer structure. For example, a three-layer structure in which a tungsten film with a thickness of 50 nm, an aluminum-silicon alloy film with a thickness of 500 nm (Al-Si), and a titanium nitride film with a thickness of 30 nm are sequentially stacked. Also good. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum instead of the aluminum and silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. Moreover, a single layer structure may be sufficient. In this embodiment mode, tantalum nitride (TaN) is used for the first conductive film 106 and tungsten (W) is used for the second conductive film 107.

Next, a resist mask is formed by photolithography, the second conductive film 107 is patterned, and the first gate electrode layer 205 is formed. Using ICP (Inductively Coupled Plasma) etching method, etching conditions (amount of power applied to coil-type electrode layer, amount of power applied to electrode layer on substrate side, electrode temperature on substrate side, etc.) By appropriately adjusting, the second conductive film can be etched into a desired taper shape. As an etching gas, a gas containing chlorine such as Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a gas containing fluorine such as CF ₄ , SF ₆ or NF _3, or O ₂ is used. It can be used as appropriate.

    A thin film transistor capable of high-speed operation can be formed by reducing the width D1 of the gate electrode layer. Two methods for forming the first gate electrode layer 205 with a narrow width in the channel direction are shown in FIGS. FIG. 3A corresponds to FIG. 1B, and the second conductive film 107 is formed over the substrate 100.

    First, the first method will be described with reference to FIGS. 3B, 3C, and 3F. A mask 220 made of resist is formed over the second conductive film 107. The mask 220 is formed using a photolithography method, a droplet discharge method, or the like. As shown in FIG. 3B, the second conductive film 107 is etched using the mask 220 to form the first gate electrode layer 210. After that, the first gate electrode layer 210 is etched in the direction of the arrow 225 without removing the mask 220. The width of the first gate electrode layer 210 is reduced to the first gate electrode layer 205, so that the first gate electrode layer 205 is formed (see FIG. 3C). The mask 220 is removed, and the first gate electrode layer 205 having a gate electrode width D1 of 10 nm to 1000 nm, preferably 200 nm to 700 nm can be completed as shown in FIG.

    Next, the second method will be described with reference to FIGS. 3D, 3E, and 3F. A mask 220 made of resist is formed over the second conductive film 107. The mask 220 is formed using a photolithography method, a droplet discharge method, or the like. The mask 220 is further slimmed in the direction of the arrow 256 by etching, ashing, or the like to form a mask 221 having a narrower width (see FIG. 3E). The second conductive film 107 is patterned using the mask 221 formed with a very small line width, and the mask 221 is removed, so that the first gate electrode layer 205 whose gate electrode layer width D1 is narrow is similarly reduced. Can be formed. By setting the width D1 of the gate electrode layer within the range, a thin film transistor having a short channel length can be formed later, and a semiconductor device capable of high-speed operation can be manufactured.

FIG. 31A is a perspective view showing an example of the doping apparatus of the present invention.

The ion source 12 includes a thermionic emission filament provided in a chamber that is a plasma chamber, and ring-shaped permanent magnets that are arranged around the chamber in a plurality of alternating polarities.

The accelerating electrode portion 13 has an ion confining electrode maintained at the same potential as the anode chamber, an extraction electrode maintained at a potential several kV lower than the ion confinement electrode, and several tens of times from the extraction electrode. The acceleration electrode is kept at a low potential of kV. The ion confinement electrode, the extraction electrode, and the acceleration electrode are grid electrodes.

Alternatively, irradiation on / off may be controlled by opening and closing a shutter for blocking the ion beam.

A plasma is generated by the action of electrons emitted from the filament on the working gas (hydrogen, phosphine, diborane, etc.) introduced from the gas inlet into the chamber, and this is confined in the chamber by the magnetic field of the permanent magnet. By applying an electric field by the extraction electrode, ions in the plasma are extracted through the ion confinement electrode, and this is accelerated by the electric field of the acceleration electrode to generate the ion beam 14.

Then, the ion beam 14 is irradiated into the doping chamber 11 and ions are implanted into the substrate 10 in an inclined state. The substrate 10 is tilted about the tilt axis 16 and held. The doping process on the entire surface of the substrate is performed by making the cross section of the ion beam 14 linear or rectangular and moving the substrate in a direction perpendicular to the longitudinal direction of the ion beam 14 (scanning direction 15).

    When changing the inclination of the substrate between the horizontal state and the inclined state, the inclination angle of the substrate is changed by a substrate stage or a transfer robot. The movement of the substrate in the scanning direction is not limited to the robot, and a rail and a drive geared motor may be used. The angle of the stage is adjusted by angle adjusting means such as a goniometer. A stage provided with a goniometer is also called a goniometer stage, which has a tilt center above the stage, tilts about that as a fulcrum, and tilts the stage surface. Further, an angle formed by the longitudinal direction of the ion beam 14 and the main surface of the substrate 10 is an angle θ. The substrate is tilted about the tilt axis 16. The tilt axis 16 may be provided at any position on the substrate. In FIG. 31, the tilt axis 16 is provided on the substrate surface in parallel with the side direction of the substrate, but may be provided obliquely on a diagonal line on the substrate surface. In this case, the substrate 10 is inclined and is in an inclined state with the diagonal line as the inclination axis.

  Since the doping apparatus of the present invention performs the doping process by moving the substrate while maintaining the tilted state by the substrate stage, it is possible to process a large-area substrate. Further, since the cross-sectional shape of the ion beam is a quadrangle, all the ion beams are irradiated onto the substrate, so that ion irradiation can be performed efficiently. Further, since the substrate is not rotated, the width of the ion beam in the longitudinal direction can be reduced.

  Further, the present invention is not particularly limited to the above-described apparatus configuration, and since there is a problem of particles, the apparatus may be configured to irradiate the ion beam in the horizontal direction in an inclined state close to a vertically standing state.

    FIG. 33 shows an example of doping with the substrate upright. The doping apparatus shown in FIG. 33A has an apparatus configuration in which the ion beam irradiation means 663 irradiates the ion beam 662 in the horizontal direction with the substrate 661 standing vertically. In addition, a robot is connected to the substrate stage that holds the substrate, and while the substrate is being transported, it is designed so that it can be moved in two ways by providing different light tilt axes for tilting. . One is a doping method in which a substrate 661 is transported while being tilted at an angle θ formed by the substrate surface and the ion beam irradiation direction as shown in FIG. In this method, as shown in FIG. 33C, the substrate is tilted and conveyed, and the ion beam is irradiated at an angle θ. Further, during irradiation with the ion beam, the substrate stage may be fixed at a certain angle, or the angle may be constantly changed within a certain angle range.

    The present invention is not particularly limited to the above-described apparatus configuration, and a substrate transport roller may be used instead of the substrate stage to hold and transport the tilted substrate. In this case, the lower surface of the substrate is held by a holding member such as a transport roller, and the lower end of the slope is held by the side guide. The side guide plays a role of suppressing the downward movement of the substrate by tilting the lower end support roller in contact with the lower end of the substrate and holding it from the side.

    Moreover, it is not specifically limited to the apparatus structure mentioned above, You may add the ion focusing apparatus and ion mass separation apparatus well-known in the conventional ion doping technique to the doping apparatus of this invention.

In addition, in order to perform doping while holding the substrate obliquely and form an impurity region below the gate electrode, it is necessary to consider the arrangement of TFTs. FIG. 31B is a schematic diagram simply showing the state of the substrate in the doping chamber 11. As shown in FIG. 31B, it is preferable to design a circuit including TFTs by combining the movement of the substrate stage for tilting the substrate and the channel length direction 17. Therefore, it is necessary to determine the arrangement of the circuit including the TFT in accordance with the position where the tilt axis 16 that determines how to move the substrate stage is provided.

    32A and 32B are a top view (A) illustrating a doping process of the semiconductor device in this embodiment, a cross-sectional view taken along line I-J in the top view (A), and a cross-section taken along line GH. FIG. 32 (C1) and (C2) which are figures are shown. As shown in FIG. 32, a plurality of semiconductor layers 31, a gate electrode layer 32, and a gate insulating layer 33 are formed on the substrate 30. In the present invention, the semiconductor layer 31 is doped with an impurity element obliquely so as to have an angle θ with the surface of the semiconductor layer. The substrate 30 shown in FIG. 32A is tilted about the tilt axis parallel to the line I-J. The impurity element is doped while being fixed in the inclined state, and as a result, the impurity element 35 is implanted obliquely as shown in FIGS. On the other hand, in the cross-sectional view (B) of the line IJ parallel to the tilt axis, the impurity element 35 is always doped into the semiconductor layer 31 at θb perpendicular to the surface of the semiconductor layer 31. 32 (C1) and 32 (C2), which are cross-sectional views taken along the line GH perpendicular to the tilt axis, the impurity element 35 is tilted at an angle θc1 or an angle θc2 in the semiconductor layer 31 depending on the tilting direction of the substrate 30. Doped. By changing the angle θc1 and the angle θc2, the impurity region 34a and the impurity region 34b can be formed in different structures as shown in FIGS. 32C1 and 32C2.

The angle θ between the impurity element 35 to be doped and the surface of the semiconductor layer is preferably 30 to 90 degrees and 90 to 150 degrees. In addition, when the two types of doping are performed in this way, it is preferable that the angle θc1 and the angle θc2 are set so that the angle difference is 5 degrees or more.

Next, an impurity element 251 imparting p-type conductivity is added using the first gate electrode layer 205 as a mask. Here, an impurity element imparting p-type conductivity is added at an angle θ1 of 30 ° to 90 ° and 90 ° to 150 ° with respect to the surface of the semiconductor layer 102, and the first p-type impurity region 103a, the first A p-type impurity region 103b is formed (see FIG. 1C). In the present embodiment, θ1 is set in the range of 30 degrees to 90 degrees. Since the impurity element imparting p-type conductivity is doped obliquely toward the surface of the semiconductor layer, the impurity element is also added to the region of the semiconductor layer 102 covered with the first gate electrode layer 205, and the first p-type impurity region 103b is added. Form. On the other hand, part of the impurity element imparting p-type conductivity is shielded by the first gate electrode layer 205, and thus the first p-type impurity region 103 a includes a semiconductor region covered with the gate electrode layer 205. Not. Thus, a p-type impurity region is selectively formed in the semiconductor layer 102, and a first p-type impurity region 103a and a first p-type impurity region 103b are formed (see FIG. 1C). Here, the first p-type impurity region 103a and the first p-type impurity region 103b include the impurity element imparting p-type at a concentration of about 5 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ^3. Added. Further, the impurity element imparting p-type conductivity may be added so as to be contained at a concentration of about 5 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity.

In this embodiment, a region where the impurity region overlaps with the gate electrode layer through the gate insulating layer is referred to as a Lov region, and a region where the impurity region does not overlap with the gate electrode layer through the gate insulating layer is referred to as a Loff region. With reference to FIGS. 27 and 28, the channel length of the thin film transistor L, the channel length direction of the Lov region 2602a for the length L _OV be described. Further, in the present embodiment, the length L _OV of the channel length L, the channel length direction of the Lov region 2602a of the thin film transistor, the length and defining shown in Figure 27 (A). Basically, the formula of width = L + L _OV gate electrode layer 2600, as shown in FIG. 27 (A) is established. In the case where the impurity element is diffused by relatively high-temperature heat treatment after the substrate is obliquely doped, the boundary of the channel formation region 2603 becomes difficult to be clarified, but FIG. ). In FIG. 27, hatching and white background are shown in the Lov region, but this does not indicate that the impurity element is not added to the white background part, but the concentration distribution of the impurity element in this region determines the doping condition. This is because it is possible to intuitively understand what is reflected. This also applies to other drawings in this specification. Therefore, it is possible to intuitively understand that the shapes of the first p-type impurity region 103a and the first impurity region 103b in FIG. 1C also reflect the doping angle θ1.

Depending on doping conditions, the peak of the concentration profile 2604 may be located above the channel formation region 2606 in the semiconductor layer or on the gate insulating layer 2601 as shown by a dotted line in FIG. In FIG. 27 (B), the channel length L of the Lov region 2605a of the length L _OV and the channel forming region 2606 overlapping with the gate electrode layer 2600 is the same as FIG. 27 (A).

Depending on doping conditions, as indicated by a dotted line in FIG. 27C, the peak of the concentration profile 2607 may be located in the base insulating film or the substrate below the semiconductor layer. In this case, the formula of the width of the gate electrode layer 2600 = L + _LOV does not hold. Since the channel is formed at the interface between the channel formation region 2609 and the gate insulating layer 2601, the channel length L is the length shown in FIG. 27C, and the Lov region 2608 a overlapping with the gate electrode layer 2600 has a length L _Point where _OV is the longest. The structure shown in FIG. 27C cannot be manufactured unless the thin film transistor has a long channel length because when the semiconductor substrate is used, the concentration profiles overlap with each other under the gate or are too close to each other. It is a structure.

  Next, in FIG. 27A, the impurity element concentration distribution in the horizontal and vertical directions of the Lov region 2602a will be described with reference to FIG. FIG. 28A is an enlarged view of one Lov region 2602a in FIG. FIG. 28B shows the concentration distribution of the impurity element in the depth direction (YZ) in the Lov region of FIG. 28A, and the same lateral direction (VX: perpendicular to the depth direction). FIG. 28C shows the distribution of the impurity concentration in one direction).

  As shown in FIG. 28B, in the Lov region, a concentration gradient of the impurity element is generated between the substrate side and the gate electrode layer side. As shown in FIG. 28C, a concentration gradient of the impurity element is generated in the Lov region.

    Note that the concentration gradients in the depth direction and the lateral direction have various gradients as shown in FIGS. 27B and 27C.

Again, an impurity element 252 imparting n-type conductivity is added using the first gate electrode layer 205 as a mask. An impurity element 252 imparting n-type is added at an angle θ2 substantially perpendicular to the surface of the semiconductor layer 102 to form a first n-type impurity region 104a and a first n-type impurity region 104b (FIG. 1). See D).). The angle θ2 is set to be different from the angle θ1 by 5 degrees or more. In the first n-type impurity region 104a and the first n-type impurity region 104b, since the impurity element imparting p-type is already added, the first p-type is inverted to invert from p-type to n-type. An impurity element imparting n-type having a higher concentration than the impurity element concentration imparting p-type conductivity of the impurity region 103a and the first p-type impurity region 103b is added. The first n-type impurity region 104a and the first n-type impurity region 104b typically contain an impurity element imparting n-type at a concentration of 1 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ^3. To form. In this embodiment mode, phosphorus (P) is used as the impurity element imparting n-type conductivity.

    Here, since the impurity element 252 imparting n-type is added in a self-aligning manner using the first gate electrode layer 205, the first p-type impurity region 103b overlaps with the first gate electrode layer 205. In this case, the impurity element 252 imparting n-type is not added and remains as a p-type impurity region. Therefore, the second p-type impurity region 208 is formed in the semiconductor layer 102, and the second p-type impurity region 208 is a Lov region. On the other hand, the first n-type impurity region 104a and the first n-type impurity region 104b are Loff regions because they are not covered with the gate electrode layer 205 and the gate electrode layer 202 formed thereafter.

    Next, after an insulating layer covering the first conductive film 106, the gate electrode layer 205, and the like is formed, the insulating layer is processed by anisotropic etching by a RIE (Reactive ion etching) method. Sidewalls (sidewall spacers) 201 are formed on the side walls of the layer 205 in a self-aligning manner (see FIG. 1D). Here, there is no particular limitation on the insulating layer, and the insulating layer may be silicon oxide with good step coverage formed by reacting TEOS (Tetra-Ethyl-Orso-Silicate) or silane with oxygen or nitrous oxide. preferable. The insulating layer can be formed by a method such as thermal CVD, plasma CVD, atmospheric pressure CVD, bias ECRCVD, or sputtering.

In this embodiment mode, since the gate electrode layer has a stacked structure, the first conductive film 106 functions as an etching stopper. Next, the first conductive film 106 is etched using the first gate electrode layer 205 and the sidewall 201 as a mask, so that the second gate electrode layer 202 is formed. In this embodiment mode, the first conductive film 106 and the second conductive film 107 are formed using a material with a high etching selection ratio; therefore, the first gate electrode layer 205 is etched from the first conductive film 106. It can be used as a mask when In the case where the etching selectivity between the first conductive film 106 and the second conductive film 107 is not so high, an insulating layer is formed over the first gate electrode layer 205 when the sidewall 201 is formed. Alternatively, a resist mask may be formed over the first gate electrode layer 205. By protecting the first gate electrode layer 205 in this manner, the first gate electrode layer 205 can be prevented from being reduced when the first conductive film 106 is etched. The etching method may be a dry etching method or a wet etching method, and a known etching method can be used. In this embodiment mode, a dry etching method is used. As the etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , SF ₆ or NF _3, or O ₂ is appropriately used. it can.

Next, using the sidewall 201 and the first gate electrode layer 205 as a mask, an impurity element 253 imparting n-type is added to the semiconductor layer 102 substantially perpendicularly to the surface of the semiconductor layer 102, and the second n-type is added. An impurity region 203a and a second n-type impurity region 203b are formed (see FIG. 2A). Here, the second n-type impurity region 203a and the second n-type impurity region 203b include an impurity element imparting n-type at a concentration of about 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ^3. Added. In this embodiment mode, phosphorus (P) is used as the impurity element imparting n-type conductivity. The regions where the sidewall 201 serves as a mask and the impurity element imparting n-type conductivity is not added are a third n-type impurity region 206a and a third n-type impurity region 206b. The third n-type impurity region 206 a and the third n-type impurity region 206 b are Lov regions because they are covered with the second gate electrode layer 202. Note that a channel formation region 207 is formed in the semiconductor layer 102 (see FIG. 2A).

    The second n-type impurity region 203a and the second n-type impurity region 203b are high-concentration impurity regions in which the concentration of an impurity element imparting n-type is high, and function as a source region and a drain region. On the other hand, the third n-type impurity region 206a and the third n-type impurity region 206b, which are low-concentration impurity regions, are covered with the second gate electrode layer 202. It is possible to suppress the deterioration of the on-current due to. As a result, a semiconductor device capable of high speed operation can be formed.

    In order to activate the impurity element, heat treatment, intense light irradiation, or laser light irradiation may be performed. Simultaneously with activation, plasma damage to the gate insulating layer and plasma damage to the interface between the gate insulating layer and the semiconductor layer can be recovered.

    Next, an insulating film 108 containing hydrogen is formed as a passivation film. The insulating film 108 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm using a plasma CVD method or a sputtering method. The insulating film 108 is not limited to a silicon nitride film, and may be a silicon nitride oxide (SiNO) film using plasma CVD, or an insulating film containing other silicon may be used as a single layer or a laminated structure.

    Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in a nitrogen atmosphere to perform a step of hydrogenating the semiconductor layer. Preferably, it carries out at 400-500 degreeC. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the insulating film 108.

    The insulating film 108 includes silicon nitride, silicon oxide, silicon oxynitride (SiON), silicon nitride oxide (SiNO), aluminum nitride (AlN), aluminum oxynitride (AlON), and aluminum nitride oxide having a nitrogen content higher than the oxygen content. (AlNO) or aluminum oxide, diamond-like carbon (DLC), and a material selected from substances including a nitrogen-containing carbon film (CN). In addition, a skeleton structure is formed by a bond of silicon (Si) and oxygen (O), and at least one of a material containing at least hydrogen as a substituent, or fluorine, an alkyl group, or an aromatic hydrocarbon as a substituent. You may use the material which has.

  Next, an insulating layer 109 to be an interlayer insulating film is formed (see FIG. 2B). In the present invention, an interlayer insulating film provided for planarization is required to have high heat resistance and insulation and a high planarization rate. As a method for forming such an insulating layer, a coating method typified by a spin coating method is preferably used.

  In this embodiment mode, a siloxane resin is used as a material for the insulating layer 109. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. The film after baking can be called a silicon oxide film (SiOx) containing an alkyl group. This silicon oxide (SiOx) film containing an alkyl group can withstand heat treatment at 300 ° C. or higher.

  For the insulating layer 109, dipping, spray coating, doctor knife, roll coater, curtain coater, knife coater, spin coating, CVD method, vapor deposition method, or the like can be employed. The insulating layer 109 may be formed by a droplet discharge method. When the droplet discharge method is used, the material liquid can be saved. Further, a method capable of transferring or drawing a pattern, such as a droplet discharge method, for example, a printing method (a method for forming a pattern such as screen printing or offset printing) or the like can be used. In addition, an inorganic material may be used. In that case, silicon oxide, silicon nitride, or silicon oxynitride can be used.

  The insulating layer 109 can be an inorganic material (silicon oxide) as long as it has high heat resistance and good planarity in addition to an insulating film having a skeleton structure formed of a bond of silicon (Si) and oxygen (O). , Silicon nitride, silicon oxynitride, silicon nitride oxide, PSG (phosphorus glass), BPSG (phosphorus boron glass), alumina film, etc.), photosensitive or non-photosensitive organic material (organic resin material) (polyimide, acrylic, polyamide) , Polyimide amide, benzocyclobutene, etc.), a resist, a low-k material having a low dielectric constant, or a film made of a plurality of types, or a stack of these films.

    Next, contact holes (openings) reaching the semiconductor layer 102 are formed in the insulating layer 109, the insulating film 108, and the gate insulating layer 105 using a resist mask. Etching may be performed once or a plurality of times depending on the selection ratio of the material to be used. In this embodiment, the first etching is performed under conditions where the selection ratio between the insulating layer 109 and the insulating film 108 and the gate insulating layer 105 is high, so that the insulating layer 109 and the insulating film 108 are removed. Next, the gate insulating layer 105 is removed by second etching, and an opening 204 reaching the second n-type impurity region 203a and the second n-type impurity region 203b which are the source region and the drain region is formed (FIG. 2 (C).)

First etching is performed to remove the insulating layer 109 and the insulating film 108. Etching (wet etching or dry etching) is performed. An inert gas may be added to the etching gas used. As the inert element to be added, one or more elements selected from He, Ne, Ar, Kr, and Xe can be used. Among them, it is preferable to use argon which has a relatively large atomic radius and is inexpensive. In this embodiment mode, CF ₄ , O ₂ , He, and Ar are used. The etching conditions for dry etching are CF ₄ flow rate of 380 sccm, O ₂ flow rate of 290 sccm, He flow rate of 500 sccm, Ar flow rate of 500 sccm, RF power of 3000 W, and pressure of 25 Pa. Etching residues can be reduced under the above conditions.

Note that in order to perform etching without leaving a residue on the gate insulating layer 105, it is preferable to increase the etching time at a rate of about 10 to 20% and perform over-etching. A taper shape may be formed by one etching, or a taper shape may be formed by a plurality of etchings. Further, using CF ₄ , O ₂ , and He, the second dry etching is performed with a CF ₄ flow rate of 550 sccm, an O ₂ flow rate of 450 sccm, a He flow rate of 350 sccm, an RF power of 3000 W, and a pressure of 25 Pa. It may be a tapered shape.

Next, as the second etching, the gate insulating layer 105 is etched to form openings reaching the source region and the drain region. The opening may be formed by etching the insulating layer 109 and then forming a mask again, or by etching the insulating film 108 and the gate insulating layer 105 using the etched insulating layer 109 as a mask. The gate insulating layer 105 is etched using CHF ₃ and Ar as etching gases. By etching under the above conditions, an etching residue can be reduced and a contact hole with high flatness with less unevenness can be formed. In order to perform etching without leaving a residue on the semiconductor layer, it is preferable to increase the etching time at a rate of about 10 to 20%.

    A conductive film is formed, and the conductive film is etched to form a source electrode layer or a drain electrode layer 112 that is electrically connected to part of each source region or drain region. The source or drain electrode layer 112 is a wiring that is in contact with a wiring or the like to be formed later and connects the thin film transistor and the wiring. The source or drain electrode layer 112 can be formed by forming a conductive film by a PVD method, a CVD method, an evaporation method, or the like, and then etching it into a desired shape. Further, the conductive layer can be selectively formed at a predetermined place by a droplet discharge method, a printing method, an electroplating method, or the like. Furthermore, a reflow method or a damascene method may be used. The material of the source or drain electrode layer 112 is Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, It is formed using a metal such as Ba or an alloy thereof, or a metal nitride thereof. Moreover, it is good also as these laminated structures. In this embodiment mode, Ti, Al, and Ti are stacked and then patterned into a desired shape to form the source or drain electrode layer 112.

    Through the above steps, the second n-type impurity region 203a, which is a high-concentration impurity region, the second n-type impurity region 203b, the third n-type impurity region 206a, which is a low-concentration impurity region, and the third layer are formed in the semiconductor layer. The thin film transistor 150 including the n-type impurity region 206b, the second p-type impurity region 208, and the channel formation region 207 can be formed (see FIG. 2D). The width D2 of the second p-type impurity region 208 shown in FIG. 2D is preferably 5 to 200 nm, and the widths of the third n-type impurity region 206a and the third n-type impurity region 206b are 10 to 200 nm. preferable. By setting the width D2 of the second p-type impurity region 208 and the width D3 of the third n-type impurity region 206a within the above ranges, the threshold value can be shifted and the cut-off current can be reduced. An n-channel thin film transistor can be manufactured.

  In this embodiment mode, a low-concentration p-type impurity region is formed in an n-channel thin film transistor; however, a low-concentration n-type impurity region can be formed in a p-channel thin film transistor in the same manner. Similarly, an n-type impurity region can be formed by adding an impurity element imparting n-type to the region of the second p-type impurity region 208 in the n-channel thin film transistor 150 manufactured in this embodiment. . In this case, an n-channel thin film transistor having an n-type impurity region in one Lov region on the source side or the drain side can be manufactured. Similarly, when a p-channel type thin film transistor is doped obliquely as shown in this embodiment to form a p-type impurity region, a p-type impurity region is provided in one Lov region on the source side or the drain side. A thin film transistor can be manufactured.

Further, the thin film transistor 150 from the substrate 100 shown in FIGS. 1 and 2 can be peeled by the following method. As a peeling method, (1) a substrate having a heat resistance of about 300 to 500 degrees is used as the substrate 100, a metal oxide film is provided between the substrate 100 and the thin film transistor 150, and the metal oxide film is weakened by crystallization. (2) An amorphous silicon film containing hydrogen is provided between the substrate 100 and the thin film transistor 150, and the amorphous silicon film is formed by laser irradiation or etching with a gas / solution. A method of removing the thin film transistor 150 by removing, (3) A method of separating the thin film transistor 150 by mechanically removing the substrate 100 on which the thin film transistor 150 is formed, or removing the substrate 100 by etching with a gas such as a solution or CF _3. Etc. In addition, the peeled thin film transistor 150 can be attached to a variety of materials or properties depending on the intended use. For example, a commercially available adhesive may be used for attachment to the flexible substrate, and an adhesive such as an epoxy resin adhesive or a resin additive may be used.

  As described above, when the peeled thin film transistor 150 is attached to a flexible substrate, it is possible to provide a semiconductor device that is thin, light, and difficult to break even when dropped. In addition, since the flexible substrate has flexibility, it can be bonded onto an irregular shape having a curved surface or unevenness, thereby realizing a wide variety of uses. Further, if the substrate 100 is reused, an inexpensive semiconductor device can be provided. Further, since the thin film transistor formed in this embodiment has a sidewall structure, an LDD region can be formed even in a thin film transistor having a submicron structure.

  When the present invention is used, the semiconductor layer has an impurity region having an impurity element imparting a different conductivity type, so that the fine characteristics of the thin film transistor can be controlled. Accordingly, a thin film transistor having a required function can be formed through a simple process, and a semiconductor device with high reliability and electrical characteristics can be manufactured at low cost. Since the thin film transistor in this embodiment is an n-channel thin film transistor having a low-concentration p-type impurity region, a semiconductor device capable of high-speed operation and reduced power consumption can be formed.

  Further, since the semiconductor device formed in this embodiment can be formed using a crystalline semiconductor film, the semiconductor device can be manufactured without using an expensive single crystal semiconductor substrate. For this reason, cost reduction is possible. Further, a thin semiconductor device can be manufactured by peeling the thin film transistor 150 manufactured in this embodiment and bonding the thin film transistor 150 to a flexible substrate.

(Embodiment 2)
An embodiment of the present invention will be described with reference to FIGS. In this embodiment mode, the semiconductor device manufactured in Embodiment Mode 1 shows a case where the doping angle θ1 of the impurity element into the semiconductor layer is different. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    As described in Embodiment 1, the semiconductor layer 102 is formed over the substrate 100, and the gate insulating layer 105, the conductive film 106, and the first gate electrode layer 205 are formed.

The angle θ1 at which the semiconductor element is doped into the semiconductor layer in the first embodiment is in the range of 30 to 90 degrees. In the present embodiment, the angle θ1 is set in the range of 90 degrees to 150 degrees. Since the impurity element 651 imparting p-type is doped obliquely toward the surface of the semiconductor layer, the impurity element 651 is also added to the region of the semiconductor layer 102 covered with the first gate electrode layer 205, so that the first p-type impurity region is added. 603a is formed. On the other hand, part of the impurity element imparting p-type conductivity is shielded by the first gate electrode layer 205, so that the first p-type impurity region 603 b includes a semiconductor region covered with the gate electrode layer 205. Not. Accordingly, a p-type impurity region is selectively formed in the semiconductor layer 102, so that a first p-type impurity region 603a and a first p-type impurity region 603b are formed (see FIG. 29A). Here, the first p-type impurity region 603a and the first p-type impurity region 603b include the impurity element imparting p-type at a concentration of about 5 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ^3. Added. Further, the impurity element imparting p-type conductivity may be added so as to be contained at a concentration of about 5 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity.

    FIG. 29B illustrates a thin film transistor 650 manufactured in this embodiment. In this embodiment, since the angle θ1 for doping the impurity element 651 imparting p-type is set in the range of 90 to 150 degrees, the second p-type impurity region 608 which is a low-concentration p-type impurity region is 3 between the n-type impurity region 206 a and the channel formation region 207. In this manner, by controlling the angle θ at which the semiconductor layer is doped, thin film transistors having different impurity region structures can be manufactured, and the electrical characteristics of the thin film transistors can be controlled.

  When the present invention is used, the semiconductor layer has an impurity region having an impurity element imparting a different conductivity type, so that the fine characteristics of the thin film transistor can be controlled. Accordingly, a thin film transistor having a required function can be formed through a simple process, and a semiconductor device with high reliability and electrical characteristics can be manufactured at low cost. Since the thin film transistor in this embodiment is an n-channel thin film transistor having a low-concentration p-type impurity region, a semiconductor device capable of high-speed operation and reduced power consumption can be formed.

(Embodiment 3)
An embodiment of the present invention will be described with reference to FIGS. This embodiment shows an example in which the structure of the gate electrode layer of the thin film transistor 150 and the impurity region in the semiconductor layer are different from each other in the semiconductor device manufactured in Embodiment 1. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    As in Embodiment Mode 1, a base film 101a and a base film 101b are stacked over the substrate 100 as base films to form the semiconductor layer 102. The semiconductor layer 102 is formed by crystallizing an amorphous semiconductor film by laser irradiation and patterning the formed crystalline semiconductor film. A gate insulating layer 105 is formed over the semiconductor layer 102, and a second conductive film 107 is formed (see FIG. 4A). In Embodiment 1, the first conductive film 106 is formed because the gate electrode layer has a stacked structure; however, in this embodiment, the second conductive film 107 is formed because the gate electrode layer has a single-layer structure. Only form.

    The second conductive film 107 is etched so as to be a thin line as shown in FIG. 3, so that the first gate electrode layer 205 is formed. Using the first gate electrode layer 205 as a mask, an impurity element 251 imparting p-type is obliquely added to the surface of the semiconductor layer 102 at an angle θ1 of 30 to 90 degrees and 90 to 150 degrees, The p-type impurity region 103a and the first p-type impurity region 103b are formed (see FIG. 4B). Since the impurity element 251 imparting p-type conductivity is doped obliquely, the first p-type impurity region 103b is also formed in the semiconductor layer covered with the first gate electrode layer 205. On the other hand, the first gate electrode layer 205 is used as a mask to shield the impurity element 251 imparting p-type, so that the first p-type impurity region 103a is formed under the first gate electrode layer 205. It is not formed in the semiconductor layer portion.

    Next, using the first gate electrode layer 205 as a mask, an impurity element imparting n-type conductivity to the surface of the semiconductor layer 102 at an angle θ2 is added to the semiconductor layer 102 so that the first n-type impurity region 104a and the first An n-type impurity region 104b is formed (see FIG. 4C). The angle θ2 is set to be different from the angle θ1 by 5 degrees or more. Since the impurity element imparting p-type conductivity is added to the first n-type impurity region 104a and the first n-type impurity region 104b, the n-type impurity region 104a is inverted to the n-type impurity region. An impurity element to be added is added. Since the impurity element 252 imparting n-type conductivity is added almost vertically, it is shielded by the first gate electrode layer 205 and is not added to the region of the semiconductor layer covered with the first gate electrode layer. Therefore, a part of the first p-type impurity region formed in the semiconductor layer under the first gate electrode layer 205 remains and becomes the second p-type impurity region 208.

    An insulating layer is formed over the gate insulating layer 105 and the first gate electrode layer 205, anisotropic etching is performed, and sidewalls 201 are formed on side surfaces of the first gate electrode layer 205 (see FIG. 4D). .) Using the sidewall 201 and the first gate electrode layer 205 as a mask, an impurity element 253 imparting n-type is added to the surface of the semiconductor layer 102 at an angle substantially the same as the angle θ2 to the semiconductor layer 102, and a second n-type impurity is added. A region 203a and a second n-type impurity region 203b are formed (see FIG. 5A). Since the impurity element 253 imparting n-type conductivity is not added to the semiconductor layer covered with the sidewalls, the third n-type impurity region 206a and the third n-type impurity region 206b, which are low-concentration n-type regions, Become. Note that a channel formation region 207 is formed in the semiconductor layer 102. Since the second n-type impurity region 203a and the second n-type impurity region 203b are high-concentration impurity regions, they function as a source region or a drain region. In Embodiment 1, since the gate electrode layer has a stacked structure, the second gate electrode layer 202 is provided over the third n-type impurity region 206a and the third n-type impurity region 206b with the gate insulating layer 105 interposed therebetween. The third n-type impurity region 206a and the third n-type impurity region 206b are Lov regions. In this embodiment mode, since the second gate electrode layer 202 is not formed over the third n-type impurity region 206a and the third n-type impurity region 206b, a Loff region is formed. In this manner, the structure of the impurity region to be formed can be controlled by changing the structure of the gate electrode layer. Therefore, the setting of the characteristics of the thin film transistor associated therewith can also have a degree of freedom.

    An insulating film 108 for hydrogenation is appropriately formed by heat treatment, laser irradiation, or the like for activating the impurity element. Hydrogenation is performed by heat treatment, so that the insulating layer 109 is formed (see FIG. 5B). The heat treatment for activating the impurity element and the heat treatment for hydrogenation may be performed in the same process, and the process can be simplified.

    Openings (contact holes) 204 reaching the source and drain regions are formed in the insulating layer 109, the insulating film 108, and the gate insulating layer 105 (see FIG. 5C). A source or drain electrode layer 112 in contact with the source region or the drain region is formed in the opening 204. Thus, the thin film transistor 150 in this embodiment is manufactured (see FIG. 5D).

  When the present invention is used, the semiconductor layer has an impurity region having an impurity element imparting a different conductivity type, so that the fine characteristics of the thin film transistor can be controlled. Accordingly, a thin film transistor having a required function can be formed through a simple process, and a semiconductor device with high reliability and electrical characteristics can be manufactured at low cost. Since the thin film transistor in this embodiment is an n-channel thin film transistor having a low-concentration p-type impurity region, a semiconductor device capable of high-speed operation and reduced power consumption can be formed.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 and 2.

(Embodiment 4)
An embodiment of the present invention will be described with reference to FIGS. This embodiment shows an example in which a processor such as a CPU is manufactured as a semiconductor device in which the thin film transistor 150, the n-channel thin film transistor, and the p-channel thin film transistor manufactured in Embodiment 1 are formed over the same substrate. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    As in Embodiment 1, a base film 301 a and a base film 301 b are stacked over the substrate 300 as base films, and a semiconductor layer 302, a semiconductor layer 303, and a semiconductor layer 304 are formed. The semiconductor layer 302, the semiconductor layer 303, and the semiconductor layer 304 are formed by crystallizing an amorphous semiconductor film by laser irradiation and patterning the formed crystalline semiconductor film. In this embodiment mode, silicon is used as a material for the semiconductor layer, and the amorphous silicon film is irradiated with laser to form a crystalline silicon film having continuously grown crystal grains.

    A method for crystallizing a semiconductor layer in this embodiment will be described with reference to FIGS. FIG. 15A is a perspective view of a substrate over which a semiconductor layer is formed in this embodiment mode, and FIG. 15B is a region 808 which is part of the crystalline semiconductor film in FIG. FIG. 15B, a semiconductor layer 304, a semiconductor layer 302, and a semiconductor layer 303 correspond to the semiconductor layers of the thin film transistors in FIGS. 6 and 7, and FIGS. 6 and 7 illustrate a line (A) in FIG. -It is sectional drawing in (B) and line (C)-(D).

    A base film 301a and a base film 301b are formed over the substrate 300, and an amorphous semiconductor film 801 is formed over the base film. In FIG. 15A, the base film 301a and the base film 301b are collectively referred to as a base film 301. A crystalline semiconductor film 803 is formed by irradiating the amorphous semiconductor film 801 with laser light 802. In this embodiment mode, as shown in FIG. 15A, the amorphous semiconductor film 801 is irradiated with laser light having a pulsed laser light oscillation frequency of 80 MHz as the laser light 802 as indicated by an arrow. A crystalline semiconductor film 803 having crystal grains continuously grown in the scanning direction 804 is formed. By forming single crystal grains that extend long along the scanning direction, it is possible to form a semiconductor film that has at least few crystal grain boundaries that hinder the movement of carriers in the thin film transistor.

    Next, as illustrated in FIG. 6A, a mask is formed over the crystalline semiconductor film by a photolithography step, and part of the crystalline semiconductor film is etched using the mask, so that the semiconductor layer 302, the semiconductor layer 303 and the semiconductor layer 304 are formed. Note that the semiconductor layer 302, the semiconductor layer 303, and the semiconductor layer 304 are etched so that a channel formation region of a thin film transistor to be formed later is parallel to the scanning direction 804 of the laser light 802.

    As shown in FIG. 15B, the semiconductor layer 302, the channel formation region 302a of the semiconductor layer 303, and the semiconductor layer 304, the channel formation region 303a, and the channel formation region 304a are parallel to the laser beam scanning direction 804, respectively. The semiconductor layer 302 has an active region of a p-channel thin film transistor 330 formed later, the semiconductor layer 303 has an active region of an n-channel thin film transistor 331 formed later, and the semiconductor layer 304 has a low-concentration p-type impurity region formed later. It functions as an active region of the n-channel thin film transistor 332.

    A gate insulating layer 395 is formed over the semiconductor layer 302, the semiconductor layer 303, and the semiconductor layer 304, and a first conductive film 396 and a second conductive film 397 are formed (see FIG. 6A). In this embodiment, a thin silicon oxide film with a thickness of 2 to 5 nm is formed as a first insulating film over the semiconductor layer 302, the semiconductor layer 303, and the semiconductor layer 304 by a GRTA (Gas Rapid Thermal Anneal) method. A stack of three layers of a silicon nitride film, a silicon oxide film, and a silicon nitride film is used as the gate insulating layer 395 over the first insulating film. The first conductive film 396 is formed by sputtering using TaN, and the second conductive film 397 is formed by using W.

    The second conductive film 397 is etched so as to be a thin line as shown in FIG. 3, so that the first gate electrode layer 305, the first gate electrode layer 306, and the first gate electrode layer 307 are formed. A resist mask 361 is formed so as to cover the semiconductor layer 302 and the semiconductor layer 303.

With the first gate electrode layer 307 as a mask, an impurity element 351 imparting p-type is obliquely applied to the semiconductor layer 304 at an angle θ1 of 30 to 90 degrees and 90 to 150 degrees toward the surface of the semiconductor layer 304. Addition is performed to form a first p-type impurity region 308a and a first p-type impurity region 308b (see FIG. 6B). Since the impurity element 351 imparting p-type conductivity is doped obliquely, the first p-type impurity region 308b is also formed in a portion of the semiconductor layer 304 covered with the first gate electrode layer 307. On the other hand, since the first gate electrode layer 307 is used as a mask to shield the impurity element 351 imparting p-type conductivity, the first p-type impurity region 308a is formed under the first gate electrode layer 307. The semiconductor layer 304 is not formed. Here, the first p-type impurity region 308a and the first p-type impurity region 308b include the impurity element imparting p-type at a concentration of about 5 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ^3. Added. Further, the impurity element imparting p-type conductivity may be added so as to be contained at a concentration of about 5 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity.

Next, the mask 361 is removed, and a mask 362 made of a resist that covers the semiconductor layer 302 is formed. The mask 362 may be newly formed or may be formed by processing the mask 361. Using the first gate electrode layer 306 and the first gate electrode layer 307 as a mask, an impurity element imparting n-type conductivity is added to the semiconductor layer 303 and the semiconductor layer 304 at an angle θ2 substantially perpendicular to the surface of the semiconductor layer. One n-type impurity region 309a, a first n-type impurity region 309b, a first n-type impurity region 310a, and a first n-type impurity region 310b are formed (see FIG. 6C). The angle θ2 is set to be different from the angle θ1 by 5 degrees or more. An impurity element imparting p-type conductivity is added to the first p-type impurity region 308a and the first p-type impurity region 308b, and thus an impurity imparting n-type is inverted so as to be inverted to the n-type impurity region. Add elements. The first n-type impurity region 309a, the first n-type impurity region 309b, the first n-type impurity region 310a, and the first n-type impurity region 310b typically have a concentration of 1 × 10 ^{17 to} 5 × 10. ^It is formed so as to contain an impurity element imparting n-type at ¹⁸ / cm ³ . In this embodiment mode, phosphorus (P) is used as the impurity element imparting n-type conductivity. Since the impurity element 352 imparting n-type conductivity is added substantially perpendicularly, the impurity element 352 is shielded by the first gate electrode layer 306 and the first gate electrode layer 307, and thus the first gate electrode layer 306 and the first gate electrode The semiconductor layer 303 and the semiconductor layer 304 which are covered with the layer 307 are not added to the regions. Therefore, a part of the first p-type impurity region formed in the semiconductor layer under the first gate electrode layer 307 remains and becomes the second p-type impurity region 324. The second p-type impurity region 324 is formed as a Lov region.

    The mask 362 is removed by etching or the like, and an insulating layer is formed over the first conductive film 396, the first gate electrode layer 305, the first gate electrode layer 306, and the first gate electrode layer 307. Etching is performed to form sidewalls 311, 312, and 313 on the side surfaces of the first gate electrode layer 305, the first gate electrode layer 306, and the first gate electrode layer 307. In this embodiment mode, silicon oxide is used as an insulating layer for forming the sidewall. Next, the first conductive film 396 is formed using the first gate electrode layer 305, the first gate electrode layer 306, the first gate electrode layer 307, the sidewall 311, the sidewall 312, and the sidewall 313 as a mask. Etching is performed to form a second gate electrode layer 380, a second gate electrode layer 381, and a second gate electrode layer 382 (see FIG. 6D). In this embodiment, the first conductive film 396 and the second conductive film 397 are formed using a material with a high etching selection ratio; therefore, the first gate electrode layer 305, the first gate electrode layer 306, The first gate electrode layer 307 can be used as a mask when the first conductive film 396 is etched. When the etching selectivity between the first conductive film 396 and the second conductive film 397 is not so high, the insulating layer is used as the first gate electrode when forming the sidewall 311, the sidewall 312, and the sidewall 313. The first gate electrode layer 305, the first gate electrode layer 306, the first gate electrode layer 307, the first gate electrode layer 307, the first gate electrode layer 307, and the first gate electrode layer 307. A resist mask may be formed over the electrode layer 306 and the first gate electrode layer 307. When the first conductive film 396 is etched by protecting the first gate electrode layer 305, the first gate electrode layer 306, and the first gate electrode layer 307 in this manner, the first gate electrode layer 305, the first gate electrode layer 306, and the first gate electrode layer 307 can be prevented from being reduced.

A mask 363 made of a resist that covers the semiconductor layer 302 is formed. Impurities imparting n-type to the semiconductor layer 303 and the semiconductor layer 304 almost perpendicularly to the surface of the semiconductor layer with the sidewalls 312, 313, the first gate electrode layer 306, and the first gate electrode layer 307 as masks The element 353 is added to form a second n-type impurity region 314a, a second n-type impurity region 314b, a second n-type impurity region 315a, and a second n-type impurity region 315b (FIG. 7A). reference.). Since the impurity element 353 imparting n-type is not added to the semiconductor layer covered with the sidewalls, the third n-type impurity region 320a, the third n-type impurity region 320b, which are low-concentration n-type regions, A third n-type impurity region 322a and a third n-type impurity region 322b are formed. Note that a channel formation region 321 and a channel formation region 323 are formed in the semiconductor layer 303 and the semiconductor layer 304. Since the second n-type impurity region 314a, the second n-type impurity region 314b, the second n-type impurity region 315a, and the second n-type impurity region 315b are high-concentration impurity regions, the source region or the drain region Function as. In the second n-type impurity region 314a, the second n-type impurity region 314b, the second n-type impurity region 315a, and the second n-type impurity region 315b, an impurity element imparting n-type conductivity is 5 × 10 ¹⁹ to It is added so as to be contained at a concentration of about 5 × 10 ²⁰ / cm ³ . In this embodiment mode, phosphorus (P) is used as the impurity element imparting n-type conductivity.

  On the other hand, the third n-type impurity region 320a, the third n-type impurity region 320b, the third n-type impurity region 322a, and the third n-type impurity region 322b, which are low-concentration impurity regions, are formed in the second gate electrode layer. 381, the Lov region covered with the second gate electrode layer 382, the electric field in the vicinity of the drain can be relaxed, and deterioration of on-current due to hot carriers can be suppressed. As a result, a semiconductor device capable of high speed operation can be formed.

A mask 364 made of a resist that covers the semiconductor layer 303 and the semiconductor layer 304 is formed. Using the mask 364, the sidewalls 311 and the first gate electrode layer 305 as masks, an impurity element 354 imparting p-type conductivity is added to the semiconductor layer 302 in a direction perpendicular to the surface of the semiconductor layer 302, so that a third p-type impurity is added. An impurity region 316a and a third p-type impurity region 316b are formed (see FIG. 7B). Here, the third p-type impurity region 316a and the third p-type impurity region 316b include the impurity element imparting p-type at a concentration of about 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ^3. Added. In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity.

  The sidewall 311 is removed to expose a part of the second gate electrode layer 380, and the exposed portion of the second gate electrode layer 380 is etched using the first gate electrode layer 305 as a mask. Accordingly, the second gate electrode layer 383 having a width substantially equal to that of the first gate electrode layer 305 is formed. Note that in this etching step, in the case where the gate insulating layer 395 is formed using the same material as the sidewall 311, a mask that covers the gate insulating layer 395 except for the sidewall 311 and the first gate electrode layer 305 may be formed. .

A mask 365 made of a resist that covers the semiconductor layer 303 and the semiconductor layer 304 is formed. The mask 365 may be used as it is without removing the mask 364, may be formed by processing the mask 364, or may be newly formed. Using the mask 365 and the first gate electrode layer 305 as a mask, an impurity element 355 imparting p-type conductivity is added to the semiconductor layer 302 in a direction perpendicular to the surface of the semiconductor layer 302, so that fourth p-type impurity regions 317a, A fourth p-type impurity region 317b, a fifth p-type impurity region 318a, and a fifth p-type impurity region 318b are formed (see FIG. 7C). Here, the fourth p-type impurity region 317a and the fourth p-type impurity region 317b include the impurity element imparting p-type at a concentration of about 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ^3. Added. Further, the fifth p-type impurity region 318a and the fifth p-type impurity region 318b are added so that the impurity element imparting p-type is contained at a concentration of about 5 × 10 ^{18 to} 5 × 10 ¹⁹ / cm ^3. To do. In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity. Note that a channel formation region 319 is formed in the semiconductor layer 302.

  The fourth p-type impurity region 317a and the fourth p-type impurity region 317b are high-concentration impurity regions and function as a source region or a drain region. The fifth p-type impurity region 318a and the fifth p-type impurity region 318b are low-concentration impurity regions and are formed as Loff regions that are not covered with the gate electrode layer. Since the fifth p-type impurity region 318a and the fifth p-type impurity region 318b are not covered with the gate electrode layer, the electric field in the vicinity of the drain is relaxed to prevent deterioration due to hot carrier injection, and the off-current is reduced. effective. As a result, a highly reliable semiconductor device with low power consumption can be manufactured.

    An insulating film 325 for hydrogenation is appropriately formed by heat treatment, laser irradiation, or the like for activating the impurity element. Hydrogenation is performed by heat treatment, so that the insulating layer 326 is formed. The heat treatment for activating the impurity element and the heat treatment for hydrogenation may be performed in the same process, and the process can be simplified.

    Openings (contact holes) reaching the source region and the drain region are formed in the insulating layer 326, the insulating film 325, and the gate insulating layer 395. A source or drain electrode layer 328a in contact with a source region or a drain region, a source or drain electrode layer 328b, a source or drain electrode layer 329a, a source or drain electrode layer 329b, a source electrode layer or A drain electrode layer 327a and a source or drain electrode layer 327b are formed (see FIG. 7D). Therefore, the p-channel thin film transistor 330, the n-channel thin film transistor 331, and the n-channel thin film transistor 332 including the p-type impurity region in this embodiment are manufactured, and a semiconductor device using the n-channel thin film transistor 332 is manufactured. In this embodiment, a processor (system processor) in which a CMOS circuit and a thin film transistor whose characteristics are controlled is provided over the same substrate.

    When the present invention is used, the semiconductor layer has an impurity region having an impurity element imparting a different conductivity type, so that the fine characteristics of the thin film transistor can be controlled. Accordingly, a thin film transistor having a required function can be formed through a simple process, and a semiconductor device with high reliability and electrical characteristics can be manufactured at low cost. That is, functional circuits that emphasize high-speed operation such as a CPU (processor), DRAM, image processing circuit, and audio processing circuit, and drive circuits that emphasize high-voltage characteristics such as buffer circuits, shift register circuits, level shifter circuits, and sampling circuits Can be formed on the same substrate. For this reason, semiconductor devices having elements having various functions and structures, such as a system LSI, can be manufactured on the same substrate. Since the thin film transistor in this embodiment is an n-channel thin film transistor having a low-concentration p-type impurity region, a semiconductor device capable of high-speed operation and reduced power consumption can be formed.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 to 3.

(Embodiment 5)
An embodiment of the present invention will be described with reference to FIGS. This embodiment mode shows an example in which an n-channel thin film transistor having two types of low-concentration p-type impurity regions is formed in the semiconductor device manufactured in Embodiment Mode 3. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    As in Embodiment 3, a base film 301 a and a base film 301 b are stacked over the substrate 300 as base films to form a semiconductor layer 302, a semiconductor layer 303, a semiconductor layer 304, and a semiconductor layer 370. The semiconductor layer 302, the semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370 are formed by crystallizing an amorphous semiconductor film by laser irradiation and patterning the formed crystalline semiconductor film. In this embodiment mode, silicon is used as a material for the semiconductor layer, and the amorphous silicon film is irradiated with laser light to form a crystalline silicon film having continuously grown crystal grains. Note that the semiconductor layer 302, the semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370 are formed so that a channel formation region of a thin film transistor to be formed later is parallel to the scanning direction of the laser light.

    A gate insulating layer 395 is formed over the semiconductor layer 302, the semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370, and a first conductive film 396 and a second conductive film 397 are formed (see FIG. 8A). ). In this embodiment, a thin silicon oxide film with a thickness of 2 to 5 nm is formed as a first insulating film over the semiconductor layer 302, the semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370 with a GRTA (Gas Rapid A stacked layer of a silicon nitride film, a silicon oxide film, and a silicon nitride film 3 is used as the gate insulating layer 395 over the first insulating film. The first conductive film 396 is formed by sputtering using TaN, and the second conductive film 397 is formed by using W.

    The second conductive film 397 is etched so as to be a thin line as shown in FIG. 3, so that the first gate electrode layer 305, the first gate electrode layer 306, the first gate electrode layer 307, and the first gate electrode layer 307 are formed. A gate electrode layer 371 is formed. A resist mask 361 is formed so as to cover the semiconductor layer 302 and the semiconductor layer 303.

Using the first gate electrode layer 307 as a mask, an impurity element 351 imparting p-type conductivity is applied to the semiconductor layer 304 and the semiconductor layer 370 at an angle θ1 of 30 to 90 degrees and 90 to 150 degrees toward the semiconductor layer surface. The first p-type impurity region 308a, the first p-type impurity region 308b, the first p-type impurity region 385a, and the first p-type impurity region 385b are formed (FIG. 8B). reference.). Since the impurity element 351 imparting p-type conductivity is doped obliquely, the first p-type impurity region 308b and the first p-type impurity region 385b include the first gate electrode layer 307 and the first gate electrode layer. The semiconductor layer 304 and the semiconductor layer 370 covered with 371 are also formed. On the other hand, the first gate electrode layer 307 and the first gate electrode layer 371 are used as a mask to shield the impurity element 351 imparting p-type conductivity, so that the first p-type impurity region 308a and the first p-type impurity region 351 are shielded. The impurity region 385a is not formed in the first gate electrode layer 307, the semiconductor layer 304 under which the first gate electrode layer 371 is formed, and the semiconductor layer 370. Here, the first p-type impurity region 308a, the first p-type impurity region 308b, the first p-type impurity region 385a, and the first p-type impurity region 385b have an impurity element imparting p-type of 5 ×. It is added so as to be contained at a concentration of about 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ . Further, the impurity element imparting p-type conductivity may be added so as to be contained at a concentration of about 5 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity.

    In this embodiment, in a thin film transistor including the semiconductor layer 304 to be formed later, a region in which the first p-type impurity region 308b is formed serves as a drain region, and in the thin film transistor including the semiconductor layer 370, the first p-type impurity is formed. A region where the region 385b is formed is a source region. By aligning the channel formation region of the semiconductor layer in parallel with the scanning direction of the laser beam and adding an impurity element obliquely from one direction using the gate electrode layer as a mask, the channel formation region and the source or drain region It is possible to form an impurity region of one conductivity type different from the conductivity of the thin film transistor only between one of the two. By using the present invention, both the thin film transistor having the different impurity region of one conductivity type in the source region and the thin film transistor having the impurity region of different conductivity type in the drain region can be formed in the same step. Which is set as the source region or the drain region can be freely designed depending on the wiring to be connected, and the present invention can sufficiently cope with any circuit. Accordingly, characteristics of finer thin film transistors can be controlled and a variety of thin film transistors can be manufactured. Therefore, a highly accurate semiconductor device that requires a plurality of circuits having different functions can be manufactured with high reliability.

Next, the mask 361 is removed, and a mask 362 made of a resist that covers the semiconductor layer 302 is formed. The mask 362 may be newly formed or may be formed by processing the mask 361. Using the first gate electrode layer 306, the first gate electrode layer 307, and the first gate electrode layer 371 as a mask, the semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370 are n-type with an angle θ2 on the surface of the semiconductor layer. An impurity element to be added is added, and the first n-type impurity region 309a, the first n-type impurity region 309b, the first n-type impurity region 310a, the first n-type impurity region 310b, and the first n-type impurity are added. A region 372a and a first n-type impurity region 372b are formed (see FIG. 8C). The angle θ2 is set to be different from the angle θ1 by 5 degrees or more. An impurity element imparting p-type conductivity is added to the first p-type impurity region 308a, the first p-type impurity region 308b, the first p-type impurity region 385a, and the first p-type impurity region 385b. Therefore, an impurity element imparting n-type conductivity is added so as to invert to the n-type impurity region. First n-type impurity region 309a, first n-type impurity region 309b, first n-type impurity region 310a, first n-type impurity region 310b, first n-type impurity region 372a, first n-type impurity region The impurity region 372b is typically formed so as to contain an impurity element imparting n-type at a concentration of 1 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ . In this embodiment mode, phosphorus (P) is used as the impurity element imparting n-type conductivity. Since the impurity element 352 imparting n-type conductivity is added substantially vertically, it is shielded by the first gate electrode layer 306, the first gate electrode layer 307, and the first gate electrode layer 371, so that the first gate electrode The semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370 which are covered with the layer 306, the first gate electrode layer 307, and the first gate electrode layer 371 are not added. Accordingly, part of the first p-type impurity region formed in the semiconductor layer below the first gate electrode layer 307 and the first gate electrode layer 371 remains, and the second p-type impurity region 324, A second p-type impurity region 377 is formed. The second p-type impurity region 324 and the second p-type impurity region 377 are formed as Lov regions.

    The mask 362 is removed by etching or the like, and is insulated over the first conductive film 396, the first gate electrode layer 305, the first gate electrode layer 306, the first gate electrode layer 307, and the first gate electrode layer 371. Layer is formed, anisotropic etching is performed, and a sidewall 311 is formed on side surfaces of the first gate electrode layer 305, the first gate electrode layer 306, the first gate electrode layer 307, and the first gate electrode layer 371. Sidewalls 312, 313, and 373 are formed. In this embodiment mode, silicon oxide is used as an insulating layer for forming the sidewall. Next, the first conductive film 396 is formed using the first gate electrode layer 305, the first gate electrode layer 306, the first gate electrode layer 307, the first gate electrode layer 371, the sidewall 311, and the sidewall 312. Etching is performed using the side wall 313 and the side wall 373 as a mask to form a second gate electrode layer 380, a second gate electrode layer 381, a second gate electrode layer 382, and a second gate electrode layer 379 (see FIG. (See FIG. 9A.) In this embodiment, the first conductive film 396 and the second conductive film 397 are formed using a material with a high etching selection ratio; therefore, the first gate electrode layer 305, the first gate electrode layer 306, The first gate electrode layer 307 and the first gate electrode layer 371 can be used as a mask when the first conductive film 396 is etched. In the case where the etching selection ratio between the first conductive film 396 and the second conductive film 397 is not so high, the insulating layer is formed when the sidewalls 311, 312, 313, and 373 are formed. The first gate electrode layer 305, the first gate electrode layer 306, the first gate electrode layer 307, the first gate electrode layer 371, or a protective film is formed on the gate electrode layer. A resist mask may be formed over the first gate electrode layer 305, the first gate electrode layer 306, the first gate electrode layer 307, and the first gate electrode layer 371. In this manner, the first conductive film 396 is etched by protecting the first gate electrode layer 305, the first gate electrode layer 306, the first gate electrode layer 307, and the first gate electrode layer 371. At this time, film loss of the first gate electrode layer 305, the first gate electrode layer 306, the first gate electrode layer 307, and the first gate electrode layer 371 can be prevented.

A mask 363 made of a resist that covers the semiconductor layer 302 is formed. The semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370 are formed using the sidewall 312, the sidewall 313, the sidewall 373, the first gate electrode layer 306, the first gate electrode layer 307, and the first gate electrode layer 371 as a mask. An impurity element 353 that imparts n-type conductivity is added to the surface of the semiconductor layer substantially perpendicularly to the surface of the semiconductor layer, so that the second n-type impurity region 314a, the second n-type impurity region 314b, the second n-type impurity region 315a, and the second An n-type impurity region 315b, a second n-type impurity region 374a, and a second n-type impurity region 374b are formed (see FIG. 9B). Since the impurity element 353 imparting n-type is not added to the semiconductor layer covered with the sidewalls, the third n-type impurity region 320a, the third n-type impurity region 320b, which are low-concentration n-type regions, A third n-type impurity region 322a, a third n-type impurity region 322b, a third n-type impurity region 375a, and a third n-type impurity region 375b are formed. Note that a channel formation region 321, a channel formation region 323, and a channel formation region 376 are formed in the semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370. Second n-type impurity region 314a, second n-type impurity region 314b, second n-type impurity region 315a, second n-type impurity region 315b, second n-type impurity region 374a, second n-type impurity region Since the impurity region 374b is a high-concentration impurity region, it functions as a source region or a drain region. In this embodiment mode, the second n-type impurity region 315b on the side where the second p-type impurity region 324 is formed is used as a drain region, and the side on which the second p-type impurity region 377 is formed. A certain second n-type impurity region 374b is used as a source region. Therefore, the second n-type impurity region 315a functions as a source region, and the second n-type impurity region 374a functions as a drain region. In the second n-type impurity region 314a, the second n-type impurity region 314b, the second n-type impurity region 315a, and the second n-type impurity region 315b, an impurity element imparting n-type conductivity is 5 × 10 ¹⁹ to It is added so as to be contained at a concentration of about 5 × 10 ²⁰ / cm ³ . In this embodiment mode, phosphorus (P) is used as the impurity element imparting n-type conductivity.

  On the other hand, the third n-type impurity region 320a, the third n-type impurity region 320b, the third n-type impurity region 322a, the third n-type impurity region 322b, and the third n-type impurity region which are low-concentration impurity regions. 375a and the third n-type impurity region 375b are Lov regions covered with the second gate electrode layer 381, the second gate electrode layer 382, and the second gate electrode layer 379; It is possible to relax and suppress deterioration of on-current due to hot carriers. As a result, a semiconductor device capable of high speed operation can be formed.

A mask 364 made of a resist that covers the semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370 is formed. Using the mask 364, the sidewall 311, and the first gate electrode layer 305 as a mask, an impurity element 354 imparting p-type conductivity is added to the semiconductor layer 302 almost perpendicularly to the surface of the semiconductor layer 302, so that a third p-type impurity is added. A region 316a and a third p-type impurity region 316b are formed (see FIG. 9C). Here, the third p-type impurity region 316a and the third p-type impurity region 316b include the impurity element imparting p-type at a concentration of about 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ^3. Added. In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity.

  The sidewall 311 is removed to expose a part of the second gate electrode layer 380, and the exposed portion of the second gate electrode layer 380 is etched using the first gate electrode layer 305 as a mask. Accordingly, the second gate electrode layer 383 having a width substantially equal to that of the first gate electrode layer 305 is formed. Note that in this etching step, in the case where the gate insulating layer 395 is formed using the same material as the sidewall 311, a mask that covers the gate insulating layer 395 except for the sidewall 311 and the first gate electrode layer 305 may be formed. .

A mask 365 made of a resist that covers the semiconductor layer 303, the semiconductor layer 304, and the semiconductor layer 370 is formed. The mask 365 may be used as it is without removing the mask 364, may be formed by processing the mask 364, or may be newly formed. Using the mask 365 and the first gate electrode layer 305 as a mask, an impurity element 355 imparting p-type conductivity is added to the semiconductor layer 302 substantially perpendicular to the surface of the semiconductor layer 302, so that a fourth p-type impurity region 317a, A fourth p-type impurity region 317b, a fifth p-type impurity region 318a, and a fifth p-type impurity region 318b are formed (see FIG. 10A). Here, the fourth p-type impurity region 317a and the fourth p-type impurity region 317b include the impurity element imparting p-type at a concentration of about 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ^3. Added. Further, the fifth p-type impurity region 318a and the fifth p-type impurity region 318b are added so that the impurity element imparting p-type is contained at a concentration of about 5 × 10 ^{18 to} 5 × 10 ¹⁹ / cm ^3. To do. In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity. Note that a channel formation region 319 is formed in the semiconductor layer 302.

  The fourth p-type impurity region 317a and the fourth p-type impurity region 317b are high-concentration impurity regions and function as a source region or a drain region. The fifth p-type impurity region 318a and the fifth p-type impurity region 318b are low-concentration impurity regions and are formed as Loff regions that are not covered with the gate electrode layer. Since the fifth p-type impurity region 318a and the fifth p-type impurity region 318b are not covered with the gate electrode layer, the electric field in the vicinity of the drain is relaxed to prevent deterioration due to hot carrier injection, and the off-current is reduced. effective. As a result, a highly reliable semiconductor device with low power consumption can be manufactured.

    An insulating film 325 for hydrogenation is appropriately formed by heat treatment, laser irradiation, or the like for activating the impurity element. Hydrogenation is performed by heat treatment, so that the insulating layer 326 is formed. The heat treatment for activating the impurity element and the heat treatment for hydrogenation may be performed in the same process, and the process can be simplified.

    Openings (contact holes) reaching the source region and the drain region are formed in the insulating layer 326, the insulating film 325, and the gate insulating layer 395. A source or drain electrode layer 328a in contact with a source region or a drain region, a source or drain electrode layer 328b, a source or drain electrode layer 329a, a source or drain electrode layer 329b, a source electrode layer or A drain electrode layer 327a, a source or drain electrode layer 327b, a source or drain electrode layer 398a, and a source or drain electrode layer 398b are formed (see FIG. 10B). In this embodiment, the source or drain electrode layer 327a serves as a source electrode layer, and the source or drain electrode layer 327b serves as a drain electrode layer. On the other hand, the source or drain electrode layer 398a serves as a drain electrode layer, and the source or drain electrode layer 398b serves as a source electrode layer. Therefore, the p-channel thin film transistor 330, the n-channel thin film transistor 331, the n-channel thin film transistor 332 having a low-concentration p-type impurity region on the drain region side, and the n-channel thin film transistor 332 having a low-concentration p-type impurity region on the source region side. A channel thin film transistor 378 is manufactured, and a semiconductor device using the channel thin film transistor 378 is manufactured. In this embodiment mode, a processor in which a CMOS circuit and a thin film transistor whose characteristics are controlled is provided over the same substrate is manufactured.

  When the present invention is used, the semiconductor layer has an impurity region having an impurity element imparting a different conductivity type, so that the fine characteristics of the thin film transistor can be controlled. Accordingly, a thin film transistor having a required function can be formed through a simple process, and a semiconductor device with high reliability and electrical characteristics can be manufactured at low cost. That is, a functional circuit that emphasizes high-speed operation such as a processor, a DRAM, an image processing circuit, and an audio processing circuit, and a drive circuit that emphasizes high breakdown voltage characteristics such as a buffer circuit, a shift register circuit, a level shifter circuit, and a sampling circuit It can be formed on the same substrate. For this reason, semiconductor devices having elements having various functions and structures, such as a system LSI, can be manufactured on the same substrate. Since the thin film transistor in this embodiment is an n-channel thin film transistor having a low-concentration p-type impurity region, a semiconductor device capable of high-speed operation and reduced power consumption can be formed.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 to 4.

(Embodiment 6)
Embodiments of the present invention will be described with reference to FIGS. 8 to 10 and FIG. This embodiment mode shows an example in which an n-channel thin film transistor having two types of low-concentration p-type impurity regions is formed in the semiconductor device manufactured in Embodiment Mode 3. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    In Embodiment 5, an n-channel thin film transistor having two types of low-concentration p-type impurity regions having different characteristics was manufactured by making a source region and a drain region of a thin film transistor having the same impurity region different from each other. In this embodiment mode, an n-channel thin film transistor including two types of low-concentration p-type impurity regions having different characteristics is manufactured by controlling the doping angle of the impurity element and changing the structure of the impurity regions.

    In Embodiment 5, as shown in FIG. 8B, the first p-type impurity region 308a, the first p-type impurity region 308b, the first p-type impurity region 385a, and the first p-type impurity region When forming 385b, an impurity element imparting p-type is doped at θ1 set at 30 to 90 degrees. In this embodiment, doping of the impurity element imparting p-type into the semiconductor layer 304 and the semiconductor layer 370 is performed in different steps at different angles.

    First, the semiconductor layer 302, the mask 361a that covers the semiconductor layer 303, and the mask 361b that covers the semiconductor layer 370 are formed, and the impurity element 951 that imparts p-type with respect to the surface of the semiconductor layer 304 at an angle θ1 is formed on the semiconductor layer 304. Added. Using the first gate electrode layer 307 as a mask, an impurity element 951 imparting p-type conductivity is added to the semiconductor layer 304 obliquely at an angle θ1 of 30 ° to 90 ° with respect to the surface of the semiconductor layer. A type impurity region 308a and a first p-type impurity region 308b are formed (see FIG. 30A). Since the impurity element 951 imparting p-type conductivity is doped obliquely, the first p-type impurity region 308 b is also formed in the semiconductor layer 304 covered with the first gate electrode layer 307. On the other hand, since the first gate electrode layer 307 is used as a mask to shield the impurity element 951 imparting p-type conductivity, the first gate electrode layer 307 is formed in the first p-type impurity region 308a. The semiconductor layer 304 is not formed.

    Next, the mask 361b covering the semiconductor layer 370 is removed, and a mask 366 covering the semiconductor layer 302, the semiconductor layer 303, and the semiconductor layer 304 is formed. An impurity element 356 imparting p-type conductivity is added. Using the first gate electrode layer 371 as a mask, an impurity element 356 imparting p-type conductivity is added to the semiconductor layer 370 obliquely at an angle θ3 of 90 ° to 150 ° with respect to the surface of the semiconductor layer. A type impurity region 985a and a first p-type impurity region 985b are formed (see FIG. 30B). Since the impurity element 356 imparting p-type conductivity is doped obliquely, the first p-type impurity region 985a is also formed in the semiconductor layer 370 covered with the first gate electrode layer 371. On the other hand, since the first gate electrode layer 371 serves as a mask to shield the impurity element 356 imparting p-type conductivity, the first p-type impurity region 985b is formed under the first gate electrode layer 371. The semiconductor layer 370 is not formed.

Here, the first p-type impurity region 308a, the first p-type impurity region 308b, the first p-type impurity region 985a, and the first p-type impurity region 985b have 5 × impurity elements imparting p-type conductivity. It is added so as to be contained at a concentration of about 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ . Further, the impurity element imparting p-type conductivity may be added so as to be contained at a concentration of about 5 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity.

    As described above, the formation region of the first p-type impurity region in the semiconductor layer 304 and the semiconductor layer 370 can be made different by changing the angle θ at which the impurity element imparting p-type is doped.

    A semiconductor device manufactured in this embodiment is illustrated in FIG. A p-channel thin film transistor 330, an n-channel thin film transistor 331, an n-channel thin film transistor 332 having a p-type impurity region, and an n-channel thin film transistor 978 having a p-type impurity region are manufactured in this embodiment mode and a semiconductor device using the p-channel thin film transistor 330 Is produced.

    The thin film transistor 332 manufactured in this embodiment includes a second p-type impurity region 324 that is a low-concentration p-type impurity region between the channel formation region 323 and the third n-type impurity region 322b. Yes. On the other hand, the thin film transistor 978 manufactured in this embodiment includes a second p-type impurity region 977 which is a low-concentration p-type impurity region between the channel formation region 376 and the third n-type impurity region 375a. is doing.

    The channel formation region of the semiconductor layer is arranged in parallel with the laser beam scanning direction, and the gate electrode layer is used as a mask, and an impurity element is added obliquely at different angles from one direction to each step. An impurity region of one conductivity type different from the conductivity of the thin film transistor can be formed only between either the source region or the drain region. By using the present invention, a thin film transistor having the different impurity region of one conductivity type in the source region and a thin film transistor having the impurity region of different conductivity type in the drain region can be formed over the same substrate. Accordingly, characteristics of finer thin film transistors can be controlled and a variety of thin film transistors can be manufactured. Therefore, a highly accurate semiconductor device that requires a plurality of circuits having different functions can be manufactured with high reliability.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 to 5.

(Embodiment 7)
An embodiment of the present invention will be described with reference to FIGS. This embodiment mode shows an example in which a semiconductor nonvolatile memory element (hereinafter referred to as a memory transistor) is formed in the semiconductor device manufactured in Embodiment Mode 4. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    As in Embodiment 4, a base film 401 a and a base film 401 b are stacked over the substrate 400 as base films to form a semiconductor layer 402, a semiconductor layer 403, a semiconductor layer 404, and a semiconductor layer 405. The semiconductor layer 402, the semiconductor layer 403, the semiconductor layer 404, and the semiconductor layer 405 are formed by crystallizing an amorphous semiconductor film by laser irradiation and patterning the formed crystalline semiconductor film. In this embodiment mode, silicon is used as a material for the semiconductor layer, and the amorphous silicon film is irradiated with laser light to form a crystalline silicon film having continuously grown crystal grains. Note that the semiconductor layer 402, the semiconductor layer 403, the semiconductor layer 404, and the semiconductor layer 405 are formed so that a channel formation region of a thin film transistor to be formed later is parallel to the scanning direction of the laser light. In this embodiment mode, laser light having a pulsed laser light oscillation frequency of 80 MHz is used as the laser light. By forming single crystal grains that extend long along the scanning direction of the laser light, it is possible to form a semiconductor film in which at least crystal grain boundaries that hinder the movement of carriers in the thin film transistor do not exist.

  An insulating film 480, an insulating film 481, an insulating film 482, and an insulating film 483 are formed over the semiconductor layer 402, the semiconductor layer 403, the semiconductor layer 404, the semiconductor layer 405, and the substrate 400, and the insulating film 406 is formed over them. To do. The insulating film 480, the insulating film 481, the insulating film 482, the insulating film 483, and the insulating film 406 formed over them have a thickness of 1 to 100 nm, preferably 1 to 10 nm, and more preferably 2 to 5 nm. It is desirable. The insulating film 480, the insulating film 481, the insulating film 482, the insulating film 483, and the insulating film 406 formed thereon function later as a tunnel oxide film in the memory transistor and as a part of the gate insulating layer in the thin film transistor. Therefore, the thinner the insulating film 480, the insulating film 481, the insulating film 482, the insulating film 483 and the insulating film 406 formed thereover, the thinner the tunnel current, the higher the speed of operation, which is preferable. Further, as the insulating film 480, the insulating film 481, the insulating film 482, the insulating film 483, and the insulating film 406 formed thereon are thinner, charges can be accumulated in the floating gate electrode at a lower voltage. is there. As a result, power consumption of a semiconductor device formed later can be reduced.

  As a method for forming the insulating film 480, the insulating film 481, the insulating film 482, and the insulating film 483, the surface of the semiconductor region is oxidized using a GRTA method, an LRTA method, or the like, and a thermal oxide film is formed. An insulating film can be formed. In addition to this method, a CVD method, a coating method, or the like may be used. The insulating film 406 can be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. Alternatively, a stacked structure of a silicon oxide film, a silicon nitride film, or a stacked structure of a silicon oxide film, a silicon nitride film, or a silicon oxide film may be employed from the substrate 400 side.

  In this embodiment, a silicon oxide film is formed as the insulating film 480, the insulating film 481, the insulating film 482, and the insulating film 483, and a silicon nitride film is formed as the insulating film 406. After removing the natural oxide film formed on the surfaces of the semiconductor layer 402, the semiconductor layer 403, the semiconductor layer 404, and the semiconductor layer 405, the semiconductor layer 402, the semiconductor are exposed to ozone water containing hydroxy radicals for several tens of seconds to several minutes. Silicon oxide films are formed on the surfaces of the layer 403, the semiconductor layer 404, and the semiconductor layer 405. After that, the silicon oxide film is further densified by a GRTA method, and an insulating film 480, an insulating film 481, an insulating film 482, and an insulating film 483 having a thickness of 1 to 2 nm are formed. By this method, processing can be performed in a short time and at a high temperature, so that a dense and thin insulating film can be formed without stretching the substrate. Next, a silicon nitride oxide film with a thickness of 1 to 5 nm is formed as the insulating film 406 over the silicon oxide film.

  Conductive particles or semiconductor particles (hereinafter referred to as dispersed particles) 407 dispersed over the insulating film 406 are formed (see FIG. 11A). As a method for manufacturing the dispersed particles, a known method such as a sputtering method, a plasma CVD method, an LPCVD method, a vapor deposition method, or a droplet discharge method can be used. When dispersed particles are formed by a plasma CVD method, an LPCVD method, a vapor deposition method, a droplet discharge method, or the like, the impact on the insulating film 406 at the time of film formation can be reduced. It is possible to suppress. As a result, a highly reliable semiconductor device can be manufactured. Further, after forming a conductive film or a semiconductor film by the above method, the dispersed particles can be formed by etching into a desired shape. The size of the dispersed particles is 0.1 to 10 nm, preferably 2 to 5 nm. Moreover, as a material of the conductive particles, gold, silver, copper, palladium, platinum, cobalt, tungsten, nickel, or the like can be used. As a material of the semiconductor particles, silicon (Si), germanium (Ge), a silicon germanium alloy, or the like can be used. In this embodiment, here, silicon microcrystals are formed as the dispersed particles 407 by a plasma CVD method (see FIG. 11A).

  An insulating film is formed over the dispersed particles 407 and the insulating film 406. As the insulating film, a silicon nitride film or a silicon nitride oxide film with a thickness of 10 to 20 nm is formed by a plasma CVD method.

  Next, a mask is formed over the dispersed particles 407 over the semiconductor layer 402 to be a memory transistor later.

A part of the dispersed particles 407 is etched using a mask to form the insulating layer 408 having the floating gate electrode 410. As a method for removing the insulating film and the dispersed particles 407, a known etching method such as a dry etching method or a wet etching method can be used. In this embodiment mode, the insulating film is removed by dry etching so that the dispersed particles 407 are exposed. Note that if dry etching is used when the insulating film 406 over which the dispersed particles 407 are formed is thin, defects may occur in the insulating film 406 due to plasma bombardment. For this reason, it is preferable to remove by wet etching. Here, silicon microcrystals that are dispersed particles are removed by a wet etching method using an NMD ₃ solution (aqueous solution containing 0.2 to 0.5% tetramethylammonium hydroxide) or the like.

  The floating gate electrode is formed of dispersed particles. For this reason, when the insulating film 406 functioning as a tunnel oxide film has a defect, it is possible to prevent all charges accumulated in the floating gate electrode from flowing into the semiconductor region from the defect. As a result, a highly reliable semiconductor memory transistor can be formed.

  Next, after the mask is removed, an insulating film 409 is formed over the insulating layer 408 and the insulating film 406 including the floating gate electrode 410 (see FIG. 11B). The insulating film 409 has a thickness of 1 to 100 nm, preferably 10 to 70 nm, and more preferably 10 to 30 nm. The insulating film 409 needs to maintain insulation between the floating gate electrode 410 and a gate electrode layer formed later in the memory transistor. For this reason, it is preferable to set the film thickness so that the leakage current does not increase between them. The insulating film 409 can be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film, similarly to the insulating film 406. Alternatively, a stacked structure such as a stacked layer of a silicon oxide film or a silicon nitride film, or a stacked layer of a silicon oxide film, a silicon nitride film, or a silicon oxide film may be employed from the substrate 100 side. Note that it is preferable to form a silicon oxide film in contact with the semiconductor layer because an interface state between the gate insulating film and the semiconductor region is lowered. Here, the insulating film 409 is formed to have a stacked structure of a silicon oxide film with a thickness of 10 nm and a silicon nitride film with a thickness of 20 nm.

  Thereafter, after forming the insulating film 409, the dispersed particles and a mask pattern covering them may be formed to form the second floating gate electrode. Furthermore, the same process may be repeated to form a plurality of stacked floating gate electrodes.

    A conductive film is formed using W on the insulating film 409. In this embodiment mode, W is used for the gate electrode layer. The conductive film is etched so as to be a thin line as shown in FIG. 3, so that a gate electrode layer 411, a gate electrode layer 412, a gate electrode layer 413, and a gate electrode layer 414 are formed (see FIG. 11C). . A mask 461 made of a resist is formed so as to cover the semiconductor layer 402, the semiconductor layer 403, and the semiconductor layer 404.

Using the gate electrode layer 414 as a mask, an impurity element 451 imparting p-type conductivity is added to the semiconductor layer 405 obliquely at an angle θ1 of 30 to 90 degrees and 90 to 150 degrees toward the semiconductor layer surface. One p-type impurity region 415a and a first p-type impurity region 415b are formed (see FIG. 11D). Since the impurity element 451 imparting p-type conductivity is doped obliquely, the first p-type impurity region 415b is also formed in the semiconductor layer 405 covered with the gate electrode layer 414. On the other hand, since the gate electrode layer 414 serves as a mask to shield the impurity element 451 imparting p-type conductivity, the first p-type impurity region 415a is formed in the semiconductor layer 405 under which the gate electrode layer 414 is formed. Not formed. Here, the first p-type impurity region 415a and the first p-type impurity region 415b include the impurity element imparting p-type at a concentration of about 5 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ^3. Added. Further, the impurity element imparting p-type conductivity may be added so as to be contained at a concentration of about 5 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity.

Next, the mask 461 is removed, and a mask 462 made of a resist that covers the semiconductor layer 403 is formed. The mask 462 may be newly formed or may be formed by processing the mask 461. Using the gate electrode layer 411, the gate electrode layer 413, and the gate electrode layer 414 as a mask, an impurity element imparting n-type is added to the semiconductor layer 402, the semiconductor layer 404, and the semiconductor layer 405 at an angle θ2 substantially perpendicular to the surface of the semiconductor layer. The first n-type impurity region 416a, the first n-type impurity region 416b, the first n-type impurity region 417a, the first n-type impurity region 417b, the first n-type impurity region 418a, the first An n-type impurity region 418b is formed (see FIG. 12A). The angle θ2 is set to be different from the angle θ1 by 5 degrees or more. An impurity element imparting p-type is added to the first p-type impurity region 415a and the first p-type impurity region 415b, and thus an impurity imparting n-type is inverted so as to be inverted to the n-type impurity region. Add elements. First n-type impurity region 416a, first n-type impurity region 416b, first n-type impurity region 417a, first n-type impurity region 417b, first n-type impurity region 418a, first n-type impurity region The impurity region 418b is typically formed to include an impurity element imparting n-type at a concentration of 1 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ . In this embodiment mode, phosphorus (P) is used as the impurity element imparting n-type conductivity. Since the impurity element 452 imparting n-type conductivity is added substantially perpendicularly, the impurity element 452 is shielded by the gate electrode layer 411, the gate electrode layer 413, and the gate electrode layer 414, and thus the gate electrode layer 411, the gate electrode layer 413, and the gate electrode layer 414. It is not added to the regions of the semiconductor layer 402, the semiconductor layer 404, and the semiconductor layer 405 that are covered with. Therefore, a part of the first p-type impurity region formed in the semiconductor layer under the gate electrode layer 414 remains and becomes the second p-type impurity region 435. The second p-type impurity region 435 is formed as a Lov region.

The mask 462 is removed by etching or the like, so that a mask 463a and a mask 463b that cover the semiconductor layer 402, the semiconductor layer 404, and the semiconductor layer 405 are formed. Using the mask 463a, the mask 463b, and the gate electrode layer 412 as a mask, an impurity element 453 imparting p-type conductivity is added to the semiconductor layer 403 almost perpendicular to the surface of the semiconductor layer 403, so that the third p-type impurity region 420a, 3 p-type impurity regions 420b are formed (see FIG. 12B). Here, the third p-type impurity region 420a and the third p-type impurity region 420b include the impurity element imparting p-type at a concentration of about 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ^3. Added. In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity.

    The masks 463a and 463b are removed by etching or the like, an insulating layer is formed over the insulating film 409, the gate electrode layer 411, the gate electrode layer 412, the gate electrode layer 413, and the gate electrode layer 414, and anisotropic etching is performed. A sidewall 421, a sidewall 422, a sidewall 423, and a sidewall 424 are formed on side surfaces of the gate electrode layer 411, the gate electrode layer 412, the gate electrode layer 413, and the gate electrode layer 414 (see FIG. 12C). In this embodiment mode, silicon oxide is used as an insulating layer for forming the sidewall. When the sidewall 421, the sidewall 422, the sidewall 423, and the sidewall 424 are formed, an insulating layer is formed over the gate electrode layer 411, the gate electrode layer 412, the gate electrode layer 413, and the gate electrode layer 414. A protective film may be formed on the gate electrode layer.

A mask 464 made of a resist that covers the semiconductor layer 403 is formed. With the sidewalls 421, 423, 424, the gate electrode layer 411, the gate electrode layer 413, and the gate electrode layer 414 as masks, the semiconductor layer 402, the semiconductor layer 404, and the semiconductor layer 405 are substantially perpendicular to the surface of the semiconductor layer. An impurity element 454 imparting n-type conductivity is added, and the second n-type impurity region 425a, the second n-type impurity region 425b, the second n-type impurity region 428a, the second n-type impurity region 428b, and the second N-type impurity region 431a and second n-type impurity region 431b are formed (see FIG. 13A). Since the impurity element 454 imparting n-type conductivity is not added to the semiconductor layer covered with the sidewalls, the third n-type impurity region 426a, the third n-type impurity region 426b, which are low-concentration impurity regions, 3 n-type impurity regions 429a, third n-type impurity regions 429b, third n-type impurity regions 432a, and third n-type impurity regions 432b. Second n-type impurity region 425a, second n-type impurity region 425b, second n-type impurity region 428a, second n-type impurity region 428b, second n-type impurity region 431a, second n-type Since the impurity region 431b is a high-concentration impurity region, it functions as a source region or a drain region. Second n-type impurity region 425a, second n-type impurity region 425b, second n-type impurity region 428a, second n-type impurity region 428b, second n-type impurity region 431a, second n-type The impurity region 431b is added so that an impurity element imparting n-type conductivity is contained at a concentration of about 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ³ . In this embodiment mode, phosphorus (P) is used as the impurity element imparting n-type conductivity.

  On the other hand, a third n-type impurity region 426a, a third n-type impurity region 426b, a third n-type impurity region 429a, a third n-type impurity region 429b, and a third n-type impurity region which are low-concentration impurity regions. 432a and the third n-type impurity region 432b are formed in a Loff region that is not covered with the gate electrode layer 411, the gate electrode layer 413, and the gate electrode layer 414; It is effective in preventing deterioration due to and reducing off-current. As a result, a highly reliable semiconductor device with low power consumption can be manufactured. Note that a channel formation region 427, a channel formation region 430, and a channel formation region 434 are formed in the semiconductor layer 402, the semiconductor layer 404, and the semiconductor layer 405.

Masks 465 a and 465 b made of resist are formed to cover the semiconductor layer 402, the semiconductor layer 404, and the semiconductor layer 405. Using the mask 465a, the mask 465b, the sidewall 422, and the gate electrode layer 412 as a mask, an impurity element 455 imparting p-type conductivity is added to the semiconductor layer 403 almost perpendicularly to the surface of the semiconductor layer 403, so that a fourth p-type impurity is added. A region 436a, a fourth p-type impurity region 436b, a fifth p-type impurity region 437a, and a fifth p-type impurity region 437b are formed (see FIG. 13B). Here, the fourth p-type impurity region 436a and the fourth p-type impurity region 436b include the impurity element imparting p-type at a concentration of about 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ^3. Added. Further, the fifth p-type impurity region 437a and the fifth p-type impurity region 437b are added so that the impurity element imparting p-type is contained at a concentration of about 5 × 10 ^{18 to} 5 × 10 ¹⁹ / cm ^3. To do. In this embodiment mode, boron (B) is used as the impurity element imparting p-type conductivity. Note that a channel formation region 438 is formed in the semiconductor layer 403.

  The fourth p-type impurity region 436a and the fourth p-type impurity region 436b are high-concentration impurity regions and function as a source region or a drain region. The fifth p-type impurity region 437a and the fifth p-type impurity region 437b are low-concentration p-type impurity regions and are formed as Loff regions that are not covered with the gate electrode layer. Since the fifth p-type impurity region 437a and the fifth p-type impurity region 437b are not covered with the gate electrode layer, the electric field in the vicinity of the drain is relaxed to prevent deterioration due to hot carrier injection, and the off-current is reduced. effective. As a result, a highly reliable semiconductor device with low power consumption can be manufactured.

    An insulating film 443 for hydrogenation is formed as appropriate by performing heat treatment, laser irradiation, or the like for activating the impurity element. Hydrogenation is performed by heat treatment, so that the insulating layer 446 is formed. The heat treatment for activating the impurity element and the heat treatment for hydrogenation may be performed in the same process, and the process can be simplified. In this embodiment, a silicon nitride oxide film and a silicon oxynitride film are successively formed as the insulating layer 446 to have a stacked structure.

    Openings (contact holes) reaching the source and drain regions are formed in the insulating layer 446, the insulating film 443, the insulating film 409, the insulating film 480, the insulating film 481, the insulating film 482, and the insulating film 483. A source or drain electrode layer 440a in contact with a source region or a drain region, a source or drain electrode layer 440b, a source or drain electrode layer 441a, a source or drain electrode layer 441b, a source electrode layer or A drain electrode layer 442a, a source or drain electrode layer 442b, a source or drain electrode layer 439a, and a source or drain electrode layer 439b are formed (see FIG. 14A). In this embodiment mode, a stack of Al, Ti, and Al is used for the source electrode layer or the drain electrode layer.

    In addition, as illustrated in FIG. 14B, an insulating layer 444 having an opening reaching the source or drain electrode layer is formed over the source or drain electrode layer, and a wiring layer 445 is formed in the opening. It is good also as a structure to do. In this embodiment mode, an insulating layer containing a siloxane polymer is used as the insulating layer 444, and the wiring layer 445 is a stacked layer of Al and Ti.

    A semiconductor device including the memory transistor 470, the p-channel thin film transistor 471, the n-channel thin film transistor 472, and the n-channel thin film transistor 473 including the low-concentration p-type impurity region can be formed over the same substrate. Since the memory transistor and the thin film transistor in the semiconductor device of this embodiment are formed using a semiconductor region in which there is almost no crystal grain boundary in the channel direction, high-speed operation is possible. In addition, since the n-channel thin film transistor including the low-concentration p-type impurity region is included, a semiconductor device such as an ID chip that can operate at high speed and has low power consumption can be formed.

    In addition, the p-channel thin film transistor 471, the n-channel thin film transistor 472, and the n-channel thin film transistor having a low-concentration p-type impurity region which are manufactured in this embodiment are each formed as an insulating layer formed on the surface of the semiconductor layer as a gate insulating layer. A stack of the film 481, the insulating film 482, the insulating film 483, and the insulating film 406 and the insulating film 409 formed thereon is used. Therefore, a thin film transistor having high withstand voltage and high withstand voltage characteristics can be obtained. Note that when the insulating film 409 is removed and the gate insulating layer is formed by stacking the insulating film 481, the insulating film 482, the insulating film 483, and the insulating film 406 formed thereon, a thin film transistor capable of high-speed operation is obtained. be able to. In this manner, a thin film transistor having characteristics that can cope with the required function can be manufactured, whereby a semiconductor device can be manufactured.

  When the present invention is used, the semiconductor layer has an impurity region having an impurity element imparting a different conductivity type, so that the fine characteristics of the thin film transistor can be controlled. Accordingly, a thin film transistor having a required function can be formed through a simple process, and a semiconductor device with high reliability and electrical characteristics can be manufactured at low cost. That is, a functional circuit that emphasizes high-speed operation such as a processor, a DRAM, an image processing circuit, and an audio processing circuit, and a drive circuit that emphasizes high breakdown voltage characteristics such as a buffer circuit, a shift register circuit, a level shifter circuit, and a sampling circuit. It can be formed on the same substrate. For this reason, semiconductor devices having elements having various functions and structures, such as a system LSI, can be manufactured on the same substrate.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 to 6.

(Embodiment 8)
One of semiconductor devices that can be formed using the manufacturing method of the present invention is an ID chip. An ID chip is a semiconductor device capable of transmitting and receiving data such as identification information wirelessly, and its practical use is being promoted in various fields. The ID chip is also called a wireless tag, an RFID (Radio frequency identification) tag, or an IC tag. In addition, an ID chip using a glass substrate can be called an IDG chip (Identification Glass Chip), and an ID chip using a flexible substrate can be called an IDF chip (Identification Flexible Chip). .

  FIG. 16 shows a typical block diagram of an ID chip typified by a contactless RFID (Radio Frequency Identification) tag, a wireless tag, etc., which is a typical example of the semiconductor device of the present invention. FIG. 16 shows a configuration having a simple function of reading fixed data such as authentication data. In FIG. 16, an ID chip 1301 includes an antenna 1302, a high frequency circuit 1303, a power supply circuit 1304, a reset circuit 1305, a clock generation circuit 1306, a data demodulation circuit 1307, a data modulation circuit 1308, a control circuit 1309, and a nonvolatile memory (NVM). ) 1310 and ROM 1311.

  In this embodiment, the memory transistor manufactured in Embodiment 5 is used as the nonvolatile memory 1310, and a thin film transistor whose electric characteristics are controlled using the present invention corresponding to functions required for each circuit is used as appropriate. That is, if a transistor that operates at high speed is required as a transistor constituting the high-frequency circuit 1303, the reset circuit 1305, the clock generation circuit 1306, the data demodulation circuit 1307, the data modulation circuit 1308, the control circuit 1309, and the ROM 1311, the present invention is used. Thus, a transistor capable of high-speed operation can be manufactured in the same process. In the case where a transistor having high withstand voltage characteristics is required as a transistor included in the power supply circuit 1304, a transistor having high withstand voltage characteristics can be manufactured at the same time as the memory transistor by using the present invention. As described above, an RFID tag can be efficiently manufactured on the same substrate. Further, the cost and size of the ID chip 1301 can be reduced.

  Further, all the circuits shown in FIG. 16 are formed on a glass substrate, a flexible substrate, or a semiconductor substrate. The antenna 1302 may be formed on the glass substrate, a flexible substrate, or a semiconductor substrate, or may be outside the substrate and connected to a semiconductor integrated circuit inside the substrate.

  The high frequency circuit 1303 is a circuit that receives an analog signal from the antenna 1302 and outputs the analog signal received from the data modulation circuit 1308 from the antenna 1302. The power supply circuit 1304 generates a constant power supply from the received signal, the reset circuit 1305 generates a reset signal, the clock generation circuit 1306 generates a clock signal, and the data demodulation circuit 1307 extracts data from the received signal. The circuit / data modulation circuit 1308 generates an analog signal to be output to the antenna based on the digital signal received from the control circuit, or changes the antenna characteristics, and the analog circuit includes the above circuit.

  On the other hand, the control circuit 1309 receives data extracted from the received signal and performs data reading. Specifically, an address signal of the NVM 1310 or the ROM 1311 is generated, data is read, and the read data is sent to the data modulation circuit. The digital circuit is composed of the above circuits.

  As described above, a highly reliable and high-performance ID chip can be manufactured using the present invention. This embodiment mode can be combined with any of Embodiment Modes 1 to 7.

(Embodiment 9)
FIG. 17A is a perspective view showing one mode of an ID chip which is one of the semiconductor devices of the present invention. As the integrated circuit, a processor which is an aggregate having various signal processing functions and a system processor having the processor as a system can be used. 1101 is an integrated circuit, 1102 is an antenna, and the antenna 1102 is connected to the integrated circuit 1101. Reference numeral 1103 denotes a support that also functions as a cover material, and 1104 corresponds to a cover material. The integrated circuit 1101 and the antenna 1102 are formed over the support 1103, and the cover material 1104 overlaps the support 1103 so as to cover the integrated circuit 1101 and the antenna 1102. Note that the cover material 1104 is not necessarily used, but the mechanical strength of the ID chip can be increased by covering the integrated circuit 1101 and the antenna 1102 with the cover material 1104.

  FIG. 17B is a perspective view showing one mode of an IC card which is one of the semiconductor devices of the present invention. Reference numeral 1105 denotes an integrated circuit, 1106 denotes an antenna, and the antenna 1106 is connected to the integrated circuit 1105. Reference numeral 1108 denotes a substrate that functions as an inlet sheet, and reference numerals 1107 and 1109 denote cover materials. The integrated circuit 1105 and the antenna 1106 are formed over a substrate 1108, and the substrate 1108 is sandwiched between two cover materials 1107 and 1109. Note that the IC card of the present invention may have a display device connected to the integrated circuit 1105.

    18A and 18B are cross-sectional views taken along the line EF of the ID chip shown in FIG. However, FIG. 18 shows an example in which the integrated circuit 1101 is formed directly on the support body, which is sealed with a thinner cover film 1150 instead of the cover material 1104. Of course, the cover material 1104 may be formed on the cover film 1150. The ID chip is sealed with a support 1103 that also functions as a cover material and a cover film 1150, and includes an integrated circuit 1101 and an antenna 1102 connected thereto.

  The integrated circuit 1101 can be formed using the integrated circuit described in any of Embodiments 1 to 8. Further, the semiconductor element used for the integrated circuit 1101 is not limited to this. For example, in addition to a thin film transistor, a memory element, a diode, a photoelectric conversion element, a resistance element, a coil, a capacitor element, an inductor, or the like can be used.

  As shown in FIG. 18A, an interlayer insulating film 1110 is formed over the thin film transistor of the integrated circuit 1101, and an antenna 1102 is formed over the interlayer insulating film 1110 and sealed with a cover film 1150 functioning as a protective film. It has been stopped.

  On the other hand, as shown in FIG. 18B, a barrier film 1121 made of a silicon nitride film or the like may be formed over the interlayer insulating film 1110, and the antenna 1102 may be formed thereover.

  By providing the barrier film, an ID chip with improved reliability can be provided without the integrated circuit 1101 being contaminated. In FIG. 18, a base film made of silicon nitride or the like is formed between the integrated circuit 1101 and the support 1103, and the integrated circuit is covered with a film having a barrier function such as a silicon nitride film. It can prevent contamination such as moisture and improve reliability.

  The antenna 1102 is preferably gold, silver, copper, aluminum, or a metal plated with them.

  In this embodiment mode, an example in which a stacked body including an integrated circuit and an antenna formed over an interlayer insulating film of the integrated circuit is bonded with different cover materials is described; however, the present invention is not limited thereto, and an antenna is formed. The cover material and the integrated circuit may be fixed with an adhesive. At this time, the integrated circuit and the antenna are connected by performing UV treatment or ultrasonic treatment using an anisotropic conductive adhesive or an anisotropic conductive film, but the present invention is not limited to this method, and various Can be used. Further, the antenna is not necessarily equal to the size of the ID chip, and may be larger or smaller and may be set as appropriate. For signal transmission / reception, radio waves such as electromagnetic waves and light can be used.

In this embodiment mode, an integrated circuit is formed directly on a support and a dense film such as silicon nitride is used as the cover film 1150. However, an integrated circuit is formed by a peeling process and bonded to the support and the cover material. But you can. As the support and the cover material, materials having flexibility such as plastic, organic resin, paper, fiber, carbon graphite, and the like can be used. By using a biodegradable resin for the cover material, it is decomposed into bacteria and reduced to the soil. Furthermore, since the integrated circuit of this embodiment is formed using silicon, aluminum, oxygen, nitrogen, or the like, a pollution-free ID chip can be formed. Further, by using an incineration-free pollution material such as paper, fiber, carbon graphite, etc., the used ID chip can be incinerated or cut. In addition, ID chips using these materials are non-polluting because they do not generate toxic gas even when incinerated.

When the integrated circuit formed by the peeling process is bonded to the support and the cover material, the thickness of the integrated circuit sandwiched between the support and the cover material is 5 μm or less, preferably 0.1 μm to 3 μm. It is good to form like this. Further, when the thickness when the support and the cover material are overlapped is defined as d, the thickness of each of the support and the cover material is preferably (d / 2) ± 30 μm, more preferably (d / 2). ± 10 μm. The thickness of the support 1103 and the second cover material is desirably 10 μm to 200 μm. Furthermore, the area of the integrated circuit 1101 is 5 mm square (25 mm ² ) or less, and desirably has an area of 0.3 mm square to 4 mm square (0.09 mm ^{2 to} 16 mm ² ). When the support 1103 and the cover material are formed of an organic resin material, they have a strong characteristic against bending. In addition, an integrated circuit formed by a separation process has stronger resistance to bending than a single crystal semiconductor. Since the integrated circuit, the support, and the cover material can be brought into close contact with each other so that there is no gap, the completed ID chip itself has a strong characteristic against bending. Such an integrated circuit surrounded by a support and a cover material may be disposed on the surface or inside of another solid object, or may be embedded in paper.

This embodiment mode can be freely combined with any of Embodiment Modes 1 to 8.
(Embodiment 10)
In this embodiment mode, a block diagram of one chip of a processor (such as a CPU) which is a typical example of a semiconductor device of the present invention will be described with reference to FIG.

  First, when the operation code is input to the data bus interface 1001, the analysis circuit 1003 (also referred to as instruction decoder) decodes the code, and the signal is input to the control signal generation circuit 1004 (CPU Timing Control). When a signal is input, a control signal is output from the control signal generation circuit 1004 to the arithmetic circuit 1009 (hereinafter referred to as ALU) and the storage circuit 1010 (hereinafter referred to as register).

  The control signal generation circuit 1004 includes an ALU controller 1005 (hereinafter referred to as ACON) that controls the ALU 1009, a circuit 1006 (hereinafter referred to as RCON) that controls the register 1010, and a timing controller 1007 (hereinafter referred to as RCON) that controls timing. And an interrupt controller 1008 (hereinafter referred to as ICON) for controlling interrupts.

  On the other hand, when an operand is input to the data bus interface 1001, it is output to the ALU 1009 and the register 1010. Then, processing based on the control signal input from the control signal generation circuit 1004 (for example, a memory read cycle, a memory write cycle, an I / O read cycle, an I / O write cycle, etc.) is performed.

  Note that the register 1010 includes a general-purpose register, a stack pointer (SP), a program counter (PC), and the like.

  An address controller 1011 (hereinafter referred to as ADRC) outputs a 16-bit address.

  Note that the structure of the processor described in this embodiment mode is an example of a processor formed using the manufacturing method of the present invention, and does not limit the structure of the present invention. Therefore, a known processor configuration other than the configuration described in this embodiment can also be used.

This embodiment mode can be used in combination with each of Embodiment Modes 1 to 9.
(Embodiment 11)

  The case where the present invention is applied to a system LSI which is an example of a semiconductor device will be described with reference to FIG.

  The system LSI is an LSI that is incorporated in a device that assumes a specific application and constitutes a system that controls the device and performs data processing. Applications are diverse and include, for example, mobile phones, PDAs, DSCs, television devices, printers, FAX machines, game machines, car navigation systems, DVD players, and the like.

    FIG. 20 shows an example of a system LSI. The system LSI typically includes a processor (CPU) core 1601, a non-volatile memory (NVM) 1604, a clock controller 1603, a main memory 1602, a memory controller 1605, an interrupt controller 1606, an I / O port 1607, and the like. The Of course, the system LSI shown in FIG. 20 is a simplified example, and various circuit designs are performed on an actual system LSI depending on the application. As the I / O port 1607, a device such as an antenna that can use an electromagnetic wave (such as a radio wave) having any frequency, light, or the like as a signal can be used.

  The memory transistor manufactured in Embodiment 7 can be used for the NVM 1604.

  In addition, as a transistor constituting the processor core 1601, the clock controller 1603, the main memory 1602, the memory controller 1605, the interrupt controller 1606, and the I / O port 1607, a transistor capable of high-speed operation manufactured using the present invention is used. Can do. Thus, various circuits can be manufactured on the same substrate.

This embodiment mode can be used in combination with each of Embodiment Modes 1 to 10.
(Embodiment 12)

  The semiconductor device of the present invention has a wide range of uses. For example, an ID chip which is one form of the semiconductor device of the present invention is a banknote, a coin, securities, certificates, bearer bonds, packaging containers, books It can be used for recording media, personal items, vehicles, foods, clothing, health supplies, daily necessities, medicines, electronic devices, and the like. A processor chip can be used instead of the ID chip.

  Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refer to checks, securities, promissory notes, and the like, and can be provided with an ID chip 20 (see FIG. 21A). The certificate refers to a driver's license, a resident's card, and the like, and an ID chip 21 can be provided (see FIG. 21B). Bearer bonds refer to stamps, gift cards, and various gift certificates. Packaging containers refer to wrapping paper such as lunch boxes, plastic bottles, and the like, and can be provided with an ID chip 23 (see FIG. 21D). Books refer to books, books, and the like, and can be provided with an ID chip 24 (see FIG. 21E). The recording medium refers to DVD software, a video tape, or the like, and can be provided with an ID chip 25 (see FIG. 21F). The vehicles refer to vehicles such as bicycles, ships, and the like, and can be provided with an ID chip 26 (see FIG. 21G). Personal belongings refer to bags, glasses, and the like, and can be provided with an ID chip 27 (see FIG. 21H). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

  Forgery can be prevented by providing ID chips on bills, coins, securities, certificates, bearer bonds, and the like. In addition, by providing ID chips for personal items such as packaging containers, books, recording media, food items, daily necessities, electronic devices, etc., the efficiency of inspection systems and rental store systems can be improved. it can. By providing ID chips on vehicles, health supplies, medicines, etc., counterfeiting and theft can be prevented, and medicines can prevent mistakes in taking medicines. The ID chip is provided by being stuck on the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin.

    The processor chip can also be used as an apparatus for measuring and evaluating a biological response of a living organism (biological signals (eg, electroencephalogram, electrocardiogram, electromyogram, blood pressure)), and can also be used in the medical field. FIG. 21C shows an example of measuring an electroencephalogram by attaching a plurality of processor chips to the human body. Information obtained from a plurality of processor chips 22a, processor chips 22b, and processor chips 22c provided in the human body is analyzed, and brain waves are measured. The physical health and mental state can be known from information obtained from brain waves and processor chips. Moreover, since the processor chip is small and light, the burden on the subject can be reduced.

  An example that can be applied to an object management or distribution system will be described with reference to FIG. Here, an example in which an ID chip (processor chip) is mounted on a product will be described. As shown in FIG. 22A, an ID chip 1402 is mounted on a beer bottle 1400 using a label 1401.

  In the ID chip 1402, basic items such as a manufacturing date, a manufacturing place, and a material used are recorded. Such basic matters do not need to be rewritten, and are preferably recorded using a non-rewritable memory such as a mask ROM or the memory transistor of the present invention. In addition, the ID chip 1402 records individual items such as the delivery destination and delivery date and time of each beer bottle. For example, as shown in FIG. 22B, when the beer bottle 1400 flows by the belt conveyor 1412 and passes through the writer device 1413, each delivery destination and delivery date and time can be recorded. Such individual items may be recorded using a rewritable and erasable memory such as EEROM.

  When product information purchased from a delivery destination is transmitted to the distribution management center through the network, based on this product information, the writer device or a personal computer that controls the writer device calculates the delivery destination and delivery date and time. A system that records on a chip should be constructed.

  Since delivery is performed for each case, an ID chip can be mounted for each case or for each of a plurality of cases, and individual items can be recorded.

  By mounting an ID chip on such a product on which a plurality of delivery destinations can be recorded, it is possible to reduce the time required for manual input and to reduce input errors caused by the time. In addition, labor costs that are the most expensive in the field of logistics management can be reduced. Therefore, by mounting the ID chip, it is possible to carry out low-cost logistics management with few mistakes.

  Furthermore, application items such as foods suitable for beer and cooking methods using beer may be recorded at the delivery destination. As a result, it can serve as an advertisement for foods and the like, and the consumer's willingness to purchase can be enhanced. Such application items may be recorded using a rewritable and erasable memory such as EEROM. By mounting the ID chip in this way, information that can be provided to the consumer can be increased, so that the consumer can purchase the product with peace of mind.

    In this example, the effect of the present invention will be described based on experimental results.

  An experiment by simulation was conducted on the current-voltage (IV) characteristics of the thin film transistor manufactured using the present invention. The thin film transistors to be measured are n-channel thin film transistors (structure A), four types of n-channel thin film transistors having a low-concentration p-type impurity region (structure B, structure C, structure D, structure E), and p-channel thin film transistors (structure F). There are four types (structure G, structure H, structure I, structure J) of p-channel thin film transistors having low-concentration n-type impurity regions, for a total of ten types. FIG. 23B, FIG. 24B, FIG. 25B, and FIG. 26B each show a structure of a thin film transistor.

    Simulation results of current-voltage (IV) characteristics of an n-channel thin film transistor having a low-concentration p-type impurity region will be described with reference to FIGS. FIG. 23A assumes a model diagram shown in FIG. 23B, and an n-channel in which a standard n-channel thin film transistor and a low-concentration p-type impurity region (hereinafter referred to as p−) are provided on the drain side. The IV characteristic of a thin film transistor is shown.

FIG. 23B illustrates the structure of each thin film transistor. Structure A is a standard n-channel thin film transistor having Loff, structure B is an n-channel thin film transistor with a p ⁻ width of 100 nm, and structure C is an n-channel thin film transistor with a p ⁻ width of 300 nm. In addition, L / W of each thin film transistor is 1000/20000 nm, the width of the Loff region is 300 nm, the thickness of the gate insulating layer is 20 nm, and the impurity concentration of the source region and the drain region (denoted as n ⁺ ) is 1 × 10 ^20. The IV characteristics were simulated by setting the impurity concentration of cm ⁻³ , the Loff region to 1 × 10 ¹⁸ cm ⁻³ , ^and the impurity concentration of p ⁻ to 1 × 10 ¹⁸ cm ⁻³ .

In FIG. 23A, the solid line indicates the IV characteristics of the structure A, and the broken line indicates the IV characteristics of the structures B and C each having p ⁻ . It can be seen that by having p ⁻ , the threshold value of the thin film transistor is shifted to the positive side. It can also be seen that the shift amount of the threshold value increases as the width of p− increases (that is, in the structure C than in the structure B).

FIG. 24 shows a simulation result of IV characteristics of a thin film transistor having p ⁻ on the source side. FIG. 24A assumes a model diagram shown in FIG. 24B, and an n-channel having a standard n-channel thin film transistor and a low-concentration p-type impurity region (hereinafter referred to as p−) on the source side. The IV characteristic of a thin film transistor is shown.

FIG. 24B illustrates the structure of each thin film transistor. Structure A is the same as the standard n-channel thin film transistor shown in FIG. 23B, structure D is an n-channel thin film transistor with a p ⁻ width of 100 nm, and structure E has a p ⁻ width of 300 nm. It is an n-channel thin film transistor. In addition, L / W, Loff region width, gate insulating layer thickness, and n ⁺ concentration of each thin film transistor were the same as those used in FIG.

In FIG. 24A, the solid line indicates the IV characteristics of the structure A, and the broken line indicates the IV characteristics of the structures D and E each having p ⁻ . By having p ⁻ , the threshold value of the thin film transistor is shifted to the positive side. Further, the threshold shift amount increases as the width of p− increases (that is, in the structure E than in the structure D). Furthermore, the cut-off current (Icut) is lower than that of a standard n-channel thin film transistor. The cut-off current (Icut) is the value of the drain current Id when the gate voltage Vg is 0 V in the Id-Vg characteristic.

  As described above, by using an n-channel thin film transistor that is covered with a gate electrode and has a low concentration p-type impurity region in one of a channel formation region and a source region or a drain region, the threshold value is shifted and cut off. The current is reduced. Conventionally, thin film transistors such as processors, DRAMs, image processing circuits, and audio processing circuits that require high-speed operation have a short channel structure. However, if the channel length is short, the threshold value decreases and the cut-off current decreases. There was a problem of increasing. However, the thin film transistor of this embodiment can reduce the cut-off current with a short channel structure. By using such a thin film transistor at a key point, the power consumption of the entire semiconductor device can be reduced. For example, it is possible to reduce power consumption during standby by connecting such a thin film transistor between a thin film transistor for logic and a power source and turning it on during operation and turning it off during non-operation. It becomes. Alternatively, power consumption can be reduced by forming logic with the thin film transistors in a block that does not particularly require high-speed operation.

    Simulation results of current-voltage (IV) characteristics of a p-channel thin film transistor having a low-concentration n-type impurity region will be described with reference to FIGS. FIG. 25A assumes a model diagram shown in FIG. 25B, and a standard p-channel thin film transistor and a p-channel provided with a low-concentration n-type impurity region (hereinafter referred to as n−) on the drain side. The IV characteristic of a thin film transistor is shown.

FIG. 25B illustrates the structure of each thin film transistor. The structure F is a standard p-channel thin film transistor having Loff, the structure G is a p-channel thin film transistor with an n ⁻ width of 100 nm, and the structure H is a p-channel thin film transistor with an n ⁻ width of 300 nm. In addition, L / W of each thin film transistor is 1000/20000 nm, the width of the Loff region is 300 nm, the thickness of the gate insulating layer is 20 nm, and the impurity concentration of the source region and the drain region (denoted as p ⁺ ) is 1 × 10 ^20. The IV characteristics were simulated by setting the impurity concentration of cm ⁻³ , the Loff region to 1 × 10 ¹⁸ cm ⁻³ , ^and the impurity concentration of p ⁻ to 1 × 10 ¹⁸ cm ⁻³ .

In FIG. 25A, the solid line indicates the IV characteristics of the structure F, and the broken lines indicate the IV characteristics of the structures G and H each having n ⁻ . It can be seen that by having n ⁻ , the threshold value of the thin film transistor is shifted to the negative side. It can also be seen that the shift amount of the threshold value increases as the width of n− increases (that is, in the structure H than in the structure G).

FIG. 26 shows simulation results of IV characteristics of a p-channel thin film transistor having n ⁻ on the source side. FIG. 26A assumes a model diagram shown in FIG. 26B, and shows a standard p-channel thin film transistor and a p-channel having a low-concentration n-type impurity region (hereinafter referred to as n−) on the source side. The IV characteristic of a thin film transistor is shown.

FIG. 26B illustrates the structure of each thin film transistor. The structure F is the same as the standard p-channel thin film transistor shown in FIG. 26B, the structure I is a p-channel thin film transistor with an n ⁻ width of 100 nm, and the structure J has an n ⁻ width of 300 nm. This is a p-channel thin film transistor. In addition, L / W, Loff region width, gate insulating layer thickness, and p ⁺ concentration of each thin film transistor were the same as those used in FIG.

In FIG. 26A, the solid line indicates the IV characteristics of the structure F, and the broken line indicates the IV characteristics of the structure I and the structure J each having n ⁻ . By having n ⁻ , the threshold value of the thin film transistor is shifted to the negative side. In addition, the threshold shift amount increases as the width of n− increases (that is, in the structure J than in the structure I). Further, the cut-off current (Icut) is lower than that of a standard p-channel thin film transistor. That is, like an n-channel thin film transistor, high-speed operation is possible and power consumption can be reduced.

The figure explaining this invention. The figure explaining this invention. The figure explaining this invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 1 is a block diagram illustrating a configuration of a semiconductor device of the present invention. The perspective view which showed the semiconductor device of this invention. Sectional drawing of the semiconductor device of this invention. 1 is a block diagram illustrating a configuration of a semiconductor device of the present invention. 1 is a block diagram illustrating a configuration of a semiconductor device of the present invention. FIG. 11 is a diagram showing an application example using a semiconductor device of the present invention. FIG. 11 is a diagram showing an application example using a semiconductor device of the present invention. The model figure used for simulation and the figure which shows a result. Model diagram used for simulation and diagram showing results The model figure used for simulation and the figure which shows a result. The model figure used for simulation and the figure which shows a result. The figure which shows _LOV definition. FIG. 6 is a graph showing a concentration distribution of impurity elements in a horizontal direction and a vertical direction of a semiconductor layer. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 1 is a schematic view of a doping apparatus that can be used in the present invention. The figure explaining the outline | summary of this invention. 1 is a schematic view of a doping apparatus that can be used in the present invention.

Claims (28)

Having a gate insulating layer on the semiconductor layer;
The semiconductor layer includes a channel formation region, a source region, a drain region, and an impurity region between the channel formation region and the source region,
The channel formation region and the drain region are provided in contact with each other,
A semiconductor device comprising a gate electrode layer over the channel formation region and the impurity region with the gate insulating layer interposed therebetween. Having a gate insulating layer on the semiconductor layer;
The semiconductor layer has a channel formation region, a source region, a drain region, and an impurity region between the channel formation region and the drain region,
The channel formation region and the source region are provided in contact with each other,
A semiconductor device comprising a gate electrode layer over the channel formation region and the impurity region with the gate insulating layer interposed therebetween. 3. The impurity region according to claim 1, wherein the impurity region has an impurity element imparting p-type,
The semiconductor device is characterized in that the source region and the drain region contain an impurity element imparting n-type conductivity. The impurity region according to claim 1 or 2, wherein the impurity region has an impurity element imparting n-type,
The semiconductor device is characterized in that the source region and the drain region include an impurity element imparting p-type conductivity. Having a gate insulating layer on the semiconductor layer;
The semiconductor layer includes a channel formation region, a source region, a drain region, a first impurity region between the channel formation region and the source region, and a first impurity region between the source region and the first impurity region. 2 impurity regions, and a third impurity region between the drain region and the channel formation region,
The channel formation region and the third impurity region are provided in contact with each other,
A gate electrode layer on the channel formation region and the first impurity region via the gate insulating layer;
The second impurity region, the third impurity region, the source region, and the drain region each include an impurity element imparting one conductivity type;
The concentration of the element imparting one conductivity type in the second impurity region and the third impurity region is lower than the concentration of the impurity element imparting the one conductivity type in the source region and the drain region, Semiconductor device. Having a gate insulating layer on the semiconductor layer;
The semiconductor layer includes a channel formation region, a source region, a drain region, a first impurity region between the channel formation region and the drain region, and a second region between the source region and the channel formation region. An impurity region, and a third impurity region between the drain region and the first impurity region;
The channel formation region and the second impurity region are provided in contact with each other,
A gate electrode layer on the channel formation region and the first impurity region via the gate insulating layer;
An impurity element imparting one conductivity type of the second impurity region, the third impurity region, the source region, and the drain region;
The concentration of the element imparting the one conductivity type in the second impurity region and the third impurity region is lower than the concentration of the impurity element imparting the one conductivity type in the source region and the drain region. A semiconductor device. In Claim 5 or Claim 6, the first impurity region has an impurity element imparting p-type,
The semiconductor device, wherein the second impurity region, the third impurity region, the source region, and the drain region each include an impurity element imparting n-type conductivity. In Claim 5 or Claim 6, the first impurity region has an impurity element imparting n-type,
The semiconductor device, wherein the second impurity region, the third impurity region, the source region, and the drain region each include an impurity element imparting p-type conductivity.     The semiconductor device according to claim 1, further comprising an insulating layer on a side surface of the gate electrode layer. In any 1 paragraph of Claims 1 thru / or 9, It has an interlayer insulation layer on the gate insulation layer and the gate electrode layer,
The interlayer insulating layer and the gate insulating layer have openings reaching the source region and the drain region;
A semiconductor device having a source electrode layer and a drain electrode layer in contact with the source region and the drain region in the opening. A gate insulating layer on the first semiconductor layer and the second semiconductor layer;
The first semiconductor layer includes a first channel formation region, a first source region, a first drain region, and a first channel between the first channel formation region and the first source region. An impurity region,
The second semiconductor layer includes a second channel formation region, a second source region, a second drain region, and a second channel formation region between the second channel formation region and the second drain region. An impurity region,
The first channel formation region and the first drain region are provided in contact with each other,
The second channel formation region and the second source region are provided in contact with each other;
Having a first gate electrode layer on the first channel formation region and the first impurity region via the gate insulating layer;
A semiconductor device comprising: a second gate electrode layer over the second channel formation region and the second impurity region with the gate insulating layer interposed therebetween. The first source region, the second source region, the first source region, and the second drain region each include an impurity element imparting n-type,
The semiconductor device, wherein the first impurity region and the second impurity region have an impurity element imparting p-type conductivity. The first source region, the second source region, the first source region, and the second drain region each include an impurity element imparting p-type,
The semiconductor device, wherein the first impurity region and the second impurity region include an impurity element imparting n-type conductivity. An amorphous semiconductor film is formed on the insulating surface,
Irradiating the amorphous semiconductor film with laser light to form a crystalline semiconductor film,
Patterning the crystalline semiconductor film to form a semiconductor layer;
Forming a gate insulating layer on the semiconductor layer;
Forming a gate electrode layer on the gate insulating layer;
Using the gate electrode layer as a mask, an impurity element imparting a first one conductivity type is added to the semiconductor layer obliquely with respect to the surface of the semiconductor layer to form a first impurity region,
Using the gate electrode layer as a mask, an impurity element imparting a second one conductivity type is added to the semiconductor layer perpendicularly to the surface of the semiconductor layer to thereby form a second impurity region, a source region, a drain region, and a channel. Forming the formation region,
The second impurity region is formed in the semiconductor layer covered with the gate electrode layer between the channel formation region and the source region;
The method for manufacturing a semiconductor device, wherein the drain region is formed in contact with the channel formation region. An amorphous semiconductor film is formed on the insulating surface,
Irradiating the amorphous semiconductor film with laser light to form a crystalline semiconductor film,
Patterning the crystalline semiconductor film to form a semiconductor layer;
Forming a gate insulating layer on the semiconductor layer;
Forming a gate electrode layer on the gate insulating layer;
Using the gate electrode layer as a mask, an impurity element imparting a first one conductivity type is added to the semiconductor layer obliquely with respect to the surface of the semiconductor layer to form a first impurity region,
Using the gate electrode layer as a mask, an impurity element imparting a second one conductivity type is added to the semiconductor layer perpendicularly to the surface of the semiconductor layer to thereby form a second impurity region, a source region, a drain region, and a channel. Forming the formation region,
The second impurity region is formed in the semiconductor layer covered with the gate electrode layer between the channel formation region and the drain region;
The method for manufacturing a semiconductor device, wherein the source region is formed in contact with the channel formation region. 16. The impurity element imparting p-type is added as the impurity element imparting the first conductivity type, and the first impurity region and the second impurity region are formed. ,
A method for manufacturing a semiconductor device, wherein an impurity element imparting n-type conductivity is added as the impurity element imparting the second conductivity type to form the source region and the drain region. 16. The impurity element imparting n-type conductivity is added as the impurity element imparting the first conductivity type, and the first impurity region and the second impurity region are formed. ,
A method for manufacturing a semiconductor device, wherein an impurity element imparting p-type conductivity is added as the impurity element imparting the second conductivity type to form the source region and the drain region. 18. The first impurity region according to claim 14, wherein an impurity element imparting a first conductivity type at an angle θ <b> 1 with respect to the surface of the semiconductor layer is added to the semiconductor layer from one direction. Form the
An impurity element imparting a second conductivity type at an angle θ2 with respect to the surface of the semiconductor layer is added to the semiconductor layer to form a second impurity region, a source region, a drain region, and a channel formation region;
A method for manufacturing a semiconductor device, wherein a difference between the angle θ1 and the angle θ2 is 5 degrees or more. An amorphous semiconductor film is formed on the insulating surface,
Irradiating the amorphous semiconductor film with laser light to form a crystalline semiconductor film,
Patterning the crystalline semiconductor film to form a semiconductor layer;
Forming a gate insulating layer on the semiconductor layer;
Forming a gate electrode layer on the gate insulating layer;
Using the gate electrode layer as a mask, an impurity element imparting a first one conductivity type is added to the semiconductor layer obliquely with respect to the surface of the semiconductor layer to form a first impurity region,
Using the gate electrode layer as a mask, an impurity element imparting a second conductivity type is added to the semiconductor layer perpendicularly to the surface of the semiconductor layer to add a second impurity region, a third impurity region, 4 impurity regions and a channel formation region,
Forming an insulating layer on a side surface of the gate electrode layer;
Using the gate electrode layer and the insulating layer as a mask, an impurity element imparting the third one conductivity type is added to the semiconductor layer perpendicularly to the surface of the semiconductor layer to be in contact with the source region and the source region. Forming a fifth impurity region, a drain region, and a sixth impurity region in contact with the drain region;
The concentrations of the impurity element having the second conductivity type and the impurity element imparting the third conductivity type in the fifth impurity region and the sixth impurity region are the concentration in the source region and the drain region. Lower than the concentration of the impurity element having the second one conductivity type and the impurity element imparting the third one conductivity type;
The second impurity region is formed in the semiconductor layer covered with the gate electrode layer between the channel formation region and the fifth impurity region,
The method for manufacturing a semiconductor device, wherein the sixth impurity region is formed in contact with the channel formation region. An amorphous semiconductor film is formed on the insulating surface,
Irradiating the amorphous semiconductor film with laser light to form a crystalline semiconductor film,
Patterning the crystalline semiconductor film to form a semiconductor layer;
Forming a gate insulating layer on the semiconductor layer;
Forming a gate electrode layer on the gate insulating layer;
Using the gate electrode layer as a mask, an impurity element imparting a first one conductivity type is added to the semiconductor layer obliquely with respect to the surface of the semiconductor layer to form a first impurity region,
Using the gate electrode layer as a mask, an impurity element imparting a second conductivity type is added to the semiconductor layer perpendicularly to the surface of the semiconductor layer to add a second impurity region, a third impurity region, 4 impurity regions and a channel formation region,
Forming an insulating layer on a side surface of the gate electrode layer;
Using the gate electrode layer and the insulating layer as a mask, an impurity element imparting the third one conductivity type is added to the semiconductor layer perpendicularly to the surface of the semiconductor layer to be in contact with the source region and the source region. Forming a fifth impurity region, a drain region, and a sixth impurity region in contact with the drain region;
The concentrations of the impurity element having the second conductivity type and the impurity element imparting the third conductivity type in the fifth impurity region and the sixth impurity region are the concentration in the source region and the drain region. Lower than the concentration of the impurity element having the second one conductivity type and the impurity element imparting the third one conductivity type;
The second impurity region is formed in the semiconductor layer covered with the gate electrode layer between the channel formation region and the sixth impurity region;
The method for manufacturing a semiconductor device, wherein the fifth impurity region is formed in contact with the channel formation region. In Claim 19 or Claim 20, an impurity element imparting p-type is added as the impurity element imparting the first conductivity type to form a first impurity region and a second impurity region,
As the impurity element imparting the second one conductivity type and the impurity element imparting the third one conductivity type, an impurity element imparting n-type is added and the third impurity region and the fourth impurity are added. A method for manufacturing a semiconductor device, comprising forming a region, the fifth impurity region, the sixth impurity region, the source region, and the drain region. 21. The first impurity region and the second impurity region are formed by adding an impurity element imparting n-type conductivity as the impurity element imparting the first conductivity type according to claim 19 or claim 20. ,
As the impurity element imparting the second one conductivity type and the impurity element imparting the third one conductivity type, an impurity element imparting p-type is added and the third impurity region and the fourth impurity are added. A method for manufacturing a semiconductor device, comprising forming a region, the fifth impurity region, the sixth impurity region, the source region, and the drain region. The interlayer insulating layer according to any one of claims 14 to 22, wherein an interlayer insulating layer is formed over the semiconductor layer, the gate insulating layer, and the gate electrode layer.
Forming an opening reaching the source region and the drain region in the interlayer insulating layer and the gate insulating layer;
A method for manufacturing a semiconductor device, wherein a source electrode layer and a drain electrode layer in contact with the source region and the drain region are formed in the opening. An amorphous semiconductor film is formed on the insulating surface,
Irradiating the amorphous semiconductor film with laser light to form a crystalline semiconductor film,
Patterning the crystalline semiconductor film to form a first semiconductor layer and a second semiconductor layer;
Forming a gate insulating layer on the first semiconductor layer and the second semiconductor layer;
Forming a first gate electrode layer and a second gate electrode layer on the gate insulating layer;
Using the first gate electrode layer and the second gate electrode layer as a mask, an impurity element imparting a first one conductivity type obliquely with respect to the surfaces of the first semiconductor layer and the second semiconductor layer is formed. Adding from one direction to form a first impurity region in the first semiconductor layer, forming a second impurity region in the second semiconductor layer;
Using the first gate electrode layer and the second gate electrode layer as a mask, an impurity element imparting a second one conductivity type perpendicular to the surface of the first semiconductor layer and the surface of the second semiconductor layer is formed. Addition to form a third impurity region, a first source region, a first drain region, and a first channel formation region in the first semiconductor layer, and a fourth impurity region in the second semiconductor layer , Forming a second source region, a second drain region, and a second channel formation region,
The third impurity region is formed in the first semiconductor layer covered with the first gate electrode layer between the first channel formation region and the first source region;
The fourth impurity region is formed in the second semiconductor layer covered with the second gate electrode layer between the second channel formation region and the second drain region;
The first drain region is formed in contact with the first channel formation region;
The method for manufacturing a semiconductor device, wherein the second source region is formed in contact with the second channel formation region. 25. The impurity element imparting p-type conductivity is added as the impurity element imparting the first conductivity type, and the first impurity region, the second impurity region, and the third impurity region are added. And forming the fourth impurity region,
An impurity element imparting n-type conductivity is added as the impurity element imparting the second one conductivity type, and the first source region, the second source region, the first drain region, and the second drain region are added. A method for manufacturing a semiconductor device, characterized by forming a drain region. 25. The first impurity region, the second impurity region, and the third impurity region by adding an impurity element imparting n-type conductivity as the impurity element imparting the first conductivity type according to claim 24. And forming the fourth impurity region,
As the impurity element imparting the second one conductivity type, an impurity element imparting p-type conductivity is added to the first source region, the second source region, the first drain region, and the second A method for manufacturing a semiconductor device, characterized by forming a drain region.     27. The method for manufacturing a semiconductor device according to claim 14, wherein the laser beam is a continuous wave laser beam. 27. The method for manufacturing a semiconductor device according to claim 14, wherein the laser light is pulsed laser light, and the frequency of the pulsed oscillation is 0.5 MHz or more.

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