JP2006018419A - Storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problems of a recording device performing striping record: a large-capacity transfer buffer is required for transfer in striping order, and parallel transfer cannot be performed until completion of the transfer of one striping unit. <P>SOLUTION: A changeover means and a plurality of storage medium control means are controlled such that data transfer is performed between a host interface and a plurality of transfer buffer memories while changing over the plurality of transfer buffer memories in a block unit smaller than the striping unit, and that data transfer is continuously performed in the striping unit between the plurality of transfer buffer memories and a plurality of storage means. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a storage device that uses a plurality of storage means such as a memory card and a hard disk and interfaces with a host device as a single drive.

  As a memory card which is a card type recording medium using a flash memory, a compact flash (registered trademark), an SD memory card, and the like have been developed. The memory card has features such as small size, low power consumption, and random access as compared with other recording media, and is therefore widely used in portable devices such as digital still cameras and mobile phones.

  However, when recording a large amount of data such as video information in a memory card in real time, for example, the resolution, frame rate, and compression rate of the screen to be recorded depends on the data transfer rate and storage capacity that can be realized by the memory card. The recordable time is limited, and its application range is limited. For example, in a video camera using a memory card as a recording medium, it is difficult to realize high image quality and long-time recording equivalent to a VTR using a magnetic tape as a recording medium.

  To compensate for the shortcomings of such memory cards, a single disk device (RAID 0: Redundant Arrays of Inexpensive Disks 0) with a large capacity and high transfer rate is realized by installing multiple memory cards in the device and striping. A method to do this is disclosed in Patent Document 1.

  In Patent Document 2, a plurality of semiconductor memory devices that can be accessed in 512-byte block units are striped in block units, and data transfer is performed in parallel between a 1-Mbyte data transfer buffer and a plurality of semiconductor memory devices. A storage device is disclosed in which data is collected on a data transfer buffer and transferred between the data transfer buffer and a host device via a single SCSI interface.

  Here, a bus (host bus) generally used in a computer system or a system incorporating a computer will be described by taking a PCI bus as an example. The PCI bus is a bus having a clock frequency of 33 MHz and a data width of 32 bits, and can transfer 4-byte data in one clock. At this time, the transfer destination address is shown by time-sharing a 32-bit bus that is the same as the data. That is, one transfer on the PCI bus consists of a clock cycle (address phase) indicating a transfer destination address and a transfer command, and a plurality of clock cycles (data phase) indicating a plurality of transfer data subsequent thereto. Data in the memory area having the indicated address as the head address and the number of continuous data as the memory size can be transferred continuously. Therefore, the instantaneous maximum transfer rate of the PCI bus is 132 MB / s.

  On the other hand, for example, in an SD memory card, data transfer using a 4-bit bus with a 50 MHz clock is defined, and data transfer of a maximum of 25 MB / s is possible. Thus, since the maximum data transfer rate of the SD memory card is much smaller than the maximum data transfer rate of the PCI bus, when data is transferred between the SD memory card and the main memory of the system via the PCI bus. Data transfer buffer memory is required.

  In particular, when data transfer to a plurality of SD memory cards is performed by switching in a time division manner on one PCI bus, it should be noted that a large data transfer buffer memory is required depending on the switching method.

  For example, as in Patent Document 2, when the striping unit is 512 bytes and striping is performed on eight memory cards, one block of data of continuous addresses on the main memory is stored in each memory card. It is recorded in units of (512 bytes). Data is transferred between each memory card and the data transfer buffer at approximately the same time and at a low speed, while data is transferred between the data transfer buffer and the main memory via the host bus in the order of addresses. While the data of one memory card is transferred on the host bus, the other memory cards cannot achieve high-speed data transfer as a whole unless data transfer to the data transfer buffer is performed in parallel. A data transfer buffer corresponding to the number of memory cards having a block size of bytes, that is, eight times the data transfer buffer is required here.

  By the way, the 512-byte block size, which is the access unit of each memory card, is set to be the same as the access unit (sector) in the conventional hard disk in order to improve drive compatibility as viewed from the software. On the other hand, the erase unit / write unit of the flash memory used in the memory card is optimally selected according to the cell structure of the internal memory, and tends to become larger than 512 bytes as the memory capacity increases. . Even in such a case, it is necessary to perform a so-called read-modify-write process using a transfer buffer in order to realize 512-byte access in consideration of the software compatibility of the host device. . For example, when only 512 bytes are written when the erase unit of the flash memory is 2 Kbytes, 2 Kbytes including 512 bytes to be rewritten inside the memory card are once read to the transfer buffer, and 512 bytes of them are stored on the transfer buffer. The process of writing the 2K bytes of the rewritten transfer buffer contents into the erased erase unit block in the flash memory is performed.

For this reason, the write performance of only the blocks smaller than the erase unit of the flash memory is lower than the maximum write performance of the flash memory. At this time, if the striping unit is smaller than the erasing unit, read / modify / write is required for all the memory cards, so that the range of the number of sectors in which writing is slow increases. Therefore, in order to realize a higher transfer rate, it is desirable that the striping unit is the same as the erase unit of the flash memory or an integral multiple of the erase unit.
JP 2000-207137 A (page 3, FIG. 1) JP-A-8-235076 (pages 5-6, FIG. 7)

  However, in the case of such a conventional storage device, the capacity required for the data transfer buffer is the product of the striping unit (flash memory erase unit or an integral multiple thereof) and the number of memory cards, so a buffer with a larger capacity is required. There was a problem of becoming.

  In the case of performing striping, there is a waiting time until the data transfer is completed between the memory card and the data transfer buffer for the data block to be accessed first at the start of data transfer. When the striping unit is increased, the data transfer buffer size is increased as described above, and this time is increased. As a result, there is a problem that latency at the start of a series of data transfer increases.

  In view of the above problems, an object of the present invention is to provide a storage device that can realize high-rate data transfer using striping by parallel operation of a plurality of memory cards using a small-capacity transfer buffer.

In order to solve the above problems, the present invention
A storage device that records and reproduces data input / output to / from a host device via a host interface in a plurality of storage media in a predetermined striping unit, and is input to each of the storage media. A plurality of transfer buffer memories for temporarily storing output data; a plurality of storage medium control means for controlling data transfer between the corresponding plurality of storage media and the plurality of transfer buffer memories; and the host Switching means for switching a data transfer path between the interface and the plurality of transfer buffer memories; and transferring data to the host interface and the plurality of transfers while switching the plurality of transfer buffer memories in units of blocks smaller than the striping unit. In addition to transferring data to and from the buffer memory, A control means for controlling the switching means and the plurality of storage medium control means so as to transfer data between the plurality of transfer buffer memories and the plurality of storage means continuously in a ping unit; It is a thing.

  As described above, according to the present invention, even when the striping unit determined by the characteristics of a plurality of low-speed storage media constituting the storage device is relatively large, the host is separated for each predetermined number of smaller data regardless of the striping unit. Since data transfer to and from the device can be switched, there is an advantage that the data access waiting time seen from the host device can be reduced. In addition, since the data transfer unit can be reduced, the capacity of the data FIFO can be reduced, and an increase in the device scale can be suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the embodiment of the present invention, a storage device that logically configures one RAID drive using four SD memory cards as storage media will be described. The storage medium may be another memory card such as a compact flash (registered trademark), an optical disk, a hard disk, or the like. Also, the number may be two, eight, etc. in addition to four.

(Embodiment 1)
First, the basic configuration of the present invention will be described as the first embodiment under the following assumptions in order to simplify the description. In other words, the memory area secured as a transfer buffer on the main memory by the host device is one area that is physically or logically continuous. However, as will be described later in Embodiment 2, the basic configuration is common even when the memory area is divided into a plurality of areas.

FIG. 1 is a block diagram illustrating a configuration of a storage device and a host device in the present embodiment.
The RAID drive 101 of the present invention is a storage device that records and reproduces data input / output to / from the host device 102 via the host interface 133 in a plurality of storage media in a predetermined striping unit. The RAID drive 101 is connected to a host device 102 that reads / writes data from / to the RAID drive 101 via a host interface 133. Examples of the host device 102 include a PC and the like in addition to video devices such as a video camera and a video recorder. The host device 102 and the RAID drive 101 may be configured integrally, or may be configured to be connected by a cable or the like. The RAID drive 101 contains four SD memory cards 110, 111, 112, and 113 as a plurality of storage media, and these can be accessed logically as a single disk drive to the host device 102 ( RAID 0). Four data FIFOs 117, 118, 119, and 120 as a plurality of transfer buffer memories are buffer memories that temporarily store data input / output to / from the four SD memory cards 110, 111, 112, and 113, respectively. . The four memory card control circuits 121, 122, 123, and 124 as a plurality of storage medium control means control data transfer between the SD memory card and the data FIFO, respectively. The control unit 134 controls the switching circuit 125 and the plurality of memory card control circuits based on the command input from the host device 102 via the host interface 133 and the transfer data address. A switching circuit 125 as a switching unit switches a transfer path between the four data FIFOs 117, 118, 119, and 120 and the host interface 133 based on a control signal from the control unit 134.

  In this embodiment, the minimum unit of data access from the host device 102 is 1 sector (512 bytes). On the other hand, the four data FIFOs 117, 118, 119, 120 each have a capacity of 128 bytes smaller than the sector size, and data transfer between the host interface 133 and the four data FIFOs is performed by the switching circuit 125 at 128. It is assumed that switching is performed in units of bytes.

  In the RAID drive 101 configured as described above, the logical address of the data in the RAID drive viewed from the host device 102 and the memory card control circuits 121 and 122 for the four SD memory cards 110, 111, 112, and 113, respectively. , 123, and 124 show the relationship between the addresses of the data in the card. Each SD memory card 110, 111, 112, 113 can be accessed in 512-byte block units, which is the minimum access unit according to the SD memory card standard. This block is called a sector, and is represented by a small square in FIG. In FIG. 2, four vertically arranged sector columns represent storage areas of four SD memory cards 110, 111, 112, and 113, respectively. Each sector is given a sector number in the SD memory card which is a serial number in the SD memory card. This number becomes an address for designating a sector in each SD memory card, and becomes an address of data in the card as seen from the memory card control circuits 121, 122, 123, and 124.

  Similarly, a sector number in the RAID drive that is a serial number is given to each sector through all data in the RAID drive 101. The RAID drive sector number is a logical address viewed from the host device 102. In FIG. 2, these two types of sector numbers are displayed in hexadecimal numbers in a square representing each sector. The number on the left represents the sector number in the RAID drive, and the number on the right represents the sector number in the SD memory card. Further, memory card numbers # 0, # 1, # 2, and # 3 are assigned to the SD memory cards 110, 111, 112, and 113, respectively, to distinguish them.

  As shown in FIG. 2, since the RAID drive 101 of this embodiment performs striping with 2 Kbytes (= 4 sectors) as a striping unit, the sector numbers in the RAID drive are consecutive from one SD memory card in order. It is assigned to 4 sectors, and the continuation is assigned to 4 consecutive sectors of the next SD memory card. The erasure unit of the SD memory cards 110, 111, 112, and 113 is also 2 Kbytes, which is the same as the striping unit. That is, as long as data transfer to each SD memory card is performed in units of 2 Kbyte blocks, which are striping units, no read / modify / write occurs, and there is no deterioration in write performance due to this.

  On the other hand, the sector numbers in the SD memory card are given in the order of the sectors arranged vertically from the head sector in the SD memory card, as shown in FIG.

  The basic operation of the RAID drive 101 configured as described above will be described with reference to FIGS. Here, a case where data is transferred from the host device 102 to the RAID drive 101 will be described, but the same applies to a case where data is transferred from the RAID drive 101 to the host device 102. In the case of data transfer to the RAID drive 101, the host device 102 first stores the data to be transferred in a host side buffer secured on the main memory 108, and then sends a data transfer command to the RAID drive 101. On the other hand, the RAID drive 101 interprets the command and transfers data from the host side buffer to the SD memory cards 110, 111, 112, and 113 in the RAID drive.

  The outline of data transfer is as follows. The switching circuit 125 is set so that the control unit 134 transfers data between the host interface and the data FIFO while switching the data FIFO in units of 128-byte blocks, which is a data FIFO size smaller than the 2 Kbyte striping unit. Control. That is, for the transfer data, one block is selected in order from each striping unit corresponding to the four SD memory cards and transferred to the corresponding data FIFO. In parallel with this, the control means 134 controls the memory card control circuit to transfer the data accumulated in each data FIFO to the SD memory card. As a result, the SD memory is continuously recorded in the striping unit. Transfer data to the card.

  FIG. 3 is a conceptual diagram of the host side buffer of the host device 102. The number (hexadecimal number) in the figure indicates the block number in the buffer, and this number is assigned to each 128-byte block that is the size of the data FIFO. Data to be transferred are arranged in the order of addresses on the buffer. The data on the buffer is striped for each 2 Kbyte striping unit and transferred to each SD memory card. That is, the transfer destination is assigned such that the striping unit 0 is the SD memory card # 0, the striping unit 1 is the SD memory card # 1, and the striping unit 4 is rotated again with the SD memory card # 0. However, since the size of the data FIFO to which the data on this buffer is directly transferred is 128 bytes, the data FIFO is transferred to the corresponding data in 1-block (128 bytes) from the top by cycling through each striping unit. This is performed for the FIFOs 117, 118, 119, and 120. That is, when the data transfer order from the host side buffer is indicated by a block number, 00, 10, 20, 30, 01, 11, 21, 31, ..., 0F, 1F, 2F, 3F, 40, 50, 60, 70 , 41, and so on.

  FIG. 4 is a timing chart when data transfer from the host device 102 to the RAID drive 101 is performed. In FIG. 4, the horizontal axis represents elapsed time. For the convenience of explanation, the time from 0 to 68 is given as the time in the figure. The numbers described in the figure are the block numbers of the host side buffer shown in FIG. 3 and indicate which data on the host side buffer is transferred or stored. (A) and (f) to (i) show read and write operations from each memory, (b) to (e) show the data accumulation status in the data FIFO, and the vertical axis shows the data accumulation amount. Represents. In this embodiment, for convenience, it is assumed that the transfer rate between the host side buffer and the data FIFO is exactly four times the transfer rate between the data FIFO and the SD memory card.

  Hereinafter, data transfer of the RAID drive 101 will be described with reference to FIG. When the RAID drive 101 receives a data transfer command from the host device 102 and actually starts data transfer from the host device 102, first, at time 0, 128-byte data from the block number 00 of the host side buffer is stored in the RAID drive 101. Forwarded to Block number 00 is the first block of striping unit 0 transferred to SD memory card # 0. The control means 134 refers to the offset within the striping unit of the corresponding memory card number and the first sector based on the first sector number in the RAID drive indicated by the data transfer command sent to the RAID drive 101 with reference to FIG. From this information, it is determined that the data of the block number 00 is transferred to the data FIFO 117, and the switching circuit 125 is controlled. As a result, the data from the block number 00 is transferred to the data FIFO 117 and stored. The transfer is completed at time 1, and as shown at time 1 in (b), 128 bytes of data of block number 00 are stored in the data FIFO 117.

  Next, at time 1, the data of block number 10, which is the first block of striping unit 1 next to striping unit 0 to which block number 00 transferred immediately before belongs, is transferred to RAID drive 101. The control means 134 determines that the block number 10 is the first block to be transferred to the SD memory card # 1 based on the memory card number obtained at the time of transfer of the immediately preceding block number 00 and the offset within the striping unit of the first sector. Can know. Based on this, the control means 134 determines to transfer the data of the block number 10 to the data FIFO 118 and controls the switching circuit 125. As a result, the data of block number 10 is transferred to the data FIFO 118 and stored. The transfer is completed at time 2, and as shown at time 2 in (c), 128 bytes of data of block number 10 are stored in the data FIFO 118.

  Similarly, the data of the block number 20 and the block number 30 are transferred to the data FIFOs 119 and 120, respectively (time 3 of (d), time 4 of (e)).

  On the other hand, since the data is stored in the data FIFO 117 at time 1, the control unit 134 next controls the memory card control circuit 121 to transfer the data in the data FIFO 117 to the SD memory card 110. Since the transfer from the data FIFO to the SD memory card requires more time than the transfer from the host device to the data FIFO (four times for convenience in this embodiment), if the transfer is started at time 1 as shown in (f), the time 5 To complete the transfer.

  Similarly, the data in the data FIFOs 118, 119 and 120 is transferred to the SD memory cards 111, 112 and 113.

  Next, the transfer to the SD memory card 110 will be described. As shown at time 4 in (b), transfer of the data of the block number 01 of the host side buffer to the data FIFO 117 is started. At this time, although data 1/4 of block number 00 still remains in data FIFO 117, all data of block number 00 has been completely transferred to SD memory card 110 at time 5, and at the same time, data of block number 01 Completes the accumulation in the data FIFO 117, so that the buffer does not overflow. At time 5 in (f), the memory card control circuit 121 starts transferring the data of the block number 01 to the SD memory card 110. Since the data of block number 00 and block number 01 are continuous data, data transfer from the data FIFO 117 to the SD memory card 110 is performed continuously with block numbers 00 and 01.

  Similarly, transfer of data of block number 02 at time 8 and transfer of data of block number 03 to data FIFO 117 are started at time 12, and transfer of these data from data FIFO 117 to SD memory card 110 is started at time 9 and time 13. The This is repeated, and finally, 2 Kbytes of data in the striping unit 0, that is, data of block numbers 00 to 0F is transferred to the SD memory card 110 continuously in time. As a result, since data for one erasure unit is continuously recorded on the SD memory card 110, read modification does not occur, and writing performance does not deteriorate.

  Since the same transfer is performed for other SD memory cards, the data to the RAID drive 101 is not degraded without degrading the writing performance of the SD memory card even though the capacity of the data FIFO is smaller than the erase unit or sector size. Transfer can be realized. The data after the striping unit 4 is continuously transferred, and the data transfer of the transfer size requested by the command from the host device 102 is completed.

(Embodiment 2)
Next, as a second embodiment, the operation of the storage device according to the present invention in a more generalized situation will be described in detail.

  FIG. 5 is a block diagram showing the configuration of the storage device and the host device in the present embodiment. In addition, the same number is attached | subjected about the component similar to Embodiment 1, and description is abbreviate | omitted. In FIG. 5, the RAID drive 101 has a shape conforming to the PC card standard, and uses a card bus 103 defined by the PC card standard for an electrical interface with the host device 102. Data transfer in this card bus standard is the same as that of the aforementioned PCI bus, and the signal of the card bus 103 is relayed to the PCI bus 105 of the host device 102 by the card bus bridge 104 that works in the same way as the PCI bus bridge. The signal of the PCI bus 105 is relayed by the host bridge 106 to the memory bus 109 that connects the host CPU 107 and the main memory 108.

  The card bus control circuit 116 performs data transfer between the card bus 103, the internal register bus 114, and the internal DMA bus 115 in accordance with a card bus standard control procedure. The switching circuit 125 switches the DMA transfer signals between the four data FIFOs 117, 118, 119 and 120 and between the transfer control circuit 128 and the card bus control circuit 116 based on the control signal from the transfer control circuit 128. In the command register 126, a data transfer command from the host device 102 through the card bus 103 is written. The command control circuit 127 interprets the command for the RAID drive 101 written in the command register 126, obtains commands for the four SD memory cards 110, 111, 112, and 113, and the four memory card control circuits 121, 122, and 123. , 124, the respective commands are transmitted. Based on the command from the command control circuit 127, the transfer control circuit 128 divides the host side buffer secured on the main memory 108 into areas corresponding to the four SD memory cards 110, 111, 112, and 113. The switching circuit 125 is controlled to transfer the data of the four data FIFOs 117, 118, 119, and 120 to the correct memory area. The table counter 129 holds the read address of the memory area descriptor table in the control process of the transfer control circuit 128. The memory area descriptor buffer 130 holds memory area descriptors corresponding to the four SD memory cards 110, 111, 112, and 113. The transfer counter 131 holds the number of transfer data of the four data FIFOs 117, 118, 119 and 120.

  Also in this embodiment, the minimum unit of data access from the host device is 1 sector (512 bytes), the size of the four data FIFOs 117, 118, 119, and 120 is 128 bytes, and 128 bytes on the card bus that is the host bus. Assume that data transfer of four cards is switched in units.

  The card bus control circuit 116 and the command register 126 correspond to a host interface. The command control circuit 127, the transfer control circuit 128, the memory area descriptor buffer 130, the table counter 129, and the transfer counter 131 correspond to control means.

  Also in this embodiment, the logical address of the in-drive data viewed from the host device 102 and the memory card control circuits 121, 122, 123, and 124 of the four SD memory cards 110, 111, 112, and 113, respectively. The relationship of the addresses of the data in the card is as shown in FIG.

  Based on the address mapping as described above, the operation of the RAID drive 101 of this embodiment will be described below. FIG. 6 is a schematic flowchart of data transfer command processing between the RAID drive 101 and the host device 102. In the figure, the flowchart on the left represents the processing procedure of the host device 102, and the flowchart on the right represents the processing procedure of the RAID drive 101.

  At the start of data transfer, the host device 102 first performs preparation 301. In preparation 301, a host-side buffer is secured on the main memory 108, and information called a memory area descriptor table (to be described later) (to be described later) is also stored on the main memory 108. When the transfer direction is data writing to the RAID drive 101, the data to be transferred is stored in the secured host side buffer.

  Next, the host device 102 writes a data transfer command to the command register 126 according to the protocol on the card bus 103 in the command writing 302, and enters the command end notification waiting state 303 from the RAID drive 101. On the other hand, command writing from the card bus 103 to the command register 126 is processed by the card bus control circuit 116 according to the card bus protocol, and the obtained data transfer command is stored in the command register 126. Receiving the command write notification from the command register 126, the command control circuit 127 exits from the command write wait state 305 and proceeds to the command processing 306.

  In the command processing 306, a card is transferred between the four SD memory cards 110, 111, 112, 113 and the host side buffer secured on the main memory 108 in response to the data transfer command stored in the command register 126. Data transfer is performed through the bus 103. Details of this command processing will be described later.

  When all data transfer corresponding to the written command is completed, the command control circuit 127 moves to a command end notification 307 and notifies the host device 102 of the end of command processing through the interrupt signal line 132. Receiving the command processing end notification, the host device 102 performs post-processing 304 if necessary.

  As described above, handshaking in units of commands is performed between the RAID drive 101 and the host device 102 using the command writing from the host device 102 as a trigger. At this time, in the preparation 301 described above, it is necessary to secure an area larger than the number of data to be transferred in the memory area secured by the host device 102 in the main memory 108. Since it is shared by all the processes (programs) that are being executed, there may be a case where a continuous area exceeding the number of transfer data cannot be secured. Therefore, when a continuous memory area larger than the number of transfer data cannot be secured, a plurality of areas smaller than that are secured, and the total size of the plurality of areas is equal to or greater than the number of transfer data.

  In general, since one memory area can be specified by the start address and size, a data structure called a memory area descriptor consisting of the value of the start address and area size is defined, and it corresponds to a plurality of memory areas secured as described above. The entire buffer memory area is specified by an array of a plurality of memory area descriptors. This arrangement is called a memory area descriptor table and is secured on the main memory 108 as described above. FIG. 7 shows an example of a memory area descriptor table in the embodiment of the present invention.

  In FIG. 7, the host-side buffer has three memories of address 0 to 2000 (hexadecimal) bytes, address 4800 (hexadecimal) to A00 (hexadecimal) bytes, and address 8000 (hexadecimal) to 2000 (hexadecimal) bytes. The memory area descriptor table 401 has a total size of 18944 bytes (37 sectors), and the memory area descriptor table 401 includes three memory area descriptors 401 and 403 in which the start address and the size value representing each divided area are stored. , 404. In FIG. 7, 0 and 1 on the left side of the size are EOT flags indicating that the next descriptor exists and does not exist, respectively. The fact that the EOT flag 1 is set in the third descriptor 404 indicates that the host-side buffer ends in the third area.

  FIG. 8 shows an example of the data structure of a command that the host device 102 writes to the command register 126 in the command writing 302. As shown in the figure, the command includes a command code 501 indicating a data transfer direction (write or read), a head sector number 502 in the RAID drive 101 of data to be transferred, a sector number 503 to be transferred, and a memory area. The descriptor table 401 is composed of a head address 504 in the main memory 108.

  Next, details of the command processing 306 will be described. In the RAID drive 101 that detected the command writing, in the command processing 306, the command control circuit 127 interprets the contents of the command register 126 according to the data structure shown in FIG. 8, and the memory card control circuits 121, 122, 123, 124 Then, necessary transfer parameters and a transfer start trigger are sent to the transfer control circuit 128.

  FIG. 9 shows a detailed flowchart of the command processing 306 in the command control circuit 127 at this time together with a control flowchart of the transfer control circuit 128. In FIG. 9, the command control circuit 127 first obtains transfer parameters to be sent to the memory card control circuits 121, 122, 123, and 124 and the transfer control circuit 128 by parameter calculation 601.

  The transfer parameters sent to the memory card control circuits 121, 122, 123, and 124 are the head sector number and the number of transfer sectors in the SD memory card of data to be transferred in each of the four SD memory cards 110, 111, 112, and 113. .

  These transfer parameter values will be described with reference to the example of FIG. FIG. 10 shows the sector number in the RAID drive 101 when the value of the head sector number 502 is 6 and the value of the transfer sector number 503 is 37 (decimal. Hereinafter, decimal notation unless otherwise specified). And the relationship of the sector numbers in the four SD memory cards. As in FIG. 2, the solid square represents the sector to be transferred, the left side of the hexadecimal number written therein represents the sector number in the RAID drive 101, and the right side represents the sector number in each memory card.

  Since the value of the head sector number 502 of the command is 6 and the value of the number of transfer sectors is 37, the head sector 702 of the RAID drive sector number 6 is changed to the tail sector 708 of the RAID drive sector number 42 (2A in hexadecimal). The 37 sectors up to are sectors to be transferred.

  As shown in the figure, for each SD memory card, the required transfer parameters are the sector number 4 and the transfer sector number 8 of the first sector 701 for the card number 0, and the sector of the first sector 702 for the card number 1. For the number 2 and the transfer sector number 10, for the card number 2, the sector number 0 and the transfer sector number 11 for the head sector 703, and for the card number 3, the sector number 0 and the transfer sector number 8 for the head sector 704.

These transfer parameters are obtained as follows. The sector number of the head sector 702 of the command and the number of transfer sectors are
S = 6, Z = 37
And the number of striping unit sectors is U = 4
The number of memory cards is N = 4
And When integer division for rounding off the remainder is represented by “/” and the remainder operation is represented by “%”, the memory card number CS including the first sector 702 is expressed as follows:
CS = (S / U)% N
Is calculated by calculating
CS = (6/4)% 4 = 1
It is.

Generally, the sector number of the first sector in each memory card is
(S / (U × N) +1) × U for a memory card with a number smaller than the memory card number CS including the first sector
As for a memory card including the first sector, (S / (U × N)) × U + (S% U)
For a memory card with a number greater than the memory card number CS including the first sector, (S / (U × N)) × U
As required.

In the example of FIG. 10, since CS = 1, the sector number in the memory card of the first sector 701 of the memory card 0 is
S0 = (6 / (4 × 4) +1) × 4 = 4
The sector number in the memory card of the first sector 702 of the memory card 1 is
S1 = (6 / (4 × 4)) × 4 + (6% 4) = 2
The sector numbers in the memory card of the first sectors 703 and 704 of the memory cards 2 and 3 are
S2 = (6 / (4 × 4)) × 4 = 0
S3 = (6 / (4 × 4)) × 4 = 0
Is required.

Next, the sector number in the RAID drive of the sector immediately after the last sector to be transferred is E = S + Z
As in the above equation, the memory card number CE including the sector immediately after the end is
CE = (E / U)% N
The sector number in the memory card of the sector immediately after the end in each memory card is smaller than the memory card number CE.
(E / (U × N) +1) × U
As for the memory card with the memory card number CE, (E / (U × N)) × U + (E% U)
For a memory card with a number greater than the memory card number CE, (E / (U × N)) × U
As required.

In the example of FIG. 10, the sector number in the RAID drive of the sector 707 immediately after the transfer target end sector 708 is E = S + Z = 43.
The memory card number CE including the sector 707 immediately after the end is
CE = (E / U)% N = (43/4)% 4 = 2
Therefore, the sector numbers in the memory card of the sectors 705 and 706 immediately after the end of the memory cards 0 and 1 are E0 = (43 / (4 × 4) +1) × 4 = 12.
E1 = (43 / (4 × 4) +1) × 4 = 12
The sector number in the memory card of the sector 707 immediately after the end of the memory card 2 is E2 = (43 / (4 × 4)) × 4 + (43% 4) = 11
The sector number in the memory card of the sector 709 immediately after the end of the memory card 3 is E3 = (43 / (4 × 4)) × 4 = 8
Is required.

Therefore, the number of transfer sectors Z0, Z1, Z2, and Z3 for each memory card is
Z0 = E0-S0 = 12-4 = 8
Z1 = E1-S1 = 12-2 = 10
Z2 = E2-S2 = 11-0 = 11
Z3 = E3-S3 = 8-0 = 8
Is required.

  In this way, the leading addresses S0, S1, S2, S3 of the transfer target sector of the SD memory card and the transfer sector numbers Z0, Z1, Z2, Z3, which are transfer parameters of each SD memory card, are obtained. The above calculation can be realized by recombination of most bits when U and N are powers of 2.

  Next, returning to FIG. 9, the command control circuit 127 that has obtained the transfer parameters as described above, in the data transfer start processing 602, transfers the transfer parameters for the four SD memory cards to the memory card control circuits 121, 122, 123, respectively. A trigger signal for starting transfer is sent to the memory card control circuits 121, 122, 123, and 124. As a result, four parallel data transfers are started between the SD memory cards 110, 111, 112, and 113 and the data FIFOs 117, 118, 119, and 120.

  The command control circuit 127 also obtains the transfer parameter to the transfer control circuit 128 at the same time in the parameter calculation 601. The transfer parameters to the transfer control circuit 128 include the SD memory card number CS including the head sector 702, the number of sectors counted from the striping boundary of the head sector 702 (hereinafter referred to as an offset value), the total of each SD memory card. These are the number of transfer sectors Z0, Z1, Z2, Z3, and the start address DAS of the memory area descriptor table.

  Among these, CS, Z0, Z1, Z2, and Z3 have already been obtained by the above-described equations. The start address DAS of the memory area descriptor table is the value of the start address field 504 written to the command register 126.

The offset value OS from the striping boundary of the first sector 702 is
OS = S% U
In the example of FIG. 10, OS = 6% 4 = 2
It is.

  The command control circuit 127 having obtained these transfer parameters in the parameter calculation 601 sends a transfer start trigger together with the transfer parameters to the transfer control circuit 128 in the data transfer start 602. Thereby, DMA transfer processing between the host side buffer on the main memory 108 and the four data FIFOs is started.

  The transfer control circuit 128 waiting in the trigger wait state 607 receives the above transfer start and trigger from the command control circuit 127, enters the cyclic DMA transfer processing 605, and performs DMA transfer on the card bus based on the given parameters. To control.

  In order to explain this cyclic DMA transfer process, first, the correspondence between the buffer memory area and the sectors of the four memory cards is shown in FIG. FIG. 11 shows a case where the buffer memory area shown in the descriptor table of FIG. 7 is applied to the same head sector number S and transfer sector number Z as in FIG.

  As in FIG. 10, the solid square represents the sector to be transferred, and the number on the left side written therein represents the same sector number in the RAID drive as in FIG. 10. On the other hand, the hexadecimal number in parentheses indicates the address range of the buffer memory area corresponding to the sector in hexadecimal.

  As shown in the figure, the 512-byte memory areas in order from the first sector 702 are made to correspond in the order of RAID drive sector numbers. Therefore, the buffer memory area (0000 to 1FFF) indicated by the first descriptor 402 ends in sectors 702 to 801, and the memory area (4800 to 51FF) indicated by the second descriptor 403 starts from the next sector 802. Correspond as shown in the figure. Similarly, from the sector 803 to the last sector 708, the memory area (8000 to 9FFF) indicated by the third descriptor 404 corresponds.

  FIG. 12 is a further detailed flowchart of the cyclic DMA transfer processing 605 in the transfer control circuit 128. Details of the cyclic DMA transfer processing 605 will be described below with reference to this flowchart. In the cyclic DMA transfer processing 605, the transfer control circuit 128 uses the transfer counter 131, the table counter 129, and the memory area descriptor buffer 130 as control variables.

  The transfer counter 131 is a card number counter TC for data transfer, total transfer number counters TZ0, TZ1, TZ2, TZ3 corresponding to each SD memory card, transfer destination memory address counters TA0, TA1, TA2, TA3, in one memory area Transfer number counters TS0, TS1, TS2, TS3, and offset counters TO0, TO1, TO2, TO3 from the striping boundary. The table counter 129 also includes a memory area descriptor table based on an address counter DTA of the memory area descriptor table, a memory area descriptor table end flag register EOT, a card number register BCS corresponding to the first byte of the memory block, and an offset BOS of the first byte of the memory block. The descriptor buffer 130 is configured by memory area start address registers BA0, BA1, BA2, BA3 and transfer size registers BS0, BS1, BS2, BS3 corresponding to each SD memory card.

  First, in the initialization step 901 of FIG. 12, each counter and buffer are initialized as follows.

TC = CS = first sector card number TO (CS) = OS × 512 = first sector offset (byte unit)
TO (except CS) = 0
TS0 = TS1 = TS2 = TS3 = 0
TZ0 = Z0 × 512 = total transfer byte number of card 0 TZ1 = Z1 × 512 = total transfer byte number of card 1 TZ2 = Z2 × 512 = total transfer byte number of card 2 TZ3 = Z3 × 512 = total transfer of card 3 Number of bytes DTA = start address of memory area descriptor table EOT = 0
BCS = CS = first sector card number BOS = OS × 512 = first sector offset (in bytes)
BS0 = BS1 = BS2 = BS3 = 0
Next, in the transfer start determination 902, it is determined whether or not the memory area descriptor processing 903 is to be performed. That is, the register EOT is 0 (meaning that an unprocessed memory area descriptor remains), and the registers BS0, BS1, BS2, and BS3 are all 0 (the registers BS0, BS1, BS2, and BS3 are empty). The process proceeds to the memory area descriptor processing 903. Otherwise, the process proceeds to data transfer end determination 905.

  In the memory area descriptor processing 903, the switching circuit 125 and the card bus control circuit 116 are controlled to read one memory area descriptor from the area on the main memory 108 pointed to by the address counter DTA of the memory area descriptor table. The head address value of the read memory area descriptor is set to BMA, the area size value is set to BMS, and the value of the table end flag is stored in EOT.

First, in one memory area indicated by BMA and BMS, a memory address corresponding to the first byte of each memory card is obtained as follows. That is, for a memory card with a number Csml smaller than the number BCS of the memory card including the first byte in the memory area,
BA (Csml) = U × (N + Csml−BCS) × 512−BOS + BMA
For memory cards that include the first byte,
BA (BCS) = BMA
For a memory card with a number Cbig greater than the number BCS of the memory card including the first byte, BA (Cbig) = U × (Cbig−BCS) × 512−BOS + BMA
And

  For example, in the example of FIG. 11, when a numerical value is substituted for the first memory area descriptor 402, the result is as follows.

BA0 = 4 × (4 + 0-1) × 512-1024 + 0 = 5120
BA1 = 0
BA2 = 4 × (2-1) × 512-1024 + 0 = 1024
BA3 = 4 × (3-1) × 512-1024 + 0 = 3072
These represent the top addresses 1400 (hexadecimal), 0000, 0400 (hexadecimal), and 0C00 (hexadecimal) of the sectors 701, 702, 703, and 704 in FIG.

  Next, the size α from the striping boundary of the SD memory with the card number 0 (corresponding to the top of the sector 804 in the first memory area in the example of FIG. 11) to the byte corresponding to the last byte in the memory area is Seek like.

α = U × BCS × 512 + BOS + BMS
Then, the SD memory card number BCE including the byte next to the last byte in the memory area and the offset BOE of the byte are obtained by the following formula.

BCE = (α / (U × 512))% N
BOE = α% (U × 512)
The number of bytes in the memory area of each memory card is
β = (α / (U × N × 512)) × (U × 512)
Against
For memory cards with numbers less than CS, subtract Ux512,
Subtract BOS for memory cards with the same number as CS,
And,
For memory cards with numbers smaller than BCE, add Ux512,
The memory card having the same number as the BCE is obtained by adding BOE.

In the example of the memory area indicated by the first descriptor 402 in FIG.
α = 4 × 1 × 512 + 1024 + 8192 = 11264
BCE = (11264 / (4 × 512))% 4 = 1
BOE = 11264% (4 × 512) = 1024
β = (11264 / (4 × 4 × 512)) × (4 × 512) = 2048
BS0 = 2048-4 × 512 + 4 × 512 = 2048
BS1 = 2048−1024 + 1024 = 2048
BS2 = 2048
BS3 = 2048
Is required.

  As described above, when the top memory addresses BA0, BA1, BA2, BA3 and transfer sizes BS0, BS1, BS2, BS3 for each card are obtained for one memory area, the counter is updated in the table counter update 904 as follows. Update and return to transfer start determination 902.

DTA = address of next descriptor BCS = BCE
BOS = BOE
When returning to the transfer start determination 902 as described above, since all of BS0, BS1, BS2, and BS3 are not 0, the process proceeds to the data transfer end determination 905.

  In the all data transfer end determination 905, when the total data transfer number counters TZ0, TZ1, TZ2, and TZ3 for each card are all 0, it is determined that all data transfer is completed, and the cyclic DMA transfer processing 605 is ended. To do. If not, the process proceeds to the intra-memory area transfer end determination 906. Naturally, in the first process, since the total data transfer number counter is not all zero, the process proceeds to the intra-area transfer end determination 906.

  In the intra-area transfer end determination 906, when the transfer number counter TS (TC) in the memory area of the current transfer target card number TC is 0, it is determined that the transfer in the memory area has ended, and the next transfer Proceed to descriptor determination 907. Otherwise, the process proceeds to the data transfer process 909. In the first process, since the transfer number counter TS (TC) is initialized to 0, the process proceeds to the next descriptor determination 907.

  In the next descriptor determination 907, it is determined whether or not the next descriptor is stored in the memory area descriptor buffer 130 for the current transfer target card number TC. That is, when the transfer size counter BS (TC) is 0, it is determined that the next descriptor is not stored, and the process proceeds to the transfer card number update 910. Otherwise, go to descriptor load 908.

  In the descriptor load 908, the descriptors BA (TC) and BS (TC) of the current transfer target card number TC are read from the memory area descriptor buffer 130, the transfer destination address counter TA (TC), and the intra-area transfer number counter TS (TC) ) Is set as follows.

TA (TC) = BA (TC)
TS (TC) = BS (TC)
Further, BS (TC) is set to 0 to invalidate this register value, and the process proceeds to data transfer processing 909.

  In the data transfer process 909, first, the continuous transfer data number TSbst in one DMA transfer is determined as follows.

TSbst = min (TZ (TC), TS (TC), (U × 512-TO (TC)), 128)
Here, min () represents the minimum value. That is, TZ (TC) is the total number of remaining data of the card number TC, TS (TC) is the number of remaining data of the card number TC in the same buffer memory area, and (U × 512-TO (TC)) is the same buffer. The number of remaining data up to the address discontinuity point in the memory area, 128 represents the maximum continuous transfer number of one SD memory card, and the minimum value of these is the transfer data number.

  Next, the transfer control circuit 128 controls the switching circuit 125 to connect the data FIFO data corresponding to the card number TC to the card bus control circuit 116, and to the card bus control circuit 116 through the switching circuit 125. A bus master DMA transfer command having an address of TA (TC) and a transfer data number of TSbst is issued. Receiving this, the card bus control circuit 116 transfers TSbst byte data from the address TA (TC) of the main memory 108 to the data FIFO selected by the switching control circuit 125 according to the card bus protocol.

  When the DMA transfer is completed, the transfer control circuit 128 updates the counter for controlling the DMA transfer in the transfer counter update 910 as described below.

TZ (TC) = TZ (TC) -TSbst
TA (TC) = TA (TC) + TSbst
TS (TC) = TS (TC) -TSbst
further,
TO (TC) + TSbst ≧ U × 512
When TA (TC) = TA (TC) + (N−1) × U × 512
TO (TC) = 0
age,
TO (TC) + TSbst <U × 512
When TO (TC) = TO (TC) + TSbst
age,
TC = TC + 1
Then, the process returns to the transfer start determination 902.

  As described above, when all data transfer in the cyclic DMA transfer process 605 is completed (when all data transfer end determination 905 determines that TZ0, TZ1, TZ2, and TZ3 are all 0), the transfer control circuit 128 ends the data transfer. Proceeding to notification 606, the command control circuit 127 is notified of the end of all data transfers. The command control circuit 127 that has received the data transfer end notification proceeds to the command end notification 606 and notifies the host device 102 of the end of the command processing by the interrupt signal 132.

  FIG. 13 shows the data transfer order in the RAID drive 101 when data is read from the RAID drive 101 to the host 102 by the operation described above. As shown in FIG. 13, in the SD memory cards 110, 111, 112, and 113, data is read simultaneously and in parallel. On the card bus 103, data of four SD memory cards is cycled every 128 bytes. While being transferred.

  FIG. 14 shows the data transfer order when writing data from the host 102 to the RAID drive 101 in the RAID drive 101. As shown in FIG. 14, data transferred while circulating data corresponding to four SD memory cards every 128 bytes in the card bus 103 is simultaneously paralleled in the SD memory cards 110, 111, 112, and 113. Written in.

  As described above, the data corresponding to the four SD memory cards is divided into 128 bytes and continuously transferred. Therefore, it is sufficient that the FIFOs 117, 118, 119, and 120 corresponding to each card have 128 bytes. Therefore, according to the present invention, parallel transfer in units of blocks in a plurality of low-speed memory cards can be realized using a buffer memory smaller than the block size.

  The storage device of the present invention configured as described above can be used as a removable medium in a video camera or the like, a medium in a PC-based nonlinear editing machine, or a PCI-RAID board using a large number of hard disks.

The block diagram which shows the basic composition of the memory | storage device of this invention The block diagram which shows the mapping of the sector number in the memory | storage device of this invention Configuration diagram of the host side buffer of the host device Timing chart showing an outline of data transfer of the storage device of the present invention The block diagram which shows the structure of the memory | storage device of this invention The flowchart which shows the operation | movement procedure of the memory | storage device and host apparatus of this invention The block diagram which shows the example of the memory area descriptor in this invention The block diagram which shows the data structure of the command in this invention The flowchart which shows the command processing operation of the memory | storage device of this invention The block diagram which shows the transfer parameter for every card | curd in this invention Configuration diagram showing mapping of memory area and card in the present invention Flowchart showing the cyclic DMA processing operation of the storage device of the present invention Timing chart showing the order of data read and transfer in the storage device of the present invention FIG. 4 is a timing chart showing the data write / transfer order of the storage device of the present invention.

Explanation of symbols

101 RAID drive 102 Host device 108 Main memory 110, 111, 112, 113 SD memory card 117, 118, 119, 120 Data FIFO
121, 122, 123, 124 Memory card control circuit 125 Switching circuit 128 Transfer control circuit 129 Table counter 130 Memory area descriptor buffer 131 Transfer counter 133 Host interface 134 Control means

Claims (2)

A storage device that performs striping recording and reproduction of data input / output with a host device via a host interface in a plurality of storage media in a predetermined striping unit,
A plurality of transfer buffer memories for temporarily storing data input / output to / from each of the plurality of storage media;
A plurality of storage medium control means for controlling data transfer between the plurality of corresponding storage media and the plurality of transfer buffer memories;
Switching means for switching a data transfer path between the host interface and the plurality of transfer buffer memories;
Data is transferred between the host interface and the plurality of transfer buffer memories while switching the plurality of transfer buffer memories in units of blocks smaller than the striping unit, and the plurality of transfer buffer memories in succession in striping units A storage device comprising: a control unit that controls the switching unit and the plurality of storage medium control units so as to transfer data to and from the plurality of storage units. The host device stores a head address of an untransferred area corresponding to each of the plurality of storage media in a storage area of the host device;
The control means has a transfer counter that is updated when switching data transfer between the storage area and the transfer buffer memory,
2. When the transfer counter is updated, it is determined whether or not there is a boundary between striping units of the storage area corresponding to the storage medium, and the transfer counter is corrected to the start address of the next striping unit corresponding to the storage medium. The recording device described.

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