JP2005332582A - Semiconductor integrated circuit device with copy preventing function - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device with copy preventing function in which data of a special function for preventing unauthorized copy is held surely by supplying a power source within some fixed time even if a state of interruption of the power source is caused suddenly, unauthorized copy by surreptitious use can be made impossible substantially based on the held data. <P>SOLUTION: This device is provided with a memory means 604 storing data used by a user, input means 601, 602 performing various logical processing for at least one input information inputted from the outside and performing access for the memory means, an output means 605 performing various logical processing for the data when the data is outputted from the memory means, and a data holding means 603 which receives supply of power source voltage and storing temporarily at least one state out of a state of the input information, a logical state of the input means, a logical state of the output means, and a state of data obtained from the output means, the data holding means is constituted so that when the power source voltage is interrupted, state data held at the point of time is continued to be held for a prescribed period. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a read only memory (ROM) having a copy protection function.

  Among ROMs, a mask ROM that fixes ROM data with a mask in a wafer process of a semiconductor integrated circuit is used in large quantities in game machines, OA equipments, etc., but ROM data is hardly protected and is stolen. There was a reality that illegal copying was done.

  Therefore, it is necessary to build a system for preventing unauthorized copying in the mask ROM device. In this case, of course, it is necessary to increase the capability of preventing unauthorized copying, but on the other hand, the device is considered not to be expensive, and preferably, it can be manufactured in a normal process. Is required.

  Conventionally, as techniques relating to ROM copy protection, those disclosed in, for example, JP-A-63-225839, JP-A-61-265649, JP-A-1-173244 and the like are known. .

  First, in the technique disclosed in Japanese Patent Laid-Open No. 63-225839, a copy prevention function is realized by holding a specific key pattern in the circuit and determining whether it matches or does not match a newly input key pattern. (Refer to page 1, left column, line 18 to right column, line 3).

  In the technique disclosed in Japanese Patent Application Laid-Open No. 61-265649, a copy prevention function is realized by using inexpensive means such as a ROM writer (first page, left column, line 15 to right column). (See line 6).

  In the technique disclosed in Japanese Patent Application Laid-Open No. 1-173244, in a system using a ROM code, once the ROM code is broken, it is easily copied from the next time (the first column, right column, line 8 to The copy protection function is realized by comparing the access order between specific addresses with a preset software access order (see the first page, right column, lines 19 to 11). (See page 6, upper left column, line 6).

  The technique disclosed in Japanese Patent Laid-Open No. 63-225839 described above requires a special mode (random pattern) to be newly input when used (the lower right column, page 2, lines 8 to 11). reference). Therefore, there is a problem that the circuit becomes complicated and the cost becomes high. In addition, since the memory unit that performs the comparison determination is limited to the nonvolatile memory (see the lower right column, line 19 to line 20 on the second page), there is a disadvantage that inconvenience is imposed on circuit design. In addition, since it is necessary to set another area for storing the key pattern, if the area is electrically called, for example, in a chip state, the key pattern can be easily obtained (that is, there is a risk of being copied). There is a problem. Also, if the key pattern consists of a combination of simple numbers, taking into account the recent progress in hardware performance and its widespread use, it takes a lot of time to try a brute force combination with a device. Therefore, there is a possibility that the key pattern can be decrypted relatively easily. Furthermore, once the ROM whose key pattern has been decrypted is obtained, it will be in a scrambled state, and thereafter, the copy protection function of the ROM will be lost, and the actual copy protection effect is only at the initial stage. There is also the problem of staying.

  In the technique disclosed in Japanese Patent Application Laid-Open No. 61-265649, data protection is performed by holding the CE terminal in the timer circuit (page 2, upper right column, line 17 to lower left column, line 4). In the lower right column of the same page, see lines 12 to 19), there is a problem that the operation address of the timer circuit is easily found, and thereby the prevention function is released in a relatively short time. That is, with this technique, a complete copy protection function in its original sense cannot be realized.

  Further, in the technique disclosed in Japanese Patent Laid-Open No. 1-173244, the access order between specific addresses is limited to the scale of the order defined in advance in software, so it is copied when handling a large amount of data. The prevention effect may be lost. In addition, since the access order is defined, the development of the software is restricted, the work is troublesome, and the software is relatively complicated. In addition, in order to read the software normally, the decoding information should always exist if the routine that operates the software is decoded. Therefore, the decoding information must be carefully read. There is a risk of copying. Furthermore, there is a disadvantage that a special test according to the access order needs to be performed because the copy prevention function operates in the simple order call test due to the provision of the access order. .

  As described above, in the conventional techniques, the basic idea of copy protection is taught, but in any technique, the ROM copy prevention function is realized by software or hardware. Moreover, none of the functions can be easily changed, and there is a possibility that a person who works illegally by stealing may be stolen relatively easily even if it takes time for temporary analysis.

  In other words, since the copy protection function has not been realized from both software and hardware sides, the copy data cannot be protected from theft of ROM data, and is left open.

  In other words, when a copy protection function is installed in a semiconductor integrated circuit, the software is not restricted as much as possible, and the semiconductor integrated circuit itself realizes effective means while suppressing the increase of special circuits and the addition of processes. There was a need.

Summarizing the requirements for the above-mentioned problems of the prior art are as follows.
Request 1) …… We want to eliminate restrictions on software and make it possible to specify the trap area for the copy protection function over a wide range after software development within the original flow of software.

  Requirement 2) …… I want to make the copy protection function not to be activated during the shipping test of the manufacturer that produces the semiconductor integrated circuit or the acceptance test of the ordering side, or to make it easy to cancel even if activated (but this Contradicts the original purpose of the copy protection function).

  Request 3) …… When hardware is analyzed by direct change of internal wiring of semiconductor integrated circuit, electrical signal analysis, etc., we want to reduce the possibility of copying based on the analysis. In other words, with the current technical analysis method that enables the operation of the internal wiring of the chip, the copy protection function part in the integrated circuit is easily invalidated, and thus it is desired to eliminate the risk as much as possible.

  An object of the present invention is to securely hold special function data for preventing unauthorized copying by turning on the power within a certain time even if the power is unexpectedly turned off. An object of the present invention is to provide a semiconductor integrated circuit device with a copy protection function capable of making illegal copying by plagiarism substantially impossible.

  According to the present invention, the storage means for storing data used by the user and the input for performing various logical processes on at least one input information input from the outside and accessing the storage means Means, output means for performing various logical processing on the data when outputting the data from the storage means, supply of power supply voltage, the state of the input information, the logic of the input means A data holding means for temporarily storing at least one of a state, a logic state of the output means, and a data state obtained from the output means. A semiconductor integrated circuit device with a copy protection function is provided, in which the state data held at that time is kept held for a predetermined period of time.

  According to the present invention, by turning on the power within a certain time even when the power is unexpectedly turned off, the data of the special function for preventing unauthorized copying is securely retained, and the retained data is stored in the retained data. Based on this, it is possible to provide a semiconductor integrated circuit device with a copy protection function capable of making illegal copying by theft substantially impossible.

  According to the first embodiment of the present invention, as shown in the principle configuration diagram of FIG. 1, there are various kinds of storage means 1 for storing data used by a user and at least one input information input from the outside. An input unit 2 for performing the logical processing of the above and accessing the storage unit, and an output unit 3 for performing various logical processes on the data when the data is output from the storage unit , Comparing at least one of the state of the input information, the state of the logic of the input unit, the state of the logic of the output unit and the state of the data obtained from the output unit with specific determination information, and When the determination means 4 for instructing and the at least one state is in a specific state based on the instruction result of the determination means, at least the data stored in the storage means is correct with respect to the output means. Processing and control means 5 for a semiconductor integrated circuit device with copy protection, characterized in that it comprises a is provided to prevent the output to.

  In a preferred embodiment, the semiconductor integrated circuit device according to the present invention has a form of a mask ROM (read-only memory in which data used by a user is fixed to a storage means by a wafer process of the semiconductor integrated circuit). ing.

  In this case, the functions realized by the determination means and the control means can be changed by means equivalent to the processing for fixing data in the storage means in the wafer process of the semiconductor integrated circuit, for example, ion implantation processing, wiring processing, etc. May be formed.

  The determination unit 4 may further include a holding unit that holds a result of determining that the at least one state is in the specific state.

  Further, according to the second embodiment of the present invention, as shown in the principle configuration diagram of FIG. 2, the storage means 1 for storing data used by the user and at least one input information input from the outside. Input means 2 for performing various logical processes and accessing the storage means, and output means for performing various logical processes on the data when outputting the data from the storage means 3 and information on a plurality of specific address areas to which addresses associated with the data of the storage unit respectively belong, and to which area of the plurality of specific address areas the input information has accessed Detection / storage means 6 for detecting and storing the access state, and data output from the storage means to at least the output means by judging the condition of the stored access state And data manipulation means 7 for performing control so as to manipulate the contents, copy protection with semiconductor integrated circuit device characterized by comprising is provided a.

  In a preferred embodiment of the present invention, the detection / storage means detects and stores the number of times that the input information has successively accessed a specific area among the plurality of specific address areas. In this case, the data operation means performs control so as to operate the contents of the output data based on the condition determination of the stored number of times.

  In this case, the data operation means controls the contents of the output data according to whether the number of accesses to the specific area stored in the detection / storage means is an even number or an odd number. Also good.

  According to the configuration of the first aspect of the present invention, at least one state (input information state, input unit logic state, output unit logic state, or data obtained from the output unit is determined by the determination unit 4. When it is determined that the state is in a specific state, the control means 5 performs processing so as to prevent at least the output means 3 from normally outputting the data stored in the storage means 1 I do. As a result, it is possible to make it impossible to illegally copy by theft.

  Further, when the semiconductor integrated circuit device according to the present invention has the form of a mask ROM, means equivalent to the process of fixing data in the storage means in the wafer process of the semiconductor integrated circuit (for example, ion implantation process, By using a wiring process or the like, the functions (that is, copy prevention functions) realized by the determination unit 4 and the control unit 5 can be changed simultaneously from both the software and hardware as necessary. This is extremely effective for theft and makes analysis difficult, and is extremely effective for those who try to make illegal copies by theft.

  In addition, in the case where a means for holding a result (for example, information indicating whether or not illegal copying is attempted) that is determined by the determining unit 4 to determine that at least one state is in a specific state, Thus, it is possible to make it difficult for a person who intends to perform illegal copying and to spend time required for the analysis. As a result, it becomes difficult or substantially impossible to perform illegal copying by theft.

  According to the configuration of the second aspect of the present invention, the detection / storage unit 6 detects which of the plurality of specific address areas the input information has accessed, and stores the access state. Is done. Then, by determining the condition of the stored access state, the data operation unit 7 controls at least the output unit 3 to operate the contents of the data output from the storage unit 1. As a result, illegal copying by theft is virtually impossible.

  The details of other structural features and operations of the present invention will be described using the embodiments described below with reference to the accompanying drawings.

  FIG. 3 schematically shows the configuration of a ROM device with copy protection function according to the first embodiment of the present invention.

  In the figure, reference numeral 10 denotes a memory cell array in which ROM cells are arranged at intersections of a plurality of word lines and a plurality of bit lines (both not shown), and 11 denotes input information fetching based on an external control signal CONT. Timing signal generating circuit for generating various timing signals for controlling timing and output data extraction timing, 12 is an address buffer for buffering a plurality of bits of address signals A0 to An, and 13 is an address signal among A0 to An A row decoder 14 for selecting one of a plurality of word lines in the memory cell array 10 based on a row address signal of higher order multiple bits, and a memory cell array 10 based on a column address signal of lower order bits of address signals A0 to An. A column decoder for selecting one of a plurality of bit lines 5 is a column gate connected to the data line corresponding to the selected bit line, 16 denotes a sense amplifier for sensing and amplifying data on the data line, 17 denotes an output buffer for outputting the data sense amplifier to the outside.

  The above configuration is a circuit element used in a typical ROM. In addition, the circuit elements 20 to 24 described below are parts that constitute the feature of the present invention.

  20 is a specific address storage unit in which a specific address as determination information is stored in advance, 21 is a comparison of the input address signals A0 to An with the specific address, and a result based on the match / mismatch is flagged as a determination result F1. A comparison / determination unit that outputs in the form of information (flag ON / flag OFF), 22 is a flag circuit that holds the determination result F1 of the comparison / determination unit 21, and 23 is information held by the flag circuit 22 (control flag output) A processing unit for appropriately processing or changing the state of input information or the state of logic for the input means (each circuit element of 11 to 14) based on the signal F2), 24 is based on the control flag output signal F2 The processing unit for appropriately processing or changing the state of output data or the state of logic for the output means (each circuit element of 15 to 17).

  FIG. 4 shows an example of the configuration of the comparison / determination unit 21 and the specific address storage unit 20, and FIG. 5 shows an example of usage of the circuit.

  First, the circuit shown in FIG. 4 includes two n-channel transistors connected in series between a high-potential power line Vcc (for example, 5 V) and a low-potential power line Vss (for example, 0 V) and responding to the potential of Vss, respectively. 31 and 32, two n-channel transistors 33 and 34 connected in series between power supply lines Vcc and Vss and responding to the potential of Vss, respectively, and responding to an external address signal (1 bit) Ai Inverter 35, AND gate 36 responsive to drain voltage of transistor 32 (source voltage of transistor 31) and address signal Ai, AND gate responsive to drain voltage of transistor 34 (source voltage of transistor 33) and output of inverter 35 37 and responds to the output of each AND gate 36 and 37 And a R gate 38.

  Note that the circuit shown in FIG. 4 shows a configuration corresponding to any one bit Ai of the address signals A0 to An, and in actuality, it is necessary to have a circuit corresponding to the number of address bits, that is, (n + 1). . In the illustrated configuration, the transistors 31 to 34 correspond to the specific address storage unit 20, and the other circuit elements 35 to 38 correspond to the comparison / determination unit 21.

  In such a configuration, the specific address can be determined by setting each of the transistors 31 to 34 to the depletion type operation mode or to the normal enhancement type operation mode. Note that the depletion mode can be realized by implanting ion atoms such as arsenic (As) and phosphorus (P) into the channel region of the n-channel transistor.

FIG. 5A shows an example of setting the operation mode of each of the transistors 31 to 34.
As shown in the figure, when the transistors 32 and 33 are set to the depletion type and the transistors 31 and 34 are set to the enhancement type, the state 1) can be realized. In the state of 1), the AND gate 37 is effective when the input address Ai is “0”, so that the power supply voltage Vcc (that is, “1”) is passed through the AND gate 37 and the OR gate 38 through the depletion type transistor 33. Is output. That is, when the input address Ai is “0”, a coincidence with the specific address “1” is detected (a flag ON determination result F1 is output).

  Further, when the transistors 31 and 34 are set to the depletion type and the transistors 32 and 33 are set to the enhancement type, the state 2) can be realized. In the state of 2), when the input address Ai is “1”, the AND gate 36 is valid, and the power supply voltage Vcc (that is, “1”) is output through the AND gate 36 and the OR gate 38 through the depletion type transistor 31. Is done. That is, when the input address Ai is “1”, the coincidence with the specific address “1” is detected (the flag ON determination result F1 is output).

  Further, when the transistors 31 and 33 are set to the depletion type and the transistors 32 and 34 are set to the enhancement type, the state of 3) can be realized. In the state of 3), when the input address Ai is “0” or “1”, the AND gate 37 or 36 is valid, and the power supply voltage Vcc (that is, “1”) is supplied to the AND gate 37 through the depletion type transistor 33 or 31. Or 36 and the OR gate 38. That is, when the input address Ai is “0” or “1”, a match with the specific address “1” is detected (the flag ON determination result F1 is output).

FIG. 5B shows an example of setting a specific address.
For example, when an address of address “0100” is set to address 04, 1), 2), 1) and 1 for each circuit (see FIG. 4) corresponding to 4-bit addresses A3, A2, A1 and A0, respectively. The transistors 31 to 34 may be set to a depletion type or an enhancement type so as to be in the state of Similarly, when the address of address “1011” is set, the states of 2), 1), 2) and 2) are set for the circuits corresponding to the 4-bit addresses A3, A2, A1 and A0, respectively. Each transistor 31 to 34 may be set to a depletion type or an enhancement type.

  Further, when two addresses of address 04 “0100” and address 05 “0101” are set, 1) for each circuit corresponding to the 4-bit addresses A3, A2, A1 and A0 (see FIG. 4). , 2), 1) and 3), the transistors 31 to 34 may be set to a depletion type or an enhancement type. That is, in this case, two addresses can be collectively set as one address area.

  In the circuit shown in FIG. 4, the setting of the specific address (or the specific address region) is realized by setting the transistor to the depletion type, but instead of the transistor to be set to the depletion type, aluminum or the like is used. Metal wiring or polysilicon wiring may be used. The circuit of FIG. 4 is configured using transistor elements and gate elements, but can be configured using fuse elements, ROM, RAM, and the like, for example. For example, when the transistor portion is formed of a fuse element, a specific address is set simultaneously at the probing test (PT) stage.

FIG. 6 shows a configuration example of the flag circuit 22.
In the figure, reference numeral 41 denotes a flip-flop as a bistable circuit having two input / output nodes A and B, which are connected in series between the internal power supply line Vcc ′ and the low potential power supply line Vss, and each input / output node A P-channel transistor QP1 and n-channel transistor QN1 having a CMOS structure responsive to the potential of the same, and p-channel transistors having a CMOS structure similarly connected in series between internal power supply lines Vcc ′ and Vss and responsive to the potential of input / output node B, respectively. A channel transistor QP2 and an n-channel transistor QN2 are provided. Each output terminal of one of the CMOS transistors QP1 and QN1 is connected to the input / output node B, and each output terminal of the other CMOS transistors QP2 and QN2 is connected to the input / output node A.

  Further, 42 is a diode that transmits the determination result F1 of the comparison / determination unit to the node A of the flip-flop 41, 43 is a capacitor connected between the output terminal of the diode 42 and the power supply line Vss, and 44 is a node of the flip-flop 41. A diode 45 for transmitting a signal appearing at B to the processing units 23 and 24 (see FIG. 2) as a control flag output signal F2, and 45 is a power supply voltage Vcc supplied to the ROM device of this embodiment. A diode 46 is connected to the line Vcc ′, and a capacitor is connected between the output terminal of the diode 45 and the power supply line Vss.

  Each of the capacitors 43 and 46 has a form of a MOS capacitor formed by a wafer process of a semiconductor integrated circuit. Since such a process can be realized using means generally known to those skilled in the art, a description thereof will be omitted.

  According to the circuit configuration illustrated in FIG. 6, the determination result F <b> 1 of the comparison / determination unit is held in the node A of the flip-flop 41 via the diode 42. A signal obtained by logically inverting the information held in the node A is output from the other node B through the diode 44 as the control flag output signal F2.

  In addition, since the capacitor 43 is connected to only one node A of the flip-flop 41, the state of the flip-flop 41 (that is, the logical state of the node A and the node B) is uniquely and stably determined when the power is turned on. Can do. This makes it possible to read data normally when the power is turned on in normal operation.

  Further, since the capacitor 46 is connected to the internal power supply line Vcc ′, even if the power supply voltage Vcc is cut once, it is latched in the flip-flop 41 by a charge of the capacitor 46 for a predetermined period after the power is turned off. Data can be retained.

  In the circuit configuration shown in FIG. 6, a bistable circuit (flip-flop 41) is used as means for holding the determination result F1 of the comparison / determination unit, but such holding means is not limited to this. For example, an irreversible element such as a fuse element that cannot return to the original state, or a reversible element such as EPROM or EEPROM that can be returned to the original state by any means may be used.

  Further, although the diodes 42, 44 and 45 are used in the circuit configuration of FIG. 6, instead of such diodes, elements having an equivalent rectifying function, for example, diode-connected normal MOS transistors may be used.

FIG. 7 shows a configuration example of the processing unit 24 for output means.
The illustrated configuration shows the configuration of a CR type oscillation circuit. A resistor 50 and a NAND in which a signal is input to one input via the resistor 50 and a control flag output signal F2 is input to the other input. A gate 51, an inverter 52 responsive to the output of the NAND gate, a capacitor 53 (capacitance value Ct) that feeds back the output of the inverter to the resistor 50, an inverter 54 responsive to the output of the inverter 52, And a resistor 55 (with a resistance value Rt) that feeds back the output of the inverter to the resistor 50. The frequency of the oscillation signal obtained from the output terminal OUT of the inverter 54 is determined by the value of Ct · Rt.

  By incorporating the oscillation circuit having such a configuration in the processing unit 24, when the determination result F1 (flag ON signal) of the comparison / determination unit 21 is input to the present circuit through the flag circuit 22 (flag ON signal F2). Oscillation operation is started and a large noise is generated in the power supply system inside the integrated circuit. Thereby, the processing unit 24 can set the reading of the ROM data stored in the memory cell array 10 to an unstable state for the output units 15 to 17. That is, it is substantially impossible to perform illegal copying by theft.

  FIG. 8 schematically shows the configuration of a ROM device with a copy protection function according to the second embodiment of the present invention.

  The configuration shown in the figure differs from the configuration of the first embodiment (see FIG. 3) in that 1) a plurality of specific addresses to which addresses associated with data in the memory cell array 10 belong instead of the specific address storage unit 20 respectively. A specific address area storage unit 20a for storing address area information, 2) a comparison / determination unit 21a having the same function instead of the comparison / determination unit 21, and 3) a processing unit In this case, an input operation circuit 23a and an output operation circuit 24a having the same functions are provided instead of 23 and 24, respectively.

  The comparison / determination unit 21a detects which specific address area has been accessed based on the comparison between the input information (address signals A0 to An) and information of a plurality of specific address areas, and the access is made. Condition determination of the state (number of accesses, access order, etc.) is performed. The result of this condition determination is output in the form of flag information (flag ON / flag OFF) as the determination result F1. The output operation circuit 24a according to the present embodiment is connected between the sense amplifier 16 and the output buffer 17, and is based on the information (control flag output signal F2) held by the flag circuit 22 and the address signals A0 to An. To manipulate the contents of the output data. That is, the output operation circuit 24a processes the logic so that it is different from the data that should be output originally, or destroys the output data itself as will be described later.

Hereinafter, specific execution examples of copy prevention will be described with reference to FIGS.
(1) As a means to cope with the above-mentioned prior art requirement 1), software usually stores data such as a main program part and subprogram part, or a program part and data part, or an independent block of data. Can be divided into address areas. In this case, it is possible to divide the interior of each address area into finer areas, and these fine address areas need not be continuous.

  Therefore, in this embodiment, as shown as an example in FIG. 9, the address to which each data belongs is divided into a plurality of specific address areas (three in the example shown, A group, B group, and C group) for comparison and determination. The unit 21a detects which specific address area the input information (address signals A0 to An) has passed (that is, whether access has been performed), sets the state in which the detection is stored as “flag ON”, and sets the input address Is not an address belonging to the specific address area, or the state in which the storage is released is set as “flag OFF”. The flag ON / OFF information is held in the flag circuit 22, and the output operation circuit 24a functions based on the information.

  In the illustrated example, the specific address area of the A group has a function of “flag ON” and the specific address area of the B group has a function of “flag OFF”. Further, the specific address area of the C group is not provided with a flag ON / OFF function. It is assumed that there is no common address area for the A group, the B group, and the C group. In addition, the C group may be all the regions other than the A group and the B group, or may be set as a part thereof.

  When the input address passes through a certain address area, if the address belongs to that area, the flag is turned on. However, as long as the same area is continuously accessed (continuous call in FIG. 9), “ Even in the “flag ON” state, the copy prevention function is not activated (that is, the output operation circuit 24a is not activated).

  When called from this area to another area, the contents of the call data (that is, output data) are copied unless the address of the area having the function of “flag OFF” (group B in the example of FIG. 9) is passed. Some operation for prevention will be received. In this case, for the call between the specific address areas, the output operation circuit 24a is operated only in the case of a call method that is not defined.

  Further, the address area is set so that there is no address call from the A group to the C group in a normal use situation. Further, in FIG. 9, when the power is turned on or the initial state of the ROM device is set to the flag ON state, the calling may be performed from the group B.

FIG. 10 illustrates a first execution example of copy protection according to the second embodiment.
In the figure, the parts indicated by 1), 2) and 3) indicate that the address call is skipped from 1) to 1), from 2) to 2), and from 3) to 3). Accordingly, in the illustrated example, the actual calling order is the order of addresses 00, 01 to 05, 12 to 15, 06 to 11. The portion indicated by ● represents the flag ON state.

  Thus, according to the execution example 1, in the actual call, even if the flag is turned on at addresses 04 and 05, it jumps to the address 12, and since this address is the B group, the flag is turned off. Therefore, the called data does not receive any operation (that is, the data is output normally).

  In the case of simple copy, the called data is subjected to some operation until the flag is turned on at addresses 04 and 05 and the flag is turned off at group B from address 06 to address 12 (that is, copy prevention is performed). Data manipulation is performed).

  FIG. 11 shows a configuration example of the specific address area detection circuit according to the first execution example described above.

  In the example shown in the figure, a configuration in the case of assuming a 16-bit ROM with four addresses A0 to A3 is shown. In the figure, reference numerals 60 to 63 denote coincidence detection circuits each having the same configuration as that shown in FIG. 4, and outputs from the coincidence detection circuits are input to an AND gate 64. The output of the AND gate 64 exhibits “1” level (flag ON) when the input addresses A3 to A0 belong to, for example, the address area of the A group, and do not belong to the address area of the A group (that is, other addresses). In the case of an address belonging to an area, a “0” level (flag OFF) is exhibited.

FIG. 12 illustrates a second execution example of copy protection according to the second embodiment.
If it passes through a specific address area, if it is an address belonging to that area, the flag is turned on as described above. At this time, the number of times the area has been continuously called (that is, the number of accesses) is stored. Try to keep it. If the stored number is other than the prescribed number, the called data will be subjected to some operation if the flag ON state is valid regardless of the inside or outside of the area. In this case, it is arbitrary whether or not to set an area in which the flag is turned off.

  Since storing the number of accesses may be constrained by software, it may be determined whether the number of continuous calls is an even number or an odd number. In this case, the flag is turned on when it jumps out of the area, and the called data is subjected to some operation. Similarly, it is optional whether or not to set an area in which the flag is turned off.

  In the case of the second execution example shown in FIG. 12, if it is set that the group A is called three times, in the case of simple copy, the flag is turned on when the address 06 is called, and thereafter the address 11 belonging to the group A passes. Later, if the count is not initialized, it will not return to normal. If the even number of calls is set as an abnormal state, it returns to normal when it passes through address 11.

  Note that the number of times can be counted using a count counter or the like using the output ("1" or "0") of the AND gate 64 in the circuit shown in FIG. Also, the determination process from the even number or the odd number can be realized by using a simple flip-flop or the like.

  FIGS. 13, 14, and 15 illustrate a third execution example, a fourth execution example, and a fifth execution example of copy protection according to the second embodiment, respectively. In each figure, (a) shows a configuration example of the output operation circuit 24a, and (b) shows the relationship between the input and output signal values.

  In the example of FIG. 13, the OR gate 70 is used to destroy the data of the output value by a combination of the flag signal (F2) and the normal output signal.

  In the example of FIG. 14, the output value data is destroyed by the combination of the flag signal (F2), the address signal (A0), and the normal output signal using the inverter 80 and the two n-channel transistors 81 and 82. I am doing so.

  In the example of FIG. 15, the output value data is destroyed by the combination of the flag signal (F2) and the two normal output signals 1 and 2 using the inverter 90 and the four n-channel transistors 91 to 94. I have to. That is, in this example, when the flag is ON, the normal output signal 1 and the normal output signal 2 are interchanged and output.

(2) As a means to deal with the above-mentioned request 2) with respect to the prior art, normal semiconductor integrated circuits are shipped from manufacturers after shipping tests are conducted to confirm that they are operating normally. . In addition, the delivered ordering side may check the operation with a simple test, and further perform a board mounting test and the like.

  In these cases, the operation check of the semiconductor integrated circuit itself is performed with a simple call pattern, and it is difficult to generate an actual operation pattern corresponding to a real machine in a shipment test or an acceptance test. Therefore, even if a semiconductor integrated circuit equipped with a copy countermeasure function is manufactured, it is difficult to guarantee test costs and reliability, and it is generally difficult to spread.

  On the other hand, if the method according to the present embodiment is used, if the location of the specific address area where the flag is turned off is known in part, if the address area and the area to be called are called alternately, for example, normal testing of all addresses is possible. It becomes.

  Further, the group B and the address to be called may be called alternately. If an even number of calls are set, the copy countermeasure function will not operate if the same address is called continuously an even number of times.

  According to such a method, since it is not a specific bit, the calling method is not limited and the test time is slightly extended, but there is an advantage that it is not necessary to use a special dedicated test device or the like. In addition, if the area of group B is made small, the illegal copying side will not easily find the area of group B, but the following 3) will be addressed, including countermeasures for it. Describes the means.

(3) As a means to deal with the above-mentioned request 3) with respect to the prior art, with the recent increase in functionality and speed of the device for analyzing a semiconductor integrated circuit, a semiconductor integrated circuit equipped with a copy protection function is relatively simple. It has been analyzed. Even in the case of the present embodiment, a circuit having a function of turning on the flag is analyzed, the circuit wiring on the chip is directly corrected, and as a result, it can be assumed that the flag is always turned off.

  In order to cope with this, in this embodiment, the wiring is multilayered so that processing cannot be performed in the upper wiring layer even if circuit correction is performed.

  As another means, if the software producer understands the operation of the contents of the call data, the data output by the “operation of the contents of the call data” It is conceivable to intentionally convert the initial production data so that the data originally required is obtained.

  Advantages of this method are that the cost of the integrated circuit itself does not increase that much, and that even if the flag circuit is disabled directly from the chip and the data is called, the data is not normal normal data (copy prevention). Can be mentioned.

An execution example of copy protection according to this technique is shown in FIGS.
In the example of FIG. 16, it is assumed that the built-in data is inverted and output when the flag is ON. In addition, during the flag ON operation, the data corresponding to the address belonging to the A group is not affected, and the data corresponding to the address belonging to the B group is preceded by the flag OFF operation.

  In this way, the data intended by the customer who ordered the semiconductor integrated circuit (ROM device) becomes actual call data.

  Similarly, in the example of FIG. 17, it is assumed that the built-in data is inverted and output when the flag is ON. In addition, the flag ON state is canceled by an even number of consecutive calls of addresses belonging to the A group, and data corresponding to addresses belonging to the A group is not affected during the flag ON operation.

  In this manner, the data intended by the customer who ordered the present semiconductor integrated circuit (ROM device) becomes the actual call data in the same manner as in the execution example of FIG.

  FIG. 18 schematically shows the configuration of a ROM device with copy protection function according to a third embodiment of the present invention.

  In the illustrated apparatus 100, input address signals A 0 to An are held in the address buffer 101, and the held address signal is supplied to the address decoder 102 on the one hand and to the encryption storage / coincidence detection circuit 103 on the other hand. Based on the decoding result of the address decoder 102, one of the word lines and bit lines in the memory cell array (ROM) 104 is selected, and the stored contents of the corresponding memory cells are read out. The read data is output as data D0 to Dm via the output circuit 105.

  The cipher memory / coincidence detection circuit 103 outputs a coincidence signal EQ when the output address of the address buffer 101 matches a specific cipher, and the flip-flop circuit (FF) 106 holds this. The output circuit 105 stops data output while the flip-flop circuit 106 holds the data, or outputs data other than the original data from the memory cell array 104. Instead of the output of the output circuit 105, the output of the address decoder 102 may be other than the original output.

  It is assumed that an address that matches the encryption is not used when the apparatus 100 is used in a normal usage pattern. In this way, use other than normal use (for example, illegal use such as plagiarism) can be prohibited.

  Hereinafter, a configuration example of the encryption storage / coincidence detection circuit 103 will be described with reference to FIGS.

  For simplification of description, each configuration example shown in FIGS. 19 to 26 shows a case where the input address signal is 4 bits, that is, A0 to A3. The transistor shown in each figure is a metal / insulator / semiconductor (MIS) type FET. The p-channel type has an outward arrow, and the n-channel type has no arrow.

FIG. 19 shows a first configuration example (103A) of the encryption storage / coincidence detection circuit 103.
In the illustrated encryption memory / coincidence detection circuit 103A, the source and gate of the load pMISFET 110 are connected to the power supply line VCC and the ground line, respectively, and the drain of the load FET 110 is connected to the input terminal of the inverter 111 on the one hand, It is connected to one end of the bit series circuit 112A. In the bit series circuit 112A, four basic circuits 120H, 121L, 122L, and 123H are connected in series, and the other end is connected to a ground line.

  In the basic circuit 120H, an nMISFET 120E and an nMISFET 120D are connected in series, an input terminal and an output terminal of an inverter 120X are connected to the gates of the FET 120E and the FET 120D, respectively, and an address signal A0 is supplied to the gate of the FET 120E. The FET 120E is an enhancement type, and its threshold voltage is between the high level and the low level, and is on when A0 is high and off when A0 is low. On the other hand, the FET 120D is a depletion type, and is turned on regardless of the output level of the inverter 120X. Accordingly, the basic circuit 120H is turned on only when the address signal A0 is at a high level.

  Note that the symbol H or L attached to the reference number of each basic circuit indicates that the signal is turned on when the potential of the control input terminal (that is, the address signal) is high or low.

  The basic circuits 121L, 122L, and 123H are configured in the same manner as the basic circuit 120H, 121X, 122X, and 123X are inverters, 121E, 122E, and 123E are enhancement-type nMISFETs, and 121D, 122D, and 123D are depletion-type nMISFETs. . Address signals A1, A2, and A3 are supplied to control input terminals of the basic circuits 121L, 122L, and 123H, respectively.

  In the above configuration, the binary serial code '1001' is fixedly stored in the bit serial circuit 112A, and the bit serial circuit 112A is turned on only when the address signals A3 to A0 match this encryption, and the inverter 111 The coincidence signal EQ output from is at a high level, and in other cases (that is, when it does not coincide with the encryption), the coincidence signal EQ is at a low level.

  As a memory cell of the memory cell array 104 in FIG. 18, there is a type in which one nMISFET is used and its storage contents are determined depending on whether or not it is made a depletion type by ion implantation. In this case, the encryption storage / coincidence detection circuit 103A of FIG. 19 is used. As a result, the memory cell array 104 and the encryption storage / coincidence detection circuit 103A can be written with data in the same process, which eliminates the need for a special process for the encryption storage / coincidence detection circuit 103A.

  The depletion type nMISFETs 120D, 121D, 122D, and 123D may be formed so as to be turned on regardless of the gate potential level, and the depletion type can be further advanced by increasing the ion implantation amount. The source and the drain may be short-circuited. This also applies to other configuration examples described below.

  Since the encryption memory / coincidence detection circuit 103A according to the first configuration example is configured integrally with the encryption storage unit and the coincidence detection unit, the configuration is simple, the number of circuit elements is small, and the storage capacity of the memory cell array is increased Is the preferred configuration today.

By the way, it is preferable that more ciphers are used for the purpose.
Therefore, as shown in FIG. 20, in the encryption storage / coincidence detection circuit 103B according to the second configuration example, the FETs 120D1 and 120D2 of the basic circuit 120 and the FETs 121D1 and 121D2 of the basic circuit 121 are made depletion type. As a result, the basic circuits 120 and 121 are turned on regardless of the level of each control input terminal (address signals A0 and A1).

  Accordingly, in the encryption storage / coincidence detection circuit 103B according to the second configuration example, the coincidence signal EQ is at a high level in any of binary numbers “0100” to “0111” in which the address signals A3 to A0 are continuous. The load pMISFET 110 is short-circuited between its gate and drain.

  Also, for a plurality of ciphers, a plurality of continuous codes are preferred for that purpose rather than a single continuous code.

  Therefore, as shown in FIG. 21, in the encryption memory / coincidence detection circuit 103C according to the third configuration example, the FETs 120D1 and 120D2 of the basic circuit 120 and the FETs 123D1 and 123D2 of the basic circuit 123 that are not adjacent to the FET 120D1 are made a depletion type. ing. The bit series circuit 112C has one end connected to the power supply line VCC and the other end connected to the ground line via the load resistor 110A. The match signal EQ is output from the other end of the bit series circuit 112C. Is done. Note that the load resistor 110A may be an nMISFET in which the gate and the drain are short-circuited.

  According to the encryption storage / coincidence detection circuit 103C according to the third configuration example, the address signals A3 to A0 supplied to the bit serial circuit 112C are binary numbers “0010”, “0011”, “1010”, or “1011”. Only when the coincidence signal EQ is high.

  There are various types of the memory cell array 104 described above. In any case, it is preferable that the encryption storage / coincidence detection circuit 103 can be formed by the same process as the memory cell array 104 because it is less expensive. Whether or not a single nMISFET is used as the memory cell of the memory cell array 104, and ions having the opposite polarity to those of the depletion type are implanted between the source and drain thereof, and the threshold voltage is set higher than a high level. That is, there is a type in which the stored contents are determined depending on whether or not a high threshold voltage type is used.

  In this case, for example, the encryption storage / coincidence detection circuit 103D of the fourth configuration example shown in FIG. 22 is used. In the figure, the x mark attached to the FET indicates that it is a high threshold voltage type.

  In the encryption memory / coincidence detection circuit 103D according to the fourth configuration example, the bit series circuit 112D includes parallel-connected basic circuits 130L, 131H, 132, and 133L connected in series. In the basic circuit 130L, the FET 120T and the FET 120E are connected in parallel, the input terminal and the output terminal of the inverter 120X are connected to the gates of the FET 120T and the FET 120E, respectively, and the address signal A0 is supplied to the input terminal of the inverter 120X. The FET 120E is a normal enhancement type, whereas the FET 120T is a high threshold voltage type.

  In the basic circuits 131H and 133L, the FET 121T and the FET 123T are high threshold voltage types, respectively. Accordingly, the basic circuits 130L, 131H, and 133L are turned on when the control input terminals (address signals A0, A1, and A3) are at the low level, the high level, and the low level, respectively. On the other hand, the FET 122E1 and the FET 122E2 of the basic circuit 132 are both normal enhancement types, and therefore the basic circuit 132 is turned on regardless of the level of the control input terminal (address signal A2).

  In the encryption storage / coincidence detection circuit 103D according to the fourth configuration example, the coincidence signal EQ is at a high level only when the address signals A3 to A0 are binary numbers "0010" or "0110".

  Further, as the memory cell of the memory cell array 104 described above, there is a type in which the memory content is determined by separating the source or drain depending on whether a contact hole is formed on the source or drain.

  In this case, for example, the encryption storage / coincidence detection circuit 103E of the fifth configuration example shown in FIG. 23 is used. In the figure, C attached to the reference numeral of the FET represents a floating type in which no contact hole is formed on the source.

  In the illustrated bit series circuit 112E, the FETs 120C, 121C, and 123C in the basic circuits 140L, 141H, and 143L correspond to the FETs 120T, 121T, and 123T in FIG. 22, respectively. Other configurations are the same as those in FIG.

  In the first to fifth configuration examples described above, the case where the encryption code is written in the bit serial circuit has been described. However, the encryption code may be written in the bit parallel circuit. One example thereof is shown in FIG. 24 as a sixth configuration example.

  In the encryption memory / coincidence detection circuit 103F according to the sixth configuration example, a bit parallel circuit 112F is connected between the load pMISFET 110 and the ground line. In the bit parallel circuit 112F, basic circuits 150L, 151H, 152Z, and 153L are connected in parallel. In the basic circuit 150L, nMISFETs 120T and 120E are connected in parallel, the FET 120E is a normal enhancement type, and the FET 120T is a high threshold voltage type. When the address buffer 101 shown in FIG. 18 is a complementary output type, the basic circuit does not require an inverter, and the FET 120T and the FET 120E are supplied with the address signal A0 and the logically inverted signal * A0, respectively.

  The basic circuits 151H, 152Z, and 153L are configured in the same manner as the basic circuit 150L. Among the basic circuits 151H and 153L, the FETs 121T and 123T are high threshold voltage types, respectively. On the other hand, in the basic circuit 152Z, both the nMISFETs 122T1 and 122T2 are high threshold voltage types.

  In the cipher memory / coincidence detection circuit 103F according to the sixth configuration example, the coincidence signal EQ is at a high level only when the address signals A3 to A0 are binary numbers "1001" or "1101".

  Even in the bit parallel circuit, a depletion type nMISFET can be used. An example thereof is shown in FIG. 25 as a seventh configuration example.

  In the cipher memory / coincidence detection circuit 103G according to the seventh configuration example, the bit parallel circuit 112G has basic circuits 160L, 161H, 162Z, and 163H connected in parallel. In the basic circuit 160L, nMISFETs 120D and 120E are connected in series, the FET 120E is a normal enhancement type, and the FET 120D is a depletion type.

  The basic circuits 161H, 162Z, and 163H are configured in the same manner as the basic circuit 160L. Of these, the basic circuit 162Z is always in an off state because one of the enhancement type FETs 122E1 and 122E2 is turned off. Yes.

  In the cipher memory / coincidence detection circuit 103G according to the seventh configuration example, the coincidence signal EQ is at a high level only when the address signals A3 to A0 are binary numbers "0001" or "0101".

  In each configuration example described above, when the cipher is a continuous code, the code starts from an even number and ends with an odd number. In the eighth configuration example (see FIG. 26) described below, this restriction is removed.

  The cipher memory / coincidence detection circuit 103H according to the eighth configuration example has a configuration in which a plurality of bit series circuits 112A in the first configuration example (see FIG. 19) are connected in parallel. That is, the bit series circuits 112P, 112Q, and 112R are connected in parallel between the load pMISFET 110 and the ground line. The bit series circuit 112P has basic circuits 220H, 221H, 222L and 223L connected in series, the bit series circuit 112Q has basic circuits 320, 321, 322H and 323L connected in series, and the bit series circuit 112R has a basic circuit. 420L, 421L, 422L, and 423H are connected in series.

  The coincidence signal EQ is at a high level only when the bit series circuit 112P, 112Q or 112R is on. The bit series circuit 112P is turned on when the address signals A3 to A0 are binary numbers “0011”, and the bit series circuit 112Q is turned on when the address signals A3 to A0 are in the range of binary numbers “0100” to “0111”. The bit serial circuit 112R is turned on when the address signals A3 to A0 are binary numbers “1000”.

  Therefore, the coincidence signal EQ is at a high level when the address signals A3 to A0 are in the range of "0011" or "0100" to "1000", and the end of the continuous code is not an odd number but an even number.

  The form of the encryption memory / coincidence detection circuit is not limited to the above-described configuration examples, and various other modifications are possible.

  For example, in FIG. 26, the memory content of the bit series circuits 112P, 112Q, and 112R is defined, and any one or any contact hole for connecting the drain of the load FET 110 and one end of the bit series circuits 112P, 112Q, and 112R It is also possible to easily manufacture a plurality of types of encryption for the mask ROM having the same stored contents.

  FIG. 27 schematically shows the configuration of a ROM device with a copy protection function according to the fourth embodiment of the present invention.

  The memory cell array 500, the timing signal generation circuit 501, the address buffer 502, the row decoder 503, the column decoder 504, and the column gate 505 shown in the figure are respectively 10 to 15 in the configuration of the first embodiment (see FIG. 3). The data output circuit 506 corresponds to the constituent elements 16 and 17 in the first embodiment (see FIG. 3).

  A feature of the ROM device according to this embodiment is that a scramble generation circuit 510 is provided in the preceding stage of the address buffer 502, and each bit of the input address signals A0 to An is scrambled and sent to the subsequent address buffer 502. This is the point. A broken line signal FLG input to the scramble generation circuit 510 indicates a scramble function activation signal, and CE is a chip enable signal (this is an external control signal CONT supplied to the timing signal generation circuit 501). Included).

FIG. 28 shows an example of the configuration of the scramble generation circuit. However, in the illustrated example for the sake of simplicity, the circuit configuration as scrambling to two bits of the address signal A0 and A ₁ is shown.

Scrambling generator shown, each connected n-channel transistors 531 and 532, each address bit inputs A0 and A ₁ and addresses between each address bit inputs A0 and A ₁ and address bit output A0 ' N-channel transistors 533 and 534 connected to the bit output terminal A ₁ ′, respectively, and the gates of the transistors are connected to a low-potential power line Vss (0 V).

  Of the n-channel transistors 531 to 534, in the illustrated example, either one of the transistors 531 and 532 and one of the transistors 533 and 534 are processed by ion implantation used in the wafer process of the semiconductor integrated circuit. , Formed in advance as a depletion type transistor. Therefore, the remaining two transistors function as enhancement type transistors.

  In the illustrated connection configuration, since the gates of the n-channel transistors 531 to 534 are connected to the power supply line Vss, the transistor formed as a depletion type is always on and the transistor formed as an enhancement type is always off. It becomes.

Therefore, by performing the appropriate depletion with respect to each n-channel transistors 531 to 534 can be scrambled relative address signals A0, A _1.

For example, when the transistors 532 and 533 are depleted by ion implantation, the address bit A ₁ is output to the address bit output terminal A0 ′, and the address bit A0 is output to the address bit output terminal A ₁ ′. Further, when the transistors 531 and 533 and the depletion of the ion implantation, the address bit output terminal A0 'and A _1' address bits A0 both of are output.

However, when the depletion of the transistors 531 and 534 are each original address bits A0 and A ₁ is output to the address bit output terminal A0 'and A _1', it can not be realized scrambling function which is desired object Therefore, the combination is not depressed.

FIG. 29 shows another configuration example of the scramble generation circuit. Similarly, in the illustrated example, for simplicity of explanation, the circuit configuration which is adapted scrambling for four bits of the address signal A0～A ₃ it is shown.

Scramble generating circuit illustrated, the n-channel transistors 541 to 544 whose one end is connected to the respective address bit inputs A0～A _3, each end to the respective address bit inputs A0～A ₃ similarly connected n Channel transistors 545 to 548, n-channel transistors 550 connected between the other ends of the transistors 541 to 544 and the low-potential power supply line Vss (0 V), and the other ends of the transistors 545 to 548 and the low potential Arithmetic operations (AND, OR, NOT, exclusive OR, etc.) as appropriate based on the n-channel transistors 551 to 554 connected between the power supply lines Vss and signals at the other ends of the transistors 545 to 548, respectively. A circuit 560, a signal at the other end of the transistor 541, and a scramble function activation signal F AND gate 561 responding to G, AND gate 562 responding to the output signal of operation circuit 560 and scramble function activation signal FLG, OR gate 563 responding to the output signal of each AND gate 561, 562 and address bit A0 have. The output terminal of the OR gate 563 is connected to the address bit output terminal A0 ′.

  The gates of the n-channel transistors 541 to 548 are connected to the low potential power line Vss, and the active low chip enable signal CE is applied to the gates of the other n-channel transistors 550 to 554. .

  In the circuit configuration shown in FIG. 29, when the chip enable signal CE is at “H” level, all of the n-channel transistors 550 to 554 are turned on, whereby the level of the input terminal of the arithmetic circuit 560 and the AND gates 561 and 562 Since the level of the input terminal is Vss (“L” level), the scramble function does not work.

On the other hand, when the chip enable signal CE is at "L" level, since the transistors 550 to 554 is turned off, the logic signal for each address bit A0～A ₃ dependent on or off state of the n-channel transistor 541 to 548 is The data is input to the arithmetic circuit 560 and the AND gates 561 and 562. At this time, if the scramble function activation signal FLG is set to “H” level, the AND gates 561 and 562 are activated, so that the scramble function can be activated.

  29, the initial value of the arithmetic circuit 560 is set by controlling the transistors 551 to 554 with the chip enable signal CE, and the scramble function is turned on / off with the scramble function activation signal FLG. Switching off is performed.

Therefore, in the same manner as in the configuration example of FIG. 28 described above, depletion is achieved by appropriately performing ion implantation processing on the n-channel transistors 541 to 548 whose gates are connected to the low-potential power line Vss. Accordingly, it is possible to scramble in any form to the address signal A0~A _3.

  As described above, according to the configuration of the fourth embodiment (see FIGS. 27 to 29), each bit of the input address signals A0 to An can be scrambled in an arbitrary form. The ROM data read from the memory cell array based on the address information is different from the correct data to be originally read. As a result, as in the above-described embodiments, it is possible to make it impossible to illegally copy by theft.

  FIG. 30 schematically shows the configuration of a ROM device with a copy protection function according to the fifth embodiment of the present invention.

  The feature of the ROM device according to the present embodiment is that a pseudo random number generation circuit 520 that realizes an equivalent function is provided in place of the scramble generation circuit 510 in the fourth embodiment (see FIG. 27). .

  In the fourth embodiment described above, the scramble function is realized by previously changing the characteristics of the transistors constituting the scramble generation circuit in a process. However, in this embodiment, the transistor is based on the control input from the outside. The same scramble function is realized by changing the characteristics. Therefore, in this embodiment, the clock CLK is used as an external control input. This clock CLK may be supplied from the outside of this device (that is, the chip), or may be appropriately supplied from other circuits inside the chip.

FIG. 31 shows an example of the configuration of the pseudorandom number generation circuit.
In comparison with the configuration of the scramble generation circuit shown in FIG. 28, each of the n-channel transistors 573 to 576 corresponds to the n-channel transistors 531 to 534, respectively. Inverters 571 and 572 are provided. 2) The outputs of the inverters 571 and 572 or the clock CLK are applied to the gates of the transistors 573 to 576.

In the configuration example of FIG. 31, by controlling the logic level of the address bit outputs A0 'and A _1' using the clock CLK from a circuit external, so as to achieve the same scrambling function and the scrambling generator of FIG. 28 ing. That is, by controlling the clock CLK, when viewed from outside the circuit, so that to output an uncertain data (pseudo random number) irrespective of the input information (address signals A0, A _1).

In the illustrated configuration example, when the clock CLK is at “H” level, the n-channel transistors 574 and 575 are turned on, while the outputs of the inverters 571 and 572 are at “L” level, so that the n-channel transistors 573 and 576 are turned on. Is turned off. As a result, the address bit A ₁ is output to the address bit output terminal A 0 ′, and the address bit A 0 is output to the address bit output terminal A ₁ ′. That is, the scramble function works. On the other hand, when the clock CLK "L" level, since the address bit output terminal A0 'and A _1' each original address bits A0 and A ₁ in is output, scrambling function does not work.

  As described above, according to the device configuration of the fifth embodiment (see FIGS. 30 and 31), the input address signals A0 to An can be scrambled based on the external control input (clock CLK). Similarly to the above-described fourth embodiment, illegal copying by theft can be made virtually impossible.

  In the fourth and fifth embodiments described above, the scramble generation (or pseudo-random number generation) circuit is arranged so as to function with respect to the input address signals A0 to An, but the arrangement form of each circuit is not limited to this. Although not shown, for example, a scramble generation (or pseudo-random number generation) function may be used for data read from the memory cell array (that is, output information), or both input information and output information A scramble generation (or pseudo-random number generation) function may be activated.

  FIG. 32 schematically shows the configuration of a ROM device with a copy protection function according to the sixth embodiment of the present invention.

  In the illustrated apparatus 600, an address decoder 602, a memory cell array 604, and an output circuit 605 correspond to the components 102, 104, and 105 in the configuration of the third embodiment (see FIG. 18), respectively, and the input circuit A part of the function 601 corresponds to the address buffer 101 of the third embodiment (see FIG. 18).

  The input circuit 601 includes an address buffer that responds to address signals A0 to An as a part of the input information IN, and an operation mode of the ROM device included in the input information (reading of original ROM data from the memory cell array 604). A function for controlling whether or not to output the trigger signal FIN based on data instructing a normal function such as an illegal function to prevent illegal copying due to theft). In the present embodiment, the trigger signal FIN is output when the data included in the input information IN indicates a special function, and the trigger signal FIN is not output in the case of the normal function.

  The feature of the ROM device according to the present embodiment is that when the power is turned off between the input circuit 601 and the output circuit 605 (power supply voltage Vcc → 0), the data held at that time is stored for a predetermined period. A power “off” detection and data holding circuit 603 having a function of continuing to hold the data. The output of the power “off” detection and data holding circuit 603 is supplied to the output circuit 605 as a determination signal FLAG, and is used to perform data output control or operation.

FIG. 33 shows a configuration example of the power “off” detection and data holding circuit.
The illustrated circuit includes p-channel transistors 611 and 612 and an n-channel transistor 613 connected in series between a high-potential power line Vcc and a low-potential power line Vss, and is connected in parallel to the n-channel transistor 613. An n-channel transistor 614 and a CMOS inverter (p-channel transistor 615 and n-channel transistor 616) connected between the power supply lines Vcc and Vss and responding to signals at the output terminals (node N1) of the transistors 612 and 614 constituting the CMOS inverter. ), An n-channel transistor 617 having a source connected to the output ends of the CMOS inverters 615 and 616 and a gate connected to the power supply line Vcc, and a drain (node N2; this is connected to each gate of the transistors 612 and 614). Connected And a capacitor 618 connected between the power supply lines Vss and a CMOS inverter (p-channel transistor 619 and n-channel transistor 620) connected between the power supply lines Vcc and Vss and responsive to the signal at the node N1. Have. The trigger signal FIN described above is input to the gates of the transistors 611 and 613 constituting the CMOS inverter, and the determination signal FLAG is taken out from the output terminals of the CMOS inverters 619 and 620 at the final stage.

  34 to 36 show various modifications of the main part (components 615 to 618) of the power “off” detection and data holding circuit, respectively.

  First, in the first modification shown in FIG. 34, the transistors 631, 633, and 634 correspond to the transistors 615, 616, and 617, respectively, and the capacitor 635 is the capacitor 618 in comparison with the main configuration shown in FIG. The difference in configuration is that an n-channel transistor 632 having a gate connected to its drain is provided between the transistors 631 and 633.

  Next, in the second modified example shown in FIG. 35, the transistors 641, 642, and 644 correspond to the transistors 615, 616, and 617, respectively, and the capacitor 645 is a capacitor in comparison with the main configuration shown in FIG. The difference is that an n-channel transistor 643 whose gate is connected to the source is provided between the output terminals of the transistors 641 and 642 and the source of the transistor 644.

  Next, in the third modified example shown in FIG. 36, in contrast to the main configuration shown in FIG. 33, each of the transistors 651 and 652 corresponds to the transistors 615 and 616, and the capacitor 656 corresponds to the capacitor 618. The difference in configuration is that 1) two impedance elements 653 and 654 are connected in series between the power supply lines Vcc and Vss, and 2) between the output terminals of the transistors 651 and 652 and the node N2. An n-channel transistor 655 that responds to the potential at the connection point of the two impedance elements is provided.

  Next, the operation of the power “off” detection and data holding circuit (see FIG. 33) in this embodiment will be described with reference to the operation timing waveform shown in FIG.

  In FIG. 37, (a) shows an operation timing waveform when the power supply voltage Vcc is raised before the level of the node N2 (potential of the capacitor 618) drops to the level of Vss, and (b) shows the level of the node N2. Shows an operation timing waveform when the power supply voltage Vcc is raised after the voltage drops to the level of Vss.

First, when the input information IN includes data instructing a special function for preventing unauthorized copying during the period from t _{1 to} t ₂ , the trigger signal FIN is output in the form of an “H” level pulse. Is done. Accordingly, the transistor 613 is turned on, and the potential of the node N1 falls to the “L” level. In response, transistor 615 is turned on, the level of Vcc is transmitted to node N2 via transistor 617, and the potential of capacitor 618 rises to the “H” level (that is, charged to the level of Vcc).

  On the other hand, when the potential of the node N1 becomes “L” level, the transistor 619 of the CMOS inverter at the final stage is turned on, so that the determination signal FLAG rises to “H” level. Once the determination signal FLAG becomes “H” level, even if the input signal (trigger signal FIN) changes to “L” level thereafter, the “H” level state is maintained. This is because when the potential of the node N2 becomes “H” level, the transistor 614 is turned on, and the potential of the node N1 is maintained at “L” level (self-holding function).

  If the data indicating the normal function is included in the input information IN, the trigger signal FIN is not output and the determination signal FLAG becomes “L” level. In this case, the original ROM data is read from the memory cell array 604.

Next, if the power supply is turned off at time t ₂ (power supply voltage Vcc → 0), the charge accumulated in the capacitor 618 is transferred from the drain region (n-type region) of the n-channel transistor 617 to the substrate (n-type region). leaks as a reverse current to the p-type region. As a result, the level of the node N2 (the potential of the capacitor 618) gradually changes from the “H” level to the “L” level. This changing time depends on a time constant determined by the capacitance of the capacitor 618 and the leakage resistance.

  On the other hand, when the power supply voltage Vcc becomes 0 V (“L” level), the determination signal FLAG also falls to the “L” level.

Then, when the level of the node N2 is to set up a power supply voltage Vcc at the time prior to t ₃ when lowered to the level of Vss (see operation timing waveforms of FIG. 37 (a)), the level of the node N2 is p-channel transistor 612 When the threshold level is equal to or higher than the threshold level, the transistor 612 is still in the off state, so that the level of the node N1 remains at the “L” level even if the p-channel transistor 611 is in the on state. Therefore, in this case, the determination signal FLAG rises to the “H” level at time t ₃ .

On the other hand, (see operation timing waveforms of FIG. 37 (b)) if the level of the node N2 is launched power supply voltage Vcc at time t ₄ after the reduction to the level of Vss, p-channel transistor 612 is turned on Thus, the level of the node N1 rises to the “H” level. In response to this, the transistor 620 of the CMOS inverter at the final stage is turned on, so that the determination signal FLAG maintains the “L” level.

  In this way, before and after the power “OFF”, if the power “OFF” period is within a certain time, the determination signal FLAG remains at the “H” level and does not change. This means that the data of “H” level is held.

  In other words, if the input information IN includes data instructing a special function for preventing unauthorized copying, this data is used as a “H” level trigger signal FIN as a power “off” detection and data holding circuit. Even if the power is turned off after that, if the period is within a certain time, the data of the special function is held at the “H” level.

  As described above, according to the apparatus configuration of the sixth embodiment (see FIGS. 32 to 37), the power is turned on within a certain time even when the power is unexpectedly turned off, thereby preventing unauthorized copying. Therefore, the illegal function copy by theft can be made virtually impossible based on the retained data.

1 is a principle configuration diagram of a semiconductor integrated circuit device with a copy protection function according to a first embodiment of the present invention; It is a principle block diagram of the semiconductor integrated circuit device with a copy prevention function which concerns on the 2nd form of this invention. 1 is a block diagram schematically showing a configuration of a ROM device with a copy protection function according to a first embodiment of the present invention. FIG. FIG. 4 is a circuit diagram illustrating a configuration example of a comparison / determination unit and a specific address storage unit in FIG. 3. FIGS. 5A and 5B are diagrams for explaining how to use the circuit of FIG. 4, in which FIG. 5A is a diagram illustrating an example of setting an operation mode of each transistor, and FIG. 5B is a diagram illustrating a setting example of a specific address or a specific address region; FIG. 4 is a circuit diagram showing a configuration example of a flag circuit in FIG. 3. It is a circuit diagram which shows one structural example of the process part for output means in FIG. It is the block diagram which showed schematically the structure of the ROM apparatus with a copy prevention function which concerns on 2nd Example of this invention. It is a figure which shows the relationship of the calling of the specific address area | region and flag ON / OFF which concern on 2nd Example. It is a figure for demonstrating the 1st execution example of copy prevention which concerns on 2nd Example. It is a figure which shows the example of 1 structure of the specific address area | region detection circuit which concerns on a 1st execution example. It is a figure for demonstrating the 2nd execution example of the copy protection which concerns on 2nd Example. It is a figure for demonstrating the 3rd execution example of the copy prevention based on 2nd Example, (a) is a structural example of an output operation circuit, (b) is a figure which shows the relationship of the input-output signal value. It is a figure for demonstrating the 4th execution example of copy prevention concerning 2nd Example, (a) is a structural example of an output operation circuit, (b) is a figure which shows the relationship of the input-output signal value. It is a figure for demonstrating the 5th example of copy prevention which concerns on 2nd Example, (a) is a structural example of an output operation circuit, (b) is a figure which shows the relationship of the input-output signal value. It is a figure for demonstrating the 6th execution example of copy prevention which concerns on 2nd Example. It is a figure for demonstrating the 7th execution example of copy prevention concerning 2nd Example. It is the block diagram which showed schematically the structure of the ROM device with a copy prevention function concerning 3rd Example of this invention. FIG. 19 is a circuit diagram illustrating a first configuration example of the encryption storage / coincidence detection circuit in FIG. 18. FIG. 19 is a circuit diagram illustrating a second configuration example of the encryption storage / coincidence detection circuit in FIG. 18. FIG. 19 is a circuit diagram illustrating a third configuration example of the encryption storage / coincidence detection circuit in FIG. 18. FIG. 19 is a circuit diagram illustrating a fourth configuration example of the encryption storage / coincidence detection circuit in FIG. 18. FIG. 19 is a circuit diagram illustrating a fifth configuration example of the encryption storage / coincidence detection circuit in FIG. 18. FIG. 19 is a circuit diagram illustrating a sixth configuration example of the encryption storage / coincidence detection circuit in FIG. 18. FIG. 19 is a circuit diagram illustrating a seventh configuration example of the encryption storage / coincidence detection circuit in FIG. 18. It is a circuit diagram which shows the 8th structural example of the encryption memory | storage / coincidence detection circuit in FIG. It is the block diagram which showed schematically the structure of the ROM apparatus with a copy prevention function concerning 4th Example of this invention. FIG. 28 is a circuit diagram showing a configuration example of a scramble generation circuit in FIG. 27. FIG. 28 is a circuit diagram showing another configuration example of the scramble generation circuit in FIG. 27. It is the block diagram which showed schematically the structure of the ROM device with a copy protection function according to the fifth embodiment of the present invention. FIG. 31 is a circuit diagram illustrating a configuration example of a pseudo random number generation circuit in FIG. 30. It is the block diagram which showed schematically the structure of the ROM device with a copy protection function according to the sixth embodiment of the present invention. FIG. 33 is a circuit diagram illustrating a configuration example of a power “off” detection and data holding circuit in FIG. 32. It is a circuit diagram which shows the 1st modification of the principal part in FIG. It is a circuit diagram which shows the 2nd modification of the principal part in FIG. It is a circuit diagram which shows the 3rd modification of the principal part in FIG. FIG. 34 is an operation timing waveform diagram of the circuit of FIG. 33.

Explanation of symbols

1 (stores data used by the user) storage means 2 (accesses the storage means) input means 3 (outputs data from the storage means) output means 4 (specifies input / output information or logic state) Determination means 5 (to prevent normal output of data in a specific case) control means 6 (detect / store access of input information to a plurality of specific address areas) detection / storage means 7 Data operation means (operating the contents of output data)

Claims (4)

Storage means for storing data used by the user;
Input means for performing various logical processes on at least one input information input from the outside and accessing the storage means;
Output means for performing various logical processes on the data when outputting the data from the storage means;
The power supply voltage is supplied, and at least one of the state of the input information, the state of the logic of the input unit, the state of the logic of the output unit, and the state of data obtained from the output unit is temporarily stored. Data holding means,
The data holding means is a semiconductor integrated circuit device with a copy protection function, which keeps holding the state data held at that time when the power supply voltage becomes "OFF" for a predetermined period.   If the data holding means includes data indicating a special function for preventing unauthorized copying in the input information input by the input means, the data is stored after the power supply voltage is turned off. The apparatus according to claim 1, wherein the apparatus is held for the predetermined period, and the output unit is controlled based on the held data.   3. The apparatus according to claim 2, wherein the data holding means includes a capacitor, and the predetermined period is determined depending on a capacitance of the capacitor.   The apparatus according to claim 1, wherein the data holding unit is provided separately from the storage unit.

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