JP2005322835A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To protect a circuit element from plasma charge and static electricity in a manufacturing process. <P>SOLUTION: There are provided a first-conductivity-type impurity layer 25b functioning as the source or drain of a transistor; a first high-concentration conductivity-type impurity layer 27b that is formed at the bottom of the first-conductivity-type impurity layer 25b, and contains a high concentration of impurities as compared with the first-conductivity-type impurity layer 25b; a second-conductivity-type impurity layer 28b formed under the first high-concentration conductivity-type impurity layer 27b by introducing second-conductivity-type impurities; an interlayer insulating film 6 formed on a semiconductor substrate; a connection hole 6a that is formed on the interlayer insulating film 6a and is positioned on the first-conductivity-type impurity layer; and wires 9a, 9b that are formed on the interlayer insulating film 6 and are connected to the first-conductivity-type impurity layer 25b by burying one portion in the connection hole 6a. A diode for discharging is composed of the second-conductivity-type impurity layer 28b and the first high concentration conductivity-type impurity layer 27a. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device capable of protecting circuit elements from static electricity and plasma charge received during the manufacturing process, and a method for manufacturing the same.

  FIG. 7 is a schematic plan view of a conventional semiconductor chip 100. In the semiconductor chip 100, a plurality of circuit elements are formed in the internal region 100c. A plurality of I / O cells 100b are formed around the inner region 100c, and a plurality of wiring pads 100a are formed further outside the I / O cell 100b. Power and signals are input to the wiring pad 100a from the outside, and these power and signals are transmitted to the circuit elements in the internal region 100c through the I / O cell 100b.

  FIG. 8 is a cross-sectional view showing the configuration of the circuit element formed in the internal region 100c. An element isolation film 102 is formed on the silicon substrate 101 by the LOCOS method, and the element regions 101 a and 101 b are isolated from each other by the element isolation film 102. Transistors are formed in each of the element regions 101a and 101b. That is, in the element region 101a, two impurity layers 105a serving as a source and a drain are formed on the silicon substrate 101 side by side with a channel region interposed therebetween. A gate oxide film 103a is formed on the channel region of the silicon substrate 101 by, for example, a thermal oxidation method, and a gate electrode 104a made of polysilicon is formed on the gate oxide film 103a. Also in the element region 101b, a gate oxide film 103b, a gate electrode 104b, and two impurity layers 105b are formed, and these configurations are the same as those of the gate oxide film 103a, the gate electrode 104a, and the two impurity layers 105a, respectively. is there.

  An interlayer insulating film 106 made of silicon oxide is formed on each transistor. A connection hole 106a and two connection holes 106b are formed in the interlayer insulating film 106 and the gate oxide films 103a and 103b. The connection hole 106a is located on the gate electrode 104a, and each of the two connection holes 106b is located on each of the two impurity layers 105b. Connection holes (not shown) are also formed on the two impurity layers 105a and the gate electrode 104b.

  A plurality of Al alloy wirings are formed on the interlayer insulating film 106. Of these wirings, the Al alloy wiring 109a is partly embedded in the connection hole 106a and the other part is an impurity layer serving as a drain. It is embedded in the connection hole 106b on 105b. In this way, the Al alloy wiring 109a connects the impurity layer 105b serving as the drain and the gate electrode 104a to each other. The Al alloy wiring 109b is partially buried in the connection hole 106b on the impurity layer 105b serving as the source, thereby being connected to the impurity layer 105b serving as the source.

  In some cases, static electricity enters the wiring pad 100a shown in FIG. 7 and is transmitted to the Al alloy wiring 109a. When the circuit element in the internal region 100 c is not fine and the gate oxide film 103 a is thick to some extent, the gate oxide film 103 a has a higher breakdown voltage than the breakdown voltage between the impurity layer 105 b and the silicon substrate 101, so that static electricity flows from the impurity layer 105 b to the silicon substrate 101. Discharged. However, in recent years, miniaturization of circuit elements has progressed and the gate oxide film 103a has become thinner, so that the breakdown voltage of the gate oxide film 103a is lower than the breakdown voltage between the impurity layer 105b and the silicon substrate 101. In this case, the gate oxide film 103a breaks down before being discharged from the impurity layer 105b to the silicon substrate 101.

As a method for preventing this, there is a method of forming an electrostatic protection circuit in a portion different from the transistor (for example, the I / O cell 100b shown in FIG. 7) (see, for example, Patent Document 1). In this case, static electricity that enters from the wiring pad 100a is absorbed by the static electricity protection circuit.
JP-A-6-252338 (FIG. 1, 10th to 12th paragraphs)

Plasma is often used in the process of forming circuit elements. For example, the wiring connected to the gate electrode of the transistor may be charged by plasma, but if all the wiring is not formed, the plasma-charged wiring may not be connected to the electrostatic protection circuit yet. . In this case, the transistor is not protected from plasma charge.
Even when static electricity enters from the wiring pad, a voltage is applied to the gate electrode until the static electricity is sufficiently absorbed by the static electricity protection circuit. For this reason, the gate oxide film located under the gate electrode may break down.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device capable of protecting circuit elements from plasma charge and static electricity received during the manufacturing process, and a method of manufacturing the same. There is.

In order to solve the above problems, a first semiconductor device according to the present invention includes:
A first conductivity type impurity layer formed on a semiconductor substrate and functioning as a source or drain of a transistor;
A high concentration first conductivity type impurity layer formed at the bottom of the first conductivity type impurity layer and having a higher impurity concentration than the first conductivity type impurity layer;
A second conductivity type impurity layer formed on the semiconductor substrate and located under the high concentration first conductivity type impurity layer;
An interlayer insulating film formed on the semiconductor substrate;
A connection hole formed in the interlayer insulating film and located on the first conductivity type impurity layer;
A wiring formed on the interlayer insulating film and connected to the first conductivity type impurity layer through the connection hole;
The second conductivity type impurity layer and the high-concentration first conductivity type impurity layer constitute a discharge diode.

  According to the first semiconductor device, the discharge diode is formed under the first conductivity type impurity layer functioning as the source or drain of the transistor. Therefore, even if the wiring is not connected to the electrostatic protection circuit, the plasma charge accumulated in the wiring connected to the first conductivity type impurity layer is discharged from the discharging diode to the semiconductor substrate. Also, static electricity that enters the wiring from the outside is discharged from the discharging diode to the semiconductor substrate. Therefore, circuit elements (ie, transistors) can be protected from both plasma charge and static electricity received during the manufacturing process.

A second semiconductor device according to the present invention includes:
A first conductivity type impurity layer formed on a semiconductor substrate and functioning as a source or drain of a transistor;
A second conductive type impurity layer formed on the semiconductor substrate and located below the first conductive type impurity layer; and an interlayer insulating film formed on the semiconductor substrate;
A connection hole formed in the interlayer insulating film and located on the first conductivity type impurity layer;
A wiring formed on the interlayer insulating film and connected to the first conductivity type impurity layer through the connection hole;
The first conductivity type impurity layer and the second conductivity type impurity layer constitute a discharge diode.

According to the second semiconductor device, the same operation and effect as the first semiconductor device can be obtained.
In the first and second semiconductor devices, when the wiring connects the first conductivity type impurity layer and the gate electrode of another transistor, in addition to the above effect, the gate insulating film of the other transistor It can also be protected from plasma charge. The wiring may be connected to the first conductivity type impurity layer by being partially embedded in the connection hole, or may be connected to the first conductivity type impurity layer via a conductor embedded in the connection hole. Also good.

A third semiconductor device according to the present invention includes:
A first conductivity type impurity layer for a transistor formed on a semiconductor substrate and functioning as a source or drain of the first transistor;
A high-concentration first conductivity type impurity layer formed at the bottom of the transistor first conductivity type impurity layer and having an impurity concentration higher than that of the transistor first conductivity type impurity layer;
A second conductive impurity layer for a diode formed on the semiconductor substrate and located under the high-concentration first conductive impurity layer;
A second conductivity type impurity layer for a transistor formed on the semiconductor substrate and functioning as a source or drain of a second transistor;
A high-concentration second conductivity type impurity layer formed at the bottom of the transistor second conductivity type impurity layer and having an impurity concentration higher than that of the transistor second conductivity type impurity layer;
A first conductivity type impurity layer for a diode formed on the semiconductor substrate and located under the high concentration second conductivity type impurity layer;
An interlayer insulating film formed on the semiconductor substrate;
A plurality of connection holes formed in the interlayer insulating film and located on each of the first conductive impurity layer for transistor and the second conductive impurity layer for transistor;
A first wiring formed on the interlayer insulating film and connected to the first conductive impurity layer for transistor via the connection hole on the first conductive impurity layer for transistor; and on the interlayer insulating film And a second wiring connected to the transistor second conductivity type impurity layer through the connection hole on the transistor second conductivity type impurity layer,
The high concentration first conductivity type impurity layer and the diode second conductivity type impurity layer constitute a first discharge diode, and the high concentration second conductivity type impurity layer and the diode first conductivity type impurity layer. Constitutes a second discharging diode.

A fourth semiconductor device according to the present invention includes:
A first conductivity type impurity layer for a transistor formed on a semiconductor substrate and functioning as a source or drain of the first transistor;
A second conductive impurity layer for a diode formed on the semiconductor substrate and positioned below the first conductive impurity layer for the transistor;
A second conductivity type impurity layer for a transistor formed on the semiconductor substrate and functioning as a source or drain of a second transistor;
A first conductive impurity layer for a diode formed on the semiconductor substrate and positioned below the second conductive impurity layer for the transistor;
An interlayer insulating film formed on the semiconductor substrate;
A plurality of connection holes formed in the interlayer insulating film and located on each of the first conductive impurity layer for transistor and the second conductive impurity layer for transistor;
A first wiring formed on the interlayer insulating film and connected to the first conductive impurity layer for transistor via the connection hole on the first conductive impurity layer for transistor; and on the interlayer insulating film And a second wiring connected to the transistor second conductivity type impurity layer through the connection hole on the transistor second conductivity type impurity layer,
The transistor first conductivity type impurity layer and the diode second conductivity type impurity layer constitute a first discharge diode, and the transistor second conductivity type impurity layer and the diode first conductivity type impurity layer. Constitutes a second discharging diode.

A fifth semiconductor device according to the present invention includes:
Two first conductivity type impurity layers formed on a semiconductor substrate and functioning as sources or drains of different transistors,
Two high-concentration first conductivity type impurity layers formed at the bottom of each of the two first conductivity type impurity layers, each having an impurity concentration higher than that of the first conductivity type impurity layer;
Two second conductivity type impurity layers formed on the semiconductor substrate and positioned below each of the two high concentration first conductivity type impurity layers;
An interlayer insulating film formed on the semiconductor substrate;
A plurality of connection holes formed in the interlayer insulating film and positioned on each of the two first conductivity type impurity layers;
A first wiring formed on the interlayer insulating film and connected to the one first conductivity type impurity layer via the connection hole on one of the first conductivity type impurity layers; And a second wiring connected to the other first conductivity type impurity layer via the connection hole on the other first conductivity type impurity layer,
At least one set of the two second conductivity type impurity layers and the two high-concentration first conductivity type impurity layers have different impurity concentrations,
Each of the two high-concentration first conductivity type impurity layers forms a discharge diode together with the second conductivity-type impurity layer located under each of the high-concentration first conductivity type impurity layers.

A sixth semiconductor device according to the present invention includes:
Two first conductivity type impurity layers formed on a semiconductor substrate and functioning as sources or drains of different transistors,
Two second conductivity type impurity layers formed on the semiconductor substrate and positioned under each of the two first conductivity type impurity layers;
An interlayer insulating film formed on the semiconductor substrate;
A plurality of connection holes formed in the interlayer insulating film and positioned on each of the two first conductivity type impurity layers;
A first wiring formed on the interlayer insulating film and connected to the one first conductivity type impurity layer via the connection hole on one of the first conductivity type impurity layers; And a second wiring connected to the other first conductivity type impurity layer through the connection hole on the other first conductivity type impurity layer,
The two second conductivity type impurity layers have different impurity concentrations,
Each of the two first conductivity type impurity layers forms a discharge diode together with the second conductivity type impurity layer located below each of the first conductivity type impurity layers.

  According to these third to sixth semiconductor devices, the same effects as the first semiconductor device can be obtained. In particular, according to the fifth and sixth semiconductor devices, since the discharge diodes having different characteristics are formed for each transistor or region, each circuit element can be protected by a diode suitable for each. .

A first semiconductor device manufacturing method according to the present invention includes:
Forming a first conductivity type impurity layer functioning as a source or drain of a transistor in the semiconductor substrate by implanting impurity ions of the first conductivity type into the semiconductor substrate;
Forming an interlayer insulating film on the semiconductor substrate;
Forming a connection hole located on the first conductivity type impurity layer in the interlayer insulating film;
By implanting impurity ions of the first conductivity type into the semiconductor substrate through the connection holes, a high concentration first conductivity having an impurity concentration higher than that of the first conductivity type impurity layer is formed at the bottom of the first conductivity type impurity layer. Forming a type impurity layer;
Forming a second conductivity type impurity layer located under the high concentration first conductivity type impurity layer by implanting second conductivity type impurity ions into the semiconductor substrate through the connection hole;
Forming a conductive film on the interlayer insulating film and in the connection hole;
Patterning the conductive film, forming a wiring part of which is embedded in the connection hole and connected to the first conductivity type impurity layer,
The high-concentration first conductivity type impurity layer and the second conductivity type impurity layer form a discharge diode.

A second semiconductor device manufacturing method according to the present invention includes:
Forming a first conductivity type impurity layer functioning as a source or drain of a transistor in the semiconductor substrate by implanting impurity ions of the first conductivity type into the semiconductor substrate;
Forming an interlayer insulating film on the semiconductor substrate;
Forming a connection hole located on the first conductivity type impurity layer in the interlayer insulating film;
By implanting impurity ions of the first conductivity type into the semiconductor substrate through the connection holes, a high concentration first conductivity having an impurity concentration higher than that of the first conductivity type impurity layer is formed at the bottom of the first conductivity type impurity layer. Forming a type impurity layer;
Forming a second conductivity type impurity layer located under the high concentration first conductivity type impurity layer by implanting second conductivity type impurity ions into the semiconductor substrate through the connection hole;
Embedding a conductor in the connection hole;
Forming a conductive film on the interlayer insulating film and on the conductor in the connection hole;
Forming a wiring connected to the first conductivity type impurity layer through the conductor by patterning the conductive film,
The high-concentration first conductivity type impurity layer and the second conductivity type impurity layer form a discharge diode.

  According to the first and second semiconductor device manufacturing methods, even if the conductive film or the wiring formed from the conductive film is charged from plasma in a later process, the charged charge functions as the source or drain of the transistor. A discharge diode formed under the one conductivity type impurity layer is discharged. Therefore, the circuit element (that is, the transistor) can be protected from the plasma charge.

A third method for manufacturing a semiconductor device according to the present invention includes:
Forming a first conductivity type impurity layer functioning as a source or drain of a transistor on the semiconductor substrate by implanting impurity ions of the first conductivity type into the semiconductor substrate;
Forming an interlayer insulating film on the semiconductor substrate;
Forming a connection hole located on the first conductivity type impurity layer in the interlayer insulating film;
Forming a second conductivity type impurity layer under the first conductivity type impurity layer by implanting second conductivity type impurity ions into the semiconductor substrate through the connection hole;
Forming a wiring connected to the first conductivity type impurity layer through the connection hole on the interlayer insulating film,
The first conductivity type impurity layer and the second conductivity type impurity layer form a discharge diode.

A fourth method for manufacturing a semiconductor device according to the present invention includes:
By implanting first conductivity type impurity ions into the semiconductor substrate, a first first conductivity type impurity layer and a second first conductivity type impurity layer that respectively function as a source or a drain of the transistor are formed on the semiconductor substrate. And a process of
Forming an interlayer insulating film on the semiconductor substrate;
A first connection hole located on the first first conductivity type impurity layer is formed in the interlayer insulating film, and a second connection hole located on the second first conductivity type impurity layer is formed. Forming, and
Impurity ions of the first conductivity type are implanted into the semiconductor substrate through the first connection hole, and the first conductivity type is implanted into the semiconductor substrate through the first connection hole and the second connection hole, respectively. By implanting impurity ions, a first high-concentration first conductivity type impurity layer having an impurity concentration higher than that of the first conductivity type impurity layer is formed at the bottom of the first first conductivity type impurity layer. Forming a second high concentration first conductivity type impurity layer having an impurity concentration lower than that of the first high concentration first conductivity type impurity layer at the bottom of the second first conductivity type impurity layer;
Impurity ions of the second conductivity type are implanted into the semiconductor substrate through the first connection hole, and the second conductivity type is introduced into the semiconductor substrate through the first connection hole and the second connection hole, respectively. Then, a first second conductivity type impurity layer is formed under the first high concentration first conductivity type impurity layer, and the second high concentration first conductivity type impurity layer is formed. Forming a second second conductivity type impurity layer having an impurity concentration lower than that of the first second conductivity type impurity layer;
A first wiring connected to the first first conductivity type impurity layer is formed on the interlayer insulating film through the first connection hole, and the second wiring is formed through the second connection hole. Forming a second wiring connected to the first conductivity type impurity layer.
The first second conductivity type impurity layer, the first high concentration first conductivity type impurity layer, the second second conductivity type impurity layer, and the second high concentration first conductivity type impurity layer are: A discharge diode is formed for each.

A fifth method for manufacturing a semiconductor device according to the present invention includes:
Forming a first conductivity type impurity layer for a transistor functioning as a source or drain of the first conductivity type transistor by implanting first conductivity type impurity ions into the semiconductor substrate;
Forming a second conductivity type impurity layer for a transistor functioning as a source or drain of a second conductivity type transistor by implanting second conductivity type impurity ions into the semiconductor substrate;
Forming an interlayer insulating film on the semiconductor substrate;
Forming a first connection hole located on the first conductivity type impurity layer for the transistor and a second connection hole located on the second conductivity type impurity layer for the transistor in the interlayer insulating film; When,
By implanting first conductivity type impurity ions into the semiconductor substrate through the first connection hole, the impurity concentration at the bottom of the transistor first conductivity type impurity layer is lower than that of the transistor first conductivity type impurity layer. Forming a high-concentration first-conductivity-type impurity layer having a high concentration;
Forming a second conductive type impurity layer for a diode under the high-concentration first conductive type impurity layer by implanting second conductive type impurity ions into the semiconductor substrate through the first connection hole; When,
By implanting second conductivity type impurity ions into the semiconductor substrate through the second connection hole, the impurity concentration at the bottom of the transistor second conductivity type impurity layer is lower than that of the transistor second conductivity type impurity layer. Forming a high-concentration second conductivity type impurity layer having a high concentration;
Forming a first conductivity type impurity layer for a diode under the high concentration second conductivity type impurity layer by implanting first conductivity type impurity ions into the semiconductor substrate via the second connection hole; When,
A first wiring connected to the first conductivity type impurity layer for the transistor through the first connection hole is formed on the interlayer insulating film, and the transistor wiring through the second connection hole. Forming a second wiring connected to the two-conductivity type impurity layer,
The high concentration first conductivity type impurity layer and the diode second conductivity type impurity layer form a first discharge diode, and the high concentration second conductivity type impurity layer and the diode first conductivity type impurity layer. Forms a second discharging diode.

  The same effects as the first semiconductor device manufacturing method can also be obtained by the third to fifth semiconductor device manufacturing methods. According to the fourth method for manufacturing a semiconductor device, a plurality of discharge diodes having different characteristics can be formed in the same process.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic plan view of a semiconductor chip according to the present embodiment. A plurality of wiring pads 11 are formed on the periphery of the semiconductor chip. A plurality of I / O cells 12 are arranged inside the wiring pad 11 in a ring shape. In the internal region 13 that is a region surrounded by the I / O cell 12, a plurality of transistors constituting a circuit are formed. The characteristics of these transistors may be the same or different in the internal regions 13A and 13B. A plurality of discharge diodes are formed as protection circuits in the internal region 13. The discharging diode is formed under the source or drain of the transistor and is directly connected to the source or drain. The I / O cell 12 is provided with an electrostatic protection circuit (not shown).

2 is a cross-sectional view showing a first method of forming a transistor and a discharge diode in the internal region 13. In this method, a transistor is formed in each of the two element regions 1a and 1b, and a discharge diode is formed under the source and drain of the transistor in the element region 1b.
First, as shown in FIG. 2A, the element isolation film 2 is formed on the silicon substrate 1 by, for example, the LOCOS method to isolate the element regions 1a and 1b from each other.

  Next, gate oxide films 3a and 3b are respectively formed on the silicon substrate 1 in the element regions 1a and 1b by a thermal oxidation method. Next, a polysilicon film is formed on the entire surface including the gate oxide films 3a and 3b, and the polysilicon film is patterned to form gate electrodes 4a and 4b on the gate oxide films 3a and 3b, respectively. Next, impurity ions (for example, N-type impurities) of the first conductivity type are implanted using the gate electrodes 4a and 4b and the element isolation film 2 as a mask. Thus, two transistor first conductivity type impurity layers 25a and 25b are formed on the silicon substrate 1 in the element regions 1a and 1b, respectively.

  Next, an interlayer insulating film 6 made of silicon oxide is formed on the entire surface including the gate oxide films 3a and 3b and the gate electrodes 4a and 4b. Next, a photoresist film (not shown) is applied on the interlayer insulating film 6, and this photoresist film is exposed and developed to form a resist pattern. Next, using this resist pattern as a mask, the interlayer insulating film 6 and the gate oxide films 3a and 3b are etched. As a result, the connection hole 6a located on the gate electrode 4a, the connection hole (not shown) located on the gate electrode 4b, and the two first conductivity type impurity layers 25a for the two transistors Two connection holes (not shown) located on the connection hole 6b and the two first-conductivity-type impurity layers 25b for the transistors are formed.

Next, after removing the resist pattern, as shown in FIG. 2B, a photoresist film is applied again, and the resist film is exposed and developed to form a resist pattern 50. The resist pattern 50 covers the connection hole 6a and the connection hole on the gate electrode 4b, but may further cover the connection hole located on the transistor first conductivity type impurity layer 25a.
Next, using the resist pattern 50 and the interlayer insulating film 6 as a mask, first conductivity type impurity ions (for example, P ions of N type impurities) are implanted at, for example, 70 keV. As a result, impurity ions are implanted into a part of the bottom of the transistor first conductivity type impurity layer 25b through the connection hole 6b, and the impurity concentration is higher than that of the transistor first conductivity type impurity layer 25b. Two layers 27b are formed. The two high-concentration first conductivity type impurity layers 27b are respectively formed directly below the connection holes 6b.

Next, by implanting second conductivity type impurity ions (for example, B ions of P-type impurities) using resist pattern 50 and interlayer insulating film 6 as a mask, a diode is formed directly below each of the two high-concentration first conductivity type impurity layers 27b. The second conductivity type impurity layer 28b is formed. The ion implantation energy at this time is, for example, 60 keV, and the second conductive type impurity layer 28b for diode is connected to the high concentration first conductive type impurity layer 27b. For example, a part of the second conductivity type impurity layer for diode 28b is overlapped with a part of the high concentration first conductivity type impurity layer 27b.
As a result, a discharge diode composed of the high-concentration first conductivity type impurity layer 27b and the diode second conductivity type impurity layer 28b is formed under each of the source and drain. The impurity concentration of this diode is adjusted so that the breakdown voltage is lower than that of the gate oxide film 3a. For example, the concentration of each of the high concentration first conductivity type impurity layer 27b and the second conductivity type impurity layer for diode 28b is 5 × 10 ¹³ / cm ² .

  Next, after removing the resist pattern 50 as shown in FIG. 2D, an Al alloy film is formed by sputtering in all the connection holes and on the interlayer insulating film 6, and this Al alloy film is patterned. As a result, a plurality of Al alloy wirings are formed on the interlayer insulating film 6. Among these Al alloy wirings, part of the Al alloy wiring 9a is embedded in the connection hole 6a, and the other part is embedded in the connection hole 6b on the impurity layer 25b serving as the drain. In this way, the Al alloy wiring 9a connects the transistor first conductivity type impurity layer 25b serving as the drain to the gate electrode 4a. The Al alloy wiring 9b is partially buried in the connection hole 6b on the transistor first conductivity type impurity layer 25b serving as the source, thereby connecting to the transistor first conductivity type impurity layer 25b serving as the source.

In the transistor and discharge diode formed in this way, when static electricity is applied to the Al alloy wiring 9a, the static electricity is discharged under the drain before the gate oxide film 3a is broken down. The silicon substrate 1 is discharged from the diode. The diode below the drain is closer to the gate oxide film 3a than the I / O cell 12. For this reason, even if static electricity is not completely absorbed by the electrostatic protection circuit formed in the I / O cell 12 and static electricity is applied to the Al alloy wiring 9a, the static electricity that has not been completely absorbed before the dielectric breakdown of the gate oxide film 3a. The diode is discharged to the substrate.
In addition, static electricity may be applied to the Al alloy wiring 9b, and this static electricity is also discharged to the silicon substrate 1 from a discharging diode formed under the source.

Plasma is used when an Al alloy film is formed by sputtering and when an Al alloy film is etched to form an Al alloy wiring. Even if an electric charge is charged from this plasma to the Al alloy film, the charged charge is used. Is discharged from the discharge diode to the silicon substrate 1 before dielectric breakdown of the gate oxide film 3a.
In some cases, an interlayer insulating film and an Al alloy wiring are laminated in this order on the Al alloy wirings 9a and 9b. Plasma is also used when laminating them. For this reason, the Al alloy wiring 9a may be charged from the plasma, but the charged charge is discharged from the discharging diode to the silicon substrate 1 before the gate oxide film 3a is broken down. Also, the charge charged in the Al alloy wiring 9b is discharged to the silicon substrate 1 from the discharge diode formed under the source.

  As described above, according to the first method, the gate oxide film of the transistor as the circuit element can be protected from plasma charge and static electricity received during the manufacturing process. Further, in order to form the high-concentration first conductivity type impurity layer 27b and the second conductivity type impurity layer 28b for the diode only at a part of the bottom of the first conductivity type impurity layer 25b for transistors, that is, just below and in the vicinity of the connection hole 6b. The influence on the characteristics of the transistor can be reduced.

In the present embodiment, the process of implanting the first conductivity type impurity ions from the connection hole 6b may be omitted. In this case, the high-concentration first conductivity type impurity layer 27b is not formed at the bottom of the transistor first conductivity type impurity layer 25b, but the transistor first conductivity type impurity layer 25b and the diode second conductivity type impurity layer 28b are formed. A discharge diode is formed. In the above-described method, the second conductivity type impurity layer 28b for the diode is formed after the high-concentration first conductivity type impurity layer 27b is formed. However, the second conductivity type for diode is implanted by implanting impurity ions of the second conductivity type. After forming the impurity layer 28b, the first conductivity type impurity ions may be implanted to form the high concentration first conductivity type impurity layer 27b.
Further, the discharging diode described above may be formed on the entire surface of the internal region 13 or may be selectively formed only in a specific region. For example, when the operation speed of the transistor is important in the internal region 13A of FIG. 1, no discharging diode is formed in the internal region 13A.

  3 and 4 are cross-sectional views showing a second method for forming a transistor and a discharge diode in the internal region 13. In this method, the same components as those in the first method are denoted by the same reference numerals and description thereof is omitted. In the present embodiment, a first conductivity type transistor is formed in each of the two element regions 1a and 1d, and a second conductivity type transistor is formed in each of the two element regions 1b and 1c. Discharge diodes are formed under the source and drain of the transistors in the element regions 1b and 1d, respectively.

  First, as shown in FIG. 3A, the element isolation film 2 is formed on the silicon substrate 1 by, for example, the LOCOS method, and the element regions 1a, 1b, 1c, and 1d are isolated from each other. Next, gate oxide films 3a, 3b, 3c and 3d are formed on the silicon substrate 1 in the element regions 1a, 1b, 1c and 1d, respectively, by thermal oxidation. Next, a polysilicon film is formed on the entire surface including the gate oxide films 3a, 3b, 3c and 3d, and the polysilicon film is patterned to form gate electrodes 4a and 4b on the gate oxide films 3a, 3b, 3c and 3d, respectively. , 4c, 4d.

  Next, a photoresist film (not shown) is formed on the entire surface including each gate oxide film and each gate electrode, and this photoresist film is exposed and developed to form a resist pattern. The resist pattern covers the element regions 1b and 1c, and has openings on the entire surface of the element regions 1a and 1d. Next, impurity ions of the first conductivity type (for example, P ions of N-type impurities) are implanted using the resist pattern, the gate electrodes 4a and 4d, and the element isolation film 2 as a mask, so that the source and drain are respectively formed in the element regions 1a and 1d. Two transistor first conductivity type impurity layers 5a and 5d are formed.

  Next, after removing the resist pattern, a photoresist film (not shown) is formed again on the entire surface including each gate oxide film and each gate electrode. Next, the photoresist film is exposed and developed to form a resist pattern. This resist pattern covers the element regions 1a and 1d, and has openings on the entire surface of the element regions 1b and 1c. Next, by implanting second conductivity type impurity ions (for example, B ions of P-type impurities) using the resist pattern, gate electrodes 4b and 4c and element isolation film 2 as a mask, the source and drain are formed in the element regions 1b and 1c. Two transistor second conductivity type impurity layers 5b and 5c are formed.

  Next, an interlayer insulating film 6 made of silicon oxide is formed on the entire surface including each gate oxide film and each gate electrode. Next, a photoresist film (not shown) is applied on the interlayer insulating film 6, and this photoresist film is exposed and developed to form a resist pattern. Next, using this resist pattern as a mask, the interlayer insulating film 6 and the gate oxide films 3a and 3b are etched. As a result, the connection hole 6a, the two connection holes 6b are formed, and the connection hole 6c located on the gate electrode 4c and the two connections located on the two first conductivity type impurity layers 5d for the transistors, respectively. A hole 6d is formed. Also, a connection hole (not shown) located on the gate electrode 4b, two connection holes (not shown) located on each of the two transistor second conductivity type impurity layers 5b, and two transistor seconds. Two connection holes (not shown) located on each of the conductive impurity layers 5c and a connection hole (not shown) located on the gate electrode 4d are also formed.

  Next, as shown in FIG. 3B, a photoresist film is applied on the interlayer insulating film 6 and each connection hole, and a resist pattern 50 is formed by exposing and developing the photoresist film. Although the resist pattern 50 exposes two connection holes 6b, the connection holes 6a, 6c and 6d, the connection holes on the gate electrodes 4b and 4d, and the connection holes on the transistor first conductivity type impurity layer 5a. Covering. The resist pattern 50 may cover the connection hole on the second conductivity type impurity layer 5c for transistors.

Next, impurity ions of the second conductivity type (for example, B ions of P-type impurities) are implanted at 25 keV, for example, using the resist pattern 50 and the interlayer insulating film 6 as a mask. As a result, impurity ions are implanted into the bottom of the transistor second conductivity type impurity layer 5b through the connection hole 6b, thereby forming the high concentration second conductivity type impurity layer 7b.
Next, impurity ions of the first conductivity type (for example, P ions of N-type impurities) are implanted using the resist pattern 50 and the interlayer insulating film 6 as a mask, so that a diode is formed immediately below each of the two high-concentration second conductivity type impurity layers 7b. The first conductivity type impurity layer 8b is formed. The ion implantation energy at this time is, for example, 140 keV, and the first conductive impurity layer for diode 8b is connected to the high-concentration second conductive impurity layer 7b. As a result, a discharge diode composed of the high-concentration second conductivity type impurity layer 7b and the diode first conductivity type impurity layer 8b is formed under each of the source and drain.

  Next, as shown in FIG. 4A, the resist pattern 50 is removed. Next, a photoresist film is applied again on the interlayer insulating film 6 and each connection hole, and the photoresist pattern is exposed and developed to form a resist pattern 51. The resist pattern 51 covers the connection holes on the connection holes 6a, 6b, and 6c, the gate electrodes 4b and 4d, and the connection holes on the transistor second conductivity type impurity layer 5c. The connection hole on the type impurity layer 5a may be covered.

Next, impurity ions of the first conductivity type are implanted at 70 keV, for example, using the resist pattern 51 and the interlayer insulating film 6 as a mask. As a result, impurity ions are implanted into the bottom of the transistor first conductivity type impurity layer 5d through the connection hole 6d to form the high concentration first conductivity type impurity layer 7d.
Next, impurity ions of the second conductivity type are implanted using the resist pattern 51 and the interlayer insulating film 6 as a mask, whereby the second conductivity type impurity layer 8d for the diode is formed immediately below the two high-concentration first conductivity type impurity layers 7d. Form. The ion implantation energy at this time is, for example, 60 keV, and the second conductive type impurity layer 8d for diode is connected to the high concentration first conductive type impurity layer 7d.
As a result, a discharge diode composed of the high-concentration first conductivity type impurity layer 7d and the diode second conductivity type impurity layer 8d is formed under the source and drain. In this diode, the impurity concentration is adjusted so that the breakdown voltage is lower than that of the gate oxide film 3c. For example, the concentration of each of the high-concentration first conductivity type impurity layer 7d and the diode second conductivity type impurity layer 8d is 5%. × 10 ¹³ / cm ²

  Next, as shown in FIG. 4B, after removing the resist pattern 51, an Al alloy film is formed by sputtering in all the connection holes and on the interlayer insulating film 6, and this Al alloy film is further patterned. Thereby, a plurality of Al alloy wirings are formed on the interlayer insulating film 6. Among these Al alloy wirings, an Al alloy wiring 9a is partly embedded in the connection hole 6a and the other part is embedded in the connection hole 6b on the second conductivity type impurity layer 5b for a transistor serving as a drain. . A part of the Al alloy wiring 9c is embedded in the connection hole 6c, and the other part is embedded in the connection hole 6d on the first conductivity type impurity layer 5d for the transistor serving as a drain. In this way, the Al alloy wiring 9a connects the transistor second conductivity type impurity layer 5b serving as the drain and the gate electrode 4a to each other, and the Al alloy wiring 9c serves as the drain first transistor conductivity type impurity layer 5d and the gate electrode. 4c are connected to each other. The Al alloy wiring 9b is partly buried in the connection hole 6b on the transistor second conductivity type impurity layer 5b serving as the source, thereby connecting to the transistor second conductivity type impurity layer 5b serving as the source. The Al alloy wiring 9d is partially buried in the connection hole 6d on the transistor first conductivity type impurity layer 5d serving as the source, thereby connecting to the transistor first conductivity type impurity layer 5d serving as the source.

In the transistor and discharge diode thus formed, when static electricity is applied to the Al alloy wirings 9a and 9c, the static electricity is formed under the drain before dielectric breakdown of the gate oxide films 3a and 3c. The discharged discharge diode is discharged to the silicon substrate 1. In addition, static electricity may be applied to the Al alloy wirings 9b and 9d, but this static electricity is also discharged from the discharge diode formed under the source to the silicon substrate 1 and from the plasma used for film formation or etching. Even if the Al alloy film is charged, the charged charge is discharged from the discharge diode to the silicon substrate 1 before dielectric breakdown of the gate oxide films 3a and 3c. The charges charged in the Al alloy wirings 9b and 9d are also discharged to the silicon substrate 1 from the discharging diode formed under the source.

As described above, according to the second method, the same effects as those of the transistor and the discharge diode formed by the first method can be obtained.
In the present embodiment, the process of implanting the second conductivity type impurity ions from the connection hole 6b may be omitted. Further, the process of implanting the first conductivity type impurity ions from the connection hole 6d may be omitted. In these cases, the high concentration second conductivity type impurity layer 7b is not formed at the bottom of the transistor second conductivity type impurity layer 5b, and the high concentration first conductivity type is not formed at the bottom of the transistor first conductivity type impurity layer 5d. The impurity layer 7d is not formed. The transistor second conductivity type impurity layer 5b and the diode first conductivity type impurity layer 8b constitute a discharge diode, and the transistor first conductivity type impurity layer 5d and the diode second conductivity type impurity layer 8d include A discharge diode is formed.
Further, the processing shown in FIG. 4A may be performed before the processing shown in FIG.

  Alternatively, the high-concentration second conductivity type impurity layer 7b may be formed after forming the diode first conductivity-type impurity layer 8b, or the high-concentration first conductivity type after forming the diode second conductivity-type impurity layer 8d. The impurity layer 7d may be formed.

  Each drawing in FIG. 5 is a cross-sectional view showing a third method of forming a transistor and a discharging diode in the internal region 13. In this method, the same components as those of the second method are denoted by the same reference numerals and description thereof is omitted. In the present embodiment, a first conductivity type transistor is formed in each of the two element regions 1a and 1e provided in the inner region 13A shown in FIG. 1 and the two element regions 1d and 1f provided in the inner region 13B. Is done. Discharge diodes having different characteristics are formed under the transistors in the element regions 1d and 1e.

  First, as shown in FIG. 5A, an element isolation film 2, gate oxide films 3a, 3d, 3e, and 3f and gate electrodes 4a, 4d, 4e, and 4f are formed on a silicon substrate 1. These forming methods are the same as the second method except for the step of forming the gate oxide films 3a, 3d, 3e, and 3f. The process for forming the gate oxide film is as follows. First, the element regions 1a and 1e are covered with a protective film such as silicon nitride, and then a first thermal oxidation process is performed. Next, after removing the protective film, a second thermal oxidation treatment is performed. Thereby, the gate oxide films 3a and 3e are formed thinner than the gate oxide films 3d and 3f.

  Next, by implanting first conductivity type ions (for example, P ions of N-type impurities) using the gate electrodes 4a, 4d, 4e, 4f and the element isolation film 2 as masks, source regions are respectively provided in the element regions 1a, 1d, 1e, 1f. Two transistor first conductivity type impurity layers 5a, 5d, 5e, and 5f to be drains are formed.

  Next, a photoresist film is applied on the interlayer insulating film 6 and each connection hole, and a resist pattern 52 is formed by exposing and developing the photoresist film. The resist pattern 52 covers the connection holes on the connection holes 6a, 6d, and 6f, the gate electrodes 4d and 4e, and the connection hole on the transistor first conductivity type impurity layer 5f. The connection hole on the type impurity layer 5a may be covered.

Next, using the resist pattern 52 and the interlayer insulating film 6 as a mask, first conductivity type impurity ions (for example, P ions of N type impurities) are implanted at, for example, 70 keV. As a result, impurity ions are implanted into the bottom of the transistor first conductivity type impurity layer 5e through the connection hole 6e to form the high concentration first conductivity type impurity layer 7e.
Next, by implanting second conductivity type impurity ions (for example, B ions of P type impurities) using the resist pattern 52 and the interlayer insulating film 6 as a mask, a diode is formed immediately below each of the two high concentration first conductivity type impurity layers 7e. A second conductivity type impurity layer 8e is formed. The ion implantation energy at this time is, for example, 60 keV, and the second conductive impurity layer 8e for diode is connected to the high-concentration first conductive impurity layer 7e.

  Next, the resist pattern 52 is removed as shown in FIG. Next, a photoresist film is applied again on the interlayer insulating film 6 and each connection hole, and a resist pattern 53 is formed by exposing and developing the photoresist film. The resist pattern 53 covers the connection holes on the connection holes 6a and 6f and the gate electrodes 4d and 4e, but may further cover the connection holes on the transistor first conductivity type impurity layers 5a and 5f. .

  Next, impurity ions of the first conductivity type are implanted with the same energy as in FIG. 5A using the resist pattern 53 and the interlayer insulating film 6 as a mask. As a result, impurity ions are implanted into the bottom of the transistor first conductivity type impurity layer 5d through the connection hole 6d to form the high concentration first conductivity type impurity layer 7d. Further, impurity ions are further implanted into the high-concentration first conductivity type impurity layer 7e through the connection hole 6d, and the impurity concentration becomes higher than the impurity concentration of the high-concentration first conductivity type impurity layer 7d.

  Next, impurity ions of the second conductivity type are implanted with the same energy as in FIG. 5A using the resist pattern 53 and the interlayer insulating film 6 as a mask. As a result, a diode second conductivity type impurity layer 8d is formed immediately below each of the two high-concentration first conductivity type impurity layers 7d. Further, impurity ions are further implanted into the diode second conductivity type impurity layer 8e, and the impurity concentration thereof is higher than the impurity concentration of the diode second conductivity type impurity layer 8d. In this way, a discharge diode composed of the high concentration first conductivity type impurity layer 7d and the diode second conductivity type impurity layer 8d is formed in the element region 1d, and the high concentration first conductivity type impurity layer 7e and A discharge diode composed of the second conductive type impurity layer 8e for diode is formed in the element region 1e. These two types of diodes have different characteristics because of different impurity concentrations. That is, the diode in the element region 1d has a higher breakdown voltage than the diode in the element region 1e. Here, since gate oxide film 3f is thicker than gate oxide film 3a, the diode in element region 1d has a lower breakdown voltage than gate oxide film 3f, and the diode in element region 1e has a lower breakdown voltage than gate oxide film 3a.

  Next, as shown in FIG. 5C, after removing the resist pattern 53, an Al alloy film is formed by sputtering in all the connection holes and on the interlayer insulating film 6, and this Al alloy film is patterned. Thereby, a plurality of Al alloy wirings are formed on the interlayer insulating film 6. Among these Al alloy wirings, an Al alloy wiring 9a is partly embedded in the connection hole 6a, and the other part is embedded in the connection hole 6e on the first conductivity type impurity layer 5e for a transistor serving as a drain. . A part of the Al alloy wiring 9f is embedded in the connection hole 6f, and the other part is embedded in the connection hole 6d on the first conductivity type impurity layer 5d for transistor serving as a drain. In this way, the Al alloy wiring 9a connects the first conductivity type impurity layer 5e for transistor serving as the drain and the gate electrode 4a to each other, and the Al alloy wiring 9f serves as the first conductivity type impurity layer 5d for transistor serving as the drain and the gate electrode. 4f are connected to each other. The Al alloy wiring 9e is partly buried in the connection hole 6e on the transistor first conductivity type impurity layer 5e serving as the source, thereby connecting to the transistor first conductivity type impurity layer 5e serving as the source.

The transistor and discharge diode formed in this way can obtain the same effect as the transistor and discharge diode formed by the second method, even if the gate oxide films 3a and 3f have different withstand voltages. be able to.
In the present embodiment, the process of implanting the first conductivity type impurity ions from the connection holes 6d and 6e may be omitted. In this case, the high-concentration first conductivity type impurity layers 7d and 7e are not formed at the bottoms of the transistor first conductivity type impurity layers 5d and 5e. The transistor first conductivity type impurity layers 5d and 5e and the diode second conductivity type impurity layers 8d and 8e constitute a discharge diode.

Alternatively, the high-concentration first conductivity type impurity layer 7d may be formed after the diode second conductivity type impurity layer 8d is formed, or after the diode second conductivity type impurity layer 8e is formed, the high concentration first conductivity type. The impurity layer 7e may be formed.
5B, the connection hole 6e may be covered with the resist pattern 53, and the first conductivity type ion implantation may be performed in this state. In this case, impurity ions are not implanted into the high-concentration first conductivity type impurity layer 7e and the second conductivity type impurity layer 8e for diode in the step shown in FIG. In the ion implantation process, it is necessary to implant more ions than the above example into the high-concentration first conductive impurity layer 7e and the second conductive impurity layer 8e for diode.

  FIG. 6 is a cross-sectional view showing a fourth method of forming a transistor and a discharge diode in the internal region 13. In the fourth method, the steps until the formation of the second conductive impurity layer for diode 28b are the same as those in the first method. Therefore, the same components as those in the first method are denoted by the same reference numerals. Description is omitted.

In this method, when the second conductive impurity layer 28b for the diode is formed, a conductive film (for example, a tungsten film) is formed in each of the connection holes 6a and 6b and on the interlayer insulating film 6. Next, by removing the tungsten film from the interlayer insulating film 6 by, for example, CMP, the tungsten plugs 10a and 10b are embedded in the connection holes 6a and 6b, respectively. Next, a metal film is formed on the tungsten plugs 10a and 10b and the interlayer insulating film 6 by a sputtering method. Next, the metal film is patterned to form wirings 9a and 9b.
This fourth method can also achieve the same effect as the first method.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the second and third methods, a tungsten plug is embedded in each connection hole in the same manner as in the fourth embodiment, and the wiring and the first conductivity type impurity layer for the transistor or the second transistor for the transistor are inserted through the tungsten plug. A conductive impurity layer may be connected. Even in this case, the same effect as the second and third methods can be obtained.

1 is a schematic plan view of a semiconductor chip according to an embodiment of the present invention. FIG. 3 is a cross-sectional view showing a first method for forming a transistor and a discharge diode in the internal region 13. Sectional drawing which shows the 2nd method of forming the transistor and the diode for discharge in the internal region 13 Sectional drawing which shows the next process of FIG. Sectional drawing which shows the 3rd method of forming the transistor and the diode for discharge in the internal region 13. FIG. Sectional drawing which shows the 4th method of forming the transistor and the diode for discharge in the internal area | region 13. FIG. 1 is a schematic plan view of a conventional semiconductor chip 100. FIG. Sectional drawing which shows the structure of the circuit element currently formed in the internal area | region 100c.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,101 ... Silicon substrate, 1a, 1b, 1c, 1d, 1e, 1f, 101a, 101b ... Element region, 2,102 ... Element isolation film, 3a, 3b, 3c, 3d, 3e, 3f, 103a, 103b ... Gate oxide film, 4a, 4b, 4c, 4d, 4e, 4f, 104a, 104b ... Gate electrode, 5a, 5d, 5e, 5f, 25a, 25b ... First conductivity type impurity layer for transistors, 5b, 5c ... for transistors Second conductivity type impurity layer, 6, 106 ... interlayer insulating film, 6a, 6b, 6c, 6d, 6e, 6f, 106a, 106b ... connection hole, 7b ... high concentration second conductivity type impurity layer, 7d, 7e, 27b ... high concentration first conductivity type impurity layer, 8b ... first conductivity type impurity layer for diode, 8d, 8e, 28b ... second conductivity type impurity layer for diode, 9a, 9b, 9c, 9d, 9e, 9f, 109a, 109b ... Al alloy wiring, 11,100a ... wiring pad, 12 , 100b ... I / O cell, 13, 13A, 13B, 100c ... internal region, 50, 51, 52, 53 ... resist pattern, 100 ... semiconductor chip, 105a, 105b ... impurity layer

Claims (14)

A first conductivity type impurity layer formed on a semiconductor substrate and functioning as a source or drain of a transistor;
A high concentration first conductivity type impurity layer formed at the bottom of the first conductivity type impurity layer and having a higher impurity concentration than the first conductivity type impurity layer;
A second conductivity type impurity layer formed on the semiconductor substrate and located under the high concentration first conductivity type impurity layer;
An interlayer insulating film formed on the semiconductor substrate;
A connection hole formed in the interlayer insulating film and located on the first conductivity type impurity layer;
A wiring formed on the interlayer insulating film and connected to the first conductivity type impurity layer through the connection hole;
The semiconductor device in which the second conductivity type impurity layer and the high concentration first conductivity type impurity layer constitute a discharge diode. A first conductivity type impurity layer formed on a semiconductor substrate and functioning as a source or drain of a transistor;
A second conductive type impurity layer formed on the semiconductor substrate and located below the first conductive type impurity layer; and an interlayer insulating film formed on the semiconductor substrate;
A connection hole formed in the interlayer insulating film and located on the first conductivity type impurity layer;
A wiring formed on the interlayer insulating film and connected to the first conductivity type impurity layer through the connection hole;
The semiconductor device in which the first conductivity type impurity layer and the second conductivity type impurity layer constitute a discharge diode.   The semiconductor device according to claim 1, wherein the wiring connects the first conductivity type impurity layer and a gate electrode of another transistor.   The semiconductor device according to claim 1, wherein the wiring is connected to the first conductivity type impurity layer by being partially embedded in the connection hole.   The semiconductor device according to claim 1, wherein the wiring is connected to the first conductivity type impurity layer via a conductor embedded in the connection hole. A first conductivity type impurity layer for a transistor formed on a semiconductor substrate and functioning as a source or drain of the first transistor;
A high-concentration first conductivity type impurity layer formed at the bottom of the transistor first conductivity type impurity layer and having an impurity concentration higher than that of the transistor first conductivity type impurity layer;
A second conductive impurity layer for a diode formed on the semiconductor substrate and located under the high-concentration first conductive impurity layer;
A second conductivity type impurity layer for a transistor formed on the semiconductor substrate and functioning as a source or drain of a second transistor;
A high-concentration second conductivity type impurity layer formed at the bottom of the transistor second conductivity type impurity layer and having an impurity concentration higher than that of the transistor second conductivity type impurity layer;
A first conductivity type impurity layer for a diode formed on the semiconductor substrate and located under the high concentration second conductivity type impurity layer;
An interlayer insulating film formed on the semiconductor substrate;
A plurality of connection holes formed in the interlayer insulating film and located on each of the first conductive impurity layer for transistor and the second conductive impurity layer for transistor;
A first wiring formed on the interlayer insulating film and connected to the first conductive impurity layer for transistor via the connection hole on the first conductive impurity layer for transistor; and on the interlayer insulating film And a second wiring connected to the transistor second conductivity type impurity layer through the connection hole on the transistor second conductivity type impurity layer,
The high concentration first conductivity type impurity layer and the diode second conductivity type impurity layer constitute a first discharge diode, and the high concentration second conductivity type impurity layer and the diode first conductivity type impurity layer. Is a semiconductor device constituting a second discharging diode. A first conductivity type impurity layer for a transistor formed on a semiconductor substrate and functioning as a source or drain of the first transistor;
A second conductive impurity layer for a diode formed on the semiconductor substrate and positioned below the first conductive impurity layer for the transistor;
A second conductivity type impurity layer for a transistor formed on the semiconductor substrate and functioning as a source or drain of a second transistor;
A first conductive impurity layer for a diode formed on the semiconductor substrate and positioned below the second conductive impurity layer for the transistor;
An interlayer insulating film formed on the semiconductor substrate;
A plurality of connection holes formed in the interlayer insulating film and located on each of the first conductive impurity layer for transistor and the second conductive impurity layer for transistor;
A first wiring formed on the interlayer insulating film and connected to the first conductive impurity layer for transistor via the connection hole on the first conductive impurity layer for transistor; and on the interlayer insulating film And a second wiring connected to the transistor second conductivity type impurity layer through the connection hole on the transistor second conductivity type impurity layer,
The transistor first conductivity type impurity layer and the diode second conductivity type impurity layer constitute a first discharge diode, and the transistor second conductivity type impurity layer and the diode first conductivity type impurity layer. Is a semiconductor device constituting a second discharging diode. Two first conductivity type impurity layers formed on a semiconductor substrate and functioning as sources or drains of different transistors,
Two high-concentration first conductivity type impurity layers formed at the bottom of each of the two first conductivity type impurity layers, each having an impurity concentration higher than that of the first conductivity type impurity layer;
Two second conductivity type impurity layers formed on the semiconductor substrate and positioned below each of the two high concentration first conductivity type impurity layers;
An interlayer insulating film formed on the semiconductor substrate;
A plurality of connection holes formed in the interlayer insulating film and positioned on each of the two first conductivity type impurity layers;
A first wiring formed on the interlayer insulating film and connected to the one first conductivity type impurity layer via the connection hole on one of the first conductivity type impurity layers; And a second wiring connected to the other first conductivity type impurity layer via the connection hole on the other first conductivity type impurity layer,
At least one set of the two second conductivity type impurity layers and the two high-concentration first conductivity type impurity layers have different impurity concentrations,
Each of the two high-concentration first conductivity type impurity layers forms a discharge diode together with the second conductivity type impurity layer located under each of the high-concentration first conductivity type impurity layers. Two first conductivity type impurity layers formed on a semiconductor substrate and functioning as sources or drains of different transistors,
Two second conductivity type impurity layers formed on the semiconductor substrate and positioned under each of the two first conductivity type impurity layers;
An interlayer insulating film formed on the semiconductor substrate;
A plurality of connection holes formed in the interlayer insulating film and positioned on each of the two first conductivity type impurity layers;
A first wiring formed on the interlayer insulating film and connected to the one first conductivity type impurity layer via the connection hole on one of the first conductivity type impurity layers; And a second wiring connected to the other first conductivity type impurity layer through the connection hole on the other first conductivity type impurity layer,
The two second conductivity type impurity layers have different impurity concentrations,
Each of the two first conductivity type impurity layers forms a discharge diode together with the second conductivity type impurity layer located below each of the first conductivity type impurity layers. Forming a first conductivity type impurity layer functioning as a source or drain of a transistor in the semiconductor substrate by implanting impurity ions of the first conductivity type into the semiconductor substrate;
Forming an interlayer insulating film on the semiconductor substrate;
Forming a connection hole located on the first conductivity type impurity layer in the interlayer insulating film;
By implanting impurity ions of the first conductivity type into the semiconductor substrate through the connection holes, a high concentration first conductivity having an impurity concentration higher than that of the first conductivity type impurity layer is formed at the bottom of the first conductivity type impurity layer. Forming a type impurity layer;
Forming a second conductivity type impurity layer located under the high concentration first conductivity type impurity layer by implanting second conductivity type impurity ions into the semiconductor substrate through the connection hole;
Forming a conductive film on the interlayer insulating film and in the connection hole;
Patterning the conductive film, forming a wiring part of which is embedded in the connection hole and connected to the first conductivity type impurity layer,
The method of manufacturing a semiconductor device, wherein the high-concentration first conductivity type impurity layer and the second conductivity type impurity layer form a discharge diode. Forming a first conductivity type impurity layer functioning as a source or drain of a transistor in the semiconductor substrate by implanting impurity ions of the first conductivity type into the semiconductor substrate;
Forming an interlayer insulating film on the semiconductor substrate;
Forming a connection hole located on the first conductivity type impurity layer in the interlayer insulating film;
By implanting impurity ions of the first conductivity type into the semiconductor substrate through the connection holes, a high concentration first conductivity having an impurity concentration higher than that of the first conductivity type impurity layer is formed at the bottom of the first conductivity type impurity layer. Forming a type impurity layer;
Forming a second conductivity type impurity layer located under the high concentration first conductivity type impurity layer by implanting second conductivity type impurity ions into the semiconductor substrate through the connection hole;
Embedding a conductor in the connection hole;
Forming a conductive film on the interlayer insulating film and on the conductor in the connection hole;
Forming a wiring connected to the first conductivity type impurity layer through the conductor by patterning the conductive film,
The method of manufacturing a semiconductor device, wherein the high-concentration first conductivity type impurity layer and the second conductivity type impurity layer form a discharge diode. Forming a first conductivity type impurity layer functioning as a source or drain of a transistor on the semiconductor substrate by implanting impurity ions of the first conductivity type into the semiconductor substrate;
Forming an interlayer insulating film on the semiconductor substrate;
Forming a connection hole located on the first conductivity type impurity layer in the interlayer insulating film;
Forming a second conductivity type impurity layer under the first conductivity type impurity layer by implanting second conductivity type impurity ions into the semiconductor substrate through the connection hole;
Forming a wiring connected to the first conductivity type impurity layer through the connection hole on the interlayer insulating film,
A method of manufacturing a semiconductor device, wherein the first conductivity type impurity layer and the second conductivity type impurity layer form a discharge diode. By implanting first conductivity type impurity ions into the semiconductor substrate, a first first conductivity type impurity layer and a second first conductivity type impurity layer that respectively function as a source or a drain of the transistor are formed on the semiconductor substrate. And a process of
Forming an interlayer insulating film on the semiconductor substrate;
A first connection hole located on the first first conductivity type impurity layer is formed in the interlayer insulating film, and a second connection hole located on the second first conductivity type impurity layer is formed. Forming, and
Impurity ions of the first conductivity type are implanted into the semiconductor substrate through the first connection hole, and the first conductivity type is implanted into the semiconductor substrate through the first connection hole and the second connection hole, respectively. By implanting impurity ions, a first high-concentration first conductivity type impurity layer having an impurity concentration higher than that of the first conductivity type impurity layer is formed at the bottom of the first first conductivity type impurity layer. Forming a second high concentration first conductivity type impurity layer having an impurity concentration lower than that of the first high concentration first conductivity type impurity layer at the bottom of the second first conductivity type impurity layer;
Impurity ions of the second conductivity type are implanted into the semiconductor substrate through the first connection hole, and the second conductivity type is introduced into the semiconductor substrate through the first connection hole and the second connection hole, respectively. Then, a first second conductivity type impurity layer is formed under the first high concentration first conductivity type impurity layer, and the second high concentration first conductivity type impurity layer is formed. Forming a second second conductivity type impurity layer having an impurity concentration lower than that of the first second conductivity type impurity layer;
A first wiring connected to the first first conductivity type impurity layer is formed on the interlayer insulating film through the first connection hole, and the second wiring is formed through the second connection hole. Forming a second wiring connected to the first conductivity type impurity layer.
The first second conductivity type impurity layer, the first high concentration first conductivity type impurity layer, the second second conductivity type impurity layer, and the second high concentration first conductivity type impurity layer are: A method for manufacturing a semiconductor device, in which a discharge diode is formed. Forming a first conductivity type impurity layer for a transistor functioning as a source or drain of the first conductivity type transistor by implanting first conductivity type impurity ions into the semiconductor substrate;
Forming a second conductivity type impurity layer for a transistor functioning as a source or drain of a second conductivity type transistor by implanting second conductivity type impurity ions into the semiconductor substrate;
Forming an interlayer insulating film on the semiconductor substrate;
Forming a first connection hole located on the first conductivity type impurity layer for the transistor and a second connection hole located on the second conductivity type impurity layer for the transistor in the interlayer insulating film; When,
By implanting first conductivity type impurity ions into the semiconductor substrate through the first connection hole, the impurity concentration at the bottom of the transistor first conductivity type impurity layer is lower than that of the transistor first conductivity type impurity layer. Forming a high-concentration first-conductivity-type impurity layer having a high concentration;
Forming a second conductive type impurity layer for a diode under the high-concentration first conductive type impurity layer by implanting second conductive type impurity ions into the semiconductor substrate through the first connection hole; When,
By implanting second conductivity type impurity ions into the semiconductor substrate through the second connection hole, the impurity concentration at the bottom of the transistor second conductivity type impurity layer is lower than that of the transistor second conductivity type impurity layer. Forming a high-concentration second conductivity type impurity layer having a high concentration;
Forming a first conductive impurity layer for a diode under the high-concentration second conductive impurity layer by implanting first conductive impurity ions into the semiconductor substrate through the second connection hole; When,
A first wiring connected to the first conductivity type impurity layer for the transistor through the first connection hole is formed on the interlayer insulating film, and the transistor wiring through the second connection hole. Forming a second wiring connected to the two-conductivity type impurity layer,
The high concentration first conductivity type impurity layer and the diode second conductivity type impurity layer form a first discharge diode, and the high concentration second conductivity type impurity layer and the diode first conductivity type impurity layer. Is a method of manufacturing a semiconductor device for forming a second discharging diode.

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