JP4601919B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, in a semiconductor device constituted by a semiconductor integrated circuit, high integration has greatly advanced. In particular, in MIS (Metal Insulated semiconductor) type semiconductor devices, in order to cope with high integration, elements such as transistors are miniaturized and enhanced in performance, and further miniaturization and higher performance are required. It has been.
[0003]
Further, in such a semiconductor device wiring formation process, the use of plasma processes such as plasma CVD and plasma etching is increasing. This is because the heat treatment amount is limited in terms of impurity diffusion and heat resistance of the metal wiring material in the wiring formation process of the semiconductor device, and the heat treatment amount can be reduced by the plasma process.
[0004]
Furthermore, in recent years, copper (Cu) wiring is sometimes introduced to improve performance. However, since the damascene method is used for forming copper (Cu) wiring, in this case, plasma is increasingly used. Increased process utilization.
[0005]
Thus, the plasma process is frequently used not only at the time of etching but also at the time of film formation, and the use of the plasma process is increasing year by year. However, as the use of plasma processes increases, device damage due to plasma processes has become apparent. This is mainly called “plasma charging damage” and has been greatly improved in recent years.
[0006]
A semiconductor device that has been subjected to such plasma charging damage is a defective product because the device characteristics deteriorate. Further, in the problem of plasma charging damage, particularly, deterioration of reliability in the gate insulating film is a serious problem.
[0007]
In order to solve such a problem, Patent Document 1 discloses a semiconductor device in which a protective diode is provided on a semiconductor substrate. In the semiconductor device disclosed in Patent Document 1, the charging current that causes plasma charging damage is released to the installation potential via the protection diode. For this reason, it is suppressed that a charging current is applied to the gate insulating film, and destruction of the gate insulating film is avoided.
[0008]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-173157 (20th paragraph, FIGS. 2 to 9)
[0009]
[Problems to be solved by the invention]
However, when the plasma process is performed on the semiconductor substrate on which the protective diode is formed, the following problems may occur. This problem will be described while explaining a conventional method for manufacturing a semiconductor device with reference to FIG.
[0010]
6A and 6B are cross-sectional views showing a process for forming an interlayer insulating film in a conventional semiconductor device. FIG. 6A is a cross-sectional view taken along the normal direction of the semiconductor substrate, and FIG. It is sectional drawing cut | disconnected along the cutting line CC 'shown to (a). The semiconductor device shown in FIG. 6 has a multilayer wiring structure.
[0011]
First, a gate insulating film 36 is formed on a p-type silicon substrate 31 provided with an element isolation 32 and an n well 33. As a method of forming the element isolation 32, an STI (Shallow Trench Isolation) method can be used. Next, a gate electrode 37 is formed on the gate insulating film (film thickness 2.2 nm) 36, and sidewalls 38 are formed on both sides of the gate insulating film 36 and the gate electrode 37. The gate electrode 37 is made of p + polysilicon.
[0012]
Next, an active region (p +) 35, a source (p +) region 34a, and a drain (p +) region 34b that function as a protective diode are formed by ion implantation. As a result, a p-channel MOS transistor including the gate insulating film 6 and the gate electrode 7 is formed. Thereafter, plasma is generated by a plasma CVD apparatus (not shown) to form a first interlayer insulating film 40.
[0013]
Further, a contact hole is formed in the first interlayer insulating film 40 and filled with tungsten to form W plugs 39a to 39c. Thereafter, the wirings 42a, 42b, 43 and 44 are simultaneously formed by using the damascene method. These wirings are copper wirings (thickness 500 nm) and are embedded in the first interlayer insulating film 40.
[0014]
The wiring 42a is formed so as to be connected to the gate electrode 37 through the W plug 39c and to be connected to the active region 35 through the W plug 39b. The wiring 42b is formed so as to be connected to the active region 35 through the W plug 39a.
[0015]
On the other hand, as can be seen from FIG. 6B, the wirings 43 and 44 are dummy wirings for ensuring flatness in a CMP (chemical mechanical polishing) process performed by the damascene method. Further, the entire periphery of the wirings 43 and 44 is insulated by the first insulating layer 40 and the second insulating layer 41 and is in an electrically floating state.
[0016]
Next, plasma is generated by a plasma CVD apparatus (not shown), and a second interlayer insulating film 41 is formed on the first interlayer insulating film 40. Thereafter, in the same manner as described above, W plugs 48a and 48b are formed also in the second interlayer insulating film 41, and wiring 45a, wiring 45b and wiring 46 are further formed. The wiring 46 is a dummy wiring similar to the wirings 43 and 44 described above, and is located immediately above the wirings 43 and 44.
[0017]
Thereafter, as shown in FIG. 6, a third interlayer insulating film 47 is formed on the second interlayer insulating film 41 by generating plasma by a plasma CVD apparatus (not shown). In this manner, a semiconductor device having a desired multilayer wiring structure can be obtained by repeating the formation of the interlayer insulating film, the W plug, and the wiring.
[0018]
As described above, the first interlayer insulating film 40, the second interlayer insulating film 41, and the third interlayer insulating film 47 are formed by a plasma process using a plasma CVD apparatus (not shown). Then, light in the ultraviolet region is emitted from the plasma toward the silicon substrate 31. Further, when such light in the ultraviolet region is incident on the active region 35, the rectification characteristics of the diode are destroyed according to the amount of the incident light, and a leak current in the positive direction is generated between the active region 5 and the n-well 3. The phenomenon of increasing occurs.
[0019]
When such a phenomenon occurs, even if the direction of application of the electric field is the reverse direction (the direction from the silicon substrate to the plasma), the charging current from the plasma 14 is set via the protective diode. The electrical stress applied to the gate insulating film 37 is reduced.
[0020]
However, in the example of FIG. 6, the wiring 44 is located immediately above the active region 35 when the second interlayer insulating film 41 is formed, and the wiring 46 is not formed when the third interlayer insulating film 47 is formed. One is located directly above the active region 35. In FIG. 6B, reference numeral 45 denotes a region obtained by projecting the active region 35 onto the cut surface of the insulating layer 40 along the normal direction of the silicon substrate 31.
[0021]
For this reason, a part of the light in the ultraviolet region radiated from the plasma toward the protective diode is absorbed by the wiring 44 when the second interlayer insulating film 41 is formed, and the wiring is formed when the third interlayer insulating film 48 is formed. 44 and the wiring 46 are absorbed. In this case, it can be said that the amount of light incident on the active region 35 is not sufficient, and the generated leak current in the positive direction is small.
[0022]
Therefore, when the direction of application of the electric field is opposite, a part of the charging current from the plasma does not flow through the protective diode but goes to the gate insulating film 36 and applies electrical stress to the gate insulating film 36. Device characteristics will deteriorate. In the plasma process, the voltage waveform in the plasma CVD apparatus may be switched, and it can be said that the application direction of the electric field to the silicon substrate 31 is not the forward direction but the reverse direction.
[0023]
As described above, in the example shown in FIG. 6, the electric field is generated both when the second interlayer insulating film 41 is formed and when the third interlayer insulating film 48 is formed even though the protective diode is formed. When the application direction is reversed, an electrical stress is applied to the gate insulating film 36 twice. From this, the limit of the role of the protection diode is pointed out.
[0024]
An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can solve the above problems and can suppress plasma charging damage without being affected by the direction of application of an electric field during a plasma process.
[0025]
[Means for Solving the Problems]
To achieve the above object, a first semiconductor device according to the present invention is provided. Manufacturing method Is (A) a step of forming at least a MOS transistor including a stacked body of a gate insulating film and a gate electrode and an active region functioning as a protective diode on a well of the semiconductor substrate; and (b) a plasma on the semiconductor substrate. Forming a first insulating layer covering the stacked body and the active region by a plasma process using a CVD apparatus; and (c) a planarizing dummy wiring in a CMP process on the first insulating layer; A step of simultaneously forming a non-dummy wiring for electrically connecting the gate electrode and the active region using a damascene method; and (d) using a plasma CVD apparatus on the first insulating layer. Forming a second insulating layer by a plasma process, wherein in the step (c), the dummy wiring The active region so as not to overlap with the semiconductor substrate normal direction region obtained by projecting the insulation layer along a line to form said non-dummy wiring and the dummy wiring It is characterized by that.
[0032]
FIG. 5 shows the amount of light in the ultraviolet region incident on the active region functioning as a diode when the second insulating layer is formed by the plasma process when the first semiconductor device manufacturing method is used. It can be increased compared to the sixth example. Therefore, the rectifying characteristics of the diode can be greatly destroyed, and the leakage current in the positive direction in the active region can be increased. For this reason, even when the direction of application of the electric field by the plasma is reversed, the charging current from the plasma can be released to the installation potential via the diode, and the gate insulating film is formed during the plasma process. A semiconductor device can be manufactured while reducing the electrical stress received.
[0033]
In the first method for manufacturing a semiconductor device, ,in front The first insulating layer and the second insulating layer are preferably silicon oxide films or silicon nitride films.
[0034]
In order to achieve the above object, a method for manufacturing a second semiconductor device according to the present invention includes: (a) a semiconductor substrate; Well of A stacked body of a gate insulating film and a gate electrode MOS transistor including When, protection Forming at least an active region functioning as a diode; and (b) on the semiconductor substrate, Using plasma CVD equipment A step of forming a base insulating layer covering the stacked body and the active region by a plasma process; and (c) the base insulating layer, For planarization in CMP processing A first dummy wiring and the gate electrode; When The active region And Electrically connected Do With the first wiring Using damascene method Forming simultaneously, (d) Using plasma CVD equipment A step of forming an insulating layer located above the base insulating layer by a plasma process; and (e) an insulating layer obtained by the step (d), For planarization in CMP processing A second dummy wiring and a second wiring electrically connected to the first wiring; Using damascene method A method of manufacturing a semiconductor device, wherein, in the step (e), the second dummy wiring includes the second active region extending along the normal direction of the semiconductor substrate. The second dummy wiring and the second wiring are formed so as not to overlap with a region obtained by projecting on the insulating layer where the dummy wiring is formed.
[0035]
When the second method for manufacturing a semiconductor device is used, when an insulating layer is further formed on the insulating layer obtained by the step (d) by a plasma process, the light enters the active region functioning as a diode. The amount of light in the ultraviolet region can be increased compared to the example of FIG. 6 shown in the prior art. Therefore, also in the second method for manufacturing a semiconductor device, the rectifying characteristics of the diode can be greatly destroyed to increase the leakage current in the positive direction in the active region, and the electrical current received by the gate insulating film during the plasma process can be increased. A semiconductor device can be manufactured while reducing unnecessary stress.
[0036]
In the second method for manufacturing a semiconductor device, ,in front The base insulating layer and the insulating layer located above the base insulating layer are preferably a silicon oxide film or a silicon nitride film.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
Hereinafter, a semiconductor device and a method of manufacturing the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. First, the configuration of the semiconductor device according to the first embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view partially showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a cross-sectional view taken along the normal direction of a semiconductor substrate constituting the semiconductor device. FIG. 1B is a cross-sectional view taken along a cutting line AA ′ shown in FIG.
[0038]
As shown in FIG. 1A, the semiconductor device according to the first embodiment includes a p-type silicon substrate 1 in the same manner as the semiconductor device shown in FIG. A plurality of element isolations 2 are formed so as to be exposed on the silicon substrate 1 at a predetermined interval.
[0039]
Further, between the element isolations 2 on the silicon substrate 1, similarly to the semiconductor device shown in FIG. 6 in the prior art, an n well 3 formed inside the silicon substrate 1 and a gate insulating film 6. A p-channel MOS transistor is formed by the gate electrode 7 made of p + polysilicon and the source (p +) region 4a and the drain (p +) region 4b provided in the surface layer portion of the silicon substrate 1.
[0040]
The gate insulating film 6 and the gate electrode 7 are formed so as to be aligned with each other like the semiconductor device shown in FIG. 6 in the prior art, and the side walls are formed on both side surfaces so as to cover both side surfaces. 8 is formed. In addition, an active region (p +) 5 that functions as a protective diode is formed in the silicon substrate 1.
[0041]
Further, a first interlayer insulating film 10 is formed on the silicon substrate 1 in the same manner as the semiconductor device shown in FIG. 6 in the prior art. A second interlayer insulating film is formed on the first interlayer insulating film 10. A film 11 is formed. Furthermore, wiring 12 a, wiring 12 b, and wiring 13 are formed in the first interlayer insulating film 10. The first interlayer insulating film 10 and the second interlayer insulating film 11 are silicon oxide films or silicon nitride films.
[0042]
The wiring 12 a, the wiring 12 b, and the wiring 13 are copper wirings (thickness 500 nm) formed simultaneously by the damascene method, and are embedded in the first interlayer insulating film 10. Among these wirings, the wiring 13 is a dummy wiring for ensuring flatness in the CMP process performed by the damascene method. The entire periphery of the wiring 13 is insulated by the first interlayer insulating film 10 and the second interlayer insulating film 11, and the wiring 13 is in an electrically floating state. Further, as shown in FIG. 1B, the wiring 13 is composed of a plurality of pieces and is formed in a square shape.
[0043]
On the other hand, the wirings 12a and 12b are non-dummy wirings. The wiring 12a is connected to the active region 5 through the W plug 9a. The wiring 12b is connected to the active region 5 through the W plug 9b and is connected to the gate electrode 7 through the W plug 9c. In the first embodiment, as shown in FIG. 1B, the wirings 12a and 12b are formed in a strip shape.
[0044]
The W plugs 9a to 9c are formed by filling tungsten in the contact holes formed in the first interlayer insulating film 10 in the same manner as the W plugs 39a to 39c shown in FIG.
[0045]
As described above, the semiconductor device according to the first embodiment has the same configuration as the semiconductor device shown in FIG. 6 in the prior art, but is different from the conventional semiconductor device as described below. Has a point.
[0046]
In the first embodiment, as shown in FIG. 1B, unlike the semiconductor device shown in FIG. 6 in the prior art, the wiring 13 which is a dummy wiring has the active region 5 in the normal direction of the silicon substrate 1. Are arranged so as not to overlap with a region (projected region) 15 obtained by projecting on the first interlayer insulating layer 10 along the line. That is, as can be seen from FIG. 1B, in the first embodiment, the dummy wiring 13 does not exist above the active region 5 that functions as a protective diode. For this reason, when the second interlayer insulating film 11 is formed by a plasma process, the amount of light in the ultraviolet region incident on the active region 5 is larger than in the example of FIG. 6 shown in the prior art. This will be described below.
[0047]
The operation of the semiconductor device manufacturing method and the dummy wiring according to the first embodiment will be described with reference to FIG. FIG. 2 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 2 shows a step of forming the second interlayer insulating film 11 constituting the semiconductor device shown in FIG.
[0048]
First, the gate insulating film 6 is formed on the silicon substrate 1 provided with the element isolation 2 and the n-well 3. Next, a gate electrode 7 is formed on the gate insulating film 6, and sidewalls 8 are formed on both sides of the gate insulating film 6 and the gate electrode 7. Next, for example, boron (B) ions are implanted to form the active region 5, the source (p +) region 4a, and the drain (p +) region 4b.
[0049]
Thereafter, plasma is generated by a plasma CVD apparatus (not shown) to form the first interlayer insulating film 10. At this time, since the wiring connected to the gate electrode 7 has not yet been formed, no charging current is generated by plasma.
[0050]
Next, a contact hole in which one end portion of the active region 5 is exposed on the bottom surface, a contact hole in which the other end portion of the active region 5 is exposed on the bottom surface, and a gate on the bottom surface are formed in the first interlayer insulating layer 10 serving as a base interlayer insulating film. Contact holes where the electrodes 7 are exposed are formed, and tungsten is filled into these contact holes to form W plugs 9a to 9c.
[0051]
Thereafter, the wiring 12a, the wiring 12b, and the wiring 13 are simultaneously formed by using the damascene method. Specifically, first, a groove is formed at a position where the wiring of the base interlayer insulating film 10 is to be provided. However, it is necessary to lay out the grooves constituting the wirings 13 serving as dummy wirings so as not to overlap the projection region 5. Next, a copper layer is formed so that the groove formed in the base interlayer insulating film 10 is filled, and the excess thickness is removed by polishing by a CMP method.
[0052]
Next, as shown in FIG. 2, plasma 14 is generated by a plasma CVD apparatus (not shown) to form a second interlayer insulating film 11. At this time, in the first embodiment, there is no dummy wiring on the projection region 15, so that more ultraviolet rays in the active region 5 than in the example of FIG. 6 shown in the prior art. Incident. For this reason, the rectification characteristic of the diode is greatly deteriorated, and the leak current in the positive direction increases between the active region 5 and the n-well 3.
[0053]
As a result, in the first embodiment, even when the direction of application of the electric field is reversed, the charging current from the plasma 14 is set via the protection diode as shown by the arrow in FIG. Escape to potential. Even when the rectification characteristic of the diode is greatly broken and the application direction of the electric field becomes the positive direction, the charging current is released to the installation potential via the protection diode without any problem.
[0054]
As described above, in the first embodiment, the charging current can be supplied to the protection diode regardless of the direction of application of the electric field during the plasma process. For this reason, compared with the prior art, the electrical stress which a gate insulating film receives can be reduced, and deterioration of a device characteristic can be suppressed.
[0055]
Here, the effects of the semiconductor device and the method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. FIG. 3 is a diagram illustrating a characteristic curve of a transistor element included in the semiconductor device according to the first embodiment of the present invention. FIG. 4 is an enlarged view of the saturation region of the characteristic curve shown in FIG.
[0056]
This transistor element is a p-channel MOS transistor as described above. 3 and 4, the horizontal axis represents the gate voltage, and the vertical axis represents the drain current. The drain voltage is set to 1.2 [V].
[0057]
The conventional semiconductor device shown in FIGS. 3 and 4 is the semiconductor device shown in FIG. 6, and FIG. 3 and FIG. 4 also show the characteristic curves of the p-channel MOS transistors that constitute the semiconductor device shown in FIG. Yes.
[0058]
As can be seen from FIG. 3 and FIG. 4, the transistor element constituting the semiconductor device according to the first embodiment has a driving capability improved by 5% or more compared to the transistor element constituting the conventional semiconductor device ( (Embodiment 1: 138 uA / um, conventional: 134 uA / um). This indicates that according to the first embodiment, plasma charging damage in the gate insulating film can be suppressed and device characteristics can be improved as compared with the conventional case.
[0059]
In the first embodiment, the semiconductor device may have a multilayer wiring structure. Further, for example, as shown in FIG. 6 in the prior art, when the wiring layer has two layers, the electric field application direction is expected to be reversed only when the first interlayer insulating film is formed. The dummy wiring formed in the second interlayer insulating film may be arranged at a position overlapping the projection region.
[0060]
(Embodiment 2)
Next, a semiconductor device and a method for manufacturing the semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view partially showing the configuration of the semiconductor device according to the second embodiment of the present invention. FIG. 5A is a cross-section taken along the normal direction of the semiconductor substrate constituting the semiconductor device. FIG. 5 and FIG. 5B are cross-sectional views taken along the cutting line BB ′ shown in FIG. In FIG. 5, the parts denoted by the same reference numerals as those shown in FIG. 1 are the same as those shown in FIG. 1.
[0061]
As shown in FIGS. 5A and 5B, also in the semiconductor device according to the second embodiment, wirings 21 to 24 and 29 are provided in the first interlayer insulating film 10 by the damascene method. The wirings 24 and 29 are dummy wirings similar to the wiring 13 shown in FIG. 1 in the first embodiment, and are formed in a square shape. Further, the wiring 21, the wiring 22, and the wiring 23 are non-dummy wirings similar to the wirings 12a and 12b illustrated in FIG. 1 in the first embodiment, and have a strip shape as in the first embodiment. Yes.
[0062]
However, in the second embodiment, unlike the first embodiment, the wiring 29 among the dummy wirings is formed so as to overlap the projection region 15. Therefore, when the second interlayer insulating film 11 and the third interlayer insulating film 28 described later are formed by the plasma process, the ultraviolet region radiated from the plasma is emitted in the same manner as the semiconductor device described with reference to FIG. Among these light beams, a part of the light beams traveling toward the protection diode is absorbed by the wiring 29.
[0063]
Note that the layout of the wiring 21, the wiring 22, and the wiring 23 is different from that of the first embodiment. The wiring 23 is connected to the active region 5 via the W plug 9a, and the wiring 22 is connected to the active region 5 via the W plug 9b. The wiring 21 is connected to the gate electrode 7 through the W plug 9c.
[0064]
On the other hand, in the second embodiment, wirings 25 and 26 that are non-dummy wirings and wirings 30 that are dummy wirings are also formed in the second interlayer insulating film 11 to form a multilayer wiring structure. . A third interlayer insulating film 28 is formed on the second interlayer insulating film 11 by a plasma process. Note that the wiring 25 is connected to the wiring 23 through the W plug 27a, and the wiring 26 is connected to the wiring 22 through the W plug 27b.
[0065]
Further, as shown in FIG. 5B, the wiring 30 that is a dummy wiring is disposed only directly above the wiring 24 that does not overlap the projection region 15, and the active region 5 extends along the normal direction of the silicon substrate 1. The second interlayer insulating layer 11 is disposed so as not to overlap with a region (not shown) obtained by projection.
[0066]
Therefore, in the third embodiment, unlike the example described with reference to FIG. 6 in the prior art, the third interlayer insulating film 28 is formed by the dummy wiring (wiring 29) formed in the second interlayer insulating film 11. During the film formation, light in the ultraviolet region toward the active region 5 is not absorbed. Therefore, compared with the example of FIG. 6 shown in the prior art, the amount of light in the ultraviolet region incident on the active region 5 when the third interlayer insulating film 28 is formed is large, and the electrical stress received by the gate insulating film 6 is It is getting smaller.
[0067]
Therefore, in the second embodiment, the electric field is applied in the opposite direction both when the second interlayer insulating film 11 is formed and when the third interlayer insulating film 28 is formed. However, it can be said that the total electrical stress applied to the gate insulating film 6 until the completion of the semiconductor device is smaller than that of the example of FIG.
[0068]
In addition, assuming charging damage when forming an interlayer insulating film formed on the wiring located in the upper layer, it is not possible to prevent the dummy wiring located in a lower layer than the wiring from overlapping the projection area. More man-hours are required than necessary for mask data and design rule check for wiring formation, which is not efficient. Therefore, in the semiconductor device and the method for manufacturing the semiconductor device according to the second embodiment, in particular, when the third interlayer insulating film 28 is formed, the application direction of the electric field is reversed or the possibility thereof. Effective when is high.
[0069]
In the second embodiment, the case where the interlayer insulating film provided with the wiring has two layers has been described. However, the second embodiment is not limited to this, and the interlayer provided with the wiring is not limited thereto. There may be three or more insulating films. In this case, only the dummy wirings directly under the interlayer insulating film where charging damage is expected to occur may be formed so as not to overlap the projection region.
[0070]
The semiconductor device and the method for manufacturing the semiconductor device according to the present invention are not limited to the first and second embodiments described above. For example, in Embodiments 1 and 2, the dummy wiring has a rectangular shape in order to enhance the effect in the CMP process and to make it easy to make a rule. However, in the present invention, the shape of the dummy wiring is particularly limited. It is not something.
[0071]
In the first and second embodiments, the W plug is used for the connection between the dummy wiring and the active region, the connection between the gate electrode connection wiring and the gate electrode, etc., but the Cu plug is used. You can also. Further, instead of providing such a plug, a dual damascene structure may be used.
[0072]
In the first and second embodiments, the wiring is a Cu wiring, but the present invention is not limited to this, and the wiring may be formed of a metal material, and may be an Al wiring. . In the case of Al wiring, the wiring may be formed by etching. In this case, the dummy wiring may be an alignment wiring for alignment confirmation in a lithography method performed before etching.
[0073]
【The invention's effect】
As described above, according to the semiconductor device and the manufacturing method of the semiconductor device according to the present invention, the semiconductor device and the manufacturing method thereof that can suppress the plasma charging damage without being affected by the direction of application of the electric field during the plasma process. Can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view partially showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a cross-sectional view taken along a normal direction of a semiconductor substrate constituting the semiconductor device. FIG. 1B is a cross-sectional view taken along a cutting line AA ′ shown in FIG.
FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the invention.
FIG. 3 is a diagram illustrating a characteristic curve of a transistor element included in the semiconductor device according to the first embodiment of the present invention.
4 is an enlarged view of a saturation region of the characteristic curve shown in FIG.
FIG. 5 is a cross-sectional view partially showing a configuration of a semiconductor device according to a second exemplary embodiment of the present invention, and FIG. 5A is a cross section cut along a normal direction of a semiconductor substrate constituting the semiconductor device; FIG. 5 and FIG. 5B are cross-sectional views taken along the cutting line BB ′ shown in FIG.
6A and 6B are cross-sectional views illustrating a process for forming an interlayer insulating film in a conventional semiconductor device, in which FIG. 6A is a cross-sectional view taken along the normal direction of the semiconductor substrate, and FIG. It is sectional drawing cut | disconnected along the cutting line CC 'shown to (a).
[Explanation of symbols]
1 p-type silicon substrate
2 element isolation
3 n-well
4a Source (p +) region
4b Drain (p +) region
5 Active region (p +)
6 Gate insulation film
7 Gate electrode
8 Sidewall
9a-9c, 27a, 27b W plug
10 First interlayer insulating film
11 Second interlayer insulating film
12a, 12b, 21, 22, 23, 25, 26 Wiring (non-dummy wiring)
13, 24, 29, 30 Wiring (dummy wiring)
14 Plasma
15 Projection area
28 Third interlayer insulating film

Claims (4)

(A) forming at least a MOS transistor including a stacked body of a gate insulating film and a gate electrode and an active region functioning as a protection diode on a well of a semiconductor substrate;
(B) on the semiconductor substrate, by a plasma process using a plasma CVD apparatus, forming a first insulating layer covering the laminate and the active region,
(C) simultaneously forming a planarization dummy wiring in a CMP process and a non-dummy wiring electrically connecting the gate electrode and the active region on the first insulating layer using a damascene method ; ,
(D) on the first insulating layer, by a plasma process using a plasma CVD device, a manufacturing method of a semiconductor device having a step of forming a second insulating layer,
In the step (c), the dummy wiring and the non-dummy are arranged so that the dummy wiring does not overlap with a region obtained by projecting the active region onto the insulating layer along the normal direction of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: forming a wiring. The first insulating layer and the second insulating layer, a method of manufacturing a semiconductor device according to claim 1, wherein a silicon oxide film or a silicon nitride film. (A) forming at least a MOS transistor including a stacked body of a gate insulating film and a gate electrode and an active region functioning as a protection diode on a well of a semiconductor substrate;
(B) forming a base insulating layer covering the stacked body and the active region on the semiconductor substrate by a plasma process using a plasma CVD apparatus ;
(C) A first dummy wiring for planarization in a CMP process and a first wiring for electrically connecting the gate electrode and the active region are simultaneously formed on the base insulating layer using a damascene method. And a process of
(D) forming an insulating layer positioned above the base insulating layer by a plasma process using a plasma CVD apparatus ;
(E) the insulating layer obtained by a process of (d), a damascene and a second dummy wiring for planarization in the CMP process, and a second wiring electrically connected to said first wiring A method of manufacturing a semiconductor device having a step of simultaneously forming using a method,
In the step (e), the second dummy wiring is obtained by projecting the active region onto the insulating layer where the second dummy wiring is formed along the normal direction of the semiconductor substrate. Forming the second dummy wiring and the second wiring so as not to overlap each other. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the base insulating layer and the insulating layer located on the base insulating layer are a silicon oxide film or a silicon nitride film.

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