JP2005311182A - Board and semiconductor device - Google Patents

Board and semiconductor device Download PDF

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JP2005311182A
JP2005311182A JP2004128462A JP2004128462A JP2005311182A JP 2005311182 A JP2005311182 A JP 2005311182A JP 2004128462 A JP2004128462 A JP 2004128462A JP 2004128462 A JP2004128462 A JP 2004128462A JP 2005311182 A JP2005311182 A JP 2005311182A
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substrate
semiconductor element
thermal expansion
expansion coefficient
board
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JP4291729B2 (en
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Takayuki Nagasaki
貴幸 長崎
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a board and a semiconductor device that reduces thermal expansion coefficient difference between the board and semiconductor element, and that between the board and the mounting board, to prevent the semiconductor element and mounting board from being damaged and enable precious board manufacturing, in terms of boards and semiconductor devices which electrically connect semiconductor elements and mounting boards having different basic thermal expansion coefficients. <P>SOLUTION: A board comprises a metal base material 42 and a resin 38; a through hole 37 is formed on a metal base material 42 corresponding to a connection area A to which a semiconductor element 31 is connected; a through hole 36 with a diameter larger than that of the through hole 37 is formed on the metal base material 42, corresponding to a connection area B to which a mount board 41 is connected; then a resin 38 is applied to both through holes 36 and 37. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、基板及び半導体装置に係り、特に熱膨張係数の異なる半導体素子と実装基板とを電気的に接続する基板及び半導体装置に関する。   The present invention relates to a substrate and a semiconductor device, and more particularly to a substrate and a semiconductor device that electrically connect semiconductor elements having different thermal expansion coefficients and a mounting substrate.

従来、熱膨張係数の異なる半導体素子と実装基板との間を電気的に接続するために、半導体素子の熱膨張係数と実装基板の熱膨張係数との略中間の熱膨張係数を有した基板が用いられている。このような基板には、基材が樹脂の基板や、板状の金属基材の両面に樹脂を設けた基板がある。   Conventionally, in order to electrically connect between a semiconductor element having a different thermal expansion coefficient and a mounting board, a board having a thermal expansion coefficient substantially in the middle of the thermal expansion coefficient of the semiconductor element and the mounting board has been provided. It is used. Such a substrate includes a substrate whose base material is a resin and a substrate in which a resin is provided on both surfaces of a plate-like metal base material.

図１は、半導体素子と実装基板とを接続した従来の金属基材を備えた基板の断面図である。図１に示すように、半導体素子１４は、基板１０に対してはんだバンプ１５によりフリップチップ実装されており、半導体素子１４と基板１０との間には、アンダーフィル樹脂１６が設けられている。実装基板１８は、基板１０に対してはんだボール１７を介して接続されている。また、半導体素子１４は、複数の配線及び絶縁層を有した多層配線構造とされている。   FIG. 1 is a cross-sectional view of a substrate provided with a conventional metal base material in which a semiconductor element and a mounting substrate are connected. As shown in FIG. 1, the semiconductor element 14 is flip-chip mounted on the substrate 10 with solder bumps 15, and an underfill resin 16 is provided between the semiconductor element 14 and the substrate 10. The mounting substrate 18 is connected to the substrate 10 via solder balls 17. The semiconductor element 14 has a multilayer wiring structure having a plurality of wirings and an insulating layer.

基板１０は、金属基材１１と、樹脂部材１２，１３と、図示していないビアとを有した構成とされている。金属基材１１は、平板状の金属板であり、その両面には樹脂部材１２，１３が設けられている。また、金属基板１１には、半導体素子１４と実装基板１８との間を電気的に接続するためのビアが形成されている（例えば、特許文献１参照。）。   The substrate 10 is configured to include a metal base material 11, resin members 12 and 13, and vias (not shown). The metal substrate 11 is a flat metal plate, and resin members 12 and 13 are provided on both surfaces thereof. In addition, a via for electrically connecting the semiconductor element 14 and the mounting substrate 18 is formed in the metal substrate 11 (see, for example, Patent Document 1).

このように、基板１０に金属基材１１を設け、金属基板１１の材料や厚さ等を適宜選択することで、基板１０全体の熱膨張係数を所望の値に変えることができる。また、このような基板１０は、大きな板状のパネルに複数の基板１０を形成した後に個々の基板１０を切り出すことで製造される。
特開２００３−３０４０６３号公報 Thus, by providing the metal base 11 on the substrate 10 and appropriately selecting the material, thickness and the like of the metal substrate 11, the thermal expansion coefficient of the entire substrate 10 can be changed to a desired value. Moreover, such a substrate 10 is manufactured by cutting out individual substrates 10 after forming a plurality of substrates 10 on a large plate-like panel.
JP 2003-304063 A

近年の半導体素子１４の高速動作化の要求に伴い、半導体素子１４の絶縁層として誘電率の低いＳｉＯＦ等のウルトラロウＫ材料が適用されている。しかし、このようなウルトラロウＫ材料により形成された絶縁層は、強度が弱くもろいため、従来のように基板１０の熱膨張係数を半導体素子１４と実装基板１８との熱膨張係数の略中間の値に設定した場合には、半導体素子１４と基板１０との間の熱膨張係数の差により、半導体素子１４に設けられた絶縁層が剥がれて、半導体素子１４が破損するという問題があった。   With the recent demand for high-speed operation of the semiconductor element 14, an ultra-low K material such as SiOF having a low dielectric constant is applied as the insulating layer of the semiconductor element 14. However, since the insulating layer formed of such an ultra-low K material is weak and fragile, the thermal expansion coefficient of the substrate 10 is approximately half the thermal expansion coefficient between the semiconductor element 14 and the mounting substrate 18 as in the prior art. When the value is set, there is a problem that the insulating layer provided on the semiconductor element 14 is peeled off due to a difference in thermal expansion coefficient between the semiconductor element 14 and the substrate 10 and the semiconductor element 14 is damaged.

また、基板１０の熱膨張係数を半導体素子１４の熱膨張係数に近づけて、ウルトラロウＫ材料により形成された絶縁層の剥がれを抑制した場合には、基板１０と実装基板１８との間の熱膨張係数の差が大きくなってしまい、実装基板１８が破損してしまうという問題があった。   Further, when the thermal expansion coefficient of the substrate 10 is brought close to the thermal expansion coefficient of the semiconductor element 14 and the peeling of the insulating layer formed of the ultra-low K material is suppressed, the heat between the substrate 10 and the mounting substrate 18 is suppressed. There is a problem that the difference in the expansion coefficient becomes large and the mounting substrate 18 is damaged.

さらに、基板１０に設けられた金属基材１１は、平板状の金属板であるため、曲げ剛性が弱いため、基板１０の製造工程において、パネルに反りが発生してしまい、基板１０を精度良く加工できないというという問題や、パネルの反りが大きい場合には、加工装置で搬送できないという問題があった。また、金属基材１１が平板状の金属板であるため、基板１０の重量が重くなり、加工装置で吸着等により搬送する際、吸着部からパネルが落ちてしまうという問題があった。   Furthermore, since the metal base material 11 provided on the substrate 10 is a flat metal plate, the bending rigidity is weak, so that the panel is warped in the manufacturing process of the substrate 10, and the substrate 10 is accurately processed. There was a problem that it could not be processed, and there was a problem that it could not be transported by the processing device when the panel warp was large. In addition, since the metal base 11 is a flat metal plate, the weight of the substrate 10 is increased, and there is a problem that the panel falls from the suction portion when transported by suction or the like with a processing apparatus.

そこで本発明は、上述した問題点に鑑みなされたものであり、基板と半導体素子との間の熱膨張係数の差、及び基板と実装基板との間の熱膨張係数の差を小さくして、半導体素子及び実装基板が破損することを防止すると共に、基板を精度良く加工することのできる基板及び半導体装置を提供することを目的とする。   Therefore, the present invention has been made in view of the above-described problems, and reduces the difference in thermal expansion coefficient between the substrate and the semiconductor element and the difference in thermal expansion coefficient between the substrate and the mounting substrate. An object of the present invention is to provide a substrate and a semiconductor device capable of preventing the semiconductor element and the mounting substrate from being damaged and processing the substrate with high accuracy.

上記課題を解決するために本発明では、次に述べる各手段を講じたことを特徴とするものである。   In order to solve the above-mentioned problems, the present invention is characterized by the following measures.

請求項１記載の発明では、板状の金属基材と、半導体素子が接続される第１の接続領域と、実装基板が接続される第２の接続領域とを備え、前記半導体素子及び実装基板が接続される基板であって、前記第１の接続領域に対応する前記金属基材に設けられた第１の貫通穴と、前記第２の接続領域に対応する前記金属基材に、前記第１の貫通穴と穴径及び／又は穴の配設ピッチの異なる第２の貫通穴を設けたことを特徴とする基板により、解決できる。   The invention according to claim 1 includes a plate-shaped metal base, a first connection region to which a semiconductor element is connected, and a second connection region to which a mounting substrate is connected, the semiconductor element and the mounting substrate. Connected to the metal base corresponding to the first connection region, and the metal base corresponding to the second connection region, the first through-hole provided in the metal base corresponding to the first connection region This can be solved by a substrate characterized in that a second through hole having a different through hole and hole diameter and / or hole arrangement pitch is provided.

上記発明によれば、半導体素子が接続される第１の接続領域に対応する金属基材に第１の貫通穴を設け、実装基板が接続される第２の接続領域に対応する金属基材に第１の貫通穴と穴径及び／又は穴の配設ピッチの異なる第２の貫通穴を設けることにより、第１の接続領域の熱膨張係数と第２の接続領域の熱膨張係数とを異ならせて、第１の接続領域と半導体素子との熱膨張係数の差、及び第２の接続領域と実装基板との熱膨張係数の差を小さくして、半導体素子及び実装基板の破損を防止することができる。また、基板に第１及び第２の貫通穴を設けたことにより、基板の反りを抑制することができる。   According to the above invention, the first through hole is provided in the metal base corresponding to the first connection region to which the semiconductor element is connected, and the metal base corresponding to the second connection region to which the mounting substrate is connected is provided. By providing a second through hole having a hole diameter and / or hole arrangement pitch different from that of the first through hole, the thermal expansion coefficient of the first connection region is different from the thermal expansion coefficient of the second connection region. Accordingly, the difference in the thermal expansion coefficient between the first connection region and the semiconductor element and the difference in the thermal expansion coefficient between the second connection region and the mounting substrate are reduced to prevent the semiconductor element and the mounting substrate from being damaged. be able to. Moreover, the board | substrate curvature can be suppressed by providing the 1st and 2nd through-hole in a board | substrate.

請求項２記載の発明では、前記第１及び第２の貫通穴には、樹脂を埋め込むことを特徴とする請求項１に記載の基板により、解決できる。   The invention according to claim 2 can be solved by the substrate according to claim 1, wherein resin is embedded in the first and second through holes.

上記発明によれば、第１及び第２の貫通穴に樹脂を埋め込むことで、金属基材を構成する金属と樹脂との熱膨張係数の違いにより、第１の接続領域の熱膨張係数と第２の接続領域の熱膨張係数とを異ならせることができる。   According to the invention, by embedding the resin in the first and second through holes, the thermal expansion coefficient of the first connection region and the first The thermal expansion coefficient of the two connection regions can be made different.

請求項３記載の発明では、請求項１または２に記載の基板と、前記基板に接続される半導体素子とを備えたことを特徴とする半導体装置により、解決できる。   The invention according to claim 3 can be solved by a semiconductor device comprising the substrate according to claim 1 or 2 and a semiconductor element connected to the substrate.

上記発明によれば、請求項１または２に記載の基板と、基板に接続される半導体素子とを備えたことにより、基板と半導体素子との間の熱膨張係数の差を小さくして、半導体素子が破損することを防止できる。   According to the above invention, since the substrate according to claim 1 or 2 and the semiconductor element connected to the substrate are provided, the difference in thermal expansion coefficient between the substrate and the semiconductor element is reduced, and the semiconductor It is possible to prevent the element from being damaged.

本発明は、基板と半導体素子との間の熱膨張係数の差、及び基板と実装基板との間の熱膨張係数の差を小さくして、半導体素子及び実装基板が破損することを防止すると共に、基板を精度良く加工することのできる基板及び半導体装置を提供することができる。   The present invention reduces the difference in thermal expansion coefficient between the substrate and the semiconductor element and the difference in thermal expansion coefficient between the substrate and the mounting board, and prevents the semiconductor element and the mounting board from being damaged. A substrate and a semiconductor device capable of processing the substrate with high accuracy can be provided.

次に、図面に基づいて本発明の実施例を説明する。   Next, embodiments of the present invention will be described with reference to the drawings.

（実施例）
始めに、図２を参照して、本発明の実施例による半導体装置３０について説明する。図２は、実装基板に実装された本発明の実施例による半導体装置の断面図である。なお、図２において、Ａは半導体素子３１がはんだバンプ３２を介して基板３５に接続される領域（以下、接続領域Ａ）、Ｂは実装基板４１がはんだボール３９を介して基板３５に接続される領域（以下、接続領域Ｂ）をそれぞれ示している。接続領域Ａは、第１の接続領域であり、接続領域Ｂは、第２の接続領域である。 (Example)
First, a semiconductor device 30 according to an embodiment of the present invention will be described with reference to FIG. FIG. 2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention mounted on a mounting substrate. In FIG. 2, A is a region where the semiconductor element 31 is connected to the substrate 35 via the solder bump 32 (hereinafter referred to as connection region A), and B is a mounting substrate 41 connected to the substrate 35 via the solder ball 39. Each region (hereinafter referred to as connection region B) is shown. The connection area A is a first connection area, and the connection area B is a second connection area.

半導体装置３０は、半導体素子３１と、基板３５とを有した構成とされている。半導体素子３１は、複数の配線及び絶縁層から構成されており、絶縁層には、半導体素子３１の高速動作を可能とするための低誘電率のウルトラロウＫ材料が適用されている。ウルトラロウＫ材料には、例えば、ＳｉＯ２に数％程度のフッ素をドーピングしたＳｉＯＦ膜がある。 The semiconductor device 30 is configured to include a semiconductor element 31 and a substrate 35. The semiconductor element 31 is composed of a plurality of wirings and an insulating layer, and an ultra-low K material having a low dielectric constant for enabling the semiconductor element 31 to operate at high speed is applied to the insulating layer. Examples of the ultra low K material include a SiOF film in which SiO 2 is doped with about several percent of fluorine.

このような構成とされた半導体素子３１は、基板３５の接続領域Ａにおいて、はんだバンプ３２を介して基板３５にフリップチップ実装されている。また、半導体素子３１と基板３５との間には、アンダーフィル樹脂３３が設けられている。   The semiconductor element 31 having such a configuration is flip-chip mounted on the substrate 35 via the solder bumps 32 in the connection region A of the substrate 35. An underfill resin 33 is provided between the semiconductor element 31 and the substrate 35.

実装基板４１は、複数の基板３５を取り付ける大きさがあり、基板３５と接続できる接続端子を有したプリント配線板であり、より具体的には、例えば、マザーボード等である。実装基板４１は、基板３５の接続領域Ｂにおいて、はんだボール３９を介して基板３５に接続されている。   The mounting substrate 41 is a printed wiring board having a size for attaching a plurality of substrates 35 and having connection terminals that can be connected to the substrate 35, and more specifically, for example, a mother board. The mounting substrate 41 is connected to the substrate 35 via solder balls 39 in the connection region B of the substrate 35.

基板３５は、多層配線構造を有したプリント回路板であり、大略すると金属基材４２と、樹脂３８と、ビア（図示せず）とを有した構成とされている。基板３５は、異なる熱膨張係数を有した半導体素子３１と実装基板４１とを電気的に接続するためのものである。半導体素子３１と実装基板４１との間は、金属基材４２を貫通するビアにより電気的に接続される。   The substrate 35 is a printed circuit board having a multilayer wiring structure, and is roughly configured to include a metal base material 42, a resin 38, and vias (not shown). The substrate 35 is for electrically connecting the semiconductor element 31 and the mounting substrate 41 having different thermal expansion coefficients. The semiconductor element 31 and the mounting substrate 41 are electrically connected by vias penetrating the metal base material 42.

図３は、金属基材の平面図である。図２及び図３に示すように、金属基材４２は、平板状の金属板であり、金属基材４２には、例えば、Ｆｅ−Ｎｉ合金（混合比１：１）を用いることができる。金属基材４２の両面には、樹脂３８が設けられている。金属基材４２の接続領域Ａに対応する部分には、第１の貫通穴である貫通穴３７が複数形成されており、この貫通穴３７には樹脂３８が充填されている。貫通穴３７は、従来のエッチング法により形成することができる。樹脂３８には、例えば、エポキシ系樹脂を用いることができる。   FIG. 3 is a plan view of the metal substrate. As shown in FIGS. 2 and 3, the metal substrate 42 is a flat metal plate. For the metal substrate 42, for example, an Fe—Ni alloy (mixing ratio 1: 1) can be used. Resin 38 is provided on both surfaces of the metal substrate 42. A plurality of through holes 37 that are first through holes are formed in a portion corresponding to the connection region A of the metal base material 42, and the through holes 37 are filled with a resin 38. The through hole 37 can be formed by a conventional etching method. For example, an epoxy resin can be used as the resin 38.

このように、半導体素子３１がはんだバンプ３２を介して基板３５に接続される接続領域Ａに対応する金属基材４２に複数の貫通穴３７を形成し、これら複数の貫通穴３７に樹脂３８を充填することで、接続領域Ａに対応した金属基材４２の熱膨張係数を貫通穴が設けられていない金属部材４２部分の熱膨張係数と異ならせることができる。   In this way, a plurality of through holes 37 are formed in the metal base material 42 corresponding to the connection region A where the semiconductor element 31 is connected to the substrate 35 via the solder bumps 32, and the resin 38 is placed in the plurality of through holes 37. By filling, the thermal expansion coefficient of the metal base material 42 corresponding to the connection region A can be made different from the thermal expansion coefficient of the metal member 42 portion where no through hole is provided.

このように、接続領域Ａに対応した金属基材４２に複数の貫通穴３７を形成し、これら複数の貫通穴３７に樹脂３８を充填することで、接続領域Ａに対応した金属基材４２の熱膨張係数と半導体素子３１の熱膨張係数との差が小さくなるように、接続領域Ａに対応した金属基材４２の熱膨張係数を設定して、熱膨張係数の差により半導体素子３１の絶縁層が損傷し、半導体装置３１が破損することを防止できる。また、貫通穴３７の穴径、形状、配設ピッチ等を適宜選択することで、接続領域Ａに対応した金属基材４２の熱膨張係数を所望の値に変えることができる。   Thus, by forming a plurality of through holes 37 in the metal base material 42 corresponding to the connection region A and filling the plurality of through holes 37 with the resin 38, the metal base material 42 corresponding to the connection region A The thermal expansion coefficient of the metal base material 42 corresponding to the connection region A is set so that the difference between the thermal expansion coefficient and the thermal expansion coefficient of the semiconductor element 31 is reduced, and the insulation of the semiconductor element 31 is determined by the difference in the thermal expansion coefficient. It is possible to prevent the layer from being damaged and the semiconductor device 31 from being damaged. Moreover, the thermal expansion coefficient of the metal base material 42 corresponding to the connection region A can be changed to a desired value by appropriately selecting the hole diameter, shape, arrangement pitch, and the like of the through holes 37.

金属基材４２の接続領域Ｂに対応する部分には、第２の貫通穴である貫通穴３６が複数形成されており、この貫通穴３６には樹脂３８が充填されている。一般的に、実装基板４１の熱膨張係数は、半導体素子３１の熱膨張係数よりも大きいので、貫通穴３７の穴径は、貫通穴３６よりも小さく形成すると良い。貫通穴３６は、従来のエッチング法により形成することができる。   A plurality of through holes 36 as second through holes are formed in a portion corresponding to the connection region B of the metal base material 42, and the through holes 36 are filled with a resin 38. Generally, since the thermal expansion coefficient of the mounting substrate 41 is larger than the thermal expansion coefficient of the semiconductor element 31, the hole diameter of the through hole 37 is preferably smaller than that of the through hole 36. The through hole 36 can be formed by a conventional etching method.

このように、実装基板４１がはんだボール３９を介して基板３５に接続される接続領域Ｂに対応した金属基材４２に貫通穴３７よりも大きい複数の貫通穴３６を形成し、これら複数の貫通穴３６に樹脂３８を充填することで、接続領域Ｂに対応した金属基材４２の熱膨張係数を、接続領域Ａに対応した金属基材４２の熱膨張係数と異なる値とすることができる。   In this way, a plurality of through holes 36 larger than the through holes 37 are formed in the metal base 42 corresponding to the connection region B where the mounting substrate 41 is connected to the substrate 35 via the solder balls 39, and the plurality of through holes By filling the hole 36 with the resin 38, the thermal expansion coefficient of the metal base material 42 corresponding to the connection region B can be set to a value different from the thermal expansion coefficient of the metal base material 42 corresponding to the connection region A.

これにより、接続領域Ｂに対応した金属基材４２の熱膨張係数と実装基板４１の熱膨張係数との差が小さくなるように、接続領域Ｂに対応した金属基材４２の熱膨張係数を設定して、熱膨張係数の差により実装基板４１が破損することを防止できる。また、貫通穴３６の穴径、形状、配設ピッチ等を適宜選択することで、接続領域Ｂに対応した金属基材４２の熱膨張係数を所望の値に変えることができる。   Thereby, the thermal expansion coefficient of the metal base material 42 corresponding to the connection region B is set so that the difference between the thermal expansion coefficient of the metal base material 42 corresponding to the connection region B and the thermal expansion coefficient of the mounting substrate 41 becomes small. Thus, the mounting substrate 41 can be prevented from being damaged due to the difference in thermal expansion coefficient. Moreover, the thermal expansion coefficient of the metal base material 42 corresponding to the connection region B can be changed to a desired value by appropriately selecting the hole diameter, shape, arrangement pitch, and the like of the through holes 36.

上記説明したように、金属基材４２の半導体素子３１が接続される接続領域Ａに貫通穴３７を形成し、金属基材４２の実装基板４１が接続される接続領域Ｂに貫通穴３７よりも穴径の大きな貫通穴３６を形成して、貫通穴３６，３７に樹脂３８を充填することで、半導体素子３１と基板３５との間の熱膨張係数の差と、実装基板４１と基板３５との間の熱膨張係数の差とを小さくして、半導体素子３１及び実装基板４１が破損することを防止することができる。また、接続領域Ａに対応する金属基材４２には、例えば、穴径が０．３０ｍｍの円筒状の貫通穴３６を配設ピッチ１．０で設け、接続領域Ｂに対応する金属基材４２には、穴径が０．７５ｍｍの円筒状の貫通穴３７を配設ピッチ１．０で設けることができる。   As described above, the through hole 37 is formed in the connection region A to which the semiconductor element 31 of the metal base 42 is connected, and the connection region B to which the mounting substrate 41 of the metal base 42 is connected is more than the through hole 37. By forming the through-hole 36 having a large hole diameter and filling the through-holes 36 and 37 with the resin 38, the difference in thermal expansion coefficient between the semiconductor element 31 and the substrate 35, the mounting substrate 41 and the substrate 35, and It is possible to prevent the semiconductor element 31 and the mounting substrate 41 from being damaged by reducing the difference in thermal expansion coefficient between the semiconductor element 31 and the mounting board 41. Further, the metal base material 42 corresponding to the connection region A is provided with, for example, cylindrical through holes 36 having a hole diameter of 0.30 mm at an arrangement pitch of 1.0, and the metal base material 42 corresponding to the connection region B is provided. Can be provided with a cylindrical through hole 37 having a hole diameter of 0.75 mm at a pitch of 1.0.

次に、図４及び図５を参照して、本実施例の基板３５と、比較例である貫通穴を有していない金属基材１１を備えた従来の基板１０とについて評価した熱膨張係数の差について説明する。なお、評価する際、半導体素子及び実装基板については同一のものを用いた。また、半導体素子の絶縁層には、ウルトラロウＫ材料を用いた。   Next, referring to FIG. 4 and FIG. 5, the thermal expansion coefficient evaluated for the substrate 35 of this example and the conventional substrate 10 provided with the metal base material 11 having no through hole as a comparative example. The difference will be described. In the evaluation, the same semiconductor element and mounting substrate were used. An ultra-low K material was used for the insulating layer of the semiconductor element.

図４は、半導体素子、実装基板、比較例の基板、及び本実施例の基板の熱膨張係数を示した図である。図４に示すように、半導体素子の熱膨張係数は３．２、実装基板の熱膨張係数は１７．０、比較例の基板１０の熱膨張係数は１２．０、本実施例の基板３５の接続領域Ａに対応する部分の熱膨張係数は８．０、本実施例の基板３５の接続領域Ｂに対応する部分の熱膨張係数は１４．０であった。また、接続領域Ａに対応する金属基材４２には、穴径が０．３０ｍｍの円筒状の貫通穴３６を配設ピッチ１．０で設け、接続領域Ｂに対応する金属基材４２には、穴径が０．７５ｍｍの円筒状の貫通穴３７を配設ピッチ１．０で設けた。   FIG. 4 is a diagram illustrating thermal expansion coefficients of the semiconductor element, the mounting substrate, the substrate of the comparative example, and the substrate of the present example. As shown in FIG. 4, the thermal expansion coefficient of the semiconductor element is 3.2, the thermal expansion coefficient of the mounting substrate is 17.0, the thermal expansion coefficient of the substrate 10 of the comparative example is 12.0, and the thermal expansion coefficient of the substrate 35 of this embodiment is The thermal expansion coefficient of the portion corresponding to the connection region A was 8.0, and the thermal expansion coefficient of the portion corresponding to the connection region B of the substrate 35 of this example was 14.0. Further, the metal base material 42 corresponding to the connection region A is provided with cylindrical through holes 36 having a hole diameter of 0.30 mm at an arrangement pitch 1.0, and the metal base material 42 corresponding to the connection region B is provided on the metal base material 42 corresponding to the connection region B. Cylindrical through holes 37 having a hole diameter of 0.75 mm were provided at a pitch of 1.0.

図５は、熱膨張係数の差を示した図である。図５に示すように、比較例の基板１０を用いた場合には、半導体素子と基板１０との間の熱膨張係数の差は８．８であり、実装基板と基板１０との間の熱膨張係数の差は５．０であった。一方、本実施例の基板３５を用いた場合には、半導体素子と基板３５との間の熱膨張係数の差は４．８であり、実装基板と基板３５との間の熱膨張係数の差は３．０であった。この評価結果から、本実施例の基板３５を適用することで、半導体素子と基板３５との間の熱膨張係数の差と、実装基板と基板３５との間の熱膨張係数の差とを従来よりも小さくできることが確認できた。   FIG. 5 is a diagram showing a difference in thermal expansion coefficient. As shown in FIG. 5, when the substrate 10 of the comparative example is used, the difference in thermal expansion coefficient between the semiconductor element and the substrate 10 is 8.8, and the heat between the mounting substrate and the substrate 10 is The difference in expansion coefficient was 5.0. On the other hand, when the substrate 35 of this example is used, the difference in thermal expansion coefficient between the semiconductor element and the substrate 35 is 4.8, and the difference in thermal expansion coefficient between the mounting substrate and the substrate 35 is. Was 3.0. From this evaluation result, by applying the substrate 35 of this example, the difference in the thermal expansion coefficient between the semiconductor element and the substrate 35 and the difference in the thermal expansion coefficient between the mounting substrate and the substrate 35 are conventionally obtained. It was confirmed that it can be made smaller.

次に、上記熱膨張係数を有した半導体素子、実装基板、比較例の基板１０、及び本実施例の基板３５を用いて、高低温サイクル試験を行った。この高低温サイクル試験では、温度サイクル試験装置を用いて、−６５℃から１２５℃までの温度範囲で、温度の上げ下げを繰り返し行い、繰り返し回数が及ぼす影響について評価した。   Next, a high-low temperature cycle test was performed using the semiconductor element having the thermal expansion coefficient, the mounting substrate, the substrate 10 of the comparative example, and the substrate 35 of the present example. In this high and low temperature cycle test, the temperature cycle test apparatus was used to repeatedly raise and lower the temperature in the temperature range from −65 ° C. to 125 ° C., and the influence of the number of repetitions was evaluated.

この高低温サイクル試験による評価結果から、比較例の基板１０に接続された半導体素子は、繰り返し回数が２００回程度で半導体素子の破損が確認されたが、本実施例の基板３５に接続された半導体素子は、繰り返し回数が５００回以上でも破損が見られなかった。このことから、本実施例の基板３５を適用することにより、半導体素子の破損を防止できることが確認できた。また、実装基板と基板３５との間の接続部分のストレス、及び半導体素子と基板３５との間の接続部分のストレスは、従来の基板１０を用いた場合と比較して１／５程度となることが確認できた。   From the evaluation result by this high and low temperature cycle test, the semiconductor element connected to the substrate 10 of the comparative example was confirmed to be damaged by about 200 repetitions, but was connected to the substrate 35 of this example. The semiconductor element was not damaged even when the number of repetitions was 500 times or more. From this, it was confirmed that the semiconductor element can be prevented from being damaged by applying the substrate 35 of this example. In addition, the stress at the connection portion between the mounting substrate and the substrate 35 and the stress at the connection portion between the semiconductor element and the substrate 35 are about 1/5 compared to the case where the conventional substrate 10 is used. I was able to confirm.

図６は、複数の基板を設けたパネルの平面図であり、図７は、図６に示したパネルのＤ１−Ｄ２方向の断面図である。図６に示すように、基板３５は、板状のパネル４５に複数の基板３５を形成し、最後に、パネル４５から基板３５を切り出すことで製造される。パネル４５は、基板３５が形成される基板形成領域（以下、基板形成領域Ｅ）と、基板３５が形成されない非形成領域（以下、非形成領域Ｆ）とを有している。なお、図６において、基板形成領域Ｅには、先に説明した貫通穴３６，３７（図示せず）が形成されている。   FIG. 6 is a plan view of a panel provided with a plurality of substrates, and FIG. 7 is a cross-sectional view in the D1-D2 direction of the panel shown in FIG. As shown in FIG. 6, the substrate 35 is manufactured by forming a plurality of substrates 35 on a plate-like panel 45 and finally cutting out the substrate 35 from the panel 45. The panel 45 has a substrate formation region where the substrate 35 is formed (hereinafter, substrate formation region E) and a non-formation region where the substrate 35 is not formed (hereinafter, non-formation region F). In FIG. 6, the previously described through holes 36 and 37 (not shown) are formed in the substrate formation region E.

図７に示すように、基板３５が形成される基板形成領域Ｅのみに貫通穴３６，３７を形成するだけでなく、非形成領域Ｆにも貫通穴４７を形成することで、パネル４５全体に貫通穴が形成され、貫通穴を有していない金属基材１１を備えた従来の基板１０と比較して、パネル４５の重量を軽くして、パネル４５を加工装置に設けられた吸着部で搬送する際、安定してパネル４５を搬送することができる。また、上記貫通穴３６，３７，４７を設けることで、パネル４５の曲げ剛性を強くすることができ、基板３５を製造する際、パネル４５及び基板３５の反りを抑制して、基板３５を精度良く加工することができる。   As shown in FIG. 7, not only the through holes 36 and 37 are formed only in the substrate forming region E where the substrate 35 is formed, but also the through holes 47 are formed in the non-formed region F, so that the entire panel 45 is formed. The weight of the panel 45 is reduced compared with the conventional substrate 10 provided with the metal base material 11 that has a through hole and does not have a through hole, and the panel 45 is a suction portion provided in the processing apparatus. When transporting, the panel 45 can be transported stably. Further, by providing the through holes 36, 37, and 47, the bending rigidity of the panel 45 can be increased, and when the substrate 35 is manufactured, the warpage of the panel 45 and the substrate 35 is suppressed, and the substrate 35 is made accurate. Can be processed well.

以上、本発明の好ましい実施例について詳述したが、本発明はかかる特定の実施形態に限定されるものではなく、特許請求の範囲内に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。なお、金属基材４２に設ける貫通穴の穴径、形状、配設ピッチ等については、上記実施例の貫通穴３６，３７の形状に限定されない。   The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims. Deformation / change is possible. In addition, about the hole diameter of the through-hole provided in the metal base material 42, a shape, arrangement | positioning pitch, etc., it is not limited to the shape of the through-holes 36 and 37 of the said Example.

本発明は、基板と半導体素子との間及び基板と実装基板との間の熱膨張係数の差を小さくして、半導体素子及び実装基板が破損することを防止すると共に、基板を精度良く加工することのできる基板及び半導体装置に適用できる。   The present invention reduces the difference in thermal expansion coefficient between the substrate and the semiconductor element and between the substrate and the mounting substrate, prevents the semiconductor element and the mounting substrate from being damaged, and processes the substrate with high accuracy. It can be applied to a substrate and a semiconductor device that can be used.

半導体素子と実装基板とを接続した従来の基板の断面図である。It is sectional drawing of the conventional board | substrate which connected the semiconductor element and the mounting board | substrate. 実装基板に実装された本発明の実施例による半導体装置の断面図である。It is sectional drawing of the semiconductor device by the Example of this invention mounted in the mounting board | substrate. 金属基材の平面図である。It is a top view of a metal base material. 半導体素子、実装基板、比較例の基板、及び本実施例の基板の熱膨張係数を示した図である。It is the figure which showed the thermal expansion coefficient of the semiconductor element, the mounting board | substrate, the board | substrate of a comparative example, and the board | substrate of a present Example. 熱膨張係数の差を示した図である。It is the figure which showed the difference of a thermal expansion coefficient. 複数の基板を設けたパネルの平面図である。It is a top view of the panel which provided the some board | substrate. 図６に示したパネルのＤ１−Ｄ２方向の断面図である。It is sectional drawing of the D1-D2 direction of the panel shown in FIG.

符号の説明Explanation of symbols

１０，３５ 基板
１１，４２ 金属基材
１２，１３ 樹脂部材
１４，３１ 半導体素子
１５，３２ はんだバンプ
１６，３３ アンダーフィル樹脂
１７，３９ はんだボール
１８，４１ 実装基板
３０ 半導体装置
３６，３７，４７ 貫通穴
３８ 樹脂
４５ パネル
Ａ，Ｂ 接続領域
Ｅ 基板形成領域
Ｆ 非形成領域 10, 35 Substrate 11, 42 Metal base material 12, 13 Resin member 14, 31 Semiconductor element 15, 32 Solder bump 16, 33 Underfill resin 17, 39 Solder ball 18, 41 Mounting substrate 30 Semiconductor device 36, 37, 47 Through Hole 38 Resin 45 Panel A, B Connection area E Substrate formation area F Non-formation area

Claims (3)

板状の金属基材と、
半導体素子が接続される第１の接続領域と、
実装基板が接続される第２の接続領域とを備え、
前記半導体素子及び実装基板が接続される基板であって、
前記第１の接続領域に対応する前記金属基材に設けられた第１の貫通穴と、
前記第２の接続領域に対応する前記金属基材に、前記第１の貫通穴と穴径及び／又は穴の配設ピッチの異なる第２の貫通穴を設けたことを特徴とする基板。 A plate-shaped metal substrate;
A first connection region to which a semiconductor element is connected;
A second connection region to which the mounting substrate is connected,
A substrate to which the semiconductor element and the mounting substrate are connected,
A first through hole provided in the metal substrate corresponding to the first connection region;
A substrate, wherein the metal substrate corresponding to the second connection region is provided with a second through hole having a hole diameter and / or a hole arrangement pitch different from that of the first through hole. 前記第１及び第２の貫通穴には、樹脂を埋め込むことを特徴とする請求項１に記載の基板。   The substrate according to claim 1, wherein a resin is embedded in the first and second through holes. 請求項１または２に記載の基板と、
前記基板に接続される半導体素子とを備えたことを特徴とする半導体装置。
A substrate according to claim 1 or 2,
A semiconductor device comprising: a semiconductor element connected to the substrate.
JP2004128462A 2004-04-23 2004-04-23 Substrate and semiconductor device Expired - Fee Related JP4291729B2 (en)

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WO2007074941A1 (en) * 2005-12-27 2007-07-05 Ibiden Co., Ltd. Multilayer printed wiring board
JP2008112790A (en) * 2006-10-30 2008-05-15 Shinko Electric Ind Co Ltd Semiconductor package and its manufacturing method
JP2008210985A (en) * 2007-02-26 2008-09-11 Toshiba Corp Semiconductor device
JP4521415B2 (en) * 2007-02-26 2010-08-11 株式会社東芝 Semiconductor device
JP5767695B2 (en) * 2011-03-22 2015-08-19 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2015146401A (en) * 2014-02-04 2015-08-13 大日本印刷株式会社 glass interposer
KR20160120486A (en) * 2015-04-08 2016-10-18 삼성전기주식회사 Circuit board and method of manufacturing the same
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KR20160126290A (en) * 2015-04-23 2016-11-02 삼성전기주식회사 Printed circuit board, semiconductor package and method of manufacturing the same
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