JP2008147498A - Multilayer wiring board, and semiconductor device package - Google Patents

Multilayer wiring board, and semiconductor device package Download PDF

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Publication number
JP2008147498A
JP2008147498A JP2006334478A JP2006334478A JP2008147498A JP 2008147498 A JP2008147498 A JP 2008147498A JP 2006334478 A JP2006334478 A JP 2006334478A JP 2006334478 A JP2006334478 A JP 2006334478A JP 2008147498 A JP2008147498 A JP 2008147498A
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wiring board
multilayer wiring
flexible portion
copper
pattern
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Katsushi Makino
勝史 牧野
Isao Kato
功 加藤
Takamasa Okuma
隆正 大熊
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Toppan Inc
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Toppan Printing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring board by which disconnection of solder bonding portions hardly occurs after mounting electronic components, and to provide a semiconductor device package by which disconnection of solder bonding portions hardly occurs. <P>SOLUTION: The multilayer wiring board 1 is formed by alternately stacking two or more conductor layers 3 including copper and insulating substrates 2 and mounting electronic components on the top. A flexible part 7 which exhibits a lower stiffness than the other parts of the conductor layers 3 is formed in a part of at least one of the conductor layers 3. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、電子機器等に使用される半導体装置等の電子部品搭載用の多層配線板に関し、特に絶縁基板上に二層以上の多層の配線パターンを有し、配線密度が向上した構成の多層配線板に関する。また、半導体集積回路素子を直接搭載・接続するタイプの回路基板や、半導体集積回路素子をリードフレームに搭載・接続した状態での半導体装置を接続する外部回路としての多層配線板等も含まれる。   The present invention relates to a multilayer wiring board for mounting an electronic component such as a semiconductor device used in an electronic device or the like, and in particular, a multilayer having a multilayer wiring pattern having two or more layers on an insulating substrate and having an improved wiring density. It relates to a wiring board. In addition, a circuit board of a type in which a semiconductor integrated circuit element is directly mounted and connected, a multilayer wiring board as an external circuit for connecting a semiconductor device with the semiconductor integrated circuit element mounted and connected to a lead frame, and the like are also included.

従来、互いに交差する配線パターンを含む配線板を作製するために、配線パターンと絶縁基板とを交互に積層することによって多層配線板を構成し、配線密度を向上させることが行われている。   Conventionally, in order to produce a wiring board including wiring patterns that intersect each other, a multilayer wiring board is formed by alternately laminating wiring patterns and insulating substrates to improve wiring density.

このような多層配線板に半導体チップ（以下、単に「チップ」と称する。）等の電子部品を実装して用いる場合、配線導体パターンの有無により以下の２つの問題点が発生する。第１はチップと多層配線板とのはんだ接合部がチップの実装後に断線することがある点である。この断線は、チップと多層配線板では熱膨張係数が異なるため、熱サイクル試験等の信頼性試験を実施するとそれぞれの熱膨張差からはんだ接合部に応力が生じることによって発生する。
第２は積層時の熱圧着工程により多層配線板を構成する絶縁基板が大きく伸縮し、影響の極めて大きい反りや歪みが発生する点である。 When an electronic component such as a semiconductor chip (hereinafter simply referred to as “chip”) is mounted on such a multilayer wiring board, the following two problems occur depending on the presence or absence of the wiring conductor pattern. The first is that the solder joint between the chip and the multilayer wiring board may be disconnected after the chip is mounted. Since the thermal expansion coefficient is different between the chip and the multilayer wiring board, this disconnection is generated when stress is generated in the solder joint due to the difference in thermal expansion when a reliability test such as a thermal cycle test is performed.
The second is that the insulating substrate constituting the multilayer wiring board greatly expands and contracts due to the thermocompression bonding process at the time of stacking, and warping and distortion having a great influence are generated.

上記問題点を解決する技術として、特許文献１及び特許文献２の技術が開示されている。本出願人による特許文献１では、配線パターンのパターン間にダミーパターンを設けて積層面での平坦性を保ち、配線パターンの再現性を高めている。特許文献２では、配線パターン間に、円形もしくは三角形のダミーパターンを配置し、配線パターン領域とダミーパターン領域との残銅率をほぼ等しくしている。残銅率を等しくすることにより、基材表裏での反り及び歪みを抑制している。
特開平９−３１２４７１号公報 特開２００４−２００２６５号公報 As techniques for solving the above-described problems, the techniques of Patent Document 1 and Patent Document 2 are disclosed. In Patent Document 1 by the present applicant, a dummy pattern is provided between wiring pattern patterns to maintain flatness on the laminated surface and to improve the reproducibility of the wiring pattern. In Patent Document 2, a circular or triangular dummy pattern is arranged between wiring patterns, and the remaining copper ratios of the wiring pattern area and the dummy pattern area are substantially equal. By equalizing the remaining copper ratio, warpage and distortion on the front and back of the substrate are suppressed.
JP-A-9-31471 Japanese Patent Laid-Open No. 2004-200265

しかしながら、上記特許文献に開示された技術では、上述した問題点を充分に解決できない。例えばダミーパターンの配置によってチップ実装面の単位面積あたりの銅面積率を７０〜９９．５％に調整した場合、多層配線板の剛性は高まるが、その一方で柔軟性が低下してチップへの追従性が小さくなり、熱サイクル試験等の信頼性試験を実施した際に断線が発生しやすくなる。   However, the technique disclosed in the above patent document cannot sufficiently solve the above-described problems. For example, when the copper area ratio per unit area of the chip mounting surface is adjusted to 70 to 99.5% by the arrangement of the dummy pattern, the rigidity of the multilayer wiring board increases, but on the other hand, the flexibility decreases and The followability is reduced, and disconnection is likely to occur when a reliability test such as a thermal cycle test is performed.

このとき、温度の上下に応じて絶縁基板の膨張・収縮が発生しており、絶縁基板に大きな応力が生じるため、応力が集中しやすいチップの四角と多層配線板とのはんだ接合部では断線の発生率が高くなる。特に、コアを有しないフレキシブル基板を用いた多層配線板ではリジッド基板を用いた多層配線板に比べ絶縁基板の伸縮が大きく、はんだ接合部の断線が発生しやすい。   At this time, the insulating substrate expands and contracts according to the temperature rise and fall, and a large stress is generated on the insulating substrate. Therefore, disconnection may occur at the solder joint between the chip square and the multilayer wiring board where stress tends to concentrate. Incidence increases. In particular, in a multilayer wiring board using a flexible substrate having no core, the insulating substrate expands and contracts more easily than a multilayer wiring board using a rigid substrate, and breakage of the solder joints is likely to occur.

一方、ダミーパターンの配置によって全体の銅面積率を６０％以下に下げれば多層配線板自体のチップへの追従性は高くなる。しかしながら、その一方で絶縁基板の反りが大きくなり、チップの実装及びプリント基板の実装が困難となる。   On the other hand, if the overall copper area ratio is lowered to 60% or less by arranging the dummy pattern, the followability of the multilayer wiring board itself to the chip is enhanced. However, on the other hand, the warping of the insulating substrate increases, making it difficult to mount the chip and the printed circuit board.

本発明は上記事情に鑑みて成されたものであり、電子部品を実装した後にはんだ接合部の断線が発生しにくい多層配線板及びはんだ接合部の断線が発生しにくい半導体装置パッケージを提供することを目的とする。   The present invention has been made in view of the above circumstances, and provides a multilayer wiring board in which disconnection of a solder joint after an electronic component is mounted and a semiconductor device package in which disconnection of the solder joint is unlikely to occur. With the goal.

本発明の多層配線板は、銅を含有して形成された導体層が２層もしくはそれ以上、絶縁層と交互に積層されて、上面に電子部品が実装される多層配線板であって、少なくとも１つの導体層の一部に、該導体層の他の部分よりも剛性が低い柔軟部が形成されていることを特徴とする。   The multilayer wiring board of the present invention is a multilayer wiring board in which two or more conductor layers formed containing copper are alternately laminated with an insulating layer, and an electronic component is mounted on the upper surface. A flexible part having a lower rigidity than the other part of the conductor layer is formed in a part of one conductor layer.

本発明の多層配線板は、柔軟部が設けられており、温度変化等によって、絶縁層が膨張又は収縮した場合も、実装された電子部品と多層配線板との間に発生する応力に剛性の低い柔軟部が追従する。   The multilayer wiring board of the present invention is provided with a flexible portion, and is rigid to the stress generated between the mounted electronic component and the multilayer wiring board even when the insulating layer expands or contracts due to a temperature change or the like. The low flexible part follows.

前記柔軟部は、前記導体層の単位面積あたりの銅面積比率を前記他の部分よりも減少させることによって形成されてもよい。   The flexible portion may be formed by reducing a copper area ratio per unit area of the conductor layer as compared with the other portions.

前記柔軟部は、前記チップの実装エリアの周縁の１点から所定の半径で描いた円を含む領域であって、かつ前記実装エリア外に形成されてもよい。また、前記実装エリアの長辺の長さをＬとしたとき、前記半径が１０／Ｌ以上３／Ｌ未満に設定されてもよい。このとき、長辺とは実装エリアが長さの異なる複数の線で形成されている場合の最も長い辺を指し、すべての辺の長さが等しい場合は一辺を指す。   The flexible portion may be a region including a circle drawn with a predetermined radius from one point on the periphery of the mounting area of the chip, and may be formed outside the mounting area. Further, when the length of the long side of the mounting area is L, the radius may be set to 10 / L or more and less than 3 / L. At this time, the long side refers to the longest side when the mounting area is formed of a plurality of lines having different lengths, and refers to one side when the lengths of all the sides are equal.

前記柔軟部の前記銅面積比率は５０パーセント以上７０パーセント未満であってもよい。また、前記柔軟部が設けられた前記導体層のうち、前記柔軟部を除く領域の銅面積率は７０％以上であってもよい。   The copper area ratio of the flexible part may be not less than 50 percent and less than 70 percent. Moreover, 70% or more of the copper area ratio of the area | region except the said flexible part may be sufficient as the said conductor layer in which the said flexible part was provided.

前記柔軟部は、前記導体層の表面に円形もしくは多角形の抜きパターンを設けることによって形成されてもよい。   The flexible portion may be formed by providing a circular or polygonal punch pattern on the surface of the conductor layer.

本発明の半導体装置パッケージは、本発明の多層配線板と、前記多層配線板の上面に実装された半導体装置とを備えたことを特徴とする。   A semiconductor device package of the present invention includes the multilayer wiring board of the present invention and a semiconductor device mounted on the upper surface of the multilayer wiring board.

本発明によれば、柔軟部が絶縁層と電子部品との接合部に発生した応力に追従するので、実装された電子部品とのはんだ接合部に断線が発生しにくい多層配線板を提供することができる。
また、半導体装置と多層配線板とのはんだ接合部に断線が発生しにくい半導体装置パッケージを提供することができる。 According to the present invention, since the flexible portion follows the stress generated at the joint between the insulating layer and the electronic component, it is possible to provide a multilayer wiring board in which disconnection is unlikely to occur at the solder joint with the mounted electronic component. Can do.
Further, it is possible to provide a semiconductor device package in which disconnection is unlikely to occur at the solder joint between the semiconductor device and the multilayer wiring board.

以下、本発明の第１実施形態の多層配線板について、図１および図２を参照して説明する。
図１は本実施形態の多層配線板１の概略断面図である。図１に示すように、本実施形態の多層配線板１は、絶縁基板（絶縁層）２と、絶縁基板２に積層して設けられる銅箔層（導体層）３を備えて構成されている。絶縁基板２と銅箔層３とは、接着剤４を介して交互に積層されており、各銅箔層３の間には、隣接する銅箔層３を電気的に接続する導通ビア５が設けられている。 The multilayer wiring board according to the first embodiment of the present invention will be described below with reference to FIGS.
FIG. 1 is a schematic sectional view of a multilayer wiring board 1 of the present embodiment. As shown in FIG. 1, the multilayer wiring board 1 of the present embodiment includes an insulating substrate (insulating layer) 2 and a copper foil layer (conductor layer) 3 provided on the insulating substrate 2 in a stacked manner. . The insulating substrate 2 and the copper foil layer 3 are alternately stacked via the adhesive 4, and between each copper foil layer 3, there are conductive vias 5 that electrically connect the adjacent copper foil layers 3. Is provided.

図２（ａ）は多層配線板１の平面図である。最上部の銅箔層３ａは、チップ等の電子部品が実装される実装エリア６と、実装エリア６の周辺に設けられた柔軟部７とを有している。柔軟部７は、図２（ａ）に示すように、実装エリア６の周縁の任意の一点を中心とする所定の半径の円を含み、かつ実装エリア６外の領域に設定される。本実施形態においては、チップの場合、頂点付近の端子と多層配線板１とのはんだ接合部に応力が集中し、断線が発生しやすいため、実装エリア６の各頂点８を中心とする半径ｒの円Ｃを含む領域に柔軟部７が設けられている。   FIG. 2A is a plan view of the multilayer wiring board 1. The uppermost copper foil layer 3 a has a mounting area 6 on which electronic components such as chips are mounted, and a flexible portion 7 provided around the mounting area 6. As shown in FIG. 2A, the flexible portion 7 includes a circle with a predetermined radius centered on an arbitrary point on the periphery of the mounting area 6 and is set in a region outside the mounting area 6. In the present embodiment, in the case of a chip, stress concentrates on the solder joint between the terminal near the vertex and the multilayer wiring board 1, and disconnection is likely to occur. Therefore, the radius r about each vertex 8 of the mounting area 6 is the center. The flexible portion 7 is provided in a region including the circle C.

半径ｒの長さは、実装エリア６の一辺の長さをＬとした場合、１／１０Ｌ以上１／３Ｌ未満、好ましくは１／６Ｌ以上１／４Ｌ未満となるように設定される。１／１０Ｌ未満では発生した応力に充分追従できず、１／３Ｌ以上では多層配線板の剛性が不足し、反り等の不具合が発生しやすくなる。本実施形態においては半径ｒが１／５Ｌに設定されている。実装エリアが長方形等、長さの異なる辺で形成されている場合は、最も長い辺の長さをＬとしてｒの長さを設定すればよい。   The length of the radius r is set to be 1 / 10L or more and less than 1 / 3L, preferably 1 / 6L or more and less than 1 / 4L, where L is the length of one side of the mounting area 6. If it is less than 1/10 L, the generated stress cannot be sufficiently tracked, and if it is 1/3 L or more, the multilayer wiring board has insufficient rigidity, and problems such as warpage tend to occur. In the present embodiment, the radius r is set to 1 / 5L. When the mounting area is formed of sides having different lengths, such as a rectangle, the length of r may be set with L being the length of the longest side.

図２（ｂ）は柔軟部７周辺の拡大図である。最上部の銅箔層３ａを含むすべての銅箔層３には、後述する配線パターンが形成されていない部分に、円形の第１抜きパターン９が多数形成されて銅箔が除去され、単位面積あたりの銅面積率が調整されている。柔軟部７には第１抜きパターン９より径の大きい第２抜きパターン（抜きパターン）１０が形成され、周囲の銅箔層よりも銅面積率が低くなるように構成されている。   FIG. 2B is an enlarged view around the flexible portion 7. In all the copper foil layers 3 including the uppermost copper foil layer 3a, a large number of first circular cut patterns 9 are formed in portions where a wiring pattern to be described later is not formed, and the copper foil is removed. The per copper area ratio is adjusted. The flexible portion 7 is formed with a second punching pattern (punching pattern) 10 having a diameter larger than that of the first punching pattern 9 so that the copper area ratio is lower than that of the surrounding copper foil layer.

第１抜きパターン９及び第２抜きパターン１０の直径およびピッチは、設定された銅面積率に基づいて適宜計算、決定される。ここで、各抜きパターン９、１０の直径は、最大でも４００μｍ以下であることが好ましい。直径がこれより大きいと、隣接する層に凹凸が影響して歪みが生じる。また、積層の際に使用する接着剤の気泡が抜けにくく、接着時に気泡をかみやすくなる。本実施形態においては、表１に示すように設定されており、柔軟部７の銅面積率は５２％、柔軟部７以外の領域の銅面積率は７８％に設定されている。   The diameter and pitch of the first punch pattern 9 and the second punch pattern 10 are appropriately calculated and determined based on the set copper area ratio. Here, it is preferable that the diameter of each extraction pattern 9, 10 is 400 μm or less at the maximum. If the diameter is larger than this, unevenness affects the adjacent layers and distortion occurs. In addition, bubbles of the adhesive used at the time of lamination are difficult to escape, and it becomes easy to bite the bubbles at the time of adhesion. In this embodiment, it is set as shown in Table 1, the copper area ratio of the flexible portion 7 is set to 52%, and the copper area ratio of the region other than the flexible portion 7 is set to 78%.

Figure 2008147498
Figure 2008147498

柔軟部７以外の領域の銅面積率は、多層配線板１の剛性を充分なレベルに保つ観点から７０％以上であることが好ましい。また、柔軟部７の銅面積率は、発生する応力に追従し、かつ反りや歪みも生じにくくするために、５０％以上７０％未満、好ましくは５０％以上６０％未満に設定されることが望ましい。銅箔層３に配線パターンが形成される場合は、当該配線パターンの面積を含めて銅面積率を算出し、各抜きパターン９、１０の直径及びピッチを設定する。
なお、多層配線板全体としての剛性を確保するために、銅箔層３全体としての銅面積率が６０％以上となるように、第１抜きパターン及び第２抜きパターンの直径およびピッチを設定することが好ましい。 The copper area ratio in the region other than the flexible portion 7 is preferably 70% or more from the viewpoint of keeping the rigidity of the multilayer wiring board 1 at a sufficient level. Further, the copper area ratio of the flexible portion 7 may be set to 50% or more and less than 70%, preferably 50% or more and less than 60%, in order to follow the generated stress and hardly cause warpage or distortion. desirable. When a wiring pattern is formed on the copper foil layer 3, the copper area ratio is calculated including the area of the wiring pattern, and the diameter and pitch of each punched pattern 9, 10 are set.
In order to secure the rigidity of the entire multilayer wiring board, the diameter and pitch of the first punch pattern and the second punch pattern are set so that the copper area ratio of the copper foil layer 3 as a whole is 60% or more. It is preferable.

上記のように構成された多層配線板１においては、柔軟部７の銅面積率が他の領域に比べて２０パーセントポイント以上少なく形成されており、応力に対して高い追従性を有する。   In the multilayer wiring board 1 configured as described above, the copper area ratio of the flexible portion 7 is formed to be less than 20 percentage points as compared with other regions, and has high followability to stress.

多層配線板１の製造方法について、図３及び図４を参照して説明する。図３及び図４は多層配線板１の製造工程を経時的に示した図である。   A method for manufacturing the multilayer wiring board 1 will be described with reference to FIGS. 3 and 4 are views showing the manufacturing process of the multilayer wiring board 1 over time.

まず、図３（ａ）に示すように、幅１０５ｍｍのテープ状であるポリイミドからなる絶縁基板２を準備する。絶縁基板２の両面には銅箔層３ｂおよび３ｃが設けられている。化学研磨により銅箔層３の厚さを１５μｍ程度に制御する。   First, as shown in FIG. 3A, an insulating substrate 2 made of polyimide having a tape shape with a width of 105 mm is prepared. Copper foil layers 3 b and 3 c are provided on both surfaces of the insulating substrate 2. The thickness of the copper foil layer 3 is controlled to about 15 μm by chemical polishing.

次に、図３（ｂ）に示すように、絶縁基板２及び銅箔層３に脱脂処理を施した後、レーザ加工によって、銅箔層３ｂ、絶縁基板２を貫通し、絶縁基板２と銅箔層３ｃとの境界面に達するビアホール１１を所定の位置に形成する。   Next, as shown in FIG. 3 (b), the insulating substrate 2 and the copper foil layer 3 are degreased, and then penetrated through the copper foil layer 3b and the insulating substrate 2 by laser processing. A via hole 11 reaching a boundary surface with the foil layer 3c is formed at a predetermined position.

次に、ビアホール１１内部にデスミア処理を施してから、無電解銅めっき及び電解銅めっきを施すことにより銅からなる被膜が形成され、図３（ｃ）に示すように、絶縁基板２両面の銅箔層３ｂ及び３ｃを電気的に接続する導通ビア５が形成される。その後、硫酸と過酸化水素水の混合液により化学研磨が行われ、導通ビア５の厚さを約１５μｍ程度にし、銅箔層３ｂと導通ビア５とがほぼ平坦となるように加工される。   Next, a desmear treatment is performed on the inside of the via hole 11, and then a film made of copper is formed by performing electroless copper plating and electrolytic copper plating. As shown in FIG. 3C, the copper on both surfaces of the insulating substrate 2 is formed. Conductive vias 5 that electrically connect the foil layers 3b and 3c are formed. Thereafter, chemical polishing is performed with a mixed solution of sulfuric acid and hydrogen peroxide solution, and the thickness of the conductive via 5 is set to about 15 μm, and the copper foil layer 3b and the conductive via 5 are processed to be substantially flat.

次に、図３（ｄ）に示すように、液状レジストを使用して銅箔層３の上面全体にレジスト層１２が形成される。
続いて、図３（ｅ）に示すように、露光・現像を行う。本工程で用いるマスクには、所望の配線パターン及び上述の第１抜きパターン９がパターン径１００μｍ・パターンピッチ２００μｍで印刷されている。 Next, as shown in FIG. 3D, a resist layer 12 is formed on the entire top surface of the copper foil layer 3 using a liquid resist.
Subsequently, as shown in FIG. 3E, exposure and development are performed. On the mask used in this step, a desired wiring pattern and the first cut pattern 9 described above are printed with a pattern diameter of 100 μm and a pattern pitch of 200 μm.

導通ビア５や図示しない銅パターン又は絶縁基板２に設けられた貫通孔などを適宜アライメントマークとして使用して、絶縁基板２とフォトマスクの位置合わせを行った後、露光処理を行うと、配線パターン及び第１抜きパターンがレジスト層１２に形成される。レジスト専用現像液をスプレーすることによって現像処理を行うと、レジスト層１２が部分的に除去され、エッチングレジスト１３が形成される。   The conductive via 5, a copper pattern (not shown), or a through-hole provided in the insulating substrate 2 is used as an alignment mark as appropriate to align the insulating substrate 2 and the photomask, and then an exposure process is performed. In addition, a first punch pattern is formed in the resist layer 12. When the development process is performed by spraying a resist-dedicated developer, the resist layer 12 is partially removed and an etching resist 13 is formed.

続いて、図４（ａ）に示すように、銅箔層３にエッチングレジスト１３を介してエッチング液をスプレー噴霧することによりエッチングレジスト１３の開口部分の銅箔が除去される。その後エッチングレジスト１３を剥離すると、配線パターン１４及びグランド／電源面１５が、銅面積率が設定範囲に調整された状態で銅箔層３に形成される。   Subsequently, as shown in FIG. 4A, the copper foil in the opening portion of the etching resist 13 is removed by spraying an etching solution onto the copper foil layer 3 through the etching resist 13. Thereafter, when the etching resist 13 is peeled off, the wiring pattern 14 and the ground / power supply surface 15 are formed on the copper foil layer 3 in a state where the copper area ratio is adjusted to the set range.

次に、図４（ｂ）に示すように、両面に配線パターン１４が形成された銅箔層３が設けられた絶縁基板２をコアとして、その両面にそれぞれテープ状の絶縁基板２ｂ及び２ｃを接着剤４を介して積層する。絶縁基板２ｂ及び２ｃの外側には銅箔層３ａ及び３ｄが設けられている。接着剤４の厚みは２５μｍとする。   Next, as shown in FIG. 4B, the insulating substrate 2 provided with the copper foil layer 3 having the wiring pattern 14 formed on both surfaces is used as a core, and the tape-shaped insulating substrates 2b and 2c are respectively formed on both surfaces. Lamination is performed via the adhesive 4. Copper foil layers 3a and 3d are provided outside the insulating substrates 2b and 2c. The thickness of the adhesive 4 is 25 μm.

次に、図４（ｃ）に示すように、銅箔層３ａ及び３ｄに上述の手順に従って導通ビア形成、配線パターンおよび抜きパターンの形成をそれぞれ行う。このとき、電子部品が実装される銅箔層３ａに露光処理を行う際には、所望の配線パターン１４及び第１抜きパターン９に加えて、柔軟部７に対向する領域に直径１５０μｍ・パターンピッチ２００μｍの第２抜きパターン１０が印刷されているマスクを用いる。   Next, as shown in FIG. 4C, the conductive via formation, the wiring pattern, and the extraction pattern are respectively formed on the copper foil layers 3a and 3d according to the above-described procedure. At this time, when performing an exposure process on the copper foil layer 3a on which the electronic component is mounted, in addition to the desired wiring pattern 14 and the first punch pattern 9, a diameter of 150 μm and a pattern pitch are formed in a region facing the flexible portion 7. A mask on which a 200 μm second punch pattern 10 is printed is used.

完成した多層配線板１の銅箔層３ａにおいては、柔軟部７の銅面積率がグランド／電源面１５に比して低くなっている。また、図４（ｄ）に示すように、多層配線板１の銅箔層３ａ上に、チップ（電子部品）１６の端子１７と配線パターン１４とをはんだ１８により接合してチップ１６を実装すると、本発明の半導体装置パッケージ２０が得られる。   In the copper foil layer 3 a of the completed multilayer wiring board 1, the copper area ratio of the flexible portion 7 is lower than that of the ground / power supply surface 15. 4D, when the chip 16 is mounted on the copper foil layer 3a of the multilayer wiring board 1 by bonding the terminals 17 of the chip (electronic component) 16 and the wiring pattern 14 with the solder 18. As shown in FIG. Thus, the semiconductor device package 20 of the present invention is obtained.

本実施形態の多層配線板１によれば、銅箔層３ａの実装エリア６に近接して設けられた柔軟部７の銅面積率が５０％以上７０％未満に設定されているため、信頼性試験等において温度が上下した際にも、絶縁基板２の膨張や収縮に伴って発生する応力に、柔軟部７が充分追従する。従って、チップ１６と多層配線板１とのはんだ接合部の断線を防ぐことができる。   According to the multilayer wiring board 1 of the present embodiment, since the copper area ratio of the flexible portion 7 provided in the vicinity of the mounting area 6 of the copper foil layer 3a is set to 50% or more and less than 70%, the reliability Even when the temperature rises or falls in a test or the like, the flexible portion 7 sufficiently follows the stress generated as the insulating substrate 2 expands and contracts. Therefore, disconnection of the solder joint between the chip 16 and the multilayer wiring board 1 can be prevented.

また、柔軟部７以外の銅面積率が７０％以上に設定されているため、多層配線板１全体としては充分な剛性が保持されている。従って、上述した断線を防ぎつつ、反りや歪みの発生しにくい多層配線板１および半導体装置パッケージ２０を提供することができる。   Further, since the copper area ratio other than the flexible portion 7 is set to 70% or more, the multilayer wiring board 1 as a whole has sufficient rigidity. Therefore, it is possible to provide the multilayer wiring board 1 and the semiconductor device package 20 that are less likely to be warped or distorted while preventing the disconnection described above.

さらに、銅箔層３ａに円形の第２抜きパターン１０を設けることによって柔軟部７を形成しているので、第２抜きパターン１０の直径およびパターンピッチを調整するだけで柔軟部７の銅面積率を容易に調整可能な多層配線板１を構成することができる。   Furthermore, since the flexible part 7 is formed by providing the circular second punching pattern 10 on the copper foil layer 3a, the copper area ratio of the flexible part 7 can be simply adjusted by adjusting the diameter and pattern pitch of the second punching pattern 10. The multilayer wiring board 1 can be easily adjusted.

次に、本発明の第２実施形態について図５を参照して説明する。なお、上述の第１実施形態と同様の構成要素については、同一の符号を付し、重複する説明を省略する。図５は本実施形態の多層配線板２１の柔軟部２７周辺の拡大平面図である。図５に示すように、本実施形態の柔軟部２７には、長方形の第２抜きパターン３０が、実装エリア６の頂点８を中心に、略放射状に形成されている。   Next, a second embodiment of the present invention will be described with reference to FIG. In addition, about the component similar to the above-mentioned 1st Embodiment, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted. FIG. 5 is an enlarged plan view around the flexible portion 27 of the multilayer wiring board 21 of the present embodiment. As shown in FIG. 5, the rectangular second punch pattern 30 is formed in the flexible portion 27 of the present embodiment substantially radially about the vertex 8 of the mounting area 6.

各第２抜きパターン３０の長手方向は、実装エリア６の頂点８付近に設けられるチップと多層配線板２１とのはんだ接合部に発生する応力のベクトルの方向とほぼ一致している。従って、応力に対する柔軟部２７の追従性がさらに高まり、より効果的にはんだ接合部の断線を防止することができる。   The longitudinal direction of each second punch pattern 30 substantially coincides with the direction of the vector of stress generated at the solder joint between the chip provided near the apex 8 of the mounting area 6 and the multilayer wiring board 21. Accordingly, the followability of the flexible portion 27 with respect to the stress is further improved, and breakage of the solder joint portion can be more effectively prevented.

以上、本発明の実施形態について説明したが、本発明の技術範囲は上記実施の形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲において種々の変更を加えることが可能である。
例えば、上記実施形態では、配線パターンが上下２層の場合について説明したが、その他、配線パターンが上下３層４層等のさらに多層の多層配線板としてもよい。また、各抜きパターンの形状は円形及び長方形に限られず、他の多角形の形状とすることも可能である。 While the embodiments of the present invention have been described above, the technical scope of the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.
For example, in the above-described embodiment, the case where the wiring pattern has two upper and lower layers has been described. However, the wiring pattern may be a multilayer wiring board having a plurality of upper and lower three layers and four layers. Further, the shape of each punch pattern is not limited to a circle and a rectangle, but may be another polygonal shape.

また、上記実施形態では、チップ１６が実装される銅箔層３ａのみに柔軟部が設けられているが、それ以外の銅箔層に柔軟部が設けられてもよいし、複数の銅箔層に柔軟部が設けられてもよい。ただし、より効率よく断線抑制効果を得るためには、少なくとも電子部品が実装される銅箔層には柔軟部が設けられることが好ましい。   Moreover, in the said embodiment, although the flexible part is provided only in the copper foil layer 3a in which the chip | tip 16 is mounted, a flexible part may be provided in other copper foil layers, and several copper foil layers A flexible part may be provided. However, in order to obtain the effect of suppressing disconnection more efficiently, at least a copper foil layer on which electronic components are mounted is preferably provided with a flexible portion.

さらに、本実施形態においては、絶縁基板を用いてすべての絶縁層を形成しているが、これに代えて、樹脂溶液を塗布して絶縁層を形成してもよい。また、絶縁基板２をポリイミドでなく、他の樹脂材料によって形成することも可能である。   Furthermore, in this embodiment, all the insulating layers are formed using the insulating substrate, but instead of this, a resin solution may be applied to form the insulating layers. In addition, the insulating substrate 2 can be formed of other resin materials instead of polyimide.

また、上記実施形態の製造工程においては、枚葉の絶縁基板を用いているが、これに代えて、テープ状のフレキシブル基板を用いてロール・ツー・ロールの連続生産方法によって多層配線板を製造してもよい。   In the manufacturing process of the above embodiment, a single-wafer insulating substrate is used. Instead, a multilayer wiring board is manufactured by a roll-to-roll continuous production method using a tape-like flexible substrate. May be.

本発明の第１実施形態の多層配線板を示す断面図である。It is sectional drawing which shows the multilayer wiring board of 1st Embodiment of this invention. （ａ）は同実施形態の平面図、（ｂ）は同実施形態の柔軟部の拡大平面図である。(A) is a top view of the embodiment, (b) is an enlarged plan view of the flexible part of the embodiment. 同実施形態の製造工程を示す模式図である。It is a schematic diagram which shows the manufacturing process of the embodiment. 同実施形態の製造工程を示す模式図である。It is a schematic diagram which shows the manufacturing process of the embodiment. 本発明の第２実施形態の多層配線板の柔軟部を示す拡大平面図である。It is an enlarged plan view which shows the flexible part of the multilayer wiring board of 2nd Embodiment of this invention.

符号の説明Explanation of symbols

１、２１…多層配線板、２…絶縁基板（絶縁層）、３…銅箔層（導体層）、６…実装エリア、７、２７…柔軟部、１０、３０…第２抜きパターン（抜きパターン）、１６…半導体チップ（電子部品）、２０…半導体装置パッケージ、 DESCRIPTION OF SYMBOLS 1, 21 ... Multilayer wiring board, 2 ... Insulating substrate (insulating layer), 3 ... Copper foil layer (conductor layer), 6 ... Mounting area, 7, 27 ... Flexible part 10, 30 ... 2nd extraction pattern (extraction pattern) ), 16... Semiconductor chip (electronic component), 20... Semiconductor device package,

Claims (8)

銅を含有して形成された導体層が２層もしくはそれ以上、絶縁層と交互に積層されて、上面に電子部品が実装される多層配線板であって、少なくとも１つの導体層の一部に、該導体層の他の部分よりも剛性が低い柔軟部が形成されていることを特徴とする多層配線板。   A multilayer wiring board in which two or more conductor layers formed containing copper are alternately laminated with insulating layers and an electronic component is mounted on the upper surface, and is formed on a part of at least one conductor layer A multilayer wiring board, characterized in that a flexible part having a lower rigidity than other parts of the conductor layer is formed. 前記柔軟部が、前記導体層の単位面積あたりの銅面積比率を前記他の部分よりも減少させることによって形成されていることを特徴とする請求項１に記載の多層配線板。   The multilayer wiring board according to claim 1, wherein the flexible portion is formed by reducing a copper area ratio per unit area of the conductor layer as compared with the other portion. 前記柔軟部が、前記電子部品の実装エリアの周縁の１点から所定の半径で描いた円を含む領域であって、かつ前記実装エリア外に形成されていることを特徴とする請求項１又は２に記載の多層配線板。   2. The flexible portion is a region including a circle drawn with a predetermined radius from one point on the periphery of the mounting area of the electronic component, and is formed outside the mounting area. 2. The multilayer wiring board according to 2. 前記実装エリアの長辺の長さをＬとしたとき、前記半径が１０／Ｌ以上３／Ｌ未満に設定されていることを特徴とする請求項３に記載の多層配線板。   4. The multilayer wiring board according to claim 3, wherein the radius is set to 10 / L or more and less than 3 / L, where L is the length of the long side of the mounting area. 前記柔軟部の前記銅面積比率が５０パーセント以上７０パーセント未満であることを特徴とする請求項２に記載の多層配線板。   The multilayer wiring board according to claim 2, wherein the copper area ratio of the flexible portion is 50% or more and less than 70%. 前記柔軟部が設けられた前記導体層のうち、前記柔軟部を除く領域の銅面積率が７０％以上であることを特徴とする請求項２に記載の多層配線板。   3. The multilayer wiring board according to claim 2, wherein a copper area ratio in a region excluding the flexible portion of the conductor layer provided with the flexible portion is 70% or more. 前記柔軟部が、前記導体層の表面に円形もしくは多角形の抜きパターンを設けることによって形成されていることを特徴とする請求項２に記載の多層配線板。   The multilayer wiring board according to claim 2, wherein the flexible portion is formed by providing a circular or polygonal cut pattern on a surface of the conductor layer. 請求項１から７のいずれか一項に記載の多層配線板と、
前記多層配線板の上面に実装された半導体装置と、
を備えたことを特徴とする半導体装置パッケージ。 The multilayer wiring board according to any one of claims 1 to 7,
A semiconductor device mounted on the upper surface of the multilayer wiring board;
A semiconductor device package comprising:
JP2006334478A 2006-12-12 2006-12-12 Multilayer wiring board, and semiconductor device package Withdrawn JP2008147498A (en)

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JP2017017181A (en) * 2015-07-01 2017-01-19 大日本印刷株式会社 Multilayer wiring structure and semiconductor device using the same
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JP2014022716A (en) * 2012-07-23 2014-02-03 Zhuhai Advanced Chip Carriers & Electronic Substrates Solutions Technologies Co Ltd Multilayer electronic support structure with integral constructional elements
KR101679619B1 (en) 2012-07-23 2016-11-25 액세스 어드밴스드 칩 캐리어즈 앤드 이-서브스트레이트 솔루션즈 Multilayer electronic structure with integral construction elements
CN105990307A (en) * 2015-03-06 2016-10-05 恒劲科技股份有限公司 Packaging substrate, packaging structure comprising packaging substrate, and manufacturing method thereof
JP2017017181A (en) * 2015-07-01 2017-01-19 大日本印刷株式会社 Multilayer wiring structure and semiconductor device using the same
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US10276515B2 (en) 2015-09-25 2019-04-30 Dai Nippon Printing Co., Ltd. Mounting component, wiring substrate, electronic device and manufacturing method thereof
US10672722B2 (en) 2015-09-25 2020-06-02 Dai Nippon Printing Co., Ltd. Mounting component and electronic device
JP2021061425A (en) * 2015-09-25 2021-04-15 大日本印刷株式会社 Mounting component, wiring board, electronic device, and manufacturing method thereof
JP7052860B2 (en) 2015-09-25 2022-04-12 大日本印刷株式会社 Mounting components, wiring boards, electronic devices, and their manufacturing methods
JP2019195108A (en) * 2019-08-06 2019-11-07 大日本印刷株式会社 Multilayer wiring structure and semiconductor device using multilayer wiring structure
JP2021061446A (en) * 2019-08-06 2021-04-15 大日本印刷株式会社 Multilayer wiring structure and semiconductor device including multilayer wiring structure

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