JP2005260144A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof wherein the handling of a thin semiconductor substrate is highly reliable with an electrode member penetrating therethrough from the main surface to the rear face starting from rear-face grinding and terminating by dicing to complete individual chips. <P>SOLUTION: A post hole 12 is formed in the semiconductor substrate 10 in the direction from the main surface to the rear face at the position of the electrode pad 11 of the semiconductor substrate 10 having an integrated circuit constructed on the main surface thereof. After an insulating film 13 is formed on the inner wall of the hole 12, at least an electrode post 14 is formed. Then, a protecting tape 16 is stuck on the main surface of the semiconductor substrate 10, and part of the substrate is removed from the rear face side by a predetermined thickness to expose the electrode post 14. This semiconductor substrate 10 is subjected to dicing from the rear face while leaving the stuck protecting tape 16 unchanged. Then, the adhesive strength of the protecting tape 16 is reduced and the chips of cut semiconductor substrate 10 are separated from the protecting tape 16. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a semiconductor device that handles a thin semiconductor chip having an electrode member penetrating from a main surface to a back surface, particularly for using a three-dimensional mounting structure, and a semiconductor device.

  As a countermeasure for high-density mounting of semiconductor chips, a three-dimensional mounting structure in which a plurality of semiconductor chips are stacked and mounted has come into practical use. In a three-dimensional mounting structure, a thin semiconductor chip having an electrode member penetrating from the main surface to the back surface may be used. In order to form this thin semiconductor chip, a back grinding process of the semiconductor substrate is required. In the back grinding process, a protective tape for grinding is usually applied to the entire main surface of the semiconductor substrate constituting the integrated circuit. Thereafter, the main surface side of the semiconductor substrate is held by the back surface grinding apparatus, and the back surface of the semiconductor substrate is ground by a predetermined thickness by the grinding member. By the back surface grinding process, the electrode member embedded and formed partway from the main surface of the semiconductor substrate toward the back surface is exposed.

  The semiconductor substrate is separated for each chip after the back grinding process as described above. At this time, the protective tape for grinding is peeled off, and a thin semiconductor substrate is handled and a dicing tape (also referred to as a die attach tape) is attached to the back side. Thereafter, the semiconductor substrate is cut into chips by inserting a dicing blade along the scribe line from the main surface. However, it is difficult to handle a semiconductor substrate that is ultra-thin (100 μm or less, 80 μm or less). There is a problem of warping and cracking until the protective tape for grinding is removed and handling and dicing tape are finished.

On the other hand, there is a tip dicing technique in which a dicing groove is formed before entering the back surface grinding process of the semiconductor substrate (see, for example, Patent Document 1). That is, through the back grinding process, the electrode member is exposed and the dicing groove is exposed, and the dicing is completed. The semiconductor substrate is easy to handle because it is in the form of individual chips with the protective tape for grinding applied.
Japanese Patent Laying-Open No. 2003-188134 (FIGS. 13-15)

  In the conventional technique (for example, Patent Document 1), there is a step of applying a dicing tape even if the dicing is performed first, and a dicing groove having a considerable depth is formed from the main surface of the semiconductor substrate. Then, the dicing tape is peeled off from the semiconductor substrate having the dicing grooves, and a protective tape for back surface grinding is attached to the main surface of the semiconductor substrate.

  When the dicing tape is peeled off from the semiconductor substrate having the dicing groove, since the dicing groove is provided, the warpage of the semiconductor substrate is increased, and there is a danger that the semiconductor substrate may be broken at worst. Further, a back surface grinding protective tape is attached to the main surface of the semiconductor substrate on which the dicing grooves are formed, and the back surface is ground. As a result, the groove is a cause of scratches and contamination, the semiconductor substrate is distorted by the grinding pressure, and a crack is caused.

  The present invention has been made in consideration of the above circumstances, and has high reliability in handling from back surface grinding to dicing and individual chips for a thin semiconductor substrate having an electrode member penetrating from the main surface to the back surface. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing a semiconductor device and a semiconductor device capable of obtaining high performance.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a post hole having a predetermined depth from a main surface side to a back surface side at a predetermined position of a semiconductor substrate constituting an integrated circuit on the main surface side, and the post hole Forming an insulating film on the inner wall, forming an electrode post having a conductive member embedded in at least the post hole, attaching a tape to the main surface side of the semiconductor substrate, and a back surface of the semiconductor substrate A step of removing the side by a predetermined thickness, exposing the electrode post, a step of cutting the semiconductor substrate from the back surface with the tape attached, a step of reducing the adhesive strength of the tape, and cutting Separating the semiconductor substrate from the tape.

  According to the method of manufacturing a semiconductor device according to the present invention, the semiconductor substrate is cut from the back surface while the tape is attached to the main surface even after the step of exposing the electrode posts. Since the semiconductor substrate is processed to be thin, it is possible to align the cutting position from the back side using infrared fluoroscopy or the like. This minimizes handling of a thin semiconductor substrate and reduces damage due to the influence of warping.

The semiconductor device manufacturing method according to the present invention preferably has one of the following characteristics to improve microfabrication and its reliability.
The step of forming the electrode posts uses either metal embedding by chemical vapor deposition, metal embedding using electroplating or electroless plating.
The method further includes forming a bump electrode on the electrode post.
The step of exposing the electrode post mainly includes a mechanical grinding step, a chemical wet etching step, and a dry etching step with respect to the back surface of the semiconductor substrate.
The step of exposing the electrode post mainly includes a mechanical grinding step and a dry etching step with respect to the back surface of the semiconductor substrate.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a post hole having a predetermined depth from a main surface side to a back surface side at a predetermined position of a semiconductor substrate constituting an integrated circuit on the main surface side, and the post hole Forming an insulating film on the inner wall, forming an electrode post having a conductive member embedded in at least the post hole, attaching a first tape to the main surface of the semiconductor substrate, and the semiconductor Removing the back side of the substrate by a predetermined thickness, exposing the electrode post, attaching a second tape to the back side of the semiconductor substrate, and attaching the first and second tapes; A step of cutting the semiconductor substrate as it is, a step of reducing the adhesive force of at least one of the first and second tapes, and the first and second tapes of the cut semiconductor substrate. And a step of separating at least one of the tapes, the.

  According to the method for manufacturing a semiconductor device of the present invention, the first tape remains adhered to the main surface even when the semiconductor substrate is cut after the step of exposing the electrode posts. In addition, the second tape is also attached to the back surface before cutting the semiconductor substrate. Thereby, handling becomes easy. The semiconductor substrate can be cut regardless of which side of the main surface or the back surface is the bottom. The cut semiconductor substrate is formed into a chip shape with the first tape and the second tape adhered to both the main surface and the back surface. Thereafter, it is handled as an individual chip by appropriately peeling from one of the tapes. At that time, the tape attached to either the main surface or the back surface protects the thin chip from damage such as warpage. The semiconductor substrate can also maintain a chip-like matrix arrangement while protecting both the main surface and the back surface. This minimizes handling of a thin semiconductor substrate and reduces damage due to the influence of warping.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a post hole having a predetermined depth from a main surface side to a back surface side at a predetermined position of a semiconductor substrate constituting an integrated circuit on the main surface side, and the post hole Forming an insulating film on the inner wall, forming an electrode post having a conductive member embedded in at least the post hole, attaching a first tape to the main surface of the semiconductor substrate, and the semiconductor Removing the back surface side of the substrate by a predetermined thickness and exposing the electrode post; cutting the semiconductor substrate from the back surface while the first tape is adhered; and a step on the back surface side of the semiconductor substrate. 2 affixing the tape, reducing the adhesive strength of at least one of the first and second tapes, and cutting the semiconductor substrate into the first and second tapes. Of including a step of separating at least one of the tapes.

  According to the method of manufacturing a semiconductor device according to the present invention, the semiconductor substrate is still attached with the first tape on the main surface when the semiconductor substrate is cut from the back surface after the step of exposing the electrode posts. In addition, after the semiconductor substrate is cut, the second tape is also attached to the back surface side. The cut semiconductor substrate can be easily handled while the first tape and the second tape are still attached to both the main surface and the back surface. The semiconductor substrate can be divided into individual chips by separating either the first tape on the main surface side or the second tape on the back surface side. In addition, a chip-like matrix arrangement can be maintained. At this time, both the first and second tapes are basically not cut together with the chip, and therefore suitable for handling such as movement while maintaining the chip-like matrix arrangement. This minimizes handling of a thin semiconductor substrate and reduces damage due to the influence of warping.

In each of the above-described semiconductor device manufacturing methods according to the present invention, it is preferable to have one of the following features to improve microfabrication and its reliability.
The step of forming the electrode posts uses either metal embedding by chemical vapor deposition, metal embedding using electroplating or electroless plating.
The method further includes forming a bump electrode on the electrode post.
The step of exposing the electrode post mainly includes a mechanical grinding step, a chemical wet etching step, and a dry etching step with respect to the back surface of the semiconductor substrate.
The step of exposing the electrode post mainly includes a mechanical grinding step and a dry etching step with respect to the back surface of the semiconductor substrate.

  The semiconductor device according to the present invention includes an electrode related to the integrated circuit, including an integrated circuit formed on the main surface side of each chip cut from the semiconductor substrate, and the one penetrating from the main surface side to the back surface side. , A first tape attached so as to cover the main surface side, and a second tape attached so as to cover the back surface side.

The semiconductor device according to the present invention is easy to handle while the first tape and the second tape are adhered to both the main surface and the back surface in the form of a thin chip. This reduces the damage of the thin chip that is easily warped and easily deformed.
The semiconductor device according to the present invention is characterized in that the first tape or the second tape maintains a matrix-like arrangement immediately after being cut into the chips.

BEST MODE FOR CARRYING OUT THE INVENTION

FIGS. 1A to 1F are cross-sectional views showing the main parts of the method for manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps.
As shown in FIG. 1A, with respect to a silicon semiconductor substrate 10 constituting an integrated circuit (not shown) on the main surface side, a predetermined depth from the main surface side to the back surface side is provided at the position of the uppermost electrode pad 11. A post hole 12 is formed. At this time, the metal of the uppermost electrode pad 11 is formed on the entire surface, and the post holes 12 are selectively formed using a resist mask or the like. Thereafter, an insulating film 13 is formed on the inner wall of the post hole 12. The insulating film 13 may be formed of an oxide film or a non-doped polycrystalline silicon film on the inner wall of the silicon.

  Next, an electrode post 14 in which a conductive member is embedded in the post hole 12 is formed. As the conductive member of the electrode post 14, a CVD (chemical vapor deposition) metal of Al or W, Cu or the like can be considered. As a conductive member of the electrode post 14, an adhesion layer and a barrier layer are also formed on the base of the main electrode material if necessary (not shown).

  For example, Cu is embedded in the electrode post 14 as follows. After forming a seed layer in the post hole 12 and forming a resist mask, a Cu electrode post 14 is selectively formed by electrolytic plating. Further, an electroless plating method may be used. Thereafter, the uppermost wiring and the electrode pad 11 are patterned by etching. Further, a passivation film 15 is formed to selectively expose the electrode pad 11 portion. Although not shown, bump electrodes may be further formed on the electrode pads 11 thereafter.

  Next, as shown in FIG. 1B, the protective tape 16 is attached to the main surface side of the semiconductor substrate 10. As the protective tape 16, for example, a UV curable tape capable of curing the adhesive material of the tape by UV (ultraviolet) irradiation, that is, reducing the adhesive force, is used. The UV curable tape is an insulating resin-based protective tape, for example, having a thickness of 150 to 200 μm, of which an adhesive layer of 20 to 60 μm excellent in UV curing. The protective tape 16 is not limited to this. When bump electrodes are arranged on the electrode pads 11, it is conceivable to use a tape having a thickness that can be protected and dealt with. In addition to the UV curable tape, if there is a tape having strong adhesive force and peeling performance and having weather resistance and reliability, it may be used.

  Next, as shown in FIG.1 (c), it transfers to the back surface grinding process of the semiconductor substrate 10. FIG. That is, in the back surface grinding apparatus (not shown), the main surface side of the semiconductor substrate 10 to which the protective tape 16 is attached is fixed to the grinding stage, and the corresponding back surface side is ground by a predetermined thickness by a grinding member (grinding stone). This is mainly a mechanical grinding process, but is not limited to this, and it is also conceivable to use a CMP (Chemical Mechanical Polishing) technique. At this stage, the electrode post 14 is not exposed, and the grinding is preferably completed immediately before the electrode post 14 is exposed and when the insulating film 13 is exposed.

Next, as shown in FIG. 1D, the electrode post 14 is exposed by further thin layer removal on the back surface of the semiconductor substrate 10. First, a spin etch process by supplying a chemical solution is performed on the back surface of the semiconductor substrate 10 to project the shape of the electrode posts 14. For example, a liquid mixture containing fluoric acid and nitric acid (HF / HNO ₃ / H ₂ O; the ratio is about 1: 1: 8) is used as the chemical solution. Thereafter, the insulating film 13 covering the electrode post 14 is removed by a dry etching process.

  Note that it is possible to omit the spin etch process by supplying the chemical solution. For example, the electrode post 14 is exposed in the back surface grinding process of the semiconductor substrate 10 in the previous stage. Thereafter, the insulating film 13 covering the predetermined thickness of the semiconductor substrate 10 and the electrode post 14 can be removed simultaneously through a dry etching process. Alternatively, the electrode post 14 is exposed from the whole or a middle portion by using a CMP (chemical mechanical polishing) technique. Thereafter, the insulating film 13 covering the predetermined thickness of the semiconductor substrate 10 and the electrode post 14 can be removed simultaneously through a dry etching process.

  Next, as shown in FIG. 1E, the semiconductor substrate 10 proceeds to the dicing process with the protective tape 16 still attached. That is, the semiconductor substrate 10 is cut from the back surface with the protective tape 16 for grinding applied. In this dicing process, for example, a technique of aligning the cutting position from the back side by infrared fluoroscopy is used. That is, since the semiconductor substrate 10 has already been processed to be as thin as 100 μm or less (or 80 μm or less), alignment using infrared fluoroscopy or the like for reading a scribe line from the back surface side is possible. After dicing, the protective tape 16 is not completely separated but remains one.

  Next, as shown in FIG. 1F, the semiconductor substrate 10 can be easily separated from the protective tape 16 if the protective tape 16 is irradiated with UV. The semiconductor substrate 10 shifts to handling such as assembling, mounting, transportation, packing, and transportation as individual chips. Alternatively, the semiconductor substrate 10 shifts to handling such as assembly, attachment, transportation, packing, and transportation while maintaining a matrix arrangement immediately after being divided into individual chips.

  According to the above-described embodiment, the semiconductor substrate 10 is cut from the back surface with the same protective tape 16 attached to the main surface after the step of exposing the electrode posts 14. Since the semiconductor substrate 10 is processed to be thin, it is possible to align the cutting position from the back side using infrared fluoroscopy or the like. As the protective tape 16, in addition to the UV curable tape, if there is a tape having strong adhesive force and peeling performance, and having weather resistance and reliability, it can be used. It is important that the protective tape 16 can share the state of being attached to the main surface side of the semiconductor substrate 10 by grinding the back surface side with respect to the main surface side of the semiconductor substrate 10 and dicing from the back surface side, both processes. . This minimizes handling of a thin semiconductor substrate and reduces damage due to the influence of warping.

2A to 2G are cross-sectional views showing the main part of the method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps. The same parts as those in the first embodiment will be described with the same reference numerals.
As shown in FIG. 2A, regarding a silicon semiconductor substrate 10 constituting an integrated circuit (not shown) on the main surface side, a predetermined depth from the main surface side to the back surface side is provided at the position of the uppermost electrode pad 11. A post hole 12 is formed. At this time, the metal of the uppermost electrode pad 11 is formed on the entire surface, and the post holes 12 are selectively formed using a resist mask or the like. Thereafter, an insulating film 13 is formed on the inner wall of the post hole 12. The insulating film 13 may be formed of an oxide film or a non-doped polycrystalline silicon film on the inner wall of the silicon.

  Next, an electrode post 14 in which a conductive member is embedded in the post hole 12 is formed. As the conductive member of the electrode post 14, a CVD (chemical vapor deposition) metal of Al or W, Cu or the like can be considered. As the conductive member of the electrode post 14, an adhesion layer or a barrier layer may be formed on the base of the main electrode material (not shown).

  For example, Cu is embedded in the electrode post 14 as follows. After forming a seed layer in the post hole 12 and forming a resist mask, a Cu electrode post 14 is selectively formed by electrolytic plating. Further, an electroless plating method may be used. Thereafter, the uppermost wiring and the electrode pad 11 are patterned by etching. Next, a passivation film 15 is formed to selectively expose a portion of the electrode pad 11. Further, the bump electrode 21 is formed on the electrode pad 11. The bump electrode 21 is formed on the electrode pad 11 by an electrolytic plating method after forming a seed layer (not shown) on the electrode pad 11 and forming a resist mask. Further, an electroless plating method may be used. Of course, a configuration in which the bump electrode 21 is not formed as in the first embodiment is also conceivable.

  Next, as shown in FIG. 2B, a protective tape 22 is attached to the main surface side of the semiconductor substrate 10. As the protective tape 22, for example, a UV curable tape capable of curing the adhesive material of the tape by UV (ultraviolet) irradiation, that is, reducing the adhesive force, is used. It is important to use a tape having a thickness that can protect the main surface side of the semiconductor substrate 10 with the bump electrodes 21 as the protective tape 22. In addition to the UV curable tape, if there is a tape having strong adhesive force and peeling performance and having weather resistance and reliability, it may be used.

  Next, as shown in FIG. 2C, the process proceeds to the back surface grinding process of the semiconductor substrate 10. That is, in a back grinding apparatus (not shown), the main surface side of the semiconductor substrate 10 to which the protective tape 22 is attached is fixed to a grinding stage, and the opposite back side is ground by a predetermined thickness by a grinding member (grinding stone). This is mainly a mechanical grinding process, but is not limited to this, and it is also conceivable to use a CMP (Chemical Mechanical Polishing) technique. Grinding conditions such as changing the grindstone may be changed immediately before the electrode post 14 is exposed. At this stage, at least the insulating film 13 is exposed or the tip of the electrode post 14 is exposed, and the grinding (or polishing) is finished.

Next, as shown in FIG. 2D, the electrode post 14 is exposed by further thin layer removal on the back surface of the semiconductor substrate 10. Here, a dry etching process is performed. Depending on the conditions of the etching gas, it is possible to remove the predetermined thickness of the semiconductor substrate 10 and simultaneously remove the insulating film 13 covering the electrode posts 14.
In addition, the process of exposing such an electrode post 14 is not limited, You may utilize the method demonstrated in FIG.1 (c), (d) in 1st Embodiment.

  Next, as shown in FIG. 2E, a protective tape 23 is attached to the back side of the semiconductor substrate 10. For the protective tape 23, use of a UV curable tape can be considered. Alternatively, if there is another tape (such as a dicing tape) having strong adhesive force, peeling performance, and reliability, it may be used.

Next, as shown in FIG. 2F, the semiconductor substrate 10 proceeds to the dicing process in a state where the protective tapes 22 and 23 are adhered to the main surface and the back surface, respectively. The semiconductor substrate 10 is cut with the protective tape 22 for grinding applied to the main surface. In this dicing process, the semiconductor substrate 10 is supported on the back side to which the protective tape 23 is attached, and is cut along the dicing line from the main surface side. After dicing, the protective tape 23 is not completely separated but remains one.
The dicing process may take a method of dicing by reading a scribe line from the back side as in the first embodiment. At that time, the protective tape 22 is not completely separated but remains one (not shown).

  Next, as illustrated in FIG. 2G, the semiconductor substrate 10 can be easily separated from the protective tape 23 by performing UV irradiation on the protective tape 23. The semiconductor substrate 10 shifts to handling such as assembling, mounting, transportation, packing, and transportation as individual chips. Alternatively, the semiconductor substrate 10 shifts to handling such as assembly, attachment, transportation, packing, and transportation while maintaining a matrix arrangement immediately after being divided into individual chips. When handled as individual chips, a protective tape 22 is attached to the back surface of the chip. The stage at which the protective tape 22 is peeled can be freely determined. Until the protective tape 22 is peeled off, it contributes to protection against damage such as warpage even in the state of individual thin chips.

  According to the above embodiment, the semiconductor substrate 10 remains attached with the same protective tape 22 on the main surface when it is cut after the step of exposing the electrode posts 14. In addition, the protective tape 23 is attached to the back side before the semiconductor substrate 10 is cut. Thereby, handling becomes easy. The semiconductor substrate 10 can be cut regardless of which side of the main surface or the back surface is the bottom. The cut semiconductor substrate 10 is formed into a chip shape with the protective tapes 22 and 23 attached to both the main surface and the back surface. Thereafter, it is handled as an individual chip by being appropriately peeled from one of the protective tapes. At that time, the tape attached to either the main surface or the back surface protects the thin chip from damage such as warpage. The semiconductor substrate 10 can also maintain a chip-like matrix arrangement while protecting both the main surface and the back surface. As a result, handling of the thin semiconductor substrate 10 is minimized, and damage due to the influence of warpage is reduced.

FIGS. 3A to 3G are cross-sectional views showing the main part of the method of manufacturing a semiconductor device according to the third embodiment of the present invention in the order of steps.
As shown in FIG. 3A, with respect to a silicon semiconductor substrate 30 constituting an integrated circuit (not shown) on the main surface side, a predetermined depth from the main surface side to the back surface side is provided at the position of the uppermost electrode pad 31. A post hole 32 is formed. In this configuration, the uppermost wiring and the electrode pad 31 are both embedded wiring. In this case, after forming the uppermost layer wiring and the formation groove of the electrode pad 31 using the first resist mask, the post hole 32 is formed using the second resist mask (the same procedure as the post via forming method). . Thereafter, the insulating film 33 is formed on the inner wall of the post hole 32 with the second resist mask as it is. The insulating film 33 may be formed of an oxide film or a non-doped polycrystalline silicon film on the inner wall of the silicon.

  Next, the electrode post 34 and the uppermost layer wiring and electrode pad 31 are formed by embedding a conductive member in the formation hole of the post hole 32 and the uppermost layer wiring and electrode pad 31. As the conductive member for the electrode post 34, the uppermost wiring layer, and the electrode pad 31, a CVD (chemical vapor deposition) metal or Cu of Al or W can be considered. As a conductive member for the electrode post 34, the uppermost layer wiring, and the electrode pad 31, it is also possible to form an adhesion layer or a barrier layer on the base of the main electrode material (not shown).

As the electrode post 34 and the uppermost layer wiring and electrode pad 31, for example, Cu embedding is formed as follows. Cu is selectively embedded by electrolytic plating after the formation of the seed layer and the resist mask in the post hole 32 and the uppermost layer wiring and electrode pad 31. Further, an electroless plating method may be used. Thereafter, if necessary, a flattening process using etch back, CMP (chemical mechanical polishing) or the like is performed. Next, a passivation film 35 is formed, and the portion of the electrode pad 31 is selectively exposed. Further, the bump electrode 36 is formed on the electrode pad 31. The bump electrode 36 is formed on the electrode pad 31 by an electrolytic plating method after forming a seed layer (not shown) on the electrode pad 31 and forming a resist mask. Further, an electroless plating method may be used.
Of course, the form of the electrode post 34, the uppermost layer wiring, and the electrode pad 31 may be replaced with the form of FIG. 1A of the first embodiment and the form of FIG. 2A of the second embodiment.

  Next, as shown in FIG. 3B, a protective tape 37 is attached to the main surface side of the semiconductor substrate 30. The protective tape 37 is the same as that of the second embodiment, and for example, a UV curable tape is used. As the protective tape 37, it is important to use a tape having a thickness capable of protecting the main surface side of the semiconductor substrate 30 with the bump electrodes 36. In addition to the UV curable tape, if there is a tape having strong adhesive force and peeling performance and having weather resistance and reliability, it may be used.

  Next, as shown in FIG. 3C, the process proceeds to the back surface grinding process of the semiconductor substrate 30. That is, in the back surface grinding apparatus (not shown), the main surface side of the semiconductor substrate 30 to which the protective tape 37 is attached is fixed to the grinding stage, and the back surface side is ground by a predetermined thickness with a grinding member (grinding stone). This is mainly a mechanical grinding process, but is not limited to this, and it is also conceivable to use a CMP (Chemical Mechanical Polishing) technique. Grinding conditions such as changing the grindstone may be changed immediately before the electrode post 34 is exposed. At this stage, at least the insulating film 33 is exposed or the tip of the electrode post 34 is exposed, and the grinding (or polishing) is finished.

Next, as shown in FIG. 3D, the electrode post 34 is exposed by further thin layer removal on the back surface of the semiconductor substrate 30. Similar to the second embodiment, the dry etching process removes the predetermined thickness of the semiconductor substrate 30 and simultaneously removes the insulating film 33 covering the electrode posts 34.
In addition, the process of exposing such an electrode post 34 is not limited, You may utilize the method demonstrated in FIG.1 (c), (d) in 1st Embodiment.

  Next, as shown in FIG. 3E, the semiconductor substrate 30 proceeds to the dicing process with the protective tape 37 still attached. That is, the semiconductor substrate 30 is cut from the back surface while the protective tape 37 for grinding is adhered. In this dicing process, as in the first embodiment, for example, a technique of aligning the cutting position from the back side by infrared fluoroscopy is used. After dicing, the protective tape 37 is not completely separated but remains one.

  Next, as shown in FIG. 3F, a protective tape 38 is attached to the back side of the semiconductor substrate 30. For the protective tape 38, use of a UV curable tape can be considered. Alternatively, if there is another tape having strong adhesive force, peeling performance and reliability, it may be used.

  Next, as shown in FIG. 3G, the semiconductor substrate 30 can be easily separated from the protective tape 37 or 38 if the protective tape 37 or 38 is irradiated with UV. The semiconductor substrate 30 shifts to handling such as assembling, mounting, transportation, packing, and transportation as individual chips. Alternatively, the semiconductor substrate 30 shifts to handling such as assembly, attachment, conveyance, packing, and conveyance while maintaining the matrix arrangement immediately after being divided into individual chips. In this configuration, both the protective tapes 37 and 38 are basically not cut together with the chip. Therefore, it is suitable for handling such as movement while keeping the chip-like matrix arrangement, and is not easily contaminated. By being peeled from one of the protective tapes, handling as individual chips becomes possible. At that time, it is determined according to handling whether the main surface or the back surface of the protective tape 37 or 38 is peeled off. A protective tape affixed to one of the surfaces protects the thin chip from damage such as warping. As a result, handling of the thin semiconductor substrate 30 is minimized, and damage caused by warpage is reduced.

  As described above, according to the present invention, since the electrode member (electrode post) is penetrated from the main surface to the back surface of the semiconductor substrate, the back surface grinding protective tape is attached to the main surface of the semiconductor substrate. After the electrode post is derived by grinding the back surface or the like, dicing is performed from the back surface while the protective tape is still attached. In addition, after the electrode post is led out by grinding the back surface, a protective tape is attached to the back surface and then dicing is performed. Alternatively, after the backside dicing, a protective tape is attached to the backside for protection. At least the main surface of the semiconductor substrate has a protective tape attached from the back grinding stage, and the semiconductor substrate is reliably protected after being thinned. This protective tape is peeled off only at the final stage of handling as a chip. This facilitates handling and reduces damage to thin chips that are easily warped and easily deformed. As a result, there are provided a semiconductor device manufacturing method and a semiconductor device that can obtain high reliability in handling from back surface grinding to dicing and individual chips for a thin semiconductor substrate having an electrode member penetrating from the main surface to the back surface. can do.

Sectional drawing which shows the principal part of the manufacturing method of the semiconductor device which concerns on 1st Embodiment to process order. Sectional drawing which shows the principal part of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment in process order. Sectional drawing which shows the principal part of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment in order of a process.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10,30 ... Semiconductor substrate, 11, 31 ... Electrode pad, 12, 32 ... Post hole, 13, 33 ... Insulating film, 14, 34 ... Electrode post, 15, 35 ... Passivation film, 16, 22, 23, 37, 38 ... protective tape, 21, 36 ... bump electrodes.

Claims (13)

Forming a post hole with a predetermined depth from the main surface side toward the back surface side at a predetermined position of the semiconductor substrate constituting the integrated circuit on the main surface side;
Forming an insulating film on the inner wall of the post hole;
Forming an electrode post having a conductive member embedded in at least the post hole;
A step of attaching a tape to the main surface side of the semiconductor substrate;
Removing the back side of the semiconductor substrate by a predetermined thickness and exposing the electrode posts;
Cutting the semiconductor substrate from the back surface with the tape attached,
Reducing the adhesive strength of the tape;
Separating the cut semiconductor substrate from the tape;
A method of manufacturing a semiconductor device including: The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the electrode post uses any one of metal embedding by chemical vapor deposition, metal embedding using an electroplating method and an electroless plating method. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a bump electrode on the electrode post. The step of exposing the electrode post mainly includes a mechanical grinding step, a chemical wet etching step, and a dry etching step with respect to the back surface of the semiconductor substrate. The manufacturing method of the semiconductor device of description. The method for manufacturing a semiconductor device according to claim 1, wherein the step of exposing the electrode post mainly includes a mechanical grinding step and a dry etching step with respect to the back surface of the semiconductor substrate. Forming a post hole with a predetermined depth from the main surface side toward the back surface side at a predetermined position of the semiconductor substrate constituting the integrated circuit on the main surface side;
Forming an insulating film on the inner wall of the post hole;
Forming an electrode post having a conductive member embedded in at least the post hole;
Attaching a first tape to the main surface side of the semiconductor substrate;
Removing the back side of the semiconductor substrate by a predetermined thickness and exposing the electrode posts;
Attaching a second tape to the back side of the semiconductor substrate;
Cutting the semiconductor substrate with the first and second tapes attached, and
Reducing the adhesive strength of at least one of the first and second tapes;
Separating the cut semiconductor substrate from at least one of the first and second tapes;
A method of manufacturing a semiconductor device including: Forming a post hole with a predetermined depth from the main surface side toward the back surface side at a predetermined location of the semiconductor substrate constituting the integrated circuit on the main surface side;
Forming an insulating film on the inner wall of the post hole;
Forming an electrode post having a conductive member embedded in at least the post hole;
Attaching a first tape to the main surface side of the semiconductor substrate;
Removing the back side of the semiconductor substrate by a predetermined thickness and exposing the electrode posts;
Cutting the semiconductor substrate from the back surface with the first tape attached,
Attaching a second tape to the back side of the semiconductor substrate;
Reducing the adhesive strength of at least one of the first and second tapes;
Separating the cut semiconductor substrate from at least one of the first and second tapes;
A method of manufacturing a semiconductor device including: 8. The method of manufacturing a semiconductor device according to claim 6, wherein the step of forming the electrode post uses any one of metal embedding by a chemical vapor deposition method, metal embedding using an electrolytic plating method or an electroless plating method. . The method for manufacturing a semiconductor device according to claim 6, further comprising a step of forming a bump electrode on the electrode post. The step of exposing the electrode post mainly includes a mechanical grinding step, a chemical wet etching step, and a dry etching step with respect to the back surface of the semiconductor substrate. The manufacturing method of the semiconductor device of description. The method for manufacturing a semiconductor device according to claim 6, wherein the step of exposing the electrode post mainly includes a mechanical grinding step and a dry etching step with respect to the back surface of the semiconductor substrate. An integrated circuit is formed on the main surface side of each chip cut from the semiconductor substrate, and includes electrodes related to the integrated circuit including those penetrating from the main surface side to the back surface side so as to cover the main surface side A semiconductor device comprising: a first tape affixed to a first tape; and a second tape affixed to cover the back side. 13. The semiconductor device according to claim 12, wherein the first tape or the second tape maintains a matrix arrangement immediately after being cut into the chips from the semiconductor substrate.

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