WO2004012247A1 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
WO2004012247A1
WO2004012247A1 PCT/JP2003/008906 JP0308906W WO2004012247A1 WO 2004012247 A1 WO2004012247 A1 WO 2004012247A1 JP 0308906 W JP0308906 W JP 0308906W WO 2004012247 A1 WO2004012247 A1 WO 2004012247A1
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WO
WIPO (PCT)
Prior art keywords
chip
protective tape
tape
dicing
semiconductor
Prior art date
Application number
PCT/JP2003/008906
Other languages
French (fr)
Japanese (ja)
Inventor
Satoshi Bannai
Original Assignee
Sony Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corporation filed Critical Sony Corporation
Publication of WO2004012247A1 publication Critical patent/WO2004012247A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386Separation by peeling
    • H01L2221/6839Separation by peeling using peeling wedge or knife or bar

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of picking up and mounting a semiconductor chip thinned by back grinding of a semiconductor wafer without damaging or damaging the semiconductor chip.
  • FIGS. 4A to 4G show a first conventional example for explaining various steps from the production of a thin semiconductor chip to the mounting thereof.
  • This conventional example is the most general process, and is suitable mainly when the target value for thinning is a wafer thickness of 150 ⁇ m or more.
  • An adhesive protective tape 8 is attached to the surface (element formation surface) of the semiconductor wafer 10 on which the element is formed (FIG. 4A), and then the back surface of the semiconductor wafer 10 is ground using the grinding device 1. (Figure 4B). Then, after the protective tape 8 is peeled off from the surface of the semiconductor wafer 10 using the peeling tape 2 or the like (FIG. 4C), the semiconductor wafer 10 is mounted on the ring frame 3 via the adhesive dicing tape 9. (FIG. 4D), dicing saw 4 singulates semiconductor ⁇ a wafer 10 (FIG. 4E). After dicing process, semiconductor The chip 11 is pushed up to the needle 5 and is sucked by the collet 6 at the same time (FIG. 4F), and is mounted on the lead frame 7 using the mounter 12 (FIG. 4G).
  • This method is applied to wafers with a wafer thickness of 150 ⁇ m or less, since the semiconductor wafer 10 may crack or chip during handling during the back grinding process to the dicing process. I can't do it.
  • FIGS. 5A to 5G a half-power dicing process for the surface of the semiconductor wafer 20 (FIG. 5A), and the application of the protective tape 8 to the surface of the semiconductor wafer 20 Process (Fig. 5B), grinding process of semiconductor wafer 20 back surface (Fig. 5C), wafer mounting process (Fig. 5D), peeling process of protective tape 8 (Fig. 5E), pick-up process of semiconductor chip 21 (Fig. 5F) and the chip mounting process (Fig. 5G).
  • a semiconductor wafer 20 is individually formed by forming a groove at a depth corresponding to a target wafer thickness in an initial half-die dicing process, and thereafter performing back surface grinding to the groove.
  • the semiconductor chip 21 is divided into two. Therefore, as compared with the first conventional example, cracking of the semiconductor wafer 20 at the time of the above-mentioned handling can be avoided, and the thickness can be reduced to 150 ⁇ m or less.
  • the semiconductor chip thinning process according to the second conventional example is disclosed, for example, in Japanese Patent Application Laid-Open No. 2002-16021.
  • FIG. 6A and FIG. Affixing process of protective tape 8 to wafer 30 surface ( ⁇ 6A), grinding process of backside of semiconductor wafer 30 (Fig. 6B), wafer mounting process (Fig. 6C), peeling process of protective tape 8 (Fig. 6C) It consists of a dicing process (Fig. 6D), a semiconductor chip 31 pick-up process (Fig. 6F), and a chip mounting process (Fig. 6G).
  • the semiconductor wafer 30 by providing a step of peeling the protective tape 8 adhered to the surface of the semiconductor wafer 30 before the dicing step after the wafer mounting step, the semiconductor wafer 30 during the transportation from the back surface grinding step to the dicing step is provided.
  • the protection tape 8 is used to prevent cracks and chips in the chip. As a result, a chip thickness of 150 m or less is realized.
  • the semiconductor chip thinning process according to the third conventional example is disclosed in Japanese Patent No. 2879797.
  • the so-called needleless method is used in the pick-up process of the semiconductor chips 21 and 31.
  • This is a method in which an ultraviolet-curing dicing tape 9 is used to pick up the semiconductor chips 21 and 31 while irradiating the dicing tape 9 with ultraviolet light to reduce the adhesive force.
  • the semiconductor chips 21 and 31 can be prevented from being cracked or chipped as compared with the needle type pickup method used in the conventional example.
  • the pickup step and the mounting step of a semiconductor chip thinned to 150 ⁇ m or less can be properly performed.
  • the die-resistant pick-up of the needleless method is required because the bending resistance of the semiconductor chip is extremely reduced.
  • the semiconductor chip may be broken at the time of pickup, depending on the method of picking up.
  • the present invention has been made in view of the above problems, and has as its object to provide a method of manufacturing a semiconductor device capable of appropriately picking up and mounting an ultra-thin semiconductor chip of 50 ⁇ m or less. Disclosure of the invention
  • the method for manufacturing a semiconductor device includes a protective tape attaching step of attaching a protective tape for grinding a back surface to the surface of the semiconductor wafer, and a grinding process for grinding the back surface of the semiconductor wafer to reduce the thickness.
  • a protective tape attaching step of attaching a protective tape for grinding a back surface to the surface of the semiconductor wafer, and a grinding process for grinding the back surface of the semiconductor wafer to reduce the thickness.
  • Back surface grinding process dicing adhesive tape is applied to the back surface of the thinned semiconductor wafer, the dicing process is used to divide the semiconductor wafer into individual chips together with the protective tape, and the chips are picked up and transferred to the chip mounting section.
  • a protective tape separating step of separating the protective tape from the chip surface.
  • the dicing, pick-up, and chip mounting processes after grinding the back surface of the wafer are performed not with the chip alone, but with the protective tape attached, thereby reducing the bending resistance of the chip. Because of this, an ultra-thin semiconductor chip of 50 ⁇ or less can be picked up and mounted without damaging it.
  • a UV-curable tape material is used for the protective tape, and the protective tape is separated by irradiating UV rays to reduce the adhesive strength.
  • FIG. 1A to 1H are perspective views illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention.
  • 1A shows a protective tape attaching process
  • FIG. 1B shows a back surface grinding process
  • FIG. 1C shows a post process of the wafer back surface
  • FIG. 1D shows a wafer mounting process
  • FIG. 1E shows a dicing process
  • 1F shows an ultraviolet irradiation step
  • FIG. 1G shows a pickup step
  • FIG. 1H shows a chip mounting step.
  • FIG. 2 is a perspective view for explaining a manufacturing process of the semiconductor device according to the embodiment of the present invention, and shows a protective tape separating process.
  • FIG. 3 is a flowchart illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention.
  • FIG. 4A to 4G are perspective views illustrating the steps of manufacturing the semiconductor device according to the first conventional example.
  • 4A shows the protective tape attaching process
  • FIG. 4B shows the back surface grinding process
  • FIG. 4C shows the protective tape separating process
  • FIG. 4D shows the wafer mounting process
  • FIG. 4E shows the dicing process
  • 4F shows a pick-up process
  • FIG. 4G shows a chip mounting process.
  • FIG. 5A to 5G are perspective views illustrating the steps of manufacturing a semiconductor device according to the second conventional example.
  • FIG. 5A shows a half-cut dicing process
  • FIG. 5B shows a protective tape attaching process
  • FIG. 5C shows a back surface grinding process
  • FIG. 5D shows a wafer mounting process
  • FIG. 5E shows a protective tape separating process.
  • Show, FIG. 5F shows a pickup process
  • FIG. 5G shows a chip mounting process.
  • FIG. 6A to 6G are perspective views illustrating the steps of manufacturing a semiconductor device according to a third conventional example.
  • FIG. 6A shows a protective tape attaching process
  • FIG. 6B shows a back surface grinding process
  • FIG. 6C shows a wafer mounting process
  • FIG. 6D shows a protective tape separating process
  • FIG. 6E shows a dicing process
  • FIG. 6F shows a pick-up process
  • FIG. 6G shows a chip mounting process.
  • 1A to 3 show an embodiment of the present invention.
  • FIGS. 1A to 1H are perspective views schematically illustrating each step of the present embodiment
  • FIG. 2 is an explanatory view of a chip mounting step
  • FIG. 3 is a process flow diagram of the present embodiment. .
  • FIG. 1A shows a protective tape attaching process in which a protective tape 42 for backside grinding is attached to the front surface 40 a of the semiconductor wafer 40 (step S 1), and the protection for the wafer surface 40 a is performed. Conventionally, a common laminating device 43 is applied for attaching the tape 42.
  • the thickness of the protective tape 42 can be appropriately selected, and is selected according to the planar state of the wafer surface 40a. That is, when a metal projection such as a bump is formed on each element of the wafer surface 40a, a thickness that can absorb the metal projection is required.
  • the thickness of the protective tape 42 is about 200 ⁇ m.
  • the protective tape 42 is made of a UV-curable and heat-shrinkable adhesive tape.
  • a dicing tape (N series) manufactured by Lintec Corporation is used as the protective tape 42.
  • a grinding process of the back surface 40b of the semiconductor wafer 40 using the back surface grinding device 44 is performed (Step S2).
  • the amount of grinding is determined according to the target wafer thickness.
  • the wafer thickness is reduced to about 20 ⁇ m by the back surface grinding step.
  • FIG. 1C shows a post-processing step after backside grinding.
  • This post-processing step is performed for the purpose of removing residual stress on the wafer back surface 40b after the back surface grinding step, and mechanical polishing by a polishing device 45 or wet etching is performed as necessary.
  • the protective tape 42 can function as a mask covering the wafer surface 40a.
  • step S 3 a step of mounting the thinned semiconductor wafer 40 on a ring frame 48 via a dicing adhesive tape (dicing tape) 47 is performed (step S 3). .
  • the dicing tape 47 an ultraviolet-curing tape that facilitates chip pickup later is used.
  • the semiconductor wafer 40 since the semiconductor wafer 40 has a protective tape 42 attached to the surface 40a of the semiconductor wafer 40 to enhance the bending resistance, the semiconductor wafer 40 may be broken during handling. Is prevented.
  • FIG. 1E shows the dicing process (step S 4).
  • the semiconductor wafer 40 is divided into individual chips together with the protective tape 42 attached to the surface 40a.
  • the blade 49 may be clogged in a general single cut, and the dicing quality may be degraded.
  • a step-cut method of dicing the semiconductor wafer 40 by exchanging the blades 49 after dicing only the protection tape 42 first can be applied.
  • step S5 the protective tape 42 attached to the front surface 40a of the diced semiconductor wafer 40 and the dicing tape attached to the back surface 40b of the semiconductor wafer 40
  • each of the protective tape 42 and the dicing tape 47 is made of a UV-curable tape material, the protective tape 42 and the dicing tape 47 are cured by irradiation with ultraviolet light, and the adhesive strength to the semiconductor wafer 40 is reduced.
  • the process of irradiating the protective tape 42 with ultraviolet light and the process of irradiating the dicing tape 47 with ultraviolet light are performed at the same time to reduce the process cost.
  • the ultraviolet irradiation step for each of the protective tape 42 and the dicing tape 47 is not limited to the case where the steps are performed simultaneously.
  • step S6 a chip 41 pickup process is performed.
  • a conventional needleless method is used for separation between the chip 41 and the dicing tape 47 during pickup.
  • the dicing tape 47 cured in the previous ultraviolet irradiation step, although the adhesive strength between the back surface of the chip 41 and the back surface is reduced, the integrated relationship between the two surfaces is still maintained due to the adhesive action between the surfaces. I have. Therefore, the separating device 52 is disposed directly below the dicing tape 47, and the slider 52a, which can move horizontally along the lower surface of the chip to be picked up, is driven to connect the chip 41 and the dicing tape 47. Between them.
  • the surface 40 a of the semiconductor wafer 40 is Since dicing is performed with the protective tape 42 adhered to the surface, the protective tape 42 remains on the surface of each divided chip 41 as it is.
  • the protective tape 42 serves to reinforce the chip 41, and acts to enhance the bending resistance of the chip 41. Thus, it is possible to prevent the chip 41 from breaking when the slider 52a is driven.
  • a chip mounting step of transferring the picked-up semiconductor chip 41 to, for example, a chip mounting portion of a lead frame 54 is performed (step S7).
  • the “chip mounting section” is not limited to the one related to the illustrated lead frame, but also includes a chip mounting section on a printed wiring board and a chip mounting section in a package container.
  • a conventionally known center 53 is used for mounting the chip 41 on the lead frame 54.
  • the mounter 53 sucks the surface of the chip 41 and transports it to the chip mounting portion on the lead frame 54, and mounts it via an adhesive or an adhesive sheet prepared in advance. At this time, since the chip 41 is reinforced by the protective tape 42, the chip 41 is prevented from cracking due to pressure during mounting.
  • step S8 a step of separating and removing the protective tape 42 from the surface of the mounted chip 41 is performed.
  • Fig. 2 is a side sectional view of the chip mounting part for explaining the chip mounting process. It is.
  • the chip 41 is joined to the lead frame 54 with an adhesive material 55.
  • the adhesive material 55 is made of an adhesive that is cured by a heating action from a heater 56 applied to the lower surface of the lead frame 54.
  • the protective tape 42 is made of a tape material having ultraviolet curability and heat shrinkability. Although the adhesive force has been reduced in the previous ultraviolet irradiation step, the protective tape 42 is in close contact with the surface of the chip 41. The effect remains.
  • the protective tape 42 is thermally contracted by using the heat of the heater 56 for curing the adhesive 55.
  • the protective tape 42 can be easily separated and removed from the surface of the chip 41.
  • chip breakage during pickup and chip breakage during mounting can be effectively prevented, and semiconductor chips manufactured as thin as 50 ⁇ m or less are properly handled.
  • a semiconductor device that can contribute to miniaturization and thinning of a device can be manufactured.
  • the chip mounting step and the protective tape separating step can be performed in the same step, thereby reducing the process cost and removing the protective tape 42.
  • the present invention can be implemented without using additional tools for Although the embodiments of the present invention have been described above, the present invention is, of course, not limited thereto, and various modifications can be made based on the technical idea of the present invention.
  • the protective tape 42 is made of an ultraviolet-curable
  • the protective tape can be made of a heat-foamable sheet material. In this case, the protective tape can be easily separated and removed from the chip surface only by the heating action on the protective tape.
  • the chip mounting step and the protective tape separation / removal step are performed in the same step. However, of course, these steps may be performed independently. Industrial applicability

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)
  • Die Bonding (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

A method for manufacturing a semiconductor device wherein an ultra-thin semiconductor chip having a thickness of 50 μm or less is properly picked up and mounted. A protective tape (42) for use in back grinding is adhered to a surface of a wafer (40), and back grinding, wafer mounting and dicing are conducted as it is. Accordingly, the protective tape (42) adhered to the surface of the chip improves the fracture-resistant property of the chip, thereby preventing the chip from cracking or breaking during the pick-up and chip-mounting steps. After the mounting, the protective tape (42) is removed from the surface of the chip.

Description

半導体装置の製造方法 Method for manufacturing semiconductor device
技 分野 Technical field
 Light
本発明は、 半導体装置の製造方法に関し、 更に詳しくは、 半導体ゥェ ーハの裏面研削によって薄厚化され田た半導体チップを損傷、 破損させる ことなく ピックアップしマウントできる半導体装置の製造方法に関する  The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of picking up and mounting a semiconductor chip thinned by back grinding of a semiconductor wafer without damaging or damaging the semiconductor chip.
背景技術 Background art
近年における電子機器の小型化 ·薄型化の要請から、 その構成部品で ある半導体チップの薄厚化は今後の製品開発に必須の条件となっている ( 半導体チップの薄厚化は、. 従来より、 素子を形成した半導体ゥエーハの 裏面研削 (バックグラインド) 工程によって実現されている。 The demand for smaller and thinner electronic devices in recent years, thinning of a required has become conditions (semiconductor chip product development of thinning the future that a component semiconductor chip. Conventionally, the element This is realized by the back grinding process of the semiconductor wafer where the pits are formed.
図 4 A〜図 4 Gは、 薄型の半導体チップの製作からマウントまでの各 種工程を説明する第 1 の従来例を示している。 本従来例は、 最も一般的 なプロセスであり、 主として、 薄厚化の目標値がゥヱーハ厚 1 5 0 μ m 以上の場合に適している。  FIGS. 4A to 4G show a first conventional example for explaining various steps from the production of a thin semiconductor chip to the mounting thereof. This conventional example is the most general process, and is suitable mainly when the target value for thinning is a wafer thickness of 150 μm or more.
素子を形成した半導体ゥユーハ 1 0の表面 (素子形成面) に粘着性の 保護テープ 8を貼り付け (図 4 A ) 、 その後、 研削装置 1を用いて半導 体ゥヱーハ 1 0の裏面を研削する (図 4 B ) 。 そして、 剥離テープ 2等 を用いて保護テープ 8を半導体ゥエーハ 1 0の表面から剥がした後 (図 4 C ) 、 粘着性のダイシングテープ 9を介して半導体ゥヱーハ 1 0をリ ングフレーム 3にマウントし (図 4 D ) 、 ダイシングソー 4によって半 導体ゥエーハ 1 0を個片化する (図 4 E ) 。 ダイシング工程後、 半導体 チップ 1 1はニー ドル 5に突き上げられると同時にコレツ ト 6で吸着さ れ (図 4 F) 、 マウンタ 1 2を用いて例えばリードフレーム 7上へマウ ントされる (図 4 G) 。 An adhesive protective tape 8 is attached to the surface (element formation surface) of the semiconductor wafer 10 on which the element is formed (FIG. 4A), and then the back surface of the semiconductor wafer 10 is ground using the grinding device 1. (Figure 4B). Then, after the protective tape 8 is peeled off from the surface of the semiconductor wafer 10 using the peeling tape 2 or the like (FIG. 4C), the semiconductor wafer 10 is mounted on the ring frame 3 via the adhesive dicing tape 9. (FIG. 4D), dicing saw 4 singulates semiconductor ゥ a wafer 10 (FIG. 4E). After dicing process, semiconductor The chip 11 is pushed up to the needle 5 and is sucked by the collet 6 at the same time (FIG. 4F), and is mounted on the lead frame 7 using the mounter 12 (FIG. 4G).
この方法では、 裏面研削工程からダイシングェ程までの間のハンドリ ング時において半導体ゥエーハ 1 0の割れや欠けが発生するおそれがあ るために、 ゥヱーハ厚 1 5 0 μ m以下の場合には適用することができな い。  This method is applied to wafers with a wafer thickness of 150 μm or less, since the semiconductor wafer 10 may crack or chip during handling during the back grinding process to the dicing process. I can't do it.
—方、 ゥヱーハ厚 1 5 0 μ m以下に薄厚化する場合には、 次の第 2お よび第 3の従来例に示すプロセスが有効とされている。  —On the other hand, when the wafer thickness is reduced to 150 μm or less, the processes shown in the following second and third conventional examples are effective.
第 2の従来例は、 図 5 A〜図 5 Gに示すように、 半導体ゥエーハ 2 0 表面のハーフ力ッ トダイシング工程 (図 5 A) 、 半導体ゥエーハ 2 0表 面への保護テープ 8の貼付工程 (図 5 B) 、 半導体ゥヱーハ 2 0裏面の 研削工程 (図 5 C) 、 ゥエーハマウント工程 (図 5 D) 、 保護テープ 8 の剥離工程(図 5 E)、半導体チップ 2 1のピックァップ工程(図 5 F)、 チップマウント工程 (図 5 G) からなつている。  In the second conventional example, as shown in FIGS. 5A to 5G, a half-power dicing process for the surface of the semiconductor wafer 20 (FIG. 5A), and the application of the protective tape 8 to the surface of the semiconductor wafer 20 Process (Fig. 5B), grinding process of semiconductor wafer 20 back surface (Fig. 5C), wafer mounting process (Fig. 5D), peeling process of protective tape 8 (Fig. 5E), pick-up process of semiconductor chip 21 (Fig. 5F) and the chip mounting process (Fig. 5G).
なお、 図において第 1の従来例と共通する部分については同一の符号 を付している。  Note that, in the figure, the same reference numerals are given to portions common to the first conventional example.
この方法は、 最初のハーフ力ッ トダイシング工程で目的とするゥヱー ハ厚に相当する深さに溝を形成し、 後に当該溝に至るまで裏面研削を施 すことによって、 半導体ゥヱーハ 2 0を個々の半導体チップ 2 1に分割 するようにしている。 したがって、 第 1の従来例に比べて、 上記ハン ド リング時における半導体ゥエーハ 2 0の割れ等を回避できるので、 1 5 0 μ m以下の薄厚化が可能である。  In this method, a semiconductor wafer 20 is individually formed by forming a groove at a depth corresponding to a target wafer thickness in an initial half-die dicing process, and thereafter performing back surface grinding to the groove. The semiconductor chip 21 is divided into two. Therefore, as compared with the first conventional example, cracking of the semiconductor wafer 20 at the time of the above-mentioned handling can be avoided, and the thickness can be reduced to 150 μm or less.
なお、 この第 2の従来例による半導体チップの薄厚化プロセスは、 例 えば特開 2 0 0 2— 1 6 0 2 1号公報に開示されている。  The semiconductor chip thinning process according to the second conventional example is disclosed, for example, in Japanese Patent Application Laid-Open No. 2002-16021.
次に、 第 3の従来例は、 図 6 Aおよぴ図 6 Gに示すように、 半導体ゥ ヱーハ 3 0表面への保護テープ 8の貼付工程 (阔 6 A) 、 半導体ゥヱー ハ 3 0の裏面研削工程 (図 6 B) 、 ゥエーハマウント工程 (図 6 C) 、 保護テープ 8の剥離工程 (図 6 D) 、 ダイシング工程 (図 6 E) 、 半導 体チップ 3 1のピックアップ工程 (図 6 F) 、 チップマウント工程 (図 6 G) からなつている。 Next, as shown in FIG. 6A and FIG. Affixing process of protective tape 8 to wafer 30 surface (阔 6A), grinding process of backside of semiconductor wafer 30 (Fig. 6B), wafer mounting process (Fig. 6C), peeling process of protective tape 8 (Fig. 6C) It consists of a dicing process (Fig. 6D), a semiconductor chip 31 pick-up process (Fig. 6F), and a chip mounting process (Fig. 6G).
なお、 図において第 1の従来例と共通する部分については同一の符号 を付している。  Note that, in the figure, the same reference numerals are given to portions common to the first conventional example.
この方法では、 半導体ゥヱーハ 3 0の表面に貼り付けた保護テープ 8 の剥離工程をゥエーハマゥント工程後ダイシング工程前に設けることに よって、 裏面研削工程からダイシングェ程までの搬送途上における半導 体ゥヱーハ 3 0の割れや欠けを保護テープ 8で防ぐようにしている。 こ れにより、 1 5 0 m以下のチップ厚を実現するようにしている。  In this method, by providing a step of peeling the protective tape 8 adhered to the surface of the semiconductor wafer 30 before the dicing step after the wafer mounting step, the semiconductor wafer 30 during the transportation from the back surface grinding step to the dicing step is provided. The protection tape 8 is used to prevent cracks and chips in the chip. As a result, a chip thickness of 150 m or less is realized.
なお、 この第 3の従来例による半導体チップの薄厚化プロセスは、 特 許第 2 8 7 7 9 9 7号公報に開示されている。  The semiconductor chip thinning process according to the third conventional example is disclosed in Japanese Patent No. 2879797.
また、 第 2, 第 3の従来例では、 半導体チップ 2 1, 3 1のピックァ ップ工程でいわゆるニー ドルレス方式で行うようにしている。 これは、 ダイシングテープ 9に紫外線硬化型のものを用い、 ダイシングテープ 9 に紫外線を照射して粘着力を低下させた状態で半導体チップ 2 1 , 3 1 のピックァップを行う方式であり、 第 1の従来例で用いられていたよう なニードル方式のピックアップ法に比べて、 半導体チップ 2 1 , 3 1の 割れや欠けを抑制できる。  In the second and third conventional examples, the so-called needleless method is used in the pick-up process of the semiconductor chips 21 and 31. This is a method in which an ultraviolet-curing dicing tape 9 is used to pick up the semiconductor chips 21 and 31 while irradiating the dicing tape 9 with ultraviolet light to reduce the adhesive force. The semiconductor chips 21 and 31 can be prevented from being cracked or chipped as compared with the needle type pickup method used in the conventional example.
上述のように、 第 2および第 3の従来例を採用することにより、 1 5 0 μ m以下に薄厚化した半導体チップのピックアップ工程およびマウン ト工程を適正に行うことができる。  As described above, by employing the second and third conventional examples, the pickup step and the mounting step of a semiconductor chip thinned to 150 μm or less can be properly performed.
しかしながら、 チップ厚が 5 0 μ m以下の超薄型になると、 半導体チ ップの抗折性が極端に低下するために、 ニー ドルレス方式のピックアツ プ方式によっても、 ピックアップ時に半導体チップが割れてしまう場合 があるという問題がある。 However, when the chip thickness becomes extremely thin, 50 μm or less, the die-resistant pick-up of the needleless method is required because the bending resistance of the semiconductor chip is extremely reduced. There is also a problem that the semiconductor chip may be broken at the time of pickup, depending on the method of picking up.
また、 仮にピックアップに成功したとしても、 マウント時に半導体チ ップが割れてしまう可能性が極めて高いという問題がある。  Also, even if the pickup is successful, there is a problem that the possibility that the semiconductor chip is broken during mounting is extremely high.
- 近年における半導体チップの薄型化あるいは薄厚化の要請は高く、 所 望とする厚さの半導体チップを製作することはできるものの、 当該製作 した半導体チップのハンドリングを適正に行うことができる技術が未だ 確立されていないのが現状である。 -In recent years, there has been a high demand for thinner or thinner semiconductor chips, and although semiconductor chips of the desired thickness can be manufactured, there is still no technology that can properly handle the manufactured semiconductor chips. It has not been established yet.
本発明は上述の問題に鑑みてなされ、 5 0 μ m以下の超薄型の半導体 チップを適正にピックアップしマウントすることができる半導体装置の 製造方法を提供することを課題とする。 発明の開示  The present invention has been made in view of the above problems, and has as its object to provide a method of manufacturing a semiconductor device capable of appropriately picking up and mounting an ultra-thin semiconductor chip of 50 μm or less. Disclosure of the invention
以上の課題を解決するに当たり、 本発明の半導体装置の製造方法は、 半導体ゥエーハの表面に、 裏面研削用の保護テープを貼り付ける保護テ ープ貼付工程と、 半導体ゥエーハの裏面を研削し薄厚化する裏面研削ェ 程と、 薄厚化した半導体ゥエーハの裏面にダイシング用粘着テープを貼 り付け、 保護テープとともに半導体ゥヱーハを個々のチップに分割する ダイシング工程と、 チップをピックアップしチップ搭載部へ移載するチ ップマウント工程と、 チップ表面から保護テープを分離する保護テープ 分離工程とを有している。  In order to solve the above problems, the method for manufacturing a semiconductor device according to the present invention includes a protective tape attaching step of attaching a protective tape for grinding a back surface to the surface of the semiconductor wafer, and a grinding process for grinding the back surface of the semiconductor wafer to reduce the thickness. Back surface grinding process, dicing adhesive tape is applied to the back surface of the thinned semiconductor wafer, the dicing process is used to divide the semiconductor wafer into individual chips together with the protective tape, and the chips are picked up and transferred to the chip mounting section. And a protective tape separating step of separating the protective tape from the chip surface.
本発明では、 ゥエーハ裏面研削後のダイシング、 ピックアップ、 チッ プマウントの各工程をチップ単独で行うのではなく、 保護テープが貼り 付けられた状態で行うようにしており、 これによりチップの抗折性を高 め、 5 0 μ ηι以下という超薄型の半導体チップを破損させることなく ピ ックアップでき、 マウントすることができる。 好適には、 保護テープは紫外線硬化型のテープ材が用いられ、 紫外線 照射によって粘着力を低下させて保護テープが分離される。 In the present invention, the dicing, pick-up, and chip mounting processes after grinding the back surface of the wafer are performed not with the chip alone, but with the protective tape attached, thereby reducing the bending resistance of the chip. Because of this, an ultra-thin semiconductor chip of 50 μηι or less can be picked up and mounted without damaging it. Preferably, a UV-curable tape material is used for the protective tape, and the protective tape is separated by irradiating UV rays to reduce the adhesive strength.
なお、 保護テープとして紫外線硬化性と熱収縮性とを兼ね備えたもの を用いれば、 保護テープの分離除去が容易となるだけでなく、 保護テー プの分離除去をチップマウント工程と同時に行うことも可能となる。 図面の簡単な説明  If a protective tape that has both UV curability and heat shrinkability is used, not only can the protective tape be separated and removed easily, but the protective tape can be separated and removed simultaneously with the chip mounting process. It becomes. BRIEF DESCRIPTION OF THE FIGURES
図 1 A〜図 1 Hは、 本発明の実施の形態による半導体装置の製造工程 を説明する斜視図である。 図 1 Aは保護テープ貼付工程を示し、 図 1 B は裏面研削工程を示し、 図 1 Cはゥエーハ裏面の後処理工程を示し、 図 1 Dはゥヱーハマゥント工程を示し、 図 1 Eはダイシング工程を示し、 図 1 Fは紫外線照射工程を示し、 図 1 Gはピックアップ工程を示し、 図 1 Hはチップマウント工程を示している。  1A to 1H are perspective views illustrating a process for manufacturing a semiconductor device according to an embodiment of the present invention. 1A shows a protective tape attaching process, FIG. 1B shows a back surface grinding process, FIG. 1C shows a post process of the wafer back surface, FIG. 1D shows a wafer mounting process, and FIG. 1E shows a dicing process. 1F shows an ultraviolet irradiation step, FIG. 1G shows a pickup step, and FIG. 1H shows a chip mounting step.
図 2は、 本発明の実施の形態による半導体装置の製造工程を説明する 斜視図であり、 保護テープ分離工程を示している。  FIG. 2 is a perspective view for explaining a manufacturing process of the semiconductor device according to the embodiment of the present invention, and shows a protective tape separating process.
図 3は、 本発明の実施の形態による半導体装置の製造工程を説明する フロー図である。  FIG. 3 is a flowchart illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention.
図 4 A〜図 4 Gは、 第 1の従来例による半導体装置の製造工程を説明 する斜視図である。 図 4 Aは保護テープ貼付工程を示し、 図 4 Bは裏面 研削工程を示し、 図 4 Cは保護テープ分離工程を示し、 図 4 Dはゥヱー ハマウント工程を示し、 図 4 Eはダイシング工程を示し、 図 4 Fはピッ クァップ工程を示し、 図 4 Gはチップマゥント工程を示している。  4A to 4G are perspective views illustrating the steps of manufacturing the semiconductor device according to the first conventional example. 4A shows the protective tape attaching process, FIG. 4B shows the back surface grinding process, FIG. 4C shows the protective tape separating process, FIG. 4D shows the wafer mounting process, and FIG. 4E shows the dicing process. 4F shows a pick-up process, and FIG. 4G shows a chip mounting process.
図 5 A〜図 5 Gは、 第 2の従来例による半導体装置の製造工程を説明 する斜視図である。 図 5 Aはハーフカッ トダイシング工程を示し、 図 5 Bは保護テープ貼付工程を示し、 図 5 Cは裏面研削工程を示し、 図 5 D はゥエーハマゥント工程を示し、 図 5 Eは保護テープ分離工程を示し、 図 5 Fはピックアップ工程を示し、 図 5 Gはチップマウント工程を示し ている。 5A to 5G are perspective views illustrating the steps of manufacturing a semiconductor device according to the second conventional example. FIG. 5A shows a half-cut dicing process, FIG. 5B shows a protective tape attaching process, FIG. 5C shows a back surface grinding process, FIG. 5D shows a wafer mounting process, and FIG. 5E shows a protective tape separating process. Show, FIG. 5F shows a pickup process, and FIG. 5G shows a chip mounting process.
図 6 A〜図 6 Gは、 第 3の従来例による半導体装置の製造工程を説明 する斜視図である。 図 6 Aは保護テープ貼付工程を示し、 図 6 Bは裏面 研削工程を示し、 図 6 Cはゥエーハマウント工程を示し、 図 6 Dは保護 テープ分離工程を示し、 図 6 Eはダイシング工程を示し、 図 6 Fはピッ クァップ工程を示し、 図 6 Gはチップマゥント工程を示している。 発明を実施するための最良の形態 .  6A to 6G are perspective views illustrating the steps of manufacturing a semiconductor device according to a third conventional example. FIG. 6A shows a protective tape attaching process, FIG. 6B shows a back surface grinding process, FIG. 6C shows a wafer mounting process, FIG. 6D shows a protective tape separating process, and FIG. 6E shows a dicing process. FIG. 6F shows a pick-up process, and FIG. 6G shows a chip mounting process. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の実施の形態について図面を参照して説明する。  Hereinafter, embodiments of the present invention will be described with reference to the drawings.
図 1 A〜図 3は、 本発明の実施の形態を示している。  1A to 3 show an embodiment of the present invention.
ここで、 図 1 A〜図 1 Hは本実施の形態の各工程を模式的に説明する 斜視図、 図 2はチップマウント工程の説明図、 図 3は本実施の形態のプ ロセスフロー図である。  Here, FIGS. 1A to 1H are perspective views schematically illustrating each step of the present embodiment, FIG. 2 is an explanatory view of a chip mounting step, and FIG. 3 is a process flow diagram of the present embodiment. .
図 1 Aは、 半導体ゥヱーハ 4 0の表面 4 0 aに、 裏面研削用の保護テ ープ 4 2を貼り付ける保護テープ貼付工程を示している(ステップ S 1 ) , ゥエーハ表面 4 0 aに対する保護テープ 4 2の貼付けは、 従来一般的 なラミネ一ト装置 4 3が適用される。  FIG. 1A shows a protective tape attaching process in which a protective tape 42 for backside grinding is attached to the front surface 40 a of the semiconductor wafer 40 (step S 1), and the protection for the wafer surface 40 a is performed. Conventionally, a common laminating device 43 is applied for attaching the tape 42.
保護テープ 4 2の厚さは適宜選定可能であり、 ゥエーハ表面 4 0 aの 平面状態によって選択される。 すなわち、 ゥエーハ表面 4 0 aの各素子 にバンプ等の金属突起物が形成されている場合には、 当該金属突起物を 吸収できる程度の厚さが必要となる。  The thickness of the protective tape 42 can be appropriately selected, and is selected according to the planar state of the wafer surface 40a. That is, when a metal projection such as a bump is formed on each element of the wafer surface 40a, a thickness that can absorb the metal projection is required.
本実施の形態では、 保護テープ 4 2の厚さは約 2 0 0 μ mである。  In the present embodiment, the thickness of the protective tape 42 is about 200 μm.
保護テープ 4 2は紫外線硬化性および熱収縮性の粘着テープで構成さ れる。 特に本実施の形態では、 保護テープ 4 2としてリンテック株式会 社製のダイシングテープ (Nシリーズ) が用いられている。 次に、 図 I Bに示すように、 裏面研削装置 4 4を用いた半導体ゥエー ハ 4 0の裏面 4 0 b の研削工程が行われる (ステップ S 2 ) 。 The protective tape 42 is made of a UV-curable and heat-shrinkable adhesive tape. In particular, in the present embodiment, a dicing tape (N series) manufactured by Lintec Corporation is used as the protective tape 42. Next, as shown in FIG. IB, a grinding process of the back surface 40b of the semiconductor wafer 40 using the back surface grinding device 44 is performed (Step S2).
研削量は、 目的とするゥエーハ厚に応じて決定される。 本実施の形態 では、 この裏面研削工程によって 2 0 μ m程度のゥヱーハ厚に薄厚化す る。  The amount of grinding is determined according to the target wafer thickness. In the present embodiment, the wafer thickness is reduced to about 20 μm by the back surface grinding step.
図 1 Cは、裏面研削後の後処理工程を示している。この後処理工程は、 裏面研削工程後のゥヱーハ裏面 4 0 bの残留応力の除去を目的として行 われるもので、 研磨装置 4 5による機械研磨や、 ウエッ トエッチングが 必要に応じて実施される。 後者の場合、 保護テープ 4 2はゥヱーハ表面 4 0 aを覆うマスクとして機能させることができる。  FIG. 1C shows a post-processing step after backside grinding. This post-processing step is performed for the purpose of removing residual stress on the wafer back surface 40b after the back surface grinding step, and mechanical polishing by a polishing device 45 or wet etching is performed as necessary. In the latter case, the protective tape 42 can function as a mask covering the wafer surface 40a.
次に、 図 1 Dに示すように、 薄厚化した半導体ゥエーハ 4 0をダイシ ング用の粘着テープ (ダイシングテープ) 4 7を介してリングフレーム 4 8にマウントする工程が行われる (ステップ S 3 ) 。  Next, as shown in FIG. 1D, a step of mounting the thinned semiconductor wafer 40 on a ring frame 48 via a dicing adhesive tape (dicing tape) 47 is performed (step S 3). .
ダイシングテープ 4 7は、 後にチップのピックアップが容易な紫外線 硬化性のものが用いられる。  As the dicing tape 47, an ultraviolet-curing tape that facilitates chip pickup later is used.
本実施の形態によれば、 半導体ゥエーハ 4 0はその表面 4 0 aに保護 テープ 4 2が貼り付けられて抗折性が高められているので、 ハンドリ ン グ中における半導体ゥエーハ 4 2の割れ等が防止される。  According to the present embodiment, since the semiconductor wafer 40 has a protective tape 42 attached to the surface 40a of the semiconductor wafer 40 to enhance the bending resistance, the semiconductor wafer 40 may be broken during handling. Is prevented.
図 1 Eはダイシング工程を示している (ステップ S 4 ) 。  FIG. 1E shows the dicing process (step S 4).
このダイシング工程では、 半導体ゥエーハ 4 0は、 その表面 4 0 aに 貼り付けられた保護テープ 4 2とともに個々のチップに分割される。 保護テープ 4 2付き半導体ゥエーハ 4 0のダイシングは、 一般的なシ ングルカッ トではブレード 4 9の目詰まりが発生し、 ダイシングの品質 が悪くなる場合がある。 この場合は、 最初に保護テープ 4 2のみをダイ シングした後、 ブレード 4 9を交換して半導体ゥヱーハ 4 0をダイシン グするステップカッ ト法を適用することができる。 次に、 図 I Fに示すように、 ダイシングした半導体ゥエーハ 4 0の表 面 4 0 aに貼り付けられている保護テープ 4 2 と、 半導体ゥヱーハ 4 0 の裏面 4 0 bに貼り付けられているダイシングテープ 4 7に対し、 それ ぞれ紫外線照射装置 5 0 A, 5 0 Bを用いて紫外線を照射する工程が行 われる (ステップ S 5 ) 。 In this dicing step, the semiconductor wafer 40 is divided into individual chips together with the protective tape 42 attached to the surface 40a. In the dicing of the semiconductor wafer 40 with the protective tape 42, the blade 49 may be clogged in a general single cut, and the dicing quality may be degraded. In this case, a step-cut method of dicing the semiconductor wafer 40 by exchanging the blades 49 after dicing only the protection tape 42 first can be applied. Next, as shown in FIG. IF, the protective tape 42 attached to the front surface 40a of the diced semiconductor wafer 40 and the dicing tape attached to the back surface 40b of the semiconductor wafer 40 A step of irradiating the tape 47 with ultraviolet light using the ultraviolet light irradiation devices 50A and 50B, respectively, is performed (step S5).
保護テープ 4 2およぴダイシングテープ 4 7はそれぞれ紫外線硬化性 のテープ材で構成されているので、 紫外線の照射により硬化し、 半導体 ゥエーハ 4 0に対する粘着力がそれぞれ低下する。  Since each of the protective tape 42 and the dicing tape 47 is made of a UV-curable tape material, the protective tape 42 and the dicing tape 47 are cured by irradiation with ultraviolet light, and the adhesive strength to the semiconductor wafer 40 is reduced.
本実施の形態では、 保護テープ 4 2に対する紫外線照射工程と、 ダイ シングテープ 4 7に対する紫外線照射工程と同時に行うようにして、 プ ロセスコス トの低減を図っている。  In the present embodiment, the process of irradiating the protective tape 42 with ultraviolet light and the process of irradiating the dicing tape 47 with ultraviolet light are performed at the same time to reduce the process cost.
なお、 保護テープ 4 2およびダイシングテープ 4 7のそれぞれに対す る紫外線照射工程は、 同時に行う場合に限られない。  Note that the ultraviolet irradiation step for each of the protective tape 42 and the dicing tape 47 is not limited to the case where the steps are performed simultaneously.
続いて、 図 1 Gに示すようにチップ 4 1 のピックアップ工程が行われ る (ステップ S 6 ) 。  Subsequently, as shown in FIG. 1G, a chip 41 pickup process is performed (step S6).
本実施の形態では、 ピックアップ時におけるチップ 4 1 とダイシング テープ 4 7との間の分離に従来のニー ドルレス方式を採用している。 先の紫外線照射工程において硬化されたダイシングテープ 4 7は、 チ ップ 4 1の裏面との間の粘着力は低下しているものの面同士の密着作用 によって依然、 両者の一体関係は持続されている。 そこで、 ダイシング テープ 4 7の直下方に分離装置 5 2を配置し、 ピックァップすべきチッ プの下面に沿って水平移動可能なスライダ 5 2 aを駆動して、 チップ 4 1 とダイシングテープ 4 7との間の分離を図るようにしている。  In the present embodiment, a conventional needleless method is used for separation between the chip 41 and the dicing tape 47 during pickup. In the dicing tape 47 cured in the previous ultraviolet irradiation step, although the adhesive strength between the back surface of the chip 41 and the back surface is reduced, the integrated relationship between the two surfaces is still maintained due to the adhesive action between the surfaces. I have. Therefore, the separating device 52 is disposed directly below the dicing tape 47, and the slider 52a, which can move horizontally along the lower surface of the chip to be picked up, is driven to connect the chip 41 and the dicing tape 47. Between them.
ところが、 チップ厚が 5 0 μ m以下という超薄型のチップ単独では、 スライダ 5 2 a の駆動時にチップが割れたり欠ける場合が多かった。 そこで、 本実施の形態においては、 半導体ゥヱーハ 4 0の表面 4 0 a に保護テープ 4 2を貼り付けた状態でダイシングしているので、 分割さ れた個々のチップ 4 1の表面には保護テープ 4 2がそのまま残存してい る。 However, in the case of an ultra-thin chip alone having a chip thickness of 50 μm or less, the chip often cracked or chipped when the slider 52a was driven. Therefore, in the present embodiment, the surface 40 a of the semiconductor wafer 40 is Since dicing is performed with the protective tape 42 adhered to the surface, the protective tape 42 remains on the surface of each divided chip 41 as it is.
したがって、 この保護テープ 4 2がチップ 4 1を補強する役目を果た し、 チップ 4 1の抗折性を高める作用を行うことになる。 これにより、 スライダ 5 2 aの駆動時におけるチップ 4 1の割れを防止することがで きる。  Therefore, the protective tape 42 serves to reinforce the chip 41, and acts to enhance the bending resistance of the chip 41. Thus, it is possible to prevent the chip 41 from breaking when the slider 52a is driven.
また、 本実施の形態によれば、 チップ 4 1の表面に保護テープ 4 2が 貼り付けられているので、 コレツ ト 5 1 の吸着作用によるチップ 4 1 の 割れを防止することができるだけでなく、 コレッ ト 5 1 との直接接触に よるチップ 4 1表面の汚染やキズの発生をも回避することができる。 続いて、 図 1 Hに示すように、 ピックアップした半導体チップ 4 1を 例えばリードフレーム 5 4のチップ搭载部へ移載するチップマウントェ 程が行われる (ステップ S 7 ) 。  Also, according to the present embodiment, since the protective tape 42 is attached to the surface of the chip 41, not only can the chip 41 be prevented from cracking due to the suction action of the collet 51, The contamination and scratches on the surface of the chip 41 due to the direct contact with the collet 51 can be avoided. Subsequently, as shown in FIG. 1H, a chip mounting step of transferring the picked-up semiconductor chip 41 to, for example, a chip mounting portion of a lead frame 54 is performed (step S7).
なお、 「チップ搭載部」 は、 図示するリードフレームに関するものだ けに限らず、 プリ ン ト配線基板上のチップ搭载部や、 パッケージ容器内 のチップ搭載部等も該当する。  The “chip mounting section” is not limited to the one related to the illustrated lead frame, but also includes a chip mounting section on a printed wiring board and a chip mounting section in a package container.
リードフレーム 5 4に対するチップ 4 1のマウントは、 従来公知のマ ゥンタ 5 3が用いられる。 マウンタ 5 3は、 チップ 4 1表面を吸着して リードフレーム 5 4上のチップ搭載部へ搬送し、 予め用意された接着剤 あるいは接着シートを介してマウン トする。 このときチップ 4 1は保護 テープ 4 2により補強されているので、 マウント時の圧力によるチップ 4 1の割れが防止される。  For mounting the chip 41 on the lead frame 54, a conventionally known center 53 is used. The mounter 53 sucks the surface of the chip 41 and transports it to the chip mounting portion on the lead frame 54, and mounts it via an adhesive or an adhesive sheet prepared in advance. At this time, since the chip 41 is reinforced by the protective tape 42, the chip 41 is prevented from cracking due to pressure during mounting.
次に、 マウントしたチップ 4 1表面から、 保護テープ 4 2を分離除去 する工程が行われる (ステップ S 8 ) 。  Next, a step of separating and removing the protective tape 42 from the surface of the mounted chip 41 is performed (step S8).
図 2はチップマウン ト工程を説明するためのチップ搭載部の側断面図 である。 チップ 4 1は、 リードフレーム 5 4に対して接着材料 5 5によ つて接合される。 接着材料 5 5は、 リードフレーム 5 4の下面に当てら れたヒータ 5 6からの加熱作用によって硬化するタイプの接着剤で構成 される。 Fig. 2 is a side sectional view of the chip mounting part for explaining the chip mounting process. It is. The chip 41 is joined to the lead frame 54 with an adhesive material 55. The adhesive material 55 is made of an adhesive that is cured by a heating action from a heater 56 applied to the lower surface of the lead frame 54.
上述のように、 保護テープ 4 2は紫外線硬化性および熱収縮性を備え るテープ材で構成され、 先の紫外線照射工程において粘着力は低下して いるものの、 チップ 4 1表面との間の密着作用は依然として残存してい る。  As described above, the protective tape 42 is made of a tape material having ultraviolet curability and heat shrinkability. Although the adhesive force has been reduced in the previous ultraviolet irradiation step, the protective tape 42 is in close contact with the surface of the chip 41. The effect remains.
そこで、 本実施の形態では、 チップマウントの際、 接着剤 5 5を硬化 させるためのヒータ 5 6の熱を利用して保護テープ 4 2を熱収縮させる ようにしている。  Therefore, in the present embodiment, at the time of chip mounting, the protective tape 42 is thermally contracted by using the heat of the heater 56 for curing the adhesive 55.
これにより、 保護テープ 4 2をチップ 4 1表面から容易に分離除去す ることができる。  Thus, the protective tape 42 can be easily separated and removed from the surface of the chip 41.
したがって、 本実施の形態によれば、 ピックアップ時におけるチップ 割れ、 マウント時のチップ割れを効果的に防止することができるので、 5 0 μ m以下という超薄型に製作した半導体チップを適正に取り扱うこ とができ、 機器の小型化 ·薄型化に貢献し得る半導体装置を製造するこ とができる。  Therefore, according to the present embodiment, chip breakage during pickup and chip breakage during mounting can be effectively prevented, and semiconductor chips manufactured as thin as 50 μm or less are properly handled. Thus, a semiconductor device that can contribute to miniaturization and thinning of a device can be manufactured.
特に、 本実施の形態によれば、 チップマウント工程と保護テープ分離 工程とを同一の工程で行うことができるので、 これによりプロセスコス トの低減を図ることができるとともに、 保護テープ 4 2の除去のための 付加的なツールを用いることなく本発明を実施することができる。 以上、 本発明の実施の形態について説明したが、 勿論、 本発明はこれ に限定されることなく、 本発明の技術的思想に基づいて種々の変形が可 能である。  In particular, according to the present embodiment, the chip mounting step and the protective tape separating step can be performed in the same step, thereby reducing the process cost and removing the protective tape 42. The present invention can be implemented without using additional tools for Although the embodiments of the present invention have been described above, the present invention is, of course, not limited thereto, and various modifications can be made based on the technical idea of the present invention.
例えば以上の実施の形態では、 保護テープ 4 2として紫外線硬化性お よび熱収縮性のあるテープ材を用いた力 S、チップ表面の性状によっては、 当該保護テープを熱発泡性のシート材で構成することも可能である。 こ の場合、 保護テープに対する加熱作用のみでチップ表面から当該保護テ ープを容易に分離除去することができる。 For example, in the above embodiment, the protective tape 42 is made of an ultraviolet-curable Depending on the strength S of the heat-shrinkable tape material and the properties of the chip surface, the protective tape can be made of a heat-foamable sheet material. In this case, the protective tape can be easily separated and removed from the chip surface only by the heating action on the protective tape.
また、 以上の実施の形態では、 チップマウント工程と保護テープ分離 除去工程とを同一工程で行うようにしたが、 勿論、 これらの工程を独立 して行うようにしてもよレ、。 産業上の利用可能性  Further, in the above embodiment, the chip mounting step and the protective tape separation / removal step are performed in the same step. However, of course, these steps may be performed independently. Industrial applicability
以上述べたように、 本発明の半導体装置の製造方法によれば、 チップ の割れや欠けを効果的に防止してチップのピックァップ工程およびマウ ント工程を適正に行うことができ、 電子機器の小型化 ·薄型化に貢献し 得る半導体装置を製造することができる。  As described above, according to the method for manufacturing a semiconductor device of the present invention, chip cracking and chipping can be effectively prevented, and the chip pick-up step and the mounting step can be appropriately performed.・ Semiconductor devices that can contribute to thinning can be manufactured.

Claims

請 求 の 範 囲 The scope of the claims
1 . 半導体ゥエーハの表面に、裏面研削用の保護テープを貼り付ける保 護テープ貼付工程と、 1. A protective tape attaching process for attaching a protective tape for backside grinding to the surface of the semiconductor wafer,
前記半導体ゥエーハの裏面を研削し薄厚化する裏面研削工程と、 前記薄厚化した半導体ゥエーハの裏面にダイシング用粘着テープを貼 り付け、 前記保護テープとともに前記半導体ゥヱーハを個々のチップに 分割するダイシング工程と、  A backside grinding step of grinding the backside of the semiconductor wafer to make it thinner; a dicing step of attaching a dicing adhesive tape to the backside of the thinned semiconductor wafer and dividing the semiconductor wafer into individual chips together with the protective tape. When,
前記チップをピックアップしチップ搭載部へ移載するチップマウント 工程と、  A chip mounting step of picking up the chip and transferring it to a chip mounting portion;
前記チップ表面から前記保護テープを分離する保護テープ分離工程と を有する  A protective tape separating step of separating the protective tape from the chip surface.
ことを特徴とする半導体装置の製造方法。  A method for manufacturing a semiconductor device, comprising:
2 . 前記チップマウント工程と前記保護テープ分離工程とを同一工程 で行う  2. Perform the chip mounting step and the protective tape separating step in the same step
ことを特徴とする請求項 1に記載の半導体装置の製造方法。  2. The method for manufacturing a semiconductor device according to claim 1, wherein:
3 . 前記保護テープおよび前記粘着テープとして紫外線硬化型のテー プ材を用い、  3. UV-curable tape material is used for the protective tape and the adhesive tape,
前記ダイシング工程後、 前記チップマウント工程の前に、 前記保護テ ープおよび前記粘着テープに対して紫外線を照射する工程を有する  Irradiating ultraviolet rays to the protective tape and the adhesive tape after the dicing step and before the chip mounting step;
ことを特徴とする請求項 1に記載の半導体装置の製造方法。  2. The method for manufacturing a semiconductor device according to claim 1, wherein:
4 . 前記チップのピックアップ工程における前記粘着テープからの前 記チップの分離を、 ニー ドルレス方式で行う  4. Separation of the chip from the adhesive tape in the chip pickup step is performed by a needleless method.
ことを特徴とする請求項 3に記載の半導体装置の製造方法。  4. The method for manufacturing a semiconductor device according to claim 3, wherein:
5 . 前記保護テープとして熱収縮性のあるテープ材を用い、  5. Using a heat-shrinkable tape material as the protective tape,
前記保護テープ分離工程における前記チップ表面からの前記保護テー プの分離を、 前記保護テープの熱収縮を利用して行う ことを特徴とする請求項 1に記載の半導体装置の製造方法。 The protection tape from the chip surface in the protection tape separating step; 2. The method for manufacturing a semiconductor device according to claim 1, wherein the separation of the tape is performed by utilizing heat shrinkage of the protective tape.
PCT/JP2003/008906 2002-07-29 2003-07-14 Method for manufacturing semiconductor device WO2004012247A1 (en)

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