JP2005234744A - Multiprocessor system and failure processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-processor system and a failure processing method for limiting the influence of failure only to a processor related to a main storage region associated with the failure. <P>SOLUTION: This system is provided with a plurality of microprocessors 20 to 2n and a main storage device 10 connected through a bus 31 to the plurality of microprocessors 20 to 2n so as to be shared by the microprocessors 20 to 2n. The main storage device 10 is provided with a register representing which processor is using each region obtained by dividing the storage space of the main storage device 10 into a plurality regions and a notification part which specifies the processor by referring to the register part when any failure is generated in any of those regions, and notifies the processor of the generation of the failure. In this case, the main storage device 10 notifies the processor of the generation of the failure through an interrupting signal line 30. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a multiprocessor system and a failure processing method, and more particularly to a failure processing method in a main storage device and a multiprocessor system that executes this processing method.

  With the recent development of multiprocessor technology, information processing apparatuses that perform system operations by connecting tens to hundreds of processors to a main storage device have appeared. In such an information processing apparatus, a memory management method for managing a memory shared by a plurality of processors is known. For example, Patent Document 1 discloses a memory management method that secures and releases ownership of a memory area at high speed. In this memory management method, a flag corresponding to each processor is provided for each area on a shared memory shared by a plurality of processors. The flag indicates that the corresponding processor is using the corresponding area on the shared memory, is not used, or is in the middle of transferring ownership to another processor. Displays whether there is. Each processor detects whether the memory area is in use or being transferred by using a flag when the memory area is secured. The memory area is operated only when it is not in use or being transferred.

  On the other hand, there is known a multiprocessor in which when a failure occurs in the main storage device, the occurrence of the failure is notified to the requesting processor that executed the memory access, and the processor executes the failure process. For example, Patent Document 2 discloses a multiprocessor system in which occurrence of a failure is notified to a requesting processor that has executed memory access, and the processor executes failure processing. In this system, when a failure occurs in the main storage device when the main storage device is accessed from an arbitrary processor, the failure detection means detects whether or not the failure has occurred, and at the same time, the processor identification means of the main storage control unit Identifies the processor of the access source, and notifies the occurrence of the failure by the failure occurrence notifying means to the processor that has caused the failure. In this way, the failure occurrence is notified to the failed processor so that the processor side software can take necessary measures such as disconnection from the main storage device. Even if a failure occurs in the main memory control unit, the remaining processors can access the main memory so that the entire system does not go down due to a transient failure caused by a specific processor. Thus, fault tolerance is improved.

JP-A-4-364550 (FIG. 1) JP-A-5-81059 (FIG. 2)

  In a multiprocessor system, a memory (main storage device) is generally shared by a plurality of processors. However, when a failure occurs in the memory, there is a possibility that the plurality of processors are affected, and the influence of the failure is large. By the way, the purpose of the memory management method of Patent Document 1 is exclusive control for securing a divided memory area, and a plurality of processors are not configured to share a specific divided memory area. In addition, usage state information corresponding to each processor is managed on the shared memory, and a failure of the shared memory itself cannot be dealt with. Furthermore, although there is a description that reliability can be improved in the event of a failure, no specific configuration or operation for failure processing is disclosed.

  On the other hand, in the system disclosed in Patent Document 2, when an uncorrectable failure occurs in the main storage device, the occurrence of the failure is notified only to the requesting processor that has executed the memory access. The system determines whether or not the system operation can be continued by executing failure processing. However, when the storage area of the main storage device is shared by multiple processors, if a failure occurs in the main storage shared by each processor, the failure processing is performed by the first processor that is notified of the occurrence of the failure. There is a possibility that another processor may perform memory access to the same area before the operation is performed. In this case, other processors execute access processing to the main storage device without knowing the failure, and the influence of the failure spreads.

  To prevent this, if an uncorrectable failure occurs in the main storage device, the uncorrectable failure is considered to have occurred at the heart of the system, and all the processors that make up the multiprocessor are considered. A method of notifying the occurrence of a failure and quickly stopping the system can be considered. However, even if the program running on the processor does not use the main memory area related to the failure at all, the processing is interrupted by the interrupt, so the influence of the failure will spread to the entire system, and the fault tolerance Is insufficient.

  An object of the present invention is to provide a multiprocessor system and a failure processing method that limit the influence of a failure to only the processors involved in the main storage area involved in the failure.

  In order to achieve the above object, according to a first aspect, a multiprocessor system according to the present invention includes a plurality of processors, and a main storage device connected to the plurality of processors via a bus and shared by the processors. System. The main storage device divides the storage space in the main storage device into multiple areas, and refers to the register section that indicates which processor is using each area, and the register section when one of the areas fails And a notification unit that identifies the processor and notifies the processor.

  In the present invention, preferably, the notification unit may include an interrupt control circuit and notify the specified processor by an interrupt.

  In the present invention, preferably, the register unit may represent which processor is used by which program each area uses.

  Furthermore, in the present invention, preferably, the register unit may be configured to indicate a plurality of areas for each processor.

  In the present invention, preferably, the register unit may be configured to indicate which processor of the plurality of processors uses which of the plurality of areas by a flag.

  Further, in the present invention, preferably, the flag may be rewritten by a program operating on the processor when the processor uses or releases the area corresponding to the flag.

  According to a second aspect of the present invention, there is provided a failure processing method for a multiprocessor system including a plurality of processors and a main storage device connected to the plurality of processors via a bus and shared by the processors. Applied. In this method, the storage space in the main storage device is divided into a plurality of areas, and a flag indicates which processor is using each area. Further, when a failure occurs in any of the areas, the processor is identified with reference to the flag and an interrupt is notified.

  According to the present invention, when a failure occurs in the main storage device, only the processor using the failed area in the storage space of the main storage device is selectively notified that the failure has occurred. To work. Therefore, it is possible to limit the propagation range of the failure only to the microprocessor (program) using the storage space where the failure has occurred, and to minimize the processors affected by the failure occurrence.

  FIG. 1 is a block diagram showing a configuration of a multiprocessor system according to an embodiment of the present invention. 1, the multiprocessor system includes microprocessors 20, 21, 22,... 2 n and a main storage device 10, and the microprocessors 20, 21, 22,. Connected through. Further, from the main memory device 10, interrupt signal lines 30 are individually connected to the microprocessors 20 to 2n.

  In the multiprocessor system as described above, the plurality of microprocessors 20 to 2n access the main storage device 10 via the system bus 31. The interrupt signal line 30 is used for the purpose of notifying the microprocessors 20 to 2n that a failure has occurred when a failure occurs in the storage space of the main storage device 10.

  In addition, the main storage device 10 includes a register unit that divides the storage space in the main storage device 10 into a plurality of areas and indicates which microprocessor program is using each area, and one of the areas is faulty. A notification unit that identifies the microprocessor and refers to it via the interrupt signal line 30 when the error occurs.

  In the multiprocessor system configured as described above, the storage space in the main storage device 10 is divided into a plurality of areas, and which microprocessor is used by each microprocessor is indicated by a flag in the register unit. When a failure occurs, the microprocessor is identified with reference to the flag and an interrupt is notified.

  Next, the configuration of the multiprocessor system, in particular, the configuration of the main storage device 10 will be described more specifically. FIG. 2 is a block diagram showing the configuration of the multiprocessor system according to the embodiment of the present invention. In FIG. 2, the description of the microprocessors 21 to 2n is omitted in order to explain the case of notifying the microprocessor 20 of a failure in the main storage device 10 as an example.

  In FIG. 2, the main storage device 10 includes a main storage unit 11, a storage control circuit 12, an interrupt control circuit 14, and an address register 15. The main storage unit 11 is managed and operated by dividing the main storage space into a plurality of areas A to H, and a failure can be individually detected for these areas. The storage control circuit 12 includes a control register group 13 for storing which storage area the microprocessors 20 to 2n are using, corresponding to the storage areas A to H, respectively. The interrupt control circuit 14 notifies each microprocessor of the occurrence of a failure via the interrupt signal line 30 based on the contents recorded in the control register group 13 in accordance with an instruction from the storage control circuit 12. For example, the occurrence of a failure is notified to the microprocessor 20 via the interrupt signal line 30 based on the contents of the control register 130 in the control register group 13.

  On the other hand, when the microprocessor 20 accesses the main storage unit 11, the microprocessor 20 accesses the main storage device 10 via the system bus 31. Address information for accessing the main storage unit 11 is decoded by the address register 15 and a predetermined area of the main storage unit 11 is allocated. For example, in FIG. 2, the areas A, B, and E are accessed by the microprocessor 20, and the bit content of the control register 130 corresponding to each area is set to a value “1” indicating that it is in use.

  FIG. 3 shows a setting example of the control register group 13 of the storage control circuit 12, and the control register group 13 is provided with control registers 130 to 13n corresponding to the microprocessors 20 to 2n belonging to the system, respectively. Yes. The control registers 130 to 13n indicate which area of the main storage space is used by the corresponding processor. In the example shown in FIG. 3, the processor # 0 uses the storage areas A, B, and E. Similarly, the processor # 1 uses the storage areas A and G, and the processor # 2 has the storage area. The areas #A, B, E, and F are used, and the processor #n uses the area B of the storage area. Each bit of the control registers 130 to 13n is a flag indicating a use state in a storage area corresponding to each of the areas A to H of the divided main storage space of the main storage unit 11 ("1" for use, "1" for nonuse). 0 ").

  In FIG. 2, a program (operating system) running on the microprocessor 20 forms a group by a predetermined microprocessor and a predetermined storage area of the main storage unit 11, and forms an independent system. Yes. At this time, for the storage area of the main storage unit 11 used by the program itself, a value indicating that the storage area is currently being used for the bit corresponding to the storage area of the control registers 130 to 13n provided for each microprocessor. Write “1” in advance. Also, when the storage area is not used or when it is no longer used (released), the value “0” is written.

  When a failure occurs in the main storage unit 11, the storage control circuit 12 identifies a storage area where the failure has occurred, and refers to the bits of the control registers 130 to 13n corresponding to this storage area. At this time, if the bits of the control registers 130 to 13n are set in a state indicating that the corresponding storage area is being used, that is, if the value is “1”, the interrupt control circuit 14 is instructed to correspond to the corresponding micro area. The occurrence of a failure is notified to the processor, for example, the microprocessor 20 via the interrupt signal line 30.

  If a failure occurs in the region G, the storage control circuit 12 refers to the control registers 130 to 13n and identifies the microprocessor that uses the region G. In the example of FIG. 3, processor # 1 (microprocessor 21) satisfies this condition based on the contents of the control register 131. The storage control circuit 12 notifies the interrupt control circuit 14 that a failure has occurred only to the processor # 1 according to the information in the control register 131.

  If a failure occurs in the area E, the storage control circuit 12 refers to the control registers 130 to 13n and identifies the microprocessor that uses the area E. In the example of FIG. 3, processors # 0 and # 2 (microprocessors 20 and 22) satisfy this condition based on the contents of the control registers 130 and 132. The storage control circuit 12 notifies the interrupt control circuit 14 that a failure has occurred to the processors # 0 and # 2 according to the information in the control registers 130 and 132.

  The microprocessor notified by an interruption that a failure has occurred in the storage area in use in the main storage unit 11 executes predetermined failure processing.

  As described above, when the multiprocessor system operates and a failure occurs in the main storage device 10, the failure has occurred only in the processor using the failed area in the storage space of the main storage device 10. Is selectively notified. Therefore, the spillover range of the failure is limited only to the microprocessor using the storage space where the failure has occurred.

It is a block diagram showing the structure of the multiprocessor system which concerns on embodiment of this invention. It is a block diagram showing the structure of the main memory which concerns on the Example of this invention. It is a figure which shows the example of a setting of the control register group which concerns on the Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Main memory device 11 Main memory part 12 Storage control circuit 13 Control register group 130-13n Control register 14 Interrupt control circuit 15 Address register 20-2n Microprocessor 30 Interrupt signal line 31 System bus

Claims (9)

In a multiprocessor system including a plurality of processors and a main storage device connected to the plurality of processors via a bus and shared by the processors,
The main storage device
A register unit that indicates which processor uses the storage space in the main storage device and each area is used by each of the areas;
A notification unit that identifies the processor by referring to the register unit when a failure occurs in any of the areas and notifies the processor of the failure;
A multiprocessor system comprising:   The multiprocessor system according to claim 1, wherein the notification unit includes an interrupt control circuit and notifies the specified processor by an interrupt.   The multiprocessor system according to claim 1, wherein the register unit represents which processor uses each of the areas.   The multiprocessor system according to claim 1, wherein the register unit is configured to instruct the plurality of areas for each processor.   2. The multiprocessor system according to claim 1, wherein the register unit is configured to indicate which of the plurality of processors is using which of the plurality of processors by a flag.   6. The multiprocessor system according to claim 5, wherein the flag is rewritten by a program operating on the processor when the processor uses or releases an area corresponding to the flag. In a failure processing method for a multiprocessor system, comprising: a plurality of processors; and a main storage device connected to the plurality of processors via a bus and shared by the processors,
The storage space in the main storage device is divided into a plurality of areas, and each of the areas is represented by a flag, which is represented by a flag,
A failure processing method characterized in that, when a failure occurs in any of the areas, the processor is identified with reference to the flag and an interrupt is notified.   The failure processing method according to claim 7, wherein the flag indicates which processor is used on which processor each area is used. 8. The failure processing method according to claim 7, wherein the flag is rewritten by a program operating on the processor when the processor uses or releases an area corresponding to the flag.

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