JP2005176006A - Despreading multiplex circuit for cdma communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the circuit scale of a despreading multiplex circuit for a CDMA communication system by which despreading processing is multiplexed. <P>SOLUTION: The despreading multiplex circuit for the CDMA communication system includes received data maintaining means 1 and 2 which accept received and demodulated data and can temporarily maintain the received data of a length at least corresponding to the length of delayed profile found in a searcher 20, multipliers 5 and 6 which read out the received data from the received data maintaining means 1 and 2 at a high speed according to the finger number and accept it, a code generating part including code generators 12-1 to 12-N which generate codes for despreading corresponding to several fingers according to pass timing signals from the searcher 20 and input them to the multipliers 5 and 6 and a selector 11, and summers 7 and 8 which perform dumping integration of the output data from the multipliers 5 and 6 in accordance with the fingers. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a despreading multiplex circuit for a CDMA (Code Division Multiple Access) communication system that multiplexes and executes a despreading process.

  The receiver in the CDMA communication system has, for example, the configuration of the main part shown in FIG. 13, and the signal received by the antenna 101 is input to the demodulation unit 103 via the bandpass filter (BPF) 102, Demodulated into in-phase component I and quadrature component Q by quadrature demodulation, input to AD converters (A / D) 106, 107 via low-pass filters (LPF) 104, 105, converted to digital signals, and despreading unit 108 and the searcher unit 109.

  The searcher unit 109 obtains a delay profile of the received signal that has passed through the multipath, detects a plurality of peaks, and notifies the despreading unit 108 of the timing of the peaks as the path timing. When N path timings are obtained, path timings corresponding to 1 to N fingers are input to the despreading unit 108. Despreading section 108 despreads the in-phase component and quadrature component of the received signal in accordance with the path timing and inputs the result to synchronous detection section 110. The synchronous detection unit 110 performs synchronous detection on the despread signal of each path, performs maximum ratio synthesis, outputs the demodulated data, and inputs the demodulated data to a subsequent circuit (not shown).

  The searcher unit 109 has, for example, the configuration shown in FIG. 14. 111 and 112 are matched filters (MF), 113 and 114 are in-phase addition circuits, 115 is a power conversion circuit, 116 is a code generator, and 117 is power. An adder circuit, 118 is a delay profile holding means, and 119 is a path timing detection circuit.

  Correlation detection between the in-phase component and the quadrature component of the received signal and the spread code from the code generator 116 is performed by the matched filters 111 and 112, and in-phase addition is performed in the in-phase addition circuits 113 and 114, and power conversion is performed. The power is converted by the circuit 115, and the value held by the delay profile holding means 118 is cumulatively added by the power adding circuit 117. Based on the result, the path timing is detected by the path timing detecting circuit 119, as described above. The despreading unit 108 is notified of the path timing.

  FIG. 15 is an explanatory diagram of a delay profile. With a configuration including the power addition circuit 117 and the delay profile holding unit 118, a delay profile having the vertical axis as the reception level and the horizontal axis as time can be obtained. In this delay profile, the time interval at which the correlation value detection process is performed is Tp, and four reception levels within the time interval Tp are equal to or greater than a predetermined value, for example, four paths (Paths) 1 to 4, and their path timings. Is detected and notified to the despreading unit 108.

  The despreading unit 108 has a finger configuration that performs despreading processing corresponding to a plurality of path timings. For example, the configuration shown in FIG. 16 is known. Reference numerals 121-1 to 121N denote fingers (1Finger to NFinger), 122 denotes a code generation unit, 123 and 124 denote despread data holding means, 125 and 126 denote multipliers, and 127 and 28 denote adders. The fingers 121-1 to 121-N have the same configuration, and supply the path timing signals corresponding to the paths 1 to N from the searcher unit 109 to the fingers 121-1 to 121-N, respectively.

  The received and demodulated in-phase component and quadrature component are input to the fingers 121-1 to 121 -N, and multipliers 125 and 126 multiply the spread codes according to the respective path timings from the code generator 122. The in-phase component and the quadrature component, which are dump-integrated by the adders 127 and 128 and the despread data holding means 123 and 124 and despread and demodulated, are input to the next-stage synchronous detection unit 110 (see FIG. 13). In the synchronous detection unit 110, synchronous detection and rake synthesis are performed, and data is restored by code determination. As shown in FIG. 15, when four path timings are detected in the searcher unit 109, the fingers 121-1 to 121-N of the despreading unit 108 are four fingers 121-1 to 121-121. -4.

In the CDMA receiver, the configuration of the searcher unit for detecting the path timing and the rake reception processing unit having a finger configuration corresponding to a plurality of path timings are used as the respective correlators to reduce the scale of the device. A receiving apparatus is known (see Patent Document 1).
Japanese Patent No. 26682493

  A receiver in a CDMA communication system detects a reception timing corresponding to a path as a path timing by a searcher unit in order to effectively receive a reception signal that has passed through a multipath, and has a finger configuration corresponding to this path timing. A despreading unit is provided, and each finger of the despreading unit includes a code generator, a multiplier, an adder, and the like. In a receiver corresponding to a plurality of users, a code generator, a multiplier, and an adder of the number of users × the number of passes are required. Therefore, there is a problem that the circuit scale increases as the number of fingers increases in order to perform reception processing efficiently and stably against fading.

  An object of the present invention is to reduce the circuit scale of a despreading unit of a receiver in a CDMA communication system.

  The despreading multiplexing circuit of the CDMA communication system according to the present invention reads received data at high speed according to the number of fingers from received data holding means capable of temporarily holding received data having a length corresponding to at least the delay profile length. And a multiplier for generating a despreading code corresponding to a plurality of fingers in accordance with a path timing signal from the searcher unit and inputting the code to the multiplier and dumping the output data of the multiplier for the finger And an adder for integration.

  The code generation unit includes a finger-compatible code generator and a selector that selects a despreading code from the code generator according to a path timing signal from the searcher unit and inputs the code to the multiplier.

  The code generation unit has a configuration in which the despreading codes corresponding to the fingers are sequentially switched, generated and output, and input to the multiplier.

  Received data holding means capable of temporarily holding received data having a length corresponding to at least the delay profile length, and a multiplier for reading received data from the received data holding means at high speed according to the number of users and the number of fingers and sequentially inputting the received data A code generation unit that generates a code for despreading corresponding to a plurality of users and corresponding to a plurality of fingers according to a path timing signal from the searcher unit, and inputs the code to the multiplier; And an adder that performs dump integration correspondingly.

  Received data holding means capable of temporarily holding received data having a length corresponding to a delay profile length corresponding to a plurality of users, and sequentially reading out received data from the received data holding means according to the number of users and the number of fingers. Generates despreading codes for multiple users and for multiple fingers according to the input multiplier and the path timing signal from the searcher unit that reads and inputs the received data from the received data holding means at high speed. The code generation unit input to the multiplier, and an adder that dumps and integrates the output data of the multiplier in correspondence with the user and the finger.

  The multiplier that holds the reception data corresponding to at least the delay profile length in the reception data holding means and inputs the reception data read at a high speed is for one finger for both a plurality of fingers or a plurality of users. In addition, an adder for performing despread processing and dump integration is also required for one finger, so that the circuit scale can be reduced.

  Referring to FIG. 1, a despreading multiplex circuit for a CDMA communication system receives received data including in-phase components and quadrature components received and demodulated, and at least corresponds to a delay profile length obtained by a searcher unit 20. Received data holding means 1 and 2 that can temporarily hold received data of a length, multipliers 5 and 6 for reading out and inputting received data from the received data holding means 1 and 2 according to the number of fingers, and a searcher unit A code generation unit including code generators 12-1 to 12 -N and a selector 11 that generate a code for despreading corresponding to a plurality of fingers in accordance with a path timing signal from 20 and input to the multipliers 5 and 6; And adders 7 and 8 that dump and integrate the output data of the multipliers 5 and 6 in correspondence with the fingers.

  FIG. 1 is an explanatory diagram of Embodiment 1 of the present invention, showing a searcher unit and a despreading unit, 1 and 2 are received data holding means, 3 is a write control circuit, 4 is a read control circuit, 6 is a multiplier, 7 and 8 are adders, 9 and 10 are despread data holding means, 11 is a selector (SEL), 12-1 to 12-N are code generators corresponding to fingers (Finger1 to FingerN), 20 Is a searcher unit, 21 and 22 are matched filters (MF), 23 and 24 are in-phase addition circuits, 25 is a power conversion circuit, 26 is a code generator, 27 is a power addition circuit, 28 is a delay profile holding means, and 29 is a path. 2 shows a timing detection circuit.

  A case where a code generation unit is configured by a plurality of finger-compatible code generators 12-1 to 12-N and a selector 11 is shown, and the received data holding means 1 and 2 have a ring buffer configuration, for example. The received and demodulated in-phase and quadrature components are written by the address signal or timing signal from the read control circuit 3, read by the address signal or timing signal from the read control circuit 4, and input to the multipliers 5 and 6. To do. The searcher unit 20 has the same configuration and operation as the configuration shown in FIG. 15 of the conventional example, and a redundant description of the configuration and operation is omitted. The path timing signal is transferred to the despreading unit according to the timing signal from the circuit 3. In the despreading unit, this path timing signal is distributed to the code generators 12-1 to 12 -N and the selector 11.

  The read control circuit 4 reads the received data held in the received data holding means 1 and 2 at a high speed according to the number of fingers and inputs it to the multipliers 5 and 6. The code generators 12-1 to 12-N generate the spread codes corresponding to the fingers 1 to N as described above, and the path timing signal from the path timing detection circuit 29 is distributed by a distribution means (not shown). The distributed code is generated in synchronization with each path timing signal. The selector 11 selects the spread code from the code generators 12-1 to 12 -N and inputs it to the multipliers 5 and 6. The data despread by the multipliers 5 and 6 is dump-integrated by the adders 7 and 8 and the despread data holding means, and the data of the in-phase and quadrature components that are time-division multiplexed corresponding to the fingers. However, in a synchronous detection unit (not shown), data is reproduced by synchronous detection, rake synthesis, and code determination.

  The received data holding means 1 and 2 correspond to a time length of at least Tp + (2 · ΔT), where Tp is the time interval for detecting the correlation value in the delay profile and ΔT is the time required for one cycle of the multiplex processing. The storage capacity is such that the received data to be written can be written. That is, the received data of the in-phase component and the quadrature component in Tp are sequentially written according to the timing signal from the write control circuit 3, and the received data is read at high speed by the timing signal from the read control circuit 4 within the time of ΔT. In order to write the received data even during the time ΔT, the received data holding means 1 and 2 are configured to have at least the storage capacity described above so as to have a margin for the time ΔT.

  FIG. 2 is an explanatory diagram of the received data holding means. As described above, the received data holding means 1 and 2 holding the in-phase component and the quadrature component in FIG. 1 are received with a time length of Tp + 2 · ΔT. A ring buffer configuration having areas A to H so that data can be written, the received data is sequentially written, and for example, the received data for 4 fingers within time ΔT is read at high speed n It shows in the order of (t) -n (t + Δ3T).

  In the first n (t), the received data written in the regions A to G within the time Tp + ΔT is subjected to the despreading process corresponding to the paths 1 to 4 (Path 1 to Path 4), for example, within the time ΔT. Reading is performed at high speed, and the received data in ΔT is written in the area H in the reading process. As shown in the upper part, the reading within ΔT is repeatedly read in order to process the received data written in the regions A to G in correspondence with the paths 1 to 4 (Path 1 to Path 4), and the time ΔT in the process is read. An operation of writing the received data demodulated into the area H is performed.

  In the next n (t + ΔT), the received data written in the areas B to H is read at high speed within the time ΔT, and the received data is written in the area A in the reading process. In the next n (t + Δ2T), the received data written in the areas C to H and A is read at high speed within the time ΔT, and the received data is written in the area B in the reading process. The received data written in the next areas D to H, A, and B is read at a high speed within the time ΔT, and the received data is written in the area C in the reading process. In the same manner, received data is written and read at high speed.

  As described above, received data corresponding to paths 1 to 4 (Path 1 to Path 4) read repeatedly from the received data holding means 1 and 2 at high speed by the control of the read control circuit 4 is time-division multiplexed. Are input to multipliers 5 and 6. For example, the code generators 12-1 to 12-4 corresponding to the paths 1 to 4 generate spreading codes synchronized with the path timing signals indicating the paths 1 to 4 from the path timing detection circuit 29, and the generated spreading The code is selected by the selector 11 according to the path timing signal and input to the multipliers 5 and 6. Therefore, the despreading process is also performed in time division, and the next dump integration process is also performed in time division, and the despread output data that has been time-division multiplexed is transferred to the subsequent synchronous detection unit or the like.

  In the first embodiment, code generators 12-1 to 12 -N corresponding to fingers (Finger 1 to Finger N) are provided, but multipliers 5 and 6, adders 7 and 8, and despread data holding are provided. The means 9 and 10 are shared with fingers to perform multiplexing processing. Therefore, there is an advantage that the circuit scale does not increase even if the number of fingers is increased. The received data holding means 1 and 2 are ring buffers that enable writing of received data corresponding to a time interval Tp at which the correlation value is detected and a time 2ΔT that is twice the time ΔT required for one cycle of the multiplex processing. Or, it can be easily configured by a normal memory or the like controlled by a write address and a read address.

  FIG. 3 is an explanatory diagram of the second embodiment of the present invention. The same reference numerals as those in FIG. 1 denote the same parts, and 13 denotes a code generator common to fingers (Finger 1 to Finger N). That is, a case is shown in which the code generation unit is configured by a code generator 13 that is shared for finger correspondence. A path timing signal from the searcher unit 20 is input to the code generator 13, a spread code for despreading synchronized with the path timing signal is generated in a time division manner, and input to the multipliers 5 and 6.

  The second embodiment can be applied to a case where one cycle time ΔT of multiplex processing is limited to one chip length or a case where a plurality of chip lengths are used, for example, one chip length or less. In the case of limiting to, a code for despreading can be continuously generated by a code multiplexing process even if a normal code generator is used. In addition, when the multi-chip length is used, the code generation initial value reload function is provided, or the generated code corresponding to the plurality of chips is temporarily stored, read repeatedly, and used, thereby reversing the correspondence with the fingers. The configuration is such that a spreading code is output.

  FIG. 4 is an explanatory diagram of the code generator. Using a shift register and an adder of modulo 2 (Mod2), the output signal of a predetermined stage of the shift register is input to the adder, and the result is added. Fig. 2 shows a normal code generator for input to an input stage. When this code generator is used, the despreading for the multiprocessing is performed in the multipliers 5 and 6 according to the path timing signal by limiting the one cycle time ΔT of the multiprocessing to one chip length or less as described above. Enter the sign for.

  FIG. 5 is an explanatory diagram of a code generator with an initial value reload function, a modulo 2 (Mod 2) that adds a plurality of flip-flops 31, a shift register 33 cascaded with a plurality of selectors 32, and an output of a predetermined stage. The selector 32 selects the output of the preceding flip-flop 31 and the initial value from the initial value register 35 and inputs them to the succeeding flip-flop 31. An outline of the operation of this code generator is shown with white triangle marks and black triangle marks for the case of code A (L-chip) generation and code B (L-chip) generation.

  First, an initial value for generating the code A is set from the initial value register 35 to each flip-flop 31 of the shift register 33 via the selector 32 to generate the first code A, and then the same initial value as the previous time. The value is set from the initial value register 35 to each flip-flop 31 of the shift register 33 via the selector 32 to generate the second code A. In the same manner, the Nth code A is generated, and then the initial value for generating the code B is set from the initial value register 35 to each flip-flop 31 of the shift register 33 via the selector 32. A code B is generated, and then the same initial value as the previous time is set from the initial value register 35 to each flip-flop 31 of the shift register 33 via the selector 32 to generate the second code B. In the same manner, the Nth code B is generated.

  FIG. 6 is an explanatory diagram of a code generator having a temporary holding means, a shift register 42 composed of a plurality of flip-flops 41, a modulo 2 (Mod 2) adder 43, a code generation control circuit 44, and a generation An outline of the case where the codes A, B, and C are generated including the code holding means 45 and the code reading control circuit 46 will be described. The code A is generated by the control of the code generation control circuit 44, temporarily stored in the generated code holding means 45, and repeatedly read from the first time to the Nth time by the control of the code reading control circuit 46. In the meantime, a code B is generated, the code B is temporarily held in the generated code holding means 45, and is repeatedly read from the first time to the Nth time under the control of the code reading control circuit 46. In the meantime, a code C is generated, and the code C is temporarily held in the generated code holding means 45. By repeating such an operation, it is possible to generate a code for despreading when one cycle of the multiprocessing is a plurality of chips.

  FIG. 7 is an explanatory diagram of Embodiment 3 of the present invention, where the same reference numerals as those in FIG. 1 denote the same parts, 14-1 to 14-K are user-compatible code generation units (User1 to UserK), and 15 is a selector ( SEL). Each of the user corresponding code generation units 14-1 to 14-K has the same configuration, and includes code generators (Finger1 to FingerN) 12-1 to 12-N for N fingers and a selector (SEL) 11. . The received data of the in-phase component and the quadrature component demodulated and received is temporarily held in the received data holding means 1 and 2, and the received data is controlled at high speed by the control of the read control circuit 4 as in the above-described embodiment. The data is read and despread processing corresponding to the user and N fingers is performed. Therefore, the multipliers 5 and 6 and the adders 7 and 8 for dump integration are configured for one finger regardless of the number of users K and the number of fingers N, and the despread data holding means 9 and 10 are used. Is configured to hold despread data of the number of users K × number of fingers N, and the multiplex processing is K × N times per cycle (ΔT).

  The searcher unit 20 has the same basic configuration as the searcher unit in FIG. 1 and generally does not cause a rapid change in the path timing. Therefore, the searcher unit 20 performs time multiplexing processing corresponding to the number of users K. The path timing corresponding to the user is detected. This user-corresponding path timing signal is input to the user-corresponding code generation units 14-1 to 14-N, the selector 15 selects a user-decoding code for despreading, and the selector 11 selects a path-corresponding despreading signal. A code is selected and input to multipliers 5 and 6, and despreading processing is performed by multiplexing the number of users K × number of fingers N.

  FIG. 8 is an explanatory diagram of a fourth embodiment of the present invention. The same reference numerals as those in FIG. 1 denote the same parts, and 16-1 to 16-K denote fingers (finger 1 to finger N) corresponding to users (User 1 to User K). A common code generator is shown, and these code generators 16-1 to 16 -K and the selector 11 constitute a code generator common to a plurality of users and a plurality of fingers. Each of the code generators 16-1 to 16-N has a code generation function similar to that of the code generator 13 in FIG. 3, for example. A sign is selected and input to multipliers 5 and 6. The received data of the in-phase component and the quadrature component demodulated and received are temporarily held in the received data holding means 1 and 2 and controlled by the read control circuit 4 in the same way as in the above-described embodiment so as to be compatible with users and fingers. Are read out and subjected to despreading processing. For this purpose, the multipliers 5 and 6 and the adders 7 and 8 have a structure for one finger, and the despread data holding means 9 and 10 have a structure for holding despread data of the number of users K × the number of fingers N. It is what you have. Multiple processing of this despreading processing is K × N times per cycle (ΔT).

  Similarly to the searcher unit in FIG. 7, the searcher unit 20 detects the path timing corresponding to the user by time multiplexing processing corresponding to the number of users N, and inputs the path timing signal to the despreading unit to generate the code. The generation of the despreading code corresponding to the user and the path from the units 16-1 to 16-K is controlled, and the despreading code selected by the selector 11 is supplied to the multipliers 5 and 6 as described above. input.

  FIG. 9 is an explanatory diagram of Embodiment 5 of the present invention, and the same reference numerals as those in FIG. 7 denote the same parts. In the fifth embodiment, the received data of the multiplexed in-phase component and quadrature component for the number K of users is temporarily held in the received data holding means 1 and 2 and read at high speed under the control of the read control circuit 4. , And input to the searcher unit 20 and the multipliers 5 and 6 for despreading processing. The selector 11 selects a despreading code corresponding to the finger, the selector 15 selects a despreading code corresponding to the user, and inputs the code to the multipliers 5 and 6. The despread data of the number of fingers × the number of users is held and input to a synchronous detection unit (not shown). Therefore, also in the fifth embodiment, the multipliers 5 and 6 and the adders 7 and 8 have a structure corresponding to one finger, and the despread data holding means 9 and 10 for performing dump integration include the number K of users. X By adopting a configuration capable of holding despread data with N fingers, the circuit scale can be reduced.

  FIG. 10 is an explanatory diagram of the multiplex processing of the searcher unit, in which (user 1 path timing update) to (user K path timing update) are sequentially performed by (user 1 search processing) to (user K search processing). For example, in the (user 1 search process), the reception data held in the areas A to G of the reception data holding means A to G is read within the time ΔT, and the path (Path 1 to Path 4) is detected. . Then, integration is performed over the time Ts by the power addition circuit 27 and the delay profile holding unit, and the path timing of the user 1 is detected by the path timing detection circuit 29. That is, the user 1 path timing is updated by the user 1 search process at time Ts. For other users 2 to K, the path timing can be detected by the same process.

  FIG. 11 is an explanatory diagram of Embodiment 6 of the present invention, and the same reference numerals as those in FIG. 8 denote the same parts. In the sixth embodiment, similarly to the fifth embodiment shown in FIG. 10, received data of multiplexed in-phase components and quadrature components of the number of users K is temporarily held in the received data holding means 1 and 2, The data is read at high speed for the user under the control of the read control circuit 4 and input to the searcher unit 20 and the multipliers 5 and 6 for despreading processing. Similarly to the embodiment shown in FIG. 8, the configuration for performing the despreading processing is a code generator (User1) corresponding to the user and common to fingers (user 1 to N common) to (User K) (common to fingers 1 to N) 16-1. 16-K is provided, and the generated despreading code is selected by the selector 11 and input to the multipliers 5 and 6. Accordingly, the multipliers 5 and 6 and the adders 7 and 8 have a configuration corresponding to one finger, and the despread data holding means 9 and 10 have a configuration in which despread data having the number of users K × the number of fingers N is held. The scale can be reduced.

  FIG. 12 is an explanatory diagram of a synchronous detection unit for inputting despread data, 51 is a channel estimation circuit, 52 to 55 are multipliers, 56 to 59 are adders, and 60 and 61 are detection data holding means. Show. The despread output data of the in-phase component and the quadrature component are input to the channel estimation circuit 51 and the multipliers 52 to 55, and the channel estimation value obtained by the channel estimation circuit 51 is input to the multipliers 52 to 55. The outputs of the multipliers 53 and 54 are input to the adder 57, and the outputs of the adders 56 and 57 are in-phase by the adders 58 and 59 and the detection data holding means 60 and 61. to add. For example, with respect to despread output data indicated as data Data1 and Data2 of fingers 1f to N, data Data1 and Data2 are output by in-phase addition corresponding to fingers 1f to Nf.

  (Supplementary Note 1) In a despreading multiplex circuit for a CDMA communication system that performs despreading processing by multiplying received data by a despreading code, it is possible to temporarily hold received data having a length corresponding to at least the delay profile length. Received data holding means, a multiplier for reading out and inputting received data at high speed according to the number of fingers from the received data holding means, and generating a code for despreading corresponding to a plurality of fingers according to a path timing signal from the searcher unit A despreading multiplex circuit for a CDMA communication system, comprising: a code generation unit that inputs to the multiplier; and an adder that dumps and integrates output data of the multiplier corresponding to a finger.

(Supplementary Note 2) The code generation unit is configured to select a code generator corresponding to the finger and a despreading code from the code generator according to a path timing signal from the searcher unit and input the code to the multiplier The despreading multiplex circuit for a CDMA communication system according to appendix 1, characterized by comprising:
(Additional remark 3) The said code generation part has the structure which switches the code | symbol for despreading corresponding to the said finger | toe sequentially, produces | generates and outputs it, and it inputs into the said multiplier, The reverse for CDMA communication systems of Additional remark 1 Diffusion multiplexing circuit.
(Additional remark 4) The said code generation part selects the code | symbol for despreading corresponding to the said finger | toe, and the code | symbol for said despreading from this several code generator according to the said path timing signal The despreading multiplex circuit for a CDMA communication system according to claim 1, further comprising: a selector that inputs to the multiplier.

(Supplementary Note 5) In a despreading multiplex circuit for a CDMA communication system that performs despreading processing by multiplying received data by a despreading code, it is possible to temporarily hold received data having a length corresponding to at least the delay profile length. Received data holding means, a multiplier for reading out received data from the received data holding means at high speed according to the number of users and the number of fingers, and sequentially inputting the received data, and corresponding to the plurality of users and corresponding to the plurality of fingers according to the path timing signal from the searcher unit A code generation unit that generates a code for despreading and inputs the code to the multiplier, and an adder that dumps and integrates the output data of the multiplier in correspondence with a user and a finger. A despreading multiplex circuit for a CDMA communication system.
(Additional remark 6) The said code generation part contains the several code generator which produces | generates the code | symbol for despreading corresponding to a finger, and the selector which selects the said code | symbol for said despreading from this several code generator. 6. A supplementary code 5, comprising: a corresponding code generation unit; and a selector that selects and outputs the code for despreading for the user and inputs the code to the multiplier by the selector of the user corresponding code generation unit. Despreading multiplexing circuit for CDMA communication system.
(Supplementary Note 7) The code generation unit includes a plurality of code generators corresponding to users that sequentially generate and output the despread codes corresponding to the fingers, and despread codes from the plurality of code generators. 6. The despreading multiplex circuit for a CDMA communication system according to claim 5, further comprising a selector that selects and inputs the selector to the multiplier.

  (Supplementary Note 8) In a despreading multiplex circuit for a CDMA communication system that performs despreading processing by multiplying received data by a despreading code, it is possible to temporarily hold received data having a length corresponding to at least the delay profile length. Received data holding means, a multiplier for reading out received data from the received data holding means at high speed according to the number of users and the number of fingers and sequentially inputting the received data, and receiving and inputting received data corresponding to the user from the received data holding means at high speed A code generation unit that generates a code for despreading corresponding to the plurality of users and corresponding to a plurality of fingers according to a path timing signal from the searcher unit, and inputs the code to the multiplier; And despread multiplexing for a CDMA communication system, characterized by comprising an adder for dump integration corresponding to a finger Road.

It is explanatory drawing of Example 1 of this invention. It is explanatory drawing of a reception data holding means. It is explanatory drawing of Example 2 of this invention. It is explanatory drawing of a code generator. It is explanatory drawing of the code generator with an initial value reload function. It is explanatory drawing of the code generator which has a temporary holding means. It is explanatory drawing of Example 3 of this invention. It is explanatory drawing of Example 4 of this invention. It is explanatory drawing of Example 5 of this invention. It is explanatory drawing of the multiplex process of a searcher part. It is explanatory drawing of Example 6 of this invention. It is explanatory drawing of a synchronous detection part. It is explanatory drawing of a CDMA receiver. It is explanatory drawing of a searcher part. It is explanatory drawing of a delay profile. It is explanatory drawing of the conventional despreading part.

Explanation of symbols

1, 2 Received data holding means 3 Write control circuit 4 Read control circuit 5, 6 Multiplier 7, 8 Adder 9, 10 Despread data holding means 11 Selector (SEL)
12-1 to 12-N Code generator 20 Searcher unit 21, 22 Matched filter (MF)
23, 24 In-phase addition circuit 25 Power conversion circuit 26 Code generator 27 Power addition circuit 28 Delay profile holding means 29 Path timing detection circuit

Claims (5)

In a despreading multiplex circuit for a CDMA communication system that performs despreading processing by multiplying received data by a despreading code,
Received data holding means capable of temporarily holding received data having a length corresponding to at least the delay profile length;
A multiplier for reading out and inputting received data at high speed according to the number of fingers from the received data holding means;
A code generation unit that generates a code for despreading corresponding to a plurality of fingers in accordance with a path timing signal from the searcher unit and inputs the code to the multiplier;
A despreading multiplex circuit for a CDMA communication system, comprising: an adder that dumps and integrates output data of the multiplier in correspondence with a finger.   The code generation unit includes a code generator corresponding to the finger, and a selector that selects a code for despreading from the code generator according to a path timing signal from the searcher unit and inputs the code to the multiplier. 2. A despreading multiplex circuit for a CDMA communication system according to claim 1.   2. The despreading multiplex circuit for a CDMA communication system according to claim 1, wherein the code generation unit has a configuration in which the despreading codes corresponding to the fingers are sequentially switched and generated and output to the multiplier. . In a despreading multiplex circuit for a CDMA communication system that performs despreading processing by multiplying received data by a despreading code,
Received data holding means capable of temporarily holding received data having a length corresponding to at least the delay profile length;
A multiplier for reading out received data at high speed according to the number of users and the number of fingers from the received data holding means and sequentially inputting them;
A code generation unit for generating a code for despreading corresponding to a plurality of users and corresponding to a plurality of fingers according to a path timing signal from a searcher unit, and inputting the code to the multiplier;
A despreading multiplex circuit for a CDMA communication system, comprising: an adder that dumps and integrates output data of the multiplier in correspondence with a user and a finger. In a despreading multiplex circuit for a CDMA communication system that performs despreading processing by multiplying received data by a despreading code,
Received data holding means capable of temporarily holding received data having a length corresponding to at least the delay profile length;
A multiplier for reading out received data at high speed according to the number of users and the number of fingers from the received data holding means and sequentially inputting them;
In accordance with a path timing signal from a searcher unit that reads and inputs user-corresponding reception data from the reception data holding means at high speed, a code for despreading corresponding to the plurality of users and corresponding to a plurality of fingers is generated and multiplied. A code generator to be input to the device;
A despreading multiplex circuit for a CDMA communication system, comprising: an adder that dumps and integrates output data of the multiplier in correspondence with a user and a finger.

Images