JP2005159192A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2005159192A
JP2005159192A JP2003398371A JP2003398371A JP2005159192A JP 2005159192 A JP2005159192 A JP 2005159192A JP 2003398371 A JP2003398371 A JP 2003398371A JP 2003398371 A JP2003398371 A JP 2003398371A JP 2005159192 A JP2005159192 A JP 2005159192A
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semiconductor element
wiring
connection terminal
wiring board
electrode
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Yoshiaki Takeoka
嘉昭 竹岡
Toshitaka Akaboshi
年隆 赤星
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problems: an increased protruding quantity of sealing resin filled in a first semiconductor element needs to arrange a second connecting terminal outside a first connecting terminal, which is a detrimental to a downsizing of a lamination-type semiconductor device having the first connecting terminal for flip chip connecting a semiconductor element in a lower stage and the second connecting terminal for wire bond connecting a semiconductor element in an upper stage. <P>SOLUTION: The first semiconductor element 4 with a bump 9 formed is positioned and mounted by the flip chip bonding at the first connecting terminal 2 of the wiring board 1 with a dummy wiring 6 provided. A first sealing resin 5 is filled in a gap between the first semiconductor element 4 and the wiring board 1, and the extra first sealing resin 5 runs out on the periphery of the first semiconductor element without adhering to the second connecting terminal 3. The wiring board 1 has a wiring area of a fixed ratio of the area of the dummy wiring 6 and the first connecting terminal 2 to the area of the first semiconductor element 4. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

本発明は、フリップチップ方式で接合させる半導体装置およびその製造方法に関するものであり、特に積層型半導体装置およびその製造方法に関するものである。 The present invention relates to a semiconductor device bonded by a flip chip method and a manufacturing method thereof, and more particularly to a stacked semiconductor device and a manufacturing method thereof.

携帯情報機器等の小型、軽量化に伴い、半導体装置パッケージの高密度化、小型化、薄型化が要求される。これらの要望に答えるために、半導体素子を重ねて多段に搭載した半導体装置が開発されており、より小型化を実現するための手段としてフリップチップ方式の接合とワイヤーボンディング方式の接合を混載した半導体装置が小型化に対して有利であるが、フリップチップ方式の接合では半導体素子と配線基板の間隙に素子表面の保護を目的とした樹脂封止が必要である。   As portable information devices and the like become smaller and lighter, semiconductor device packages are required to have higher density, size, and thickness. In order to meet these demands, a semiconductor device in which semiconductor elements are stacked in multiple stages has been developed, and a semiconductor in which flip chip bonding and wire bonding bonding are mixedly mounted as a means for realizing further miniaturization. Although the device is advantageous for downsizing, flip-chip bonding requires resin sealing for the purpose of protecting the element surface in the gap between the semiconductor element and the wiring board.

従来の積層型半導体装置の製造方法を工程図５を参照して説明する。   A conventional method for manufacturing a stacked semiconductor device will be described with reference to FIG.

図５(ａ)の配線基板１を準備する工程と、図５(ｂ)の配線基板１の配線層面にある第１接続端子部を覆うサイズの絶縁性で熱硬化性樹脂シート１２を貼り付ける工程と、図５(ｃ)の第１半導体素子４に形成したバンプ９と配線基板１の第１接続端子２を位置合わせして搭載し、熱と加圧力によって余分な第１封止樹脂５を第２接続端子３に被らない様に第１半導体素子４の外側に押し出して硬化させ、接続を行う工程と、図５(ｄ)の第２半導体素子８を第１半導体素子４の裏面に搭載する工程と、図５(ｅ)の第２半導体素子８の電極端子と配線基板１の第２接続端子３をボンディングワイヤー１０でワイヤーボンディング接続を行う工程と、図５(ｆ)の配線基板１に実装された第１の半導体素子４と第２半導体素子８の全体を覆うように第２の封止樹脂１１でモールドする工程から半導体装置の製造が完了する。   A step of preparing the wiring board 1 of FIG. 5A and an insulating thermosetting resin sheet 12 of a size covering the first connection terminal portion on the wiring layer surface of the wiring board 1 of FIG. The bumps 9 formed on the first semiconductor element 4 in FIG. 5C and the first connection terminals 2 of the wiring board 1 are aligned and mounted, and excess first sealing resin 5 is applied by heat and pressure. A step of extruding to the outside of the first semiconductor element 4 so as not to cover the second connection terminal 3 and curing, and connecting the second semiconductor element 8 of FIG. 5D to the back surface of the first semiconductor element 4 Mounting step, wire bonding connection between the electrode terminal of the second semiconductor element 8 of FIG. 5E and the second connection terminal 3 of the wiring substrate 1 with the bonding wire 10, and the wiring of FIG. The second sealing is performed so as to cover the entire first semiconductor element 4 and second semiconductor element 8 mounted on the substrate 1. Manufacturing a semiconductor device the step of molding a resin 11 is completed.

この製造方法の中で、図５(ｃ)の第２接続端子３に被らないように第１の封止樹脂５を充填させることが半導体装置の小型化に対し重要となる。
特開平１１−219984号公報 In this manufacturing method, it is important for the miniaturization of the semiconductor device to fill the first sealing resin 5 so as not to cover the second connection terminals 3 in FIG.
JP-A-11-219984

しかしながら、従来の半導体装置では、第1半導体素子４と配線基板１との間隙に充填する第1の封止樹脂５の必要量が配線基板１の第1半導体素子４を実装する領域の配線で占める体積によって異なり、一定厚みの熱硬化性樹脂シートを供給すると、第1の封止樹脂５のはみ出しが品種によって異なってしまうため、第2半導体素子と接続する第2接続端子の位置が一定の間隔で配置することが出来なくなり、半導体装置の小型化の障害となっていた。   However, in the conventional semiconductor device, the necessary amount of the first sealing resin 5 filling the gap between the first semiconductor element 4 and the wiring substrate 1 is the wiring in the region where the first semiconductor element 4 of the wiring substrate 1 is mounted. When a thermosetting resin sheet having a constant thickness is supplied depending on the volume occupied, the protrusion of the first sealing resin 5 varies depending on the product type, so that the position of the second connection terminal connected to the second semiconductor element is constant. It was impossible to arrange them at intervals, which was an obstacle to miniaturization of semiconductor devices.

以下、課題について図面を参照しながら説明する。   The problem will be described below with reference to the drawings.

図６は、第1半導体素子を実装する領域に配線が最も少ない場合の配線基板の平面図とＡ−Ａ´の断面図であり、配線基板１に第1半導体素子と接続する第1接続端子２と第2半導体素子と接続する第2接続端子３が形成されている。また、図７は第1半導体素子を実装する領域に配線が密に形成されている場合の平面図とＢ−Ｂ´の断面図であり、配線基板１´の第1半導体素子を実装する領域には第1接続端子２´の配線が密に形成されている。３′は第2半導体素子と接続する第2接続端子である。   FIG. 6 is a plan view of a wiring board and a cross-sectional view taken along the line AA ′ in the case where the number of wirings is the smallest in the region where the first semiconductor element is mounted. 2 and a second connection terminal 3 connected to the second semiconductor element. FIGS. 7A and 7B are a plan view and a cross-sectional view taken along line BB ′ in the case where wirings are densely formed in the region where the first semiconductor element is mounted, and the region where the first semiconductor element is mounted on the wiring board 1 ′. The wiring of the first connection terminal 2 'is densely formed. Reference numeral 3 'denotes a second connection terminal connected to the second semiconductor element.

図８は図６の配線基板１に第1半導体素子４をフリップチップ実装したあとの平面図と断面図であるが、第1半導体素子４と配線基板１の間隙に充填され余分な第1封止樹脂５が第2接続端子３に被ること無く充填されている。しかし、図９は図７の配線基板１´に第1半導体素子４をフリップチップ実装したあとの平面図と断面図であるが、同一厚み、サイズの熱硬化性樹脂シートを供給しても第1半導体素子４と配線基板１´との間隙の体積が第1接続端子２´の配線で占める体積によって異なり、余分な第1封止樹脂５のはみ出しが大きくなり、第2接続端子３´に被ってしまうことによって、第2接続端子３′の接合品質が確保できなくなるという課題が発生する。   FIG. 8 is a plan view and a cross-sectional view after the first semiconductor element 4 is flip-chip mounted on the wiring board 1 of FIG. 6, but the gap between the first semiconductor element 4 and the wiring board 1 is filled. The stop resin 5 is filled without covering the second connection terminal 3. However, FIG. 9 is a plan view and a cross-sectional view after the first semiconductor element 4 is flip-chip mounted on the wiring board 1 ′ in FIG. 7. However, even if a thermosetting resin sheet having the same thickness and size is supplied, 1 The volume of the gap between the semiconductor element 4 and the wiring board 1 ′ differs depending on the volume occupied by the wiring of the first connection terminal 2 ′, and the excess protrusion of the first sealing resin 5 becomes large, and the second connection terminal 3 ′ The covering causes a problem that the bonding quality of the second connection terminal 3 ′ cannot be ensured.

本発明は、配線基板に形成される第1接続端子の配線面積の差によって、供給する熱硬化性樹脂シートの厚み、サイズを変更しなくても良く、また、第2接続端子への第１封止樹脂の付着を防止でき、接続品質の確保が可能となる半導体装置およびその製造方法を提供することを目的とする。   In the present invention, the thickness and size of the thermosetting resin sheet to be supplied need not be changed depending on the wiring area difference of the first connection terminals formed on the wiring board, and the first connection to the second connection terminals is not necessary. An object of the present invention is to provide a semiconductor device that can prevent adhesion of sealing resin and ensure connection quality and a method for manufacturing the same.

この発明の半導体装置は、実装面に電極を有する第1半導体素子と、この第1半導体素子の実装領域に第1半導体素子の電極と導通のある配線および第1半導体素子の電極と導通のないダミー配線を有して導通のある配線と導通のないダミー配線の面積和が第1半導体素子の面積と一定の比率となる配線面積を有した配線基板と、配線基板上にフリップチップボンディングされた第１半導体素子と配線基板との間隙に充填された第1封止樹脂と、第１半導体素子の配線基板と反対側の面に固着され表面に設けられた電極端子が配線基板とワイヤーボンディングで接続された第２半導体素子と、第１半導体素子と第２半導体素子の全体を覆うようにモールドした第２封止樹脂を備えたものである。   The semiconductor device according to the present invention includes a first semiconductor element having an electrode on a mounting surface, a wiring that is electrically connected to the electrode of the first semiconductor element in the mounting region of the first semiconductor element, and no electrical connection to the electrode of the first semiconductor element. A wiring board having a wiring area in which the sum of the areas of the conductive wiring and the non-conductive dummy wiring having the dummy wiring is a constant ratio to the area of the first semiconductor element, and flip chip bonding on the wiring board The first sealing resin filled in the gap between the first semiconductor element and the wiring board, and the electrode terminal fixed on the surface of the first semiconductor element opposite to the wiring board and provided on the surface are connected to the wiring board by wire bonding. The second semiconductor element is connected, and the second sealing resin is molded so as to cover the whole of the first semiconductor element and the second semiconductor element.

上記構成において、配線基板の配線層形成面で第1半導体素子の実装領域にある、第1半導体素子の電極と導通のある配線が回路形成され、第1半導体素子の電極と導通のないダミー配線は、第1の半導体素子の面積に対して一定の比率の面積から、第1半導体素子の電極と導通がありかつ回路形成された配線の面積を差し引いた面積を有する。   In the above configuration, a dummy wiring that is electrically connected to the electrode of the first semiconductor element in the mounting region of the first semiconductor element on the wiring layer forming surface of the wiring substrate is formed in a circuit, and is not conductive to the electrode of the first semiconductor element. Has an area obtained by subtracting the area of the wiring that is electrically connected to the electrode of the first semiconductor element and that is formed with a circuit from the area of a certain ratio with respect to the area of the first semiconductor element.

上記構成において、第１半導体素子の電極と配線基板の第１接続端子とがバンプを介して接続されている。   In the above configuration, the electrode of the first semiconductor element and the first connection terminal of the wiring substrate are connected via the bump.

この発明の半導体装置の製造方法は、複数個の半導体素子が厚さ方向に多段に重ねて配置された半導体装置の製造方法であって、
下段の第１の半導体素子が実装される範囲に第１接続端子およびダミー配線を有しその外側に第２接続端子を有する配線基板を準備する工程と、配線基板の第１接続端子およびダミー配線上に絶縁性の熱硬化性樹脂シートを貼り付ける工程と、第１半導体素子の電極と配線基板の第1接続端子とを位置合わせし、加熱しながら加圧力により押圧して余分な樹脂を押し出し、第１半導体素子の電極と配線基板の第１接続端子とをフリップチップボンディングするとともに第1半導体素子と配線基板の間に介在する熱硬化性樹脂シートを熱により硬化する工程と、第1半導体素子の裏面に上段となる第2半導体素子を固着する工程と、第２半導体素子の電極と配線基板の配線層形成面上において第１接続端子よりも外側に配置された第２接続端子とをボンディングワイヤを介してワイヤーボンディング方式により接続する工程と、第１半導体素子と第２半導体素子の全体を覆うように第２封止樹脂でモールドする工程を含むものである。 A manufacturing method of a semiconductor device of the present invention is a manufacturing method of a semiconductor device in which a plurality of semiconductor elements are arranged in multiple stages in the thickness direction,
A step of preparing a wiring board having a first connection terminal and a dummy wiring in a range where the lower first semiconductor element is mounted and having a second connection terminal outside the first connection terminal; and the first connection terminal and the dummy wiring of the wiring board The process of affixing an insulating thermosetting resin sheet on top, align the electrode of the first semiconductor element and the first connection terminal of the wiring board, and press the excess resin by applying pressure while heating Flip-chip bonding the electrode of the first semiconductor element and the first connection terminal of the wiring board, and curing the thermosetting resin sheet interposed between the first semiconductor element and the wiring board by heat, the first semiconductor A step of fixing an upper second semiconductor element to the back surface of the element, and an electrode of the second semiconductor element and a second connection terminal disposed outside the first connection terminal on the wiring layer forming surface of the wiring substrate. Bo The method includes a step of connecting via a bonding wire by a wire bonding method, and a step of molding with a second sealing resin so as to cover the entire first semiconductor element and second semiconductor element.

上記構成において、第１半導体素子の電極と配線基板の第１接続端子とをバンプを介してフリップチップボンディングする。   In the above configuration, the electrode of the first semiconductor element and the first connection terminal of the wiring board are flip-chip bonded via the bump.

本発明の半導体装置によれば、第1半導体素子を実装する領域の配線基板に第1接続端子の配線以外にダミー配線を設けた構造となっており、その第1接続端子の配線とダミー配線の体積和を品種に関係なく固定することにより、品種によって熱硬化性樹脂シートの厚みを変更すること無く第1半導体素子と配線基板の間隙に第1封止樹脂を充填することができ、熱硬化性樹脂シートの厚みを一定化でき、第1封止樹脂のはみ出しを制御することが可能となる。これにより、熱硬化性樹脂シートの切替えロスを無くし、また、はみ出す第1封止樹脂量を制御できることから、第２接続端子を一定の位置に配置した上で、第2接続端子への第1封止樹脂の被りを無くすことで、半導体パッケージの小型化を可能とし、第２接続端子へのワイヤーボンド接続品質を安定させることができる。   According to the semiconductor device of the present invention, the wiring board in the region where the first semiconductor element is mounted has a structure in which dummy wiring is provided in addition to the wiring of the first connection terminal. The wiring of the first connection terminal and the dummy wiring By fixing the volume sum regardless of the product type, the first sealing resin can be filled in the gap between the first semiconductor element and the wiring board without changing the thickness of the thermosetting resin sheet depending on the product type. The thickness of the curable resin sheet can be made constant, and the protrusion of the first sealing resin can be controlled. As a result, the switching loss of the thermosetting resin sheet can be eliminated and the amount of the first sealing resin protruding can be controlled. Therefore, the first connection to the second connection terminal after the second connection terminal is arranged at a fixed position. By eliminating the covering of the sealing resin, the semiconductor package can be miniaturized, and the quality of wire bond connection to the second connection terminal can be stabilized.

本発明の半導体装置の製造方法によれば、上記のように第2接続端子への第1封止樹脂の被りを無くすことで、第２接続端子へのワイヤーボンド接続品質を確保することが可能となる。   According to the method for manufacturing a semiconductor device of the present invention, it is possible to ensure the quality of wire bond connection to the second connection terminal by eliminating the covering of the first sealing resin to the second connection terminal as described above. It becomes.

発明の実施するための最良の形態BEST MODE FOR CARRYING OUT THE INVENTION

本発明の半導体装置およびその製造方法の一実施形態について、以下、図面を参照しながら説明する。   An embodiment of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.

まず、本発明の一実施形態の半導体装置について説明する。図１は本実施形態の半導体装置の断面図である。   First, a semiconductor device according to an embodiment of the present invention will be described. FIG. 1 is a cross-sectional view of the semiconductor device of this embodiment.

図１に示すように本実施形態の半導体装置は、ダミー配線６を設けた配線基板１の第1接続端子２にバンプ９を形成した第1半導体素子４を位置合わせしてフリップチップボンディングで搭載している。第1半導体素子４と配線基板１の間隙には第1封止樹脂５が充填されており、第１半導体素子の周辺に余分な第1封止樹脂５がはみ出している。第２半導体素子８は第1半導体素子４の裏面に固着されており、配線基板１の第2接続端子３とボンディングワイヤー１０によって接続されている。また、第1半導体素子４と第2半導体素子８全体を第２封止樹脂１１で覆うようにモールドされている。   As shown in FIG. 1, in the semiconductor device of this embodiment, the first semiconductor element 4 on which the bump 9 is formed is aligned with the first connection terminal 2 of the wiring board 1 provided with the dummy wiring 6, and is mounted by flip chip bonding. doing. A gap between the first semiconductor element 4 and the wiring substrate 1 is filled with a first sealing resin 5, and excess first sealing resin 5 protrudes around the first semiconductor element. The second semiconductor element 8 is fixed to the back surface of the first semiconductor element 4 and is connected to the second connection terminal 3 of the wiring substrate 1 by the bonding wire 10. The first semiconductor element 4 and the entire second semiconductor element 8 are molded so as to be covered with the second sealing resin 11.

この配線基板１に形成されているダミー配線６は、図２に示すように配線基板１上の第1半導体素子４の実装領域で第1半導体素子４の電極に相対する位置に形成された第1接続端子２の内側に配置されている。このダミー配線６の大きさは、第1半導体素子４の実装領域で第1半導体素子４の面積に対して一定の比率の面積から第1接続端子２の面積を差し引いた面積とし、これを品種間で固定化することにより第1半導体素子４と配線基板１の間隙の体積を合わせることが出来る。これを式に表すと配線必要面積（チップ面積×ａ％）＝第1接続端子面積＋ダミー配線面積となる。これは、第1半導体素子４と配線基板１の隙間寸法を考慮すると、体積を表すことになる。   As shown in FIG. 2, the dummy wiring 6 formed on the wiring board 1 is a first wiring formed on the wiring board 1 at a position facing the electrode of the first semiconductor element 4 in the mounting region of the first semiconductor element 4. 1 Arranged inside the connection terminal 2. The size of the dummy wiring 6 is the area obtained by subtracting the area of the first connection terminal 2 from the area of the fixed ratio to the area of the first semiconductor element 4 in the mounting region of the first semiconductor element 4. The volume of the gap between the first semiconductor element 4 and the wiring board 1 can be matched by fixing between the two. When this is expressed in an equation, the required wiring area (chip area × a%) = first connection terminal area + dummy wiring area. This represents the volume in consideration of the gap size between the first semiconductor element 4 and the wiring board 1.

また、配線の形状は第1封止樹脂５の流れを阻害しない形状とし、第1半導体素子４の実装領域の中央部に位置し外周部方向に対し流れをせき止めない形状が良く、例えば丸型、星型にすることが望ましい。   Also, the shape of the wiring should be a shape that does not hinder the flow of the first sealing resin 5 and is located in the center of the mounting region of the first semiconductor element 4 so that the flow is not blocked in the direction of the outer periphery. It is desirable to use a star shape.

図３は本実施形態の半導体装置の第1半導体素子４の実装前後の断面図である。図３に示すように第１半導体素子４を実装前に配線基板１に熱硬化性樹脂シート１２をあらかじめ貼り付けておき、次に第１半導体素子４を実装する。実装は配線基板１上の第1接続端子２にバンプ９を形成した第1半導体素子４を位置合わせしてフリップチップ実装されており、第１半導体素子４と配線基板１の間隙には実装前の硬化反応が行われていない熱硬化性樹脂シート１２が熱と加圧によって溶融した後硬化し第１封止樹脂５となり充填され余分な第１封止樹脂５は第１半導体素子４の周辺にはみ出している。このはみ出した第１封止樹脂５のはみ出し量は配線基板１上に形成されたダミー配線６の体積により変化する。これは第１半導体４と配線基板１の間隙が約４０から５０マイクロメートルであるのに対し配線基板１上に形成された第１接続端子２とダミー配線６の高さが約１５〜２０マイクロメートルであるため、第１接続端子２とダミー配線６の体積が第１半導体素子４と配線基板１の間隙の体積の中で占める割合が高くなり、余分な第１封止樹脂５が第１半導体素子の外周にはみ出すためである。   FIG. 3 is a cross-sectional view of the semiconductor device of this embodiment before and after mounting the first semiconductor element 4. As shown in FIG. 3, a thermosetting resin sheet 12 is attached in advance to the wiring board 1 before mounting the first semiconductor element 4, and then the first semiconductor element 4 is mounted. The mounting is flip-chip mounted by aligning the first semiconductor element 4 formed with the bump 9 on the first connection terminal 2 on the wiring board 1, and in the gap between the first semiconductor element 4 and the wiring board 1 before mounting. The thermosetting resin sheet 12 that has not undergone the curing reaction is cured after being melted by heat and pressure and cured to become the first sealing resin 5, and the excess first sealing resin 5 is around the first semiconductor element 4. It sticks out. The amount of the protruding first sealing resin 5 varies depending on the volume of the dummy wiring 6 formed on the wiring substrate 1. This is because the gap between the first semiconductor 4 and the wiring board 1 is about 40 to 50 micrometers, whereas the height of the first connection terminal 2 and the dummy wiring 6 formed on the wiring board 1 is about 15 to 20 micrometers. Therefore, the ratio of the volume of the first connection terminal 2 and the dummy wiring 6 to the volume of the gap between the first semiconductor element 4 and the wiring substrate 1 is high, and the excess first sealing resin 5 is the first. This is because it protrudes from the outer periphery of the semiconductor element.

そこで、ダミー配線６を設けることによって品種が変わり、第１接続端子２の配線面積が異なる配線基板１に対し半導体素子４を実装する前に供給する熱硬化性樹脂シートを一定の厚みで供給しても、ダミー配線６で体積の調整を行うことで第１封止樹脂５のはみ出し量を制御することが可能となる。   Therefore, by providing the dummy wiring 6, the product type is changed, and the thermosetting resin sheet supplied before mounting the semiconductor element 4 on the wiring board 1 having a different wiring area of the first connection terminal 2 is supplied with a constant thickness. However, the amount of protrusion of the first sealing resin 5 can be controlled by adjusting the volume with the dummy wiring 6.

次に本実施形態の半導体装置の製造方法を工程図４を参照して説明する。図４は実施形態の半導体装置の製造方法を示す工程ごとの断面図である。(ａ)はダミー配線６を形成した配線基板１を準備する工程である。(ｂ)は配線基板１の配線層面にある第１接続端子２を覆うサイズの絶縁性で熱硬化性の樹脂シート１２を貼り付ける工程である。(ｃ)は第１半導体素子４に形成したバンプ９と配線基板１の第１接続端子２を位置合わせして搭載し、熱と加圧力によって余分な第１封止樹脂５を第２接続端子３に被らない様に第１半導体素子４の外側に押し出して硬化させ、接続を行う工程である。(ｄ)は第２半導体素子８を第１半導体素子４の裏面に搭載する工程である。（ｅ）は第２半導体素子８の電極端子と配線基板１の第２接続端子３をボンディングワイヤー１０でワイヤーボンディング接続を行う工程である。(ｆ)は配線基板１に実装された第１の半導体素子４と第２半導体素子８の全体を覆うように第２の封止樹脂１１でモールドする工程であり、これにより半導体装置の製造が完了する。   Next, the manufacturing method of the semiconductor device according to the present embodiment will be described with reference to FIGS. FIG. 4 is a cross-sectional view for each process showing the manufacturing method of the semiconductor device of the embodiment. (a) is a step of preparing the wiring board 1 on which the dummy wiring 6 is formed. (b) is a step of attaching an insulating and thermosetting resin sheet 12 having a size covering the first connection terminal 2 on the wiring layer surface of the wiring substrate 1. (c) mounts the bump 9 formed on the first semiconductor element 4 and the first connection terminal 2 of the wiring board 1 in alignment, and puts the excess first sealing resin 5 on the second connection terminal by heat and pressure. 3 is a process of extruding to the outside of the first semiconductor element 4 so as not to cover 3 and curing and connecting. (d) is a step of mounting the second semiconductor element 8 on the back surface of the first semiconductor element 4. (E) is a step of performing wire bonding connection between the electrode terminal of the second semiconductor element 8 and the second connection terminal 3 of the wiring board 1 by the bonding wire 10. (f) is a step of molding with the second sealing resin 11 so as to cover the whole of the first semiconductor element 4 and the second semiconductor element 8 mounted on the wiring board 1, thereby making it possible to manufacture the semiconductor device. Complete.

本実施形態の半導体装置の製造方法によれば、品種が変わり配線基板１の第１接続端子２の配線面積が異なった場合に配線基板１に貼り付けられた熱硬化性樹脂シートの厚みを一定化しても第１半導体素子４と配線基板１の間隙に充填されて第１半導体素子４の周辺にはみ出す第１封止樹脂５のはみ出し量を制御することが可能となり、第２接続端子を第１半導体素子４の周辺の近傍に配置することが出来る。これにより半導体装置の小型化が可能となり、また、第２半導体素子８と接続する第２接続端子３への第１封止樹脂５の付着を防止できることから、ワイヤーボンド接続品質の確保も可能となる。   According to the method for manufacturing a semiconductor device of the present embodiment, the thickness of the thermosetting resin sheet attached to the wiring board 1 is constant when the type is changed and the wiring area of the first connection terminal 2 of the wiring board 1 is different. The amount of the first sealing resin 5 that fills the gap between the first semiconductor element 4 and the wiring substrate 1 and protrudes to the periphery of the first semiconductor element 4 can be controlled, and the second connection terminal is connected to the second connection terminal. 1 can be arranged in the vicinity of the periphery of the semiconductor element 4. As a result, the semiconductor device can be reduced in size, and the first sealing resin 5 can be prevented from adhering to the second connection terminals 3 connected to the second semiconductor element 8, so that the wire bond connection quality can be ensured. Become.

なお、この発明において、配線基板の配線層形成面で第1半導体素子の実装領域にある、第1半導体素子の電極と導通のある第１接続端子に接続される配線は回路形成されたものでもよい。   In the present invention, the wiring connected to the first connection terminal electrically connected to the electrode of the first semiconductor element in the mounting region of the first semiconductor element on the wiring layer forming surface of the wiring board may be formed with a circuit. Good.

上記のように、本発明によれば、絶縁性の熱硬化性樹脂シートは、半導体素子と配線基板の間隙の体積を充填できる量以上で一定の厚みのシートを供給し、加熱しながら加圧力により、押圧する工程で余分な樹脂を押し出すが、余分となる樹脂の量を配線基板の配線領域の体積で制御することができる。   As described above, according to the present invention, the insulating thermosetting resin sheet supplies a sheet having a constant thickness in an amount that can fill the gap between the semiconductor element and the wiring board, and applies pressure while heating. Thus, excess resin is extruded in the pressing step, but the amount of excess resin can be controlled by the volume of the wiring region of the wiring board.

すなわち、第1半導体素子と配線基板の間隙にある第1封止樹脂のはみ出し量が、第1半導体素子のサイズが異なっても、第1半導体素子の電極と導通があり回路形成された配線と、第1半導体素子の電極と導通がなく第1の半導体素子の面積に対して一定の比率の面積から第1半導体素子の電極と導通があり回路形成された配線の面積を差し引いた面積のダミー配線を有した配線基板で制御することができ、一定のはみ出し量とすることができる。   That is, the amount of protrusion of the first sealing resin in the gap between the first semiconductor element and the wiring board is electrically connected to the electrode of the first semiconductor element even if the size of the first semiconductor element is different. A dummy having an area obtained by subtracting the area of the wiring formed in the circuit that is electrically connected to the electrode of the first semiconductor element from the area of a constant ratio with respect to the area of the first semiconductor element without conduction to the electrode of the first semiconductor element Control can be performed with a wiring board having wiring, and a certain amount of protrusion can be obtained.

本発明にかかる半導体装置およびその製造方法は、熱硬化性樹脂シートの厚みを変更すること無く第1半導体素子からはみ出す第1封止樹脂量を制御でき、半導体パッケージの小型化が可能となる等の効果があり、フリップチップ方式で接合させる積層型の半導体装置およびその製造方法として有用である。   The semiconductor device and the manufacturing method thereof according to the present invention can control the amount of the first sealing resin that protrudes from the first semiconductor element without changing the thickness of the thermosetting resin sheet, and can reduce the size of the semiconductor package. Therefore, it is useful as a stacked semiconductor device to be bonded by a flip chip method and a manufacturing method thereof.

本発明の一実施形態にかかる半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device concerning one Embodiment of this invention. 本発明の一実施形態にかかる半導体装置の配線基板を示す平面図である。It is a top view which shows the wiring board of the semiconductor device concerning one Embodiment of this invention. 本発明の一実施形態にかかる半導体装置を示し、（ａ）は第1半導体素子の実装前の断面図、（ｂ）は実装後の断面図である。1 shows a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view before mounting a first semiconductor element, and (b) is a cross-sectional view after mounting. 本発明の一実施形態にかかる半導体装置の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the semiconductor device concerning one Embodiment of this invention. 従来の半導体装置の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the conventional semiconductor device. 従来の半導体装置の配線基板を示し、（ａ）は平面図、（ｂ）は断面図である。The wiring board of the conventional semiconductor device is shown, (a) is a top view, (b) is sectional drawing. 別の従来の半導体装置の配線基板を示し、（ａ）は平面図、（ｂ）は断面図である。The wiring board of another conventional semiconductor device is shown, (a) is a top view, (b) is sectional drawing. 従来の半導体装置で第1半導体素子の実装後を示し、（ａ）は平面図、（ｂ）は断面図である。FIG. 4A is a plan view and FIG. 4B is a cross-sectional view illustrating a conventional semiconductor device after the first semiconductor element is mounted. 別の従来の半導体装置で第1半導体素子の実装後を示し、（ａ）は平面図、（ｂ）は断面図である。FIG. 5A shows a state in which the first semiconductor element is mounted in another conventional semiconductor device, where (a) is a plan view and (b) is a cross-sectional view.

符号の説明Explanation of symbols

１．１´・・・配線基板
２．２´・・・第1接続端子
３．３´・・・第2接続端子
４・・・第1半導体素子
５・・・第1封止樹止
６・・・ダミー配線
７・・・第1封止樹脂はみ出し
８・・・第2半導体素子
９・・・バンプ
１０・・・ボンディングワイヤー
１１・・・第２封止樹脂
１２・・・熱硬化性樹脂シート 1.1 '... wiring board 2.2' ... first connection terminal 3.3 '... second connection terminal 4 ... first semiconductor element 5 ... first sealing tree 6 ... Dummy wiring 7 ... First sealing resin protrusion 8 ... Second semiconductor element 9 ... Bump 10 ... Bonding wire 11 ... Second sealing resin 12 ... thermosetting Resin sheet

Claims (5)

実装面に電極を有する第1半導体素子と、この第1半導体素子の実装領域に前記第1半導体素子の電極と導通のある配線および前記第1半導体素子の電極と導通のないダミー配線を有して前記導通のある配線と前記導通のないダミー配線の面積の和が前記第1半導体素子の面積と一定の比率となる配線面積を有した配線基板と、前記配線基板上にフリップチップボンディングされた前記第１半導体素子と前記配線基板との間隙に充填された第1封止樹脂と、前記第１半導体素子の前記配線基板と反対側の面に固着され表面に設けられた電極端子が前記配線基板とワイヤーボンディングで接続された第２半導体素子と、前記第１半導体素子と前記第２半導体素子の全体を覆うようにモールドした第２封止樹脂を備えた半導体装置。   A first semiconductor element having an electrode on a mounting surface; a wiring that is conductive to the electrode of the first semiconductor element; and a dummy wiring that is not conductive to the electrode of the first semiconductor element in the mounting region of the first semiconductor element. A wiring substrate having a wiring area in which a sum of areas of the conductive wiring and the non-conductive dummy wiring is a constant ratio to the area of the first semiconductor element, and flip chip bonding is performed on the wiring substrate. A first sealing resin filled in a gap between the first semiconductor element and the wiring board, and an electrode terminal fixed to the surface of the first semiconductor element opposite to the wiring board and provided on the surface are the wiring A semiconductor device comprising: a second semiconductor element connected to a substrate by wire bonding; and a second sealing resin molded so as to cover the whole of the first semiconductor element and the second semiconductor element. 配線基板の配線層形成面で第1半導体素子の実装領域にある、前記第1半導体素子の電極と導通のある配線が回路形成され、前記第1半導体素子の電極と導通のないダミー配線は、前記第1の半導体素子の面積に対して一定の比率の面積から、前記第1半導体素子の電極と導通がありかつ回路形成された前記配線の面積を差し引いた面積を有する請求項1記載の実施形態の半導体装置。   A wiring that is electrically connected to the electrode of the first semiconductor element in the mounting region of the first semiconductor element on the wiring layer forming surface of the wiring board is formed, and the dummy wiring that is not electrically connected to the electrode of the first semiconductor element is 2. The implementation according to claim 1, wherein an area having a constant ratio with respect to an area of the first semiconductor element is obtained by subtracting an area of the wiring that is electrically connected to the electrode of the first semiconductor element and is formed in a circuit. Form of semiconductor device. 第１半導体素子の電極と配線基板の第１接続端子とがバンプを介して接続されている請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the electrode of the first semiconductor element and the first connection terminal of the wiring board are connected via a bump. 複数個の半導体素子が厚さ方向に多段に重ねて配置された半導体装置の製造方法であって、
下段の第１の半導体素子が実装される範囲に第１接続端子およびダミー配線を有しその外側に第２接続端子を有する配線基板を準備する工程と、前記配線基板の前記第１接続端子および前記ダミー配線上に絶縁性の熱硬化性樹脂シートを貼り付ける工程と、前記第１半導体素子の電極と前記配線基板の前記第1接続端子とを位置合わせし、加熱しながら加圧力により押圧して余分な樹脂を押し出し、前記第１半導体素子の電極と前記配線基板の第１接続端子とをフリップチップボンディングするとともに前記第1半導体素子と前記配線基板の間に介在する前記熱硬化性樹脂シートを前記熱により硬化する工程と、前記第1半導体素子の裏面に上段となる前記第2半導体素子を固着する工程と、前記第２半導体素子の電極と前記配線基板の配線層形成面上において前記第１接続端子よりも外側に配置された第２接続端子とをボンディングワイヤを介してワイヤーボンディング方式により接続する工程と、前記第１半導体素子と前記第２半導体素子の全体を覆うように第２封止樹脂でモールドする工程を含む半導体装置の製造方法。 A method of manufacturing a semiconductor device in which a plurality of semiconductor elements are arranged in multiple stages in the thickness direction,
A step of preparing a wiring board having a first connection terminal and a dummy wiring in a range where the lower first semiconductor element is mounted and having a second connection terminal outside the first connection terminal; and the first connection terminal of the wiring board; The step of attaching an insulating thermosetting resin sheet on the dummy wiring, the electrode of the first semiconductor element and the first connection terminal of the wiring board are aligned, and pressed with pressure while heating. Excessive resin is extruded to flip chip bond the electrode of the first semiconductor element and the first connection terminal of the wiring board, and the thermosetting resin sheet is interposed between the first semiconductor element and the wiring board Curing with heat, fixing the second semiconductor element on the back surface of the first semiconductor element, forming the electrode of the second semiconductor element and the wiring layer of the wiring substrate A step of connecting a second connection terminal disposed outside the first connection terminal on the surface by a wire bonding method via a bonding wire; and covering the entire first semiconductor element and the second semiconductor element. A method for manufacturing a semiconductor device including a step of molding with a second sealing resin. 第１半導体素子の電極と配線基板の第１接続端子とをバンプを介してフリップチップボンディングする請求項４記載の半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 4, wherein the electrode of the first semiconductor element and the first connection terminal of the wiring board are flip-chip bonded via a bump.
JP2003398371A 2003-11-28 2003-11-28 Semiconductor device and its manufacturing method Pending JP2005159192A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008311554A (en) * 2007-06-18 2008-12-25 Alps Electric Co Ltd Semiconductor module and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008311554A (en) * 2007-06-18 2008-12-25 Alps Electric Co Ltd Semiconductor module and method of manufacturing the same

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