KR20080065871A - Multi chip stack package having groove in circuit board and method of fabricating the same - Google Patents

Multi chip stack package having groove in circuit board and method of fabricating the same Download PDF

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Publication number
KR20080065871A
KR20080065871A KR1020070003080A KR20070003080A KR20080065871A KR 20080065871 A KR20080065871 A KR 20080065871A KR 1020070003080 A KR1020070003080 A KR 1020070003080A KR 20070003080 A KR20070003080 A KR 20070003080A KR 20080065871 A KR20080065871 A KR 20080065871A
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South Korea
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semiconductor chip
adhesive layer
groove
disposed
stack package
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KR1020070003080A
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Korean (ko)
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권용재
이동호
강선원
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삼성전자주식회사
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Priority to KR1020070003080A priority Critical patent/KR20080065871A/en
Publication of KR20080065871A publication Critical patent/KR20080065871A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A multi chip stack package including a groove in a wiring substrate is provided to avoid contamination caused by an adhesive layer by easily controlling a region where the adhesive layer is formed. A wiring substrate includes a central region(50b) and an outer region(50a) surrounding the central region wherein a groove(55b) is formed between the central region and the outer region. A first semiconductor chip(10-1) is disposed on the central region. A first adhesive layer(15-1) is extended to the inside of the groove, disposed between the first semiconductor chip and the wiring substrate. A second semiconductor chip is disposed on the first semiconductor chip. A second adhesive layer is disposed between the first semiconductor chip and the second semiconductor chip. The groove can be disposed to surround the central region. The semiconductor chips can include through electrodes(13) electrically connected to the wiring substrate.

Description

배선 기판 내에 홈을 구비하는 멀티 칩 스택 패키지 및 그의 제조 방법{Multi chip stack package having groove in circuit board and method of fabricating the same}Multi chip stack package having grooves in wiring board and method of manufacturing the same {Multi chip stack package having groove in circuit board and method of fabricating the same}

도 1a 및 도 1b는 본 발명의 일 실시예에 따른 멀티 칩 스택 패키지의 제조방법을 순차적으로 나타낸 평면도들이다.1A and 1B are plan views sequentially illustrating a method of manufacturing a multichip stack package according to an exemplary embodiment of the present invention.

도 2a 내지 도 2f는 본 발명의 일 실시예에 따른 멀티 칩 스택 패키지의 제조방법을 순차적으로 나타낸 단면도들이다.2A through 2F are cross-sectional views sequentially illustrating a method of manufacturing a multichip stack package according to an exemplary embodiment of the present invention.

도 3은 본 발명의 다른 실시예에 따른 멀티 칩 스택 패키지를 나타낸 단면도다. 3 is a cross-sectional view showing a multi-chip stack package according to another embodiment of the present invention.

도 4는 본 발명의 또 다른 실시예에 따른 멀티 칩 스택 패키지를 나타낸 단면도다. 4 is a cross-sectional view illustrating a multi-chip stack package according to another embodiment of the present invention.

본 발명은 반도체 칩 패키지에 관한 것으로, 더욱 자세하게는 다수 개의 반도체 칩을 구비하는 멀티 칩 스택 패키지에 관한 것이다.The present invention relates to a semiconductor chip package, and more particularly to a multi-chip stack package having a plurality of semiconductor chips.

최근 전자기기가 고기능화, 경박단소화됨에 따라, 반도체 칩 패키 지(semiconductor chip package)도 다기능화, 소형화되고 있다. 반도체 칩 패키지를 소형화하기 위해 플립 칩 패키지(flip chip package)가 제안되고 있고, 반도체 칩 패키지를 다기능화, 고용량화하기 위해 칩 스택 패키지(chip stack package) 또는 스택 패키지가 제안되고 있다.Recently, as electronic devices have become highly functional and light and small, semiconductor chip packages have become more versatile and smaller in size. In order to miniaturize a semiconductor chip package, a flip chip package has been proposed, and a chip stack package or a stack package has been proposed to make the semiconductor chip package multifunctional and high in capacity.

상기 스택 패키지는 복수 개의 반도체 패키지들을 적층하는 것으로서 신뢰성 측면에서는 우수한 장점이 있으나, 각각의 패키지 두께만큼 패키지 전체의 두께가 증가하기 때문에 경박화가 어려운 단점이 있다. 반면, 칩 스택 패키지는 하나의 패키지 내에 복수 개의 반도체 칩들을 적층한 것으로서 스택 패키지에 비하여 두께가 감소되는 장점이 있다.The stack package stacks a plurality of semiconductor packages and has excellent advantages in terms of reliability. However, the stack package has a disadvantage that it is difficult to reduce the thickness because the entire package thickness increases by the thickness of each package. On the other hand, the chip stack package is a stack of a plurality of semiconductor chips in one package has the advantage that the thickness is reduced compared to the stack package.

상기 칩 스택 패키지를 제조하는 방법은 인쇄 회로 기판 상에 반도체 칩을 접착제를 사용하여 본딩하는 단계를 구비한다. 이러한 과정에서 상기 접착제는 상기 인쇄 회로 기판 상과 상기 반도체 칩 사이를 충진할 뿐 아니라, 상기 반도체 칩과 상기 인쇄 회로 기판 사이의 공간으로부터 밀려나와(squeezed out) 상기 반도체 칩의 측벽을 타고 올라가 상기 반도체 칩의 상부면에 이르기까지 연장될 수 있다. 이 경우, 상기 반도체 칩을 상기 인쇄 회로 기판 상에 접착시키는 본딩 장비를 오염시켜, 후속 반도체 칩 본딩 공정의 진행을 어렵게 할 수 있다.The method of manufacturing the chip stack package includes bonding a semiconductor chip with an adhesive on a printed circuit board. In this process, the adhesive not only fills the space between the printed circuit board and the semiconductor chip, but also squeezes out of the space between the semiconductor chip and the printed circuit board to climb up the sidewall of the semiconductor chip. It may extend up to the top surface of the chip. In this case, the bonding equipment for adhering the semiconductor chip onto the printed circuit board may be contaminated to make it difficult to proceed with the subsequent semiconductor chip bonding process.

본 발명이 이루고자 하는 기술적 과제는 접착제의 퍼짐성이 조절된 멀티 칩 스택 패키지의 및 그의 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a multichip stack package in which adhesive spreadability is controlled.

상기 기술적 과제를 이루기 위하여 본 발명의 일 실시예는 멀티 칩 스택 패키지를 제공한다. 상기 패키지는 중앙 영역과 그를 둘러싸는 외곽 영역을 갖는 배선 기판을 구비한다. 상기 중앙 영역과 상기 외곽 영역 사이에 홈(groove)이 배치된다. 상기 중앙 영역 상에 제1 반도체 칩이 배치된다. 상기 제1 반도체 칩과 상기 배선 기판 사이에 제1 접착제층이 배치된다. 상기 제1 접착제층은 상기 홈 내로 연장된다. 상기 제1 반도체 칩 상에 제2 반도체 칩이 배치된다. 상기 제1 반도체 칩과 상기 제2 반도체 칩 사이에 제2 접착체층이 배치된다.In order to achieve the above technical problem, an embodiment of the present invention provides a multi-chip stack package. The package includes a wiring board having a central region and an outer region surrounding the central region. Grooves are disposed between the central area and the outer area. The first semiconductor chip is disposed on the central region. A first adhesive layer is disposed between the first semiconductor chip and the wiring board. The first adhesive layer extends into the groove. The second semiconductor chip is disposed on the first semiconductor chip. A second adhesive layer is disposed between the first semiconductor chip and the second semiconductor chip.

상기 기술적 과제를 이루기 위하여 본 발명의 일 실시예는 멀티 칩 스택 패키지의 제조방법을 제공한다. 먼저, 중앙 영역과 그를 둘러싸는 외곽 영역을 구비하는 배선 기판을 제공한다. 상기 중앙 영역과 상기 외곽 영역 사이에 홈(groove)을 형성한다. 상기 중앙 영역 상에 제1 접착제층이 도포된 제1 반도체 칩을 배치한다. 상기 제1 반도체 칩 상에 압력을 가하여 상기 제1 반도체 칩을 상기 배선 기판 상에 부착시킴과 동시에 상기 제1 접착제층은 밀려나와 상기 홈 내로 흘러들어간다. 상기 제1 반도체 칩 상에 제2 접착제층이 도포된 제2 반도체 칩을 배치한다. 상기 제2 반도체 칩 상에 압력을 가하여 상기 제2 반도체 칩을 상기 제1 반도체 칩 상에 부착시킨다.In order to achieve the above technical problem, an embodiment of the present invention provides a method of manufacturing a multichip stack package. First, a wiring board having a central area and an outer area surrounding the area is provided. Grooves are formed between the central area and the outer area. A first semiconductor chip coated with a first adhesive layer is disposed on the central region. Pressure is applied to the first semiconductor chip to attach the first semiconductor chip to the wiring board, and at the same time, the first adhesive layer is pushed out and flows into the groove. A second semiconductor chip on which the second adhesive layer is applied is disposed on the first semiconductor chip. Pressure is applied on the second semiconductor chip to attach the second semiconductor chip on the first semiconductor chip.

이하, 첨부한 도면들을 참조하여 본 발명의 바람직한 실시예들을 상세히 설명한다. 그러나, 본 발명은 여기서 설명되어지는 실시예들에 한정되지 않고 다른 형태로 구체화될 수도 있다. 오히려, 여기서 소개되는 실시예들은 개시된 내용이 철저하고 완전해질 수 있도록 그리고 당업자에게 본 발명의 사상이 충분히 전달될 수 있도록 하기 위해 제공되어지는 것이다. 명세서 전체에 걸쳐서 동일한 참조번호들은 동일한 구성요소들을 나타낸다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. Like numbers refer to like elements throughout.

도 1a 및 도 1b는 본 발명의 일 실시예에 따른 멀티 칩 스택 패키지의 제조방법을 나타낸 평면도들이다. 도 2a 내지 도 2f는 본 발명의 일 실시예에 따른 멀티 칩 스택 패키지의 제조방법을 나타낸 단면도들로서, 도 2a는 도 1a의 절단선 Ⅰ-Ⅰ를 따라 취해진 단면도이며, 도 2c는 도 1b의 절단선 Ⅲ-Ⅲ를 따라 취해진 단면도이다.1A and 1B are plan views illustrating a method of manufacturing a multichip stack package according to an exemplary embodiment of the present invention. 2A through 2F are cross-sectional views illustrating a method of manufacturing a multi-chip stack package according to an exemplary embodiment of the present invention. FIG. 2A is a cross-sectional view taken along the cutting line I-I of FIG. 1A, and FIG. It is a sectional view taken along the line III-III.

도 1a 및 도 2a를 참조하면, 중앙 영역(50b)과 그를 둘러싸는 외곽 영역(50a)을 구비하는 배선 기판(50)을 제공한다. 상기 중앙 영역(50b)과 상기 외곽 영역(50a) 사이에 홈(groove; 55b)이 형성된다. 본 실시예에 있어서, 상기 중앙 영역(50b)은 후술하는 반도체 칩이 배치되는 영역을 의미한다.1A and 2A, a wiring board 50 having a central region 50b and an outer region 50a surrounding the same is provided. Grooves 55b are formed between the central region 50b and the outer region 50a. In the present embodiment, the central region 50b means a region where semiconductor chips, which will be described later, are disposed.

구체적으로, 상기 배선 기판(50)은 베이스 기판(50')을 구비한다. 상기 베이스 기판(50') 상에 단자 패드들(51a, 51b)이 배치된다. 상기 단자 패드들(51a, 51b) 중 일부는 상기 중앙 영역(50b) 내에 형성되고, 다른 일부는 상기 외곽 영역(50a) 내에 형성된다. 상기 단자 패드들(51a, 51b) 상에 솔더 레지스트층(55)을 형성한다. 상기 솔더 레지스트층(55) 내에 상기 단자 패드들(51a, 51b)을 노출시키는 개구부들(55a, 55c) 및 상기 홈들(55b)을 형성한다. 상기 홈들(55b) 내에는 상기 베이스 기판(50')이 노출될 수 있다. 이와 같이, 상기 개구부들(55a, 55c)을 형성함과 동시에 상기 홈들(55b)을 형성함으로써, 상기 홈들(55b)을 형성하기 위한 별도의 공정이 추가되지 않는다. 상기 홈들(55b)은 그의 입구면적이 그의 바닥면적에 비해 넓을 수 있다.Specifically, the wiring board 50 includes a base board 50 '. Terminal pads 51a and 51b are disposed on the base substrate 50 '. Some of the terminal pads 51a and 51b are formed in the central area 50b and others are formed in the outer area 50a. The solder resist layer 55 is formed on the terminal pads 51a and 51b. Openings 55a and 55c and the grooves 55b exposing the terminal pads 51a and 51b are formed in the solder resist layer 55. The base substrate 50 ′ may be exposed in the grooves 55b. As such, by forming the openings 55b and the grooves 55b at the same time, a separate process for forming the grooves 55b is not added. The grooves 55b may have a wider entrance area than that of their bottom area.

상기 배선 기판(50)은 전기 회로가 형성된 회로 기판이다. 구체적으로, 상기 배선 기판(50)은 인쇄회로기판(PCB) 또는 연성인쇄회로필름(FPC)일 수 있다. 상기 단자 패드(51a, 51b)는 상기 배선 기판(50) 상에 형성된 전기 회로로 전기 신호를 입력 또는 출력하기 위한 단자로서, 도전성 물질로 이루어지며, 예를 들어, 금, 은, 구리, 니켈, 알루미늄, 주석, 납, 백금, 비스무스, 인듐 등의 금속으로 이루어질 수 있다.The wiring board 50 is a circuit board on which an electric circuit is formed. Specifically, the wiring board 50 may be a printed circuit board (PCB) or a flexible printed circuit film (FPC). The terminal pads 51a and 51b are terminals for inputting or outputting an electrical signal to an electric circuit formed on the wiring board 50 and are made of a conductive material. For example, gold, silver, copper, nickel, It may be made of metals such as aluminum, tin, lead, platinum, bismuth and indium.

도 1b 및 도 2b를 참조하면, 상기 배선 기판(50)의 중앙 영역(50b) 상에 제1 반도체 칩(10_1)을 배치시킨다. 상기 제1 반도체 칩(10_1)은 상기 배선 기판(50)을 바라보는 하부면과 그 반대면인 상부면을 구비한다. 또한, 상기 제1 반도체 칩(10_1)은 관통전극들(13)을 구비한다. 상기 관통전극들(13)은 상기 제1 반도체 칩(10_1) 내에 구비된 전기소자에 데이터를 입력 또는 출력하는 단자의 역할을 하며, 상기 반도체 칩(10_1)을 관통하여, 상기 상부면과 상기 하부면 내에 노출된다. 상기 하부면 내에 노출된 상기 관통전극들(13) 상에 도전성 범프들(17)이 배치될 수 있다.1B and 2B, the first semiconductor chip 10_1 is disposed on the central region 50b of the wiring board 50. The first semiconductor chip 10_1 has a lower surface facing the wiring board 50 and an upper surface opposite thereto. In addition, the first semiconductor chip 10_1 includes through electrodes 13. The through electrodes 13 serve as terminals for inputting or outputting data to an electric element provided in the first semiconductor chip 10_1, penetrating through the semiconductor chip 10_1, and the upper and lower surfaces thereof. Exposed in plane. Conductive bumps 17 may be disposed on the through electrodes 13 exposed in the lower surface.

상기 제1 반도체 칩(10_1)의 하부면 상에 제1 접착체층(15_1)을 도포한다. 이 때, 상기 제1 접착제층(15_1)은 상기 도전성 범프들(17)을 매몰시키지 않을 정도의 두께로 도포한다. 상기 제1 접착제층(15_1)은 NCF(Non-Conductive Film), ACF(Anisotropic Conductive Film), DAF(Die Bonding Tape) 또는 NCP(Non- Conductive Paste)일 수 있다.The first adhesive layer 15_1 is coated on the lower surface of the first semiconductor chip 10_1. In this case, the first adhesive layer 15_1 is coated to a thickness such that the conductive bumps 17 are not buried. The first adhesive layer 15_1 may be a non-conductive film (NCF), an anisotropic conductive film (ACF), a die bonding tape (DAF), or a non-conductive paste (NCP).

도 2c를 참조하면, 상기 반도체 칩(10_1)의 상부면 상에 압력을 가하여 상기 제1 반도체 칩(10_1)을 상기 배선 기판(50) 상에 부착시킨다. 이 때, 상기 도전성 범프들(17)은 상기 중앙 영역(50b) 내에 형성된 상기 단자 패드들(51a) 상에 접촉한다. 또한, 상기 제1 접착제층(15_1)은 상기 반도체 칩(10_1)과 상기 배선 기판(50) 사이의 갭을 필링한 후, 상기 반도체 칩(10_1)과 상기 배선 기판(50) 사이의 영역으로부터 밀려나온다. 상기 밀려나온 제1 접착제층(15_1)은 상기 외곽 영역(50a) 방향으로 진행하다가 상기 홈(55b)을 만나 상기 홈(55b) 내부로 흘러들어간다. 따라서, 상기 홈(55b)에 의해 제1 접착제층(15_1)의 외측으로의 진행이 멈추게 된다. 다시 말해서, 상기 홈(55b)을 형성함으로써, 상기 제1 접착제층(15_1)가 형성되는 영역을 용이하게 제어할 수 있다. 이로써, 상기 제1 접착제층(15_1)이 상기 제1 반도체 칩(10_1)의 측벽을 타고 올라가는 현상을 막을 수 있어, 본딩 장비의 오염을 막을 수 있다. 이와 더불어서, 상기 외곽 영역(50a) 내에 형성된 상기 단자 패드(51b)를 오염시키지 않을 수 있다.Referring to FIG. 2C, pressure is applied to an upper surface of the semiconductor chip 10_1 to attach the first semiconductor chip 10_1 to the wiring board 50. In this case, the conductive bumps 17 contact the terminal pads 51a formed in the central region 50b. In addition, the first adhesive layer 15_1 is filled from the gap between the semiconductor chip 10_1 and the wiring board 50 after filling the gap between the semiconductor chip 10_1 and the wiring board 50. Comes out. The extruded first adhesive layer 15_1 proceeds toward the outer region 50a and meets the groove 55b and flows into the groove 55b. Accordingly, the groove 55b stops the progress of the first adhesive layer 15_1. In other words, by forming the groove 55b, the region where the first adhesive layer 15_1 is formed can be easily controlled. As a result, the first adhesive layer 15_1 may be prevented from climbing up the sidewalls of the first semiconductor chip 10_1, thereby preventing contamination of the bonding equipment. In addition, the terminal pad 51b formed in the outer region 50a may not be contaminated.

한편, 상기 제1 반도체 칩(10_1)을 상기 배선 기판(50) 상에 부착시키는 과정에서 열이 가해질 수 있다. 이 때, 상기 홈(55b)은 열에 의한 상기 솔더 레지스트층(55)의 전단 변형(shear strain)의 발생을 최소화시키는 변형 버퍼(strain buffer)의 역할을 수행할 수 있어, 패키지의 신뢰성을 향상시킬 수 있다.Meanwhile, heat may be applied in the process of attaching the first semiconductor chip 10_1 on the wiring board 50. In this case, the groove 55b may serve as a strain buffer to minimize generation of shear strain of the solder resist layer 55 due to heat, thereby improving reliability of the package. Can be.

도 2d를 참조하면, 상기 제1 반도체 칩(10_1) 상에 제2 반도체 칩(10_2)을 배치시킨다. 상기 제2 반도체 칩(10_2) 또한 관통전극들(13)을 구비하며, 상기 제2 반도체 칩(10_2)의 상기 관통전극들(13) 상에도 도전성 범프들(17)이 배치된다.Referring to FIG. 2D, a second semiconductor chip 10_2 is disposed on the first semiconductor chip 10_1. The second semiconductor chip 10_2 also includes through electrodes 13, and conductive bumps 17 are also disposed on the through electrodes 13 of the second semiconductor chip 10_2.

상기 제2 반도체 칩(10_2)의 하부면 상에 제2 접착체층(15_2)을 도포한다. 이 때, 상기 제2 접착제층(15_2)은 상기 도전성 범프들(17)을 매몰시키지 않을 정도의 두께로 도포한다. 상기 제2 접착제층(15_2)은 NCF(Non-Conductive Film), ACF(Anisotropic Conductive Film), DAF(Die Bonding Tape), NCP(Non-Conductive Paste) 또는 스핀 온 폴리머(spin on polymer)일 수 있다. 그러나, 상기 제2 접착제층(15_2)과 상기 제1 접착제층(15_1)의 물성은 서로 다를 수 있다. 구체적으로, 상기 물성은 유리전이온도(Tg), 모듈러스(modulus), 열팽창계수(Coefficient of Thermal Expansion, CTE), 푸아송의 비(poisson's ratio) 또는 유동도일 수 있다. 일 예로서, 상기 제1 접착제층(15_1)의 유동도는 상기 제2 접착제층(15_2)의 유동도보다 클 수 있다. 왜냐하면, 상기 제1 접착제층(15_1)은 물성 차이가 큰 반도체 칩(10_1)과 상기 배선 기판(50) 사이의 응력조절 및 접착력 향상을 위해 유동도가 큰 것이 바람직하고, 상기 제2 접착제층(15_2)의 경우 물성 차이가 크지 않은 반도체 칩들(10_1, 10_2) 사이에 배치되기 때문에 상기 제1 접착제층(15_1)에 비해 유동도가 낮아도 별 무리가 없기 때문이다.The second adhesive layer 15_2 is coated on the lower surface of the second semiconductor chip 10_2. At this time, the second adhesive layer 15_2 is applied to a thickness such that the conductive bumps 17 are not buried. The second adhesive layer 15_2 may be a non-conductive film (NCF), an anisotropic conductive film (ACF), a die bonding tape (DAF), a non-conductive paste (NCP), or a spin on polymer (NCP). . However, physical properties of the second adhesive layer 15_2 and the first adhesive layer 15_1 may be different from each other. Specifically, the physical properties may be glass transition temperature (Tg), modulus, coefficient of thermal expansion (CTE), poisson's ratio or fluidity. As an example, the flow rate of the first adhesive layer 15_1 may be greater than the flow rate of the second adhesive layer 15_2. This is because the first adhesive layer 15_1 has a high fluidity to improve stress control and adhesion between the semiconductor chip 10_1 having a large difference in physical properties and the wiring board 50, and the second adhesive layer ( Since 15_2 is disposed between the semiconductor chips 10_1 and 10_2 having a small difference in physical properties, there is no problem even if the fluidity is lower than that of the first adhesive layer 15_1.

도 2e를 참조하면, 상기 제2 반도체 칩(10_2)의 상부면 상에 압력을 가하여 상기 제2 반도체 칩(10_2)을 상기 제1 반도체 칩(10_1) 상에 부착시킨다. 이 때, 상기 제2 반도체 칩(10_2)의 도전성 범프들(17)은 상기 제1 반도체 칩(10_1)의 상부면 내에 노출된 관통전극(13) 상에 접촉한다. 또한, 상기 제2 접착제층(15_2)은 상기 제2 반도체 칩(10_2)과 상기 제1 반도체 칩(10_1) 사이의 갭을 필링한다. 만약, 상기 제2 접착제층(15_2)이 상기 제1 접착제층(15_1)과 유동도가 유사할 경우, 상기 제2 접착제층(15_2)은 상기 제2 반도체 칩(10_2)과 상기 제1 반도체 칩(10_1) 사이의 영역으로부터 밀려나온다. 상기 밀려나온 제2 접착제층(15_2)은 상기 홈(55b) 내부로 흘러들어갈 수 있다. 따라서, 상기 홈(55b)에 의해 제2 접착제층(15_2)의 외측으로의 진행 또한 정지시킬 수 있다.Referring to FIG. 2E, pressure is applied to an upper surface of the second semiconductor chip 10_2 to attach the second semiconductor chip 10_2 on the first semiconductor chip 10_1. In this case, the conductive bumps 17 of the second semiconductor chip 10_2 are in contact with the through electrode 13 exposed in the upper surface of the first semiconductor chip 10_1. In addition, the second adhesive layer 15_2 fills the gap between the second semiconductor chip 10_2 and the first semiconductor chip 10_1. If the second adhesive layer 15_2 has a fluidity similar to that of the first adhesive layer 15_1, the second adhesive layer 15_2 may include the second semiconductor chip 10_2 and the first semiconductor chip. It is pushed out from the area between 10_1. The extruded second adhesive layer 15_2 may flow into the groove 55b. Therefore, the groove 55b can also stop the progress of the second adhesive layer 15_2 to the outside.

도 2f를 참조하면, 상기 제2 반도체 칩(10_2) 상에 제3 내지 제8 접착제층들(15_3, 15_4, 15_5, 15_6, 15_7, 15_8)을 사용하여 제3 내지 제8 반도체 칩들(10_3, 10_4, 10_5, 10_6, 10_7, 10_8)을 각각 부착시킨다. 상기 제3 내지 제8 반도체 칩들(10_3, 10_4, 10_5, 10_6, 10_7, 10_8)을 하부 반도체 칩들 상에 각각 부착시키는 방법은 상기 제2 반도체 칩(10_2)을 상기 제1 반도체 칩(10_1) 상에 부착시키는 방법과 유사하므로, 그에 대한 설명을 생략하기로 한다. 이 때, 제3 내지 제8 접착제층들(15_3, 15_4, 15_5, 15_6, 15_7, 15_8)은 상기 제2 접착제층(15_2)과 물성이 거의 유사할 수 있다.Referring to FIG. 2F, third to eighth semiconductor chips 10_3 may be formed on the second semiconductor chip 10_2 using third to eighth adhesive layers 15_3, 15_4, 15_5, 15_6, 15_7 and 15_8. 10_4, 10_5, 10_6, 10_7, 10_8), respectively. The method of attaching the third to eighth semiconductor chips 10_3, 10_4, 10_5, 10_6, 10_7, and 10_8 to the lower semiconductor chips respectively may include attaching the second semiconductor chip 10_2 to the first semiconductor chip 10_1. Since it is similar to the method of attaching to the description thereof will be omitted. In this case, the third to eighth adhesive layers 15_3, 15_4, 15_5, 15_6, 15_7, and 15_8 may have substantially the same physical properties as the second adhesive layer 15_2.

상기 반도체 칩들(10_1, 10_2, 10_3, 10_4, 10_5, 10_6, 10_7, 10_8)은 기억 소자들일 수 있다. 구체적으로, 메모리 낸드 플래쉬(NAND Flash) 반도체 칩들일 수 있다. 그러나, 이에 한정되지 않고 상기 반도체 칩들(10_1, 10_2, 10_3, 10_4, 10_5, 10_6, 10_7, 10_8) 각각은 같은 종류 또는 서로 다른 종류의 반도체 칩들일 수 있다. 또한, 본 실시예에서는 8개의 반도체 칩들이 적층되는 스택 칩 반도체 패키지를 예로 들어 설명하였으나, 상기 반도체 칩들의 개수는 이에 한정되지 않는 다.The semiconductor chips 10_1, 10_2, 10_3, 10_4, 10_5, 10_6, 10_7, and 10_8 may be memory devices. In more detail, they may be memory NAND flash semiconductor chips. However, the present invention is not limited thereto, and each of the semiconductor chips 10_1, 10_2, 10_3, 10_4, 10_5, 10_6, 10_7, and 10_8 may be the same kind or different kinds of semiconductor chips. In addition, in the present embodiment, a stack chip semiconductor package in which eight semiconductor chips are stacked is described as an example, but the number of the semiconductor chips is not limited thereto.

상기 반도체 칩들(10_1, 10_2, 10_3, 10_4, 10_5, 10_6, 10_7, 10_8) 중 최상부에 위치한 반도체 칩(10_8) 상에 제9 접착제층(15_9)을 사용하여 제어용 반도체 칩(20)을 부착한다. 상기 제어용 반도체 칩(20)의 단자는 와이어(W)를 통해 상기 외곽 영역(50a) 내에 형성된 상기 단자 패드(51b)에 전기적으로 연결된다. 이 때, 상술한 바와 같이 상기 외곽 영역(50a) 내에 형성된 상기 단자 패드(51b)는 상기 제1 접착제층(15_1)에 의해 오염되지 않을 수 있어, 상기 제어용 반도체 칩(20)과 상기 단자 패드(51b) 사이의 전기적 접속 신뢰성을 향상시킬 수 있다.The control semiconductor chip 20 is attached using a ninth adhesive layer 15_9 on the semiconductor chip 10_8 positioned at the top of the semiconductor chips 10_1, 10_2, 10_3, 10_4, 10_5, 10_6, 10_7, and 10_8. . The terminal of the control semiconductor chip 20 is electrically connected to the terminal pad 51b formed in the outer region 50a through a wire (W). At this time, as described above, the terminal pad 51b formed in the outer region 50a may not be contaminated by the first adhesive layer 15_1, so that the control semiconductor chip 20 and the terminal pad ( The electrical connection reliability between 51b) can be improved.

이어서, 적어도 상기 반도체 칩들(10_1, 10_2, 10_3, 10_4, 10_5, 10_6, 10_7, 10_8, 20)의 측면들 및 상부면을 감싸는 봉지재(70)가 도포된다.Subsequently, an encapsulant 70 covering at least the side surfaces and the upper surface of the semiconductor chips 10_1, 10_2, 10_3, 10_4, 10_5, 10_6, 10_7, 10_8, and 20 is coated.

도 3은 본 발명의 다른 실시예에 따른 멀티 칩 스택 패키지를 나타낸 단면도다. 본 실시예에 따른 멀티 칩 스택 패키지는 후술하는 것을 제외하고는 도 2a 내지 도 2f를 참조하여 설명한 멀티 칩 스택 패키지와 유사하다.3 is a cross-sectional view showing a multi-chip stack package according to another embodiment of the present invention. The multichip stack package according to the present embodiment is similar to the multichip stack package described with reference to FIGS. 2A through 2F except as described below.

도 3를 참조하면, 배선 기판(50)과 제1 반도체 칩(10_1) 사이에 배치된 제1 접착제층(15_1)에 비해 제1 반도체 칩(10_1)과 제2 반도체 칩(10_2) 사이에 배치된 제2 접착제층(15_2)의 유동도는 낮다. 따라서, 상기 제2 접착제층(15_2)는 제1 반도체 칩(10_1)과 제2 반도체 칩(10_2) 사이를 충진할 뿐, 제1 반도체 칩(10_1)과 제2 반도체 칩(10_2) 사이의 영역으로부터 밀려나오지 않을 수 있다. 상기 제2 반도체 칩(10_2) 상에 제3 내지 제8 반도체 칩들(10_3, 10_4, 10_5, 10_6, 10_7, 10_8)을 차례로 부착시키는 제3 내지 제8 접착제층들(15_3, 15_4, 15_5, 15_6, 15_7, 15_8) 또한 상기 제2 접착제층(15_2)과 유사한 유동도를 가져 반도체 칩들 사이의 영역만 충진할 뿐 그로부터 밀려나오지 않을 수 있다.Referring to FIG. 3, the first semiconductor chip 10_1 and the second semiconductor chip 10_2 may be disposed in comparison with the first adhesive layer 15_1 disposed between the wiring board 50 and the first semiconductor chip 10_1. The flow rate of the prepared second adhesive layer 15_2 is low. Therefore, the second adhesive layer 15_2 only fills between the first semiconductor chip 10_1 and the second semiconductor chip 10_2, and a region between the first semiconductor chip 10_1 and the second semiconductor chip 10_2. May not be pushed out of it. Third to eighth adhesive layers 15_3, 15_4, 15_5, and 15_6 which sequentially attach third to eighth semiconductor chips 10_3, 10_4, 10_5, 10_6, 10_7, and 10_8 to the second semiconductor chip 10_2. , 15_7 and 15_8 may also have similar flow rates as the second adhesive layer 15_2 to fill only the regions between the semiconductor chips and may not be pushed out therefrom.

도 4는 본 발명의 또 다른 실시예에 따른 멀티 칩 스택 패키지를 나타낸 단면도다. 본 실시예에 따른 멀티 칩 스택 패키지는 후술하는 것을 제외하고는 도 2a 내지 도 2f를 참조하여 설명한 멀티 칩 스택 패키지와 유사하다.4 is a cross-sectional view illustrating a multi-chip stack package according to another embodiment of the present invention. The multichip stack package according to the present embodiment is similar to the multichip stack package described with reference to FIGS. 2A through 2F except as described below.

도 4를 참조하면, 반도체 칩들(10_1, 10_2, 10_3, 10_4, 10_5, 10_6, 10_7, 10_8) 중 최상부에 위치한 반도체 칩(10_8) 상에 제어용 반도체 칩(20)이 배치된다. 이 때, 상기 제어용 반도체 칩(20)은 그의 하부에 전도성 범프들(27)을 구비하며, 상기 전도성 범프들(27)은 상기 최상부에 반도체 칩(10_8)의 더미 관통전극들(미도시)에 전기적으로 접속할 수 있다.Referring to FIG. 4, the control semiconductor chip 20 is disposed on the semiconductor chip 10_8 positioned at the top of the semiconductor chips 10_1, 10_2, 10_3, 10_4, 10_5, 10_6, 10_7, and 10_8. In this case, the control semiconductor chip 20 includes conductive bumps 27 at a lower portion thereof, and the conductive bumps 27 are disposed on the dummy through electrodes (not shown) of the semiconductor chip 10_8 at the top thereof. It can be electrically connected.

상술한 바와 같이 본 발명에 따르면, 배선 기판 내에 홈을 형성하여 접착제층이 형성되는 영역을 용이하게 제어할 수 있다. 그 결과, 접착제층에 의한 오염을 방지할 수 있다.As described above, according to the present invention, it is possible to easily control the region in which the adhesive layer is formed by forming a groove in the wiring board. As a result, contamination by the adhesive layer can be prevented.

상기에서는 본 발명의 바람직한 실시예를 참조하여 설명하였지만, 해당 기술 분야의 숙련된 당업자는 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (8)

중앙 영역과 그를 둘러싸는 외곽 영역을 구비하고, 상기 중앙 영역과 상기 외곽 영역 사이에 홈(groove)을 구비하는 배선 기판;A wiring board having a center region and an outer region surrounding the wiring region, the wiring board having a groove between the center region and the outer region; 상기 중앙 영역 상에 배치된 제1 반도체 칩;A first semiconductor chip disposed on the central region; 상기 제1 반도체 칩과 상기 배선 기판 사이에 배치되고 상기 홈 내로 연장된 제1 접착제층;A first adhesive layer disposed between the first semiconductor chip and the wiring substrate and extending into the groove; 상기 제1 반도체 칩 상에 배치된 제2 반도체 칩; 및A second semiconductor chip disposed on the first semiconductor chip; And 상기 제1 반도체 칩과 상기 제2 반도체 칩 사이에 배치된 제2 접착체층을 포함하는 것을 특징으로 하는 멀티 칩 스택 패키지.And a second adhesive layer disposed between the first semiconductor chip and the second semiconductor chip. 제1 항에 있어서,According to claim 1, 상기 홈은 상기 중앙 영역을 둘러싸도록 배치되는 것을 특징으로 하는 멀티 칩 스택 패키지.And the groove is disposed to surround the central area. 제1 항에 있어서,According to claim 1, 상기 홈의 입구면적은 상기 홈의 바닥면적에 비해 넓은 것을 특징으로 하는 멀티 칩 스택 패키지.The inlet area of the groove is larger than the bottom area of the groove multi chip stack package. 제1 항에 있어서,According to claim 1, 상기 반도체 칩들은 상기 배선 기판과 전기적으로 연결된 관통전극들을 구비하는 것을 특징으로 하는 멀티 칩 스택 패키지.And the semiconductor chips include through electrodes electrically connected to the wiring board. 제1 항에 있어서,According to claim 1, 상기 제2 접착제층과 상기 제1 접착제층은 물성이 서로 다른 것을 특징으로 하는 멀티 칩 스택 패키지.The second adhesive layer and the first adhesive layer is a multi-chip stack package, characterized in that the physical properties are different. 제5 항에 있어서,The method of claim 5, 상기 제1 접착제층은 상기 제2 접착제층에 비해 유동도가 큰 것을 특징으로 하는 멀티 칩 스택 패키지.The first adhesive layer is a multi-chip stack package, characterized in that the fluidity is greater than the second adhesive layer. 제1 항에 있어서,According to claim 1, 상기 제2 반도체 칩 상에 배치된 제어용 반도체 칩을 더 포함하는 것을 특징으로 하는 멀티 칩 스택 패키지.And a control semiconductor chip disposed on the second semiconductor chip. 중앙 영역과 그를 둘러싸는 외곽 영역을 구비하는 배선 기판을 제공하고,Providing a wiring board having a central region and an outer region surrounding the central region, 상기 중앙 영역과 상기 외곽 영역 사이에 홈(groove)을 형성하고,Grooves are formed between the central area and the outer area, 상기 중앙 영역 상에 제1 접착제층이 도포된 제1 반도체 칩을 배치하고,Disposing a first semiconductor chip coated with a first adhesive layer on the central region; 상기 제1 반도체 칩 상에 압력을 가하여 상기 제1 반도체 칩을 상기 배선 기판 상에 부착시킴과 동시에 상기 제1 접착제층은 밀려나와 상기 홈 내로 흘러들어 가고,Pressure is applied to the first semiconductor chip to attach the first semiconductor chip to the wiring board, and at the same time, the first adhesive layer is pushed out and flows into the groove; 상기 제1 반도체 칩 상에 제2 접착제층이 도포된 제2 반도체 칩을 배치하고,Disposing a second semiconductor chip coated with a second adhesive layer on the first semiconductor chip; 상기 제2 반도체 칩 상에 압력을 가하여 상기 제2 반도체 칩을 상기 제1 반도체 칩 상에 부착시키는 것을 포함하는 것을 특징으로 하는 멀티 칩 스택 패키지의 제조방법.And attaching the second semiconductor chip onto the first semiconductor chip by applying pressure on the second semiconductor chip.
KR1020070003080A 2007-01-10 2007-01-10 Multi chip stack package having groove in circuit board and method of fabricating the same KR20080065871A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101054440B1 (en) * 2009-04-27 2011-08-05 삼성전기주식회사 Electronic device package and manufacturing method thereof
US9466632B2 (en) 2015-01-09 2016-10-11 Samsung Electronics Co., Ltd. Image sensor package and an image sensor module having the same
US9721930B2 (en) 2015-06-30 2017-08-01 Samsung Electronics Co., Ltd. Semiconductor package and method for fabricating the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101054440B1 (en) * 2009-04-27 2011-08-05 삼성전기주식회사 Electronic device package and manufacturing method thereof
US9466632B2 (en) 2015-01-09 2016-10-11 Samsung Electronics Co., Ltd. Image sensor package and an image sensor module having the same
US9721930B2 (en) 2015-06-30 2017-08-01 Samsung Electronics Co., Ltd. Semiconductor package and method for fabricating the same

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