JP2005134240A - Capacitance detector circuit, capacitance detection method, and fingerprint sensor using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitance detecting circuit, its detection method, and a fingerprint sensor, which detect a value ΔCs of a minute change in a capacitance value Cs at an intersection of a column line and a row line intersecting each other with sufficient sensitivity, by reducing the influence of disturbance noises and raising a signal to noise ratio. <P>SOLUTION: This capacitance detecting circuit is a circuit for detecting the capacitance of each intersection between a plurality of column lines and row lines which intersect as a voltage value, and is provided with: a code generating unit for generating a code having orthogonality in time sequence; a column line group selection unit for dividing the plurality of column lines into groups of column lines of a predetermined number of column lines and selecting a group of column lines being an object to be measured; a column line drive unit for driving a plurality of column lines in response to the code for each group of column lines to be selected; a capacitance measuring unit which outputs as a measured voltage a total sum of current values corresponding to the capacitance values of the intersections between row lines and the driven column lines; and a decoding processing unit for performing operation for a sum of products of the measured voltage and the code, for each group of column lines and finding a voltage value corresponding to the capacitance of each intersection. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a capacitance detection circuit and a detection method for detecting a minute capacitance, and a fingerprint sensor using the same.

  Conventionally, as the most promising fingerprint sensor in biometrics (biometric authentication technology), column wiring and row wiring are respectively formed on the surface of two films at predetermined intervals, and this film is interposed via an insulating film or the like. Thus, pressure-sensitive capacitive sensors have been developed that are arranged to face each other at a predetermined interval. In this pressure-sensitive capacitive sensor, when the finger is placed, the film shape changes corresponding to the unevenness of the fingerprint, the distance between the column wiring and the row wiring changes depending on the location, and the fingerprint shape changes between the column wiring and the row wiring. It is detected as the capacity of the intersection. In this pressure-sensitive capacitance sensor, as a conventional technique that can be applied to detect a capacitance less than several hundred fF (femtofarad), there is a detection circuit that converts a capacitance into an electric signal by a switched capacitor circuit. This is a switched capacitor that is driven by a first sensor driving signal and detects a detection target capacitance, and a reference capacitor that is driven by a second sensor driving signal and serves as a detection circuit reference capacitor. The first and second sample and hold units connected to the circuit and operating alternately sample each output signal, and then obtain a detection signal by obtaining a difference between the sampling results.

The detection circuit can stably detect a signal proportional to the capacitance value Cs to be detected and inversely proportional to the feedback capacitance Cf in a common switched capacitor circuit, and the reset switch of the switched capacitor circuit. The influence (feedthrough) in which the charge Qd accumulated in the parasitic capacitance between the gate electrode and the other electrode of the (feedback control switch) leaks to the other electrode is offset. In addition, it is expected that the low-frequency noise included in the offset component of the reference potential of the switched capacitor circuit or the input signal can be removed to some extent by obtaining the difference between the two sampling results (for example, patents). Reference 1).
JP-A-8-145717 (paragraphs 0018-0052, FIGS. 1 to 4)

However, a capacitance detection circuit such as a fingerprint sensor is required to have high sensitivity because the capacitance change is minute. However, it is required for noise transmitted from the human body (including high-frequency noise) and circuit noise. It is necessary to have all tolerances.
Further, in order to detect a capacitance change, there is a demand that there is no influence of crosstalk noise from adjacent lines or the like between column wirings or row wirings.

In response to the above-described request, the charging voltage corresponding to the charge charged in the capacitor at the intersection is detected at the time of rise of the column wiring, and then the capacitance of the intersection at the time of falling of the column wiring. A capacity detection circuit that detects a discharge voltage corresponding to the electric charge discharged from the battery and detects a change in the capacity using the charge voltage and the discharge voltage is also conceivable.
That is, this capacitance detection circuit obtains a difference voltage obtained by subtracting the discharge voltage from the charge voltage, and uses this difference voltage as a voltage corresponding to the capacitance change, thereby causing the influence of the feedthrough of the amplifier circuit that occurs with the same polarity. It is possible to remove the voltage offset due to the above and other offset components generated in other circuits, and to remove noise having a frequency sufficiently lower than the sampling frequency.

When detecting a change in capacitance of each sensor element of a capacitance sensor, a normal detection circuit including the above-described capacitance detection circuit drives only a single column wiring and crosses a plurality of row wirings serving as detection lines. It is the structure which detects the change of the capacitance value Cs of a part (sensor element).
However, as already described, the capacitance change per sensor element (one intersection) is a very small value of about several hundred fF.

For this reason, even if the conventional capacitance detection circuit removes the offset component in the circuit including the amplifier circuit, it is affected by noise originally superimposed on the capacitance sensor.
In other words, the capacitance detection circuit has an accurate capacitance due to the influence of such disturbance noise by superimposing power supply noise or conduction noise transmitted to the capacitance sensor via the human body on the signal of the column wiring and row wiring. There is a drawback that change cannot be detected.

In particular, an inverter fluorescent lamp, which is the mainstream of recent fluorescent lamps, is a noise source having a fundamental frequency of several tens of KHz because a high frequency is generated by a semiconductor to light the fluorescent lamp.
However, in the capacitance detection circuit, the sampling frequency of the capacitance change when obtaining the difference between the charge voltage and the discharge voltage is close to the fundamental frequency of the noise source.

For this reason, in this capacitance detection circuit, even if the difference between the charging voltage and the discharging voltage is obtained, a beat component caused by the frequency difference, that is, when two waves having slightly different frequencies are superimposed, the frequency A “beat (beat frequency)” equal to the difference between the two remains, and the noise component of the disturbance cannot be completely removed.
Therefore, when the user intends to use a fingerprint sensor or the like, it is used in the vicinity of the user's human body having a noise source having a frequency close to the sampling frequency of the capacitance detection circuit, for example, in the vicinity of the inverter fluorescent lamp described above. When the sensor is connected to a device having an inverter circuit used for a backlight of a liquid crystal display element, the disturbance noise caused by the above beat cannot be completely removed, and the capacitance change The S / N ratio of the signal to be detected is lowered, and the user's fingerprint cannot be read accurately.

  The present invention has been made in view of the above circumstances, and its purpose is to improve the S / N ratio by reducing the influence of disturbance noise, and to meet the intersection where column wiring and row wiring intersect ( It is an object of the present invention to provide a capacitance detection circuit, a detection method, and a fingerprint sensor capable of detecting a minute capacitance value Cs of the sensor element) and a capacitance change value ΔCs of the capacitance value Cs with sufficient sensitivity.

The capacitance detection circuit of the present invention is a capacitance detection circuit that detects a change in capacitance at the intersection of a column wiring and a row wiring as a voltage value by intersecting a row wiring with a plurality of column wirings, and is orthogonal in time series. A code generation means for generating a code having a plurality of column wirings, a column wiring group selection means for dividing the plurality of column wirings into column wiring groups made up of a predetermined number of column wirings, and selecting a column wiring group to be measured; For each column wiring group, a current value corresponding to the capacitance of the intersection of the column wiring driving means for driving a plurality of column wirings based on the code, the row wiring, and the plurality of driven column wirings. Capacity measuring means for outputting the sum as a measurement voltage;
For each column wiring group, there is provided a decoding operation means for performing a product-sum operation using the measured voltage and the sign to obtain a voltage value corresponding to the capacity of each intersection.

With this configuration, the capacitance detection circuit of the present invention simultaneously drives a plurality of column wirings intersecting the row wirings by using orthogonal PN codes (pseudo random codes), that is, a plurality of column wirings in units of row wirings. Are simultaneously driven, the capacitance value Cs and the capacitance change value ΔCs to be detected are multiplexed, and increased as the capacitance value N · Cs and the capacitance change value N · ΔCs (N is the number of column wirings driven simultaneously) That is, the number of intersections to be multiplexed), by performing capacitance / voltage conversion to obtain a detection signal, a substantially large capacitance value and capacitance change are measured, and disturbances such as relative beats are relatively measured. By using an M-sequence PN code that reduces noise, improves the S / N ratio, and is excellent in autocorrelation, it is possible to eliminate the influence of crosstalk between column wirings.
In addition, the capacity detection circuit of the present invention uses a PN code identical to the PN code used for multiplexing to perform a multiply-add operation (predetermined operation) on the multiplexed detection signal detected by the decoding operation unit in time series. Is used to decode the multiplexed detection value as the capacitance value Cs and capacitance change value ΔCs of each sensor element corresponding to the row wiring (can be calculated if the capacitance value Cs is obtained), so that one column wiring The detection result can be obtained with the same resolution as when the is driven.

  The capacitance detection circuit of the present invention is also applicable to the configuration in which the capacitance of the intersection portion of the area type capacitance sensor in which a plurality of the row wirings are arranged in a matrix with respect to the plurality of column wirings is detected. By using it for a fingerprint sensor or the like, a highly accurate determination result can be obtained by the above-described effect, and a sensor with excellent operability can be provided.

  The capacitance detection circuit of the present invention may be configured to detect the capacitance of the intersection of a line-type capacitance sensor in which one row wiring is formed corresponding to the plurality of column wirings. The sensor can be applied to a sensor for detecting the presence / absence or roughness of the surface, so that the surface condition can be detected with high accuracy by the above-described effect, and only with one row wiring. Therefore, a small and low-cost sensor can be provided.

The capacitance detection circuit of the present invention is formed by a predetermined number of column wirings adjacent to each other.
For this reason, the capacity detection circuit of the present invention can arbitrarily set the number of column wirings subject to product-sum operation and adjust the processing load, so it corresponds to the computing capacity of the system used. It is possible to perform the process.

In the capacitance detection circuit of the present invention, the column wiring group is formed by column wirings having a predetermined interval.
For this reason, the capacitance detection circuit of the present invention detects the entire area on average in the detection for each column wiring group, so that the fluctuation of the detection value is small compared to the case of measuring for each specific region. Therefore, it is possible to easily set sensitivity in measurement.

In the capacity detection circuit of the present invention, the code generation means generates a PN code having autocorrelation, sequentially shifts the bit arrangement of the PN code, and outputs the code as a PN code having a phase different in time series To do.
That is, the PN code generation means generates a PN code, for example, an M-sequence, with a code having good autocorrelation, and multiplexes the capacity changes at the intersection while shifting the PN code of the M-sequence with good autocorrelation. Since decoding is performed in correspondence with the phase of the same PN code at the time of decoding, it is possible to suppress the occurrence of crosstalk between the column wirings, and it is possible to detect the capacitance change at the intersection with high accuracy.

In the capacity detection circuit of the present invention, the code generation means generates Walsh orthogonal codes having different bit arrangements in time series and outputs the codes as the codes.
As a result, in the capacitance detection circuit of the present invention, the number of times each column wiring is driven is halved with respect to the number of detections, and the influence of crosstalk between column wirings is suppressed. Can be done more accurately.

  Since the fingerprint sensor of the present invention can detect a change in capacitance at the intersection (sensor element) using the capacitance detection circuit, it can collect fingerprints with high accuracy.

  The capacitance detection method of the present invention is a capacitance detection method in which a row wiring intersects a plurality of column wirings, and a capacitance change at the intersection of the column wiring and the row wiring is detected as a voltage value. A code generation process for generating a code having a plurality of column wirings, a column wiring group selection process for dividing the plurality of column wirings into column wiring groups each including a predetermined number of column wirings, and selecting a column wiring group to be measured; A column wiring driving process for driving a plurality of column wirings based on the code, and a current value corresponding to a capacitance at an intersection of the row wiring and the plurality of driven column wirings. A capacity measurement process for outputting the sum as a measurement voltage, and a decoding operation process for performing a product-sum operation for each column wiring group using the measurement voltage and the sign to obtain a voltage value corresponding to the capacitance of each intersection. Have.

  As described above, according to the capacitance detection circuit of the present invention, a capacitance value obtained by adding capacitance changes at a plurality of intersections is detected by multiplexing a PN code and driving a plurality of column wirings at a time. As a result, the influence of disturbance noise superimposed on the row wiring and the like is relatively reduced, the detection sensitivity is improved, and decoding is performed using the PN code used for multiplexing, and the capacitance change value at each intersection Therefore, it is possible to detect the capacitance change value at each intersection with a resolution that is substantially the same as that detected by driving a single column wiring.

  The capacitance detection circuit of the present invention is used in a matrix-shaped capacitance sensor configured by crossing row wirings with respect to a plurality of column wirings, and detects a change in capacitance at an intersection (sensor element) between the column wirings and the row wirings. A capacity detection circuit for generating a code having orthogonality in time series, and dividing the plurality of column wirings forming a matrix into a predetermined number of column wiring groups, A group selection circuit selects a column wiring group to be measured, and a column wiring driving circuit sequentially drives a plurality of column wirings for each column wiring group, and a capacitance detection circuit The sum of current values corresponding to the capacitances of the intersections with the plurality of driven column wirings is output as a measurement voltage, and the decoding operation circuit calculates the product-sum operation for each column wiring group by the measurement voltage and the sign. Do It is an detection value by separating the voltage value corresponding to the capacitance of each intersection portion.

A capacitance detection circuit according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram illustrating a configuration example of the capacitance detection circuit according to the first embodiment.
The code generation unit 1 generates a PN code used to generate a column drive signal that drives each column wiring of the column wiring group 2 of the sensor unit 4. As this PN code, an M-sequence PN code having high autocorrelation is used. In the sensor unit 4, the column wirings of the column wiring group 2 and the row wirings of the row wiring group 3 intersect in a matrix, and each intersection forms a sensor element (sensor element 55 in FIG. 4).
2A is a plan view of the sensor unit 4, and FIG. 2B is a cross-sectional view. As shown in FIG. 2A, for example, each column wiring of the column wiring group 2 and each row wiring of the row wiring group 3 arranged at a pitch of 50 μm intersect each other. As shown in FIG. 2B, a row wiring group 3 composed of a plurality of row wirings is arranged on a substrate 50, an insulating film 51 is laminated on the surface, and only a gap 52 is formed on the surface of the insulating film 51. The film 54 is disposed with a space therebetween, and the column wiring group 2 including a plurality of column wirings is attached to the lower surface of the film 54. A sensor element is formed as a capacitive element having a predetermined capacitance at the intersection of the row wiring of the row wiring group 3 and the column wiring of the column wiring group 2 with the gap 52 and the insulating film 51 interposed therebetween.

When the finger 56 is put on the sensor unit 4 described above, the film 54 and the column wiring of the column wiring group 2 are deformed due to the unevenness of the finger 56 as shown in FIG. The capacitance of the sensor element 55 formed at the intersection between the column wiring group 2 and the row wiring group 3 changes.
FIG. 4 is a conceptual diagram showing a matrix of capacitive elements (sensor elements) between the column wirings and the row wirings of the sensor unit 4. The sensor unit 4 is composed of matrix-like sensor elements 55, 55..., And the column wiring drive unit 5 and the capacitance detection circuit 100 are connected to each other. The column wiring drive unit 5 outputs a drive pulse train to the column wiring group 2 corresponding to the bit arrangement of the PN code, that is, in parallel to the column wiring of the column wiring group 2 of the sensor unit 4, respectively. A predetermined drive pulse (drive signal) is output to A drive pulse pattern in this drive pulse train (a pattern that does not drive) is generated based on the PN code, and drives a plurality of column wires in the column wire group 2 in accordance with the bit string data of the PN code ( The capacitance change value of each intersection (sensor element) formed by each driven column wiring and row wiring (corresponding to each row wiring) is multiplexed.

Returning to FIG. 1, the capacitance detection circuit 100 includes a charge amplifier circuit 6, a sample hold circuit 7, a selector circuit 8, an A / D converter 9, a decoding operation circuit 10, a timing control circuit 11, and a column wiring selector 13. Yes.
The charge amplifier circuit 6 is provided in each row wiring in the row wiring group 3 of the sensor unit 4, and enters and exits according to the capacitance of the intersection (sensor element) (based on the charge / discharge current). Current corresponding to the amount of change) is detected, the current is amplified and converted into a voltage, and output as a detection signal (measurement voltage). The sample hold circuit 7 is provided for each charge amplifier circuit 6 and samples the measurement voltage of the detection signal by the input of the S / H (sampling hold) signal output from the timing control circuit 11 as voltage information. Hold temporarily. The selector circuit 8 switches the voltage information held in each of the sample hold circuits 7 sequentially, for example, in the order of the row arrangement, and outputs the voltage information to the A / D converter 9.
The A / D converter 9 converts the measurement voltage, which is analog voltage information input in time series, into digital value measurement data at the timing of the A / D clock input from the decoding arithmetic circuit 10. The result is output to the decoding arithmetic circuit 10.
Further, when processing at a high speed, the A / D converter 9 is provided in each charge amplifier circuit 6 without providing the sample hold circuit 7, and the analog measurement voltage is converted into digital measurement data. You may do it.

In the digitized measurement data, the decoding calculation circuit 10 calculates a difference between the measurement data at the time of charging the sensor element at the intersection and the measurement data at the time of discharging, and removes an offset component due to feedthrough, and Arithmetic processing for decoding a signal multiplexed by a PN code by a product-sum operation using the same PN code as the encoded PN code and separating the signal into voltage data components indicating capacitance values for each sensor element And so on.
When a start signal indicating that capacitance detection is started is input from the decoding arithmetic circuit 10, the timing control circuit 11 receives a code generator 1, a column wiring driver 5, a charge amplifier circuit 6, a sample hold circuit 7, and a selector. A clock and a control signal are output to the circuit 8 and the column wiring selector 13, and the operation timing of the entire capacitance detection circuit 100 is controlled.

The column wiring selector 13 divides the column wiring of the column wiring group 2 into a predetermined number of column wiring groups, and outputs a drive signal based on the PN code from the code generator 1 for each column wiring group.
FIG. 8 shows a configuration of a column wiring selector (group selector) that selects a column wiring group to be driven among the column wirings of the entire sensor. In the first embodiment, adjacent continuous column wirings are bundled into a group. For example, when a PN code having a 15-bit length is used (N = 15), every 15 column wirings are bundled into one group, and the whole is set to 17 groups (M = 17). Wiring can be controlled.
Further, in this first embodiment, the column wiring selector 13 does not change the selection of each column wiring group by the control signal from the timing control circuit 11 until the PN code circulates for one cycle, An operation of switching the column wiring group is performed for each period.

  Next, the configuration of the charge amplifier circuit 6 will be described with reference to FIG. FIG. 5 is a conceptual diagram showing a configuration example of the charge amplifier circuit 6. As shown in this figure, the charge amplifier circuit 6 includes an operational amplifier 121 and a feedback capacitor connected between the inverting input terminal and the output terminal of the operational amplifier 121. Cf and an analog switch 124 for discharging the charge of the feedback capacitor Cf. The non-inverting input terminal of the operational amplifier 121 is connected to the reference potential. In the figure, Cp is a parasitic capacitance of the operational amplifier 121 and the like, Cs is a capacitance of the sensor element at the above-described intersection (total of multiplexed sensor elements), and Cy is a capacitance of the sensor element with respect to the column wiring that is not detected. Is the sum of

Next, an example of the operation of the capacitance detection circuit according to the first embodiment of the present invention having the above configuration will be described with reference to FIG. Here, a 15-bit PN code generated from a PN code generation circuit 20 described later will be described as an example.
It is assumed that the decoding operation circuit 10 has received a signal from the outside to start capacity detection, that is, a fingerprint collection by the fingerprint sensor (sensor unit 4).
As a result, the decoding arithmetic circuit 10 outputs a start signal that instructs the timing control circuit 11 to start detection. Next, the timing control circuit 11 outputs a clock signal and a reset signal to the code generator 1.
The code generator 1 initializes an internal four-stage LFSR (Linear Feedback Shift Register) with the reset signal, generates an M-sequence PN code in synchronization with the clock signal, and sequentially outputs the PN code. .

Here, the code generation unit 1 performs PN code generation and includes, for example, a PN code generation circuit 20 shown in FIG. 6A, and outputs an M-sequence PN code in synchronization with a clock.
That is, the PN code generation circuit 20 (referred to as LFSR) generates an M-sequence 15-bit PN code, and includes a 4-bit shift register 21 and an exclusive OR (hereinafter referred to as EXOR) 22. Has been. The EXOR 22 is connected to the output of the tap 1 (output of the first bit of the shift register 21) of the shift register 21 and the output of the tap 4 (output of the fourth bit of the shift register 21). A logical OR operation is performed, and the operation result is output to the input of the shift register 21. Then, the PN code generation circuit 20 shifts the data of each bit of the shift register 21 in synchronization with the clock signal, thereby sequentially generating the data of the bit string of the PN code in time series in synchronization with the clock signal. Then, as shown in FIG. 6B, the PN code generation circuit 20 synchronizes the bit string data with the clock signal {1 (MSB), 1, 1, 1, 0, 1, 0, 1 , 1, 0, 0, 1, 0, 0, 0 (LSB)} (in FIG. 6B, the time advances from left to right), an internal storage shift register (for storage shown later) Write to the shift register 23) in time series. Here, the PN code generation circuit 20 outputs PN codes in time series in the order of LSB bits to MSB bits.

Further, as shown in FIG. 7A, every cycle shifted by 15 bits, that is, when the bit string of the PN code is 15 bits, the cycle is shifted by 1 bit to have the same bit arrangement (matching phase). Each time, the number of bits of autocorrelation becomes the maximum (+15), and the number of bits of autocorrelation becomes the minimum (−1) in the middle of the cycle. In FIG. 7A, the vertical axis represents autocorrelation (the number of coincident bits), and the horizontal axis represents the number of bits for shifting (one cycle with a 15-bit shift). The phase shift indicates that only the bit shift is performed on the initial bit arrangement in the PN code without changing the arrangement of the bit data.
Then, as shown in FIG. 7B, as the nature of the PN code, the bit string of the PN code is compared with the bit string obtained by cycling the bit string of the PN code having the same bit string as the PN code. When the phases are synchronized, the signs match, so the result of the product-sum operation is the maximum (+15), but when the phases are different, the number of bits with the same sign is 1 bit less than the number of bits that do not match, Since the result of the product-sum operation is almost averaged and becomes the minimum (−1), the information multiplexed at the time of decoding can be separated by using a product-sum operation (CDMA (Code Division Multiple Access of a mobile phone)). ) Close to the principle of multiplexing and demultiplexing in the system).

Next, as shown in FIG. 8, the column wiring drive unit 5 divides the column wiring group 2 into a predetermined number, for example, M column wiring groups 41 to 4M, and stores the shift register 23 at predetermined time intervals. Are output to the column wiring groups to be sequentially selected. Here, the number of column wirings in each column wiring group is the same as the number of bits in the bit string of the PN code generated by the PN code generation circuit 20. In the first embodiment, for example, if the number of bits of the PN code is 15 bits, the number of column wirings in each column wiring group of the column wiring groups 41 to 4M is 15.
As shown in FIG. 10, when the capacitance measurement at the intersection of the column wiring and the row wiring is completed over one cycle in each column wiring group unit, the next column wiring group is sequentially selected. The order in which the column wiring groups are selected may be the order of the column wiring groups 41 to 4M, or may be selected in the order of random positions regardless of the position.

Next, the measurement of the capacitance at the intersection in each column wiring group will be described.
As shown in FIG. 9, in accordance with the PN code output from the code generator 1, a predetermined column wiring group of the column wiring group 2, such as a column, is driven by a drive signal string input via the column wiring selector 13. A plurality of column wirings in the wiring group 41 are driven simultaneously.
If the PN code is 15 bits {1 (MSB), 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0, 0 (LSB)}, One period as a generation period of the bit string is formed at times t1 to t15 having a fixed interval for shifting these bits in time series. The PN code bit string {1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0, 0} generated by the PN code generation circuit 20 is sequentially stored. The shift register 23 shifts. The storage shift register 23 is formed of 15 registers 23 1 to 23 15 for storing 1-bit data, and data is shifted from the left (in the direction of the register 231) to the right (in the direction of the register 2315). That is, at time t 1, “1” of the first bit of the PN code bit string is input to the leftmost register 231 of the storage shift register 23. At time t 2, the first bit “1” stored in the register 231 is shifted to the register 232, and the second bit “1” of the bit string of the PN code is input to the register 231. .

  Hereinafter, the above-described operations are performed at times t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, thereby register 2315, 2314, 2313, 2312. , 2311, 2310, 239, 238, 237, 236, 235, 234, 233, 232, 231 each include a bit string {1 (MSB), 1, 1, 1, 0, 1, 0, 1, 1 of the PN code. , 0, 0, 1, 0, 0, 0 (LSB)} data is input. Here, the data stored in each of the registers 2315, 2314, 2313, 2312, 2311, 2310, 239, 238, 237, 236, 235, 234, 233, 232, 231 of the storage shift register 23 is a column. It is supplied to the driver circuits 515, 514, 513, 512, 511, 510, 59, 58, 57, 56, 55, 54, 53, 52, 51 in the wiring drive section 5, respectively. At the end of time t1 to t15, the PN code bit string {1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0, 0} The driver circuits 515, 514, 513, 512, 511, 510, 59, 58, 57, 56, 55, 54, 53, 52 and 51 in the section 5 are supplied. The operation between the time t1 and the time t15 is one cycle of the fingerprint collecting process in the present invention.

  Next, let us look at the operation of the storage shift register 23 during the actual operation. When a fingerprint acquisition start signal is input, 15 clock signals are input from the timing control circuit 11, and in the initial state, the registers 2315, 2314,..., 231 of the storage shift register 23 are {1, 1, 1,1,0,1,0,1,1,0,0,1,0,0,0}. Then, at the first time t1 of one cycle in the fingerprint collecting process, a clock is input from the timing control circuit 11, and each register 2315, 2314,..., 231 of the storage shift register 23 is shifted by one bit and stored. The data to be processed is a bit array {1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1} (FIG. 9). The column wiring drive unit 5 is connected to the corresponding column wirings C15, C14, C13 by driver circuits 515, 514, 513, 512, 511, 510, 59, 58, 57, 56, 55, 54, 53, 52, 51. In C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, and C1, a drive pulse train composed of a drive pulse having a predetermined constant width based on the clock signal output from the timing control circuit 11 (See FIGS. 11 (c) and 12 (f)).

  At this time, the column wiring drive unit 5 outputs the drive pulse (predetermined voltage) when the bit data is “1” in the case of the drive pulse train P1 corresponding to the bit string of the PN code, and the bit data is “0”. In this case, the drive pulse is not output, and the ground potential is output to the column wiring other than the column wiring outputting the drive pulse. Therefore, at time t1, as shown in FIG. 12, the column wirings C1, C5, C8, C9, C11, C13, C14, C15 are driven by a predetermined drive pulse of the drive pulse train P1. Yes. Each of the row wirings R1, R2, R3,... Has a total value of the capacitances of the capacitive sensors formed by the plurality of driven column wirings, that is, a capacitance value multiplexed by the bit arrangement of the PN code. Will be connected.

At this time, as shown in FIGS. 11 (b) and 12 (a), the timing control circuit 11 has a timing just before the rising of each driving pulse of the driving pulse train for driving the column wiring and a slight falling. A reset signal is output to the charge amplifier circuit 6 at the previous time point, and, as shown in FIGS. 11 (d) and 12 (b), the sample / hold signal is supplied to the sample / hold circuit at a time point just before the reset signal. 7 is output.
Further, the timing control circuit 11 outputs N (N is the number of sample hold circuits 7) switching signals to the selector circuit 8 at intervals at which sample hold signals are sequentially input. As a result, as shown in FIG. 12C, each signal held in the sample-and-hold circuits 7, 7... By one sample-and-hold signal is sequentially selected until the next sample-and-hold signal. To the A / D converter 9. As a result, the A / D converter 9 sequentially converts the measurement voltage in the detection signal for each row wiring to the digital at the timing of the A / D clock (synchronized with the switching signal) input from the decoding arithmetic circuit 10. The data is converted to data and output to the decoding arithmetic circuit 10 for each row wiring as measurement data d1. Then, the decoding arithmetic circuit 10 writes the data string in the measurement data that is sequentially input to the internal memory for each row wiring.

Here, the operation of the charge amplifier circuit 6 will be described in detail. First, when a reset signal is output from the timing control circuit 11 at time td1 slightly before time t1 shown in FIG. 11, the analog switch 124 (MOS transistor, FIG. 5) is turned on, and the feedback capacitor Cf is discharged. The output OUT of the operational amplifier 121 is short-circuited with the inverting input terminal and becomes a reference potential. In addition, the row wiring connected to the inverting input terminal of the operational amplifier 121 also becomes the reference potential.
Next, when this reset signal is turned off, the output voltage of the operational amplifier 121 slightly rises due to feedthrough due to the gate parasitic capacitance of the analog switch 124 (see the symbol Fd after time td1 in FIG. 11A).

  At time t1, when a predetermined drive pulse corresponding to the bit pattern of the PN code in the drive pulse train (drive pulse train P1 in (f) in FIG. 12) rises (inputs), the drive pulse is connected to the column wiring. The voltage value of the output OUT of the operational amplifier 121 is applied to the inverting input terminal of the operational amplifier 121 via the sensor element (capacitance Cs) at the intersection of the wiring, and flows based on the voltage value of the drive pulse. As shown in the figure, it descends gradually.

Next, at time td2, the timing control circuit 11 outputs a sample hold signal (S / H signal) to the sample hold circuit 7. Thereby, the sample hold circuit 7 holds the measurement voltage Va output from the output OUT of the operational amplifier 121 in the charge amplifier circuit 6 at the time when the sample hold signal is input.
Next, at time td3, the timing control circuit 11 outputs a reset signal to the charge amplifier circuit 6 again. As a result, the output OUT of the operational amplifier 121 and the inverting input terminal are short-circuited, the feedback capacitor Cf is discharged, and the output OUT of the operational amplifier 121 returns to the reference potential. When the reset signal is turned off, the output voltage of the operational amplifier 121 slightly increases due to the feedthrough due to the gate parasitic capacitance of the analog switch 124 as in the case described above (reference Fd after time td3 in FIG. 11A). reference).

Next, at time td4, when the drive pulse in the drive pulse train P1 falls, the column wiring driven by the drive pulse and the sensor element (capacitance Cs) at the intersection of the row wiring are based on the voltage of the drive pulse. As a result, the output OUT of the operational amplifier 121 gradually rises.
Next, at time td5, the timing control circuit 11 outputs a sample hold signal to the sample hold circuit 7. Thereby, the sample hold circuit 7 holds (holds) the measurement voltage Vb of the output OUT of the operational amplifier 121 at the time when the sample hold signal is input.
Next, at time td6 (becomes td1 corresponding to the next time t2), the timing control circuit 11 outputs a reset signal to the charge amplifier circuit 6. As a result, the output OUT and the inverting input terminal of the operational amplifier 121 in the charge amplifier circuit 6 are short-circuited, the feedback capacitor Cf is discharged, and the output OUT of the operational amplifier 121 returns to the reference potential. Thereafter, the above operation is repeated (FIGS. 11A and 11B).

In the measurement described above, the offset Vk due to the feedthrough current of the analog switch 124 is generated in the + direction regardless of whether the output OUT drops from the reference potential or rises. As in this embodiment, when the capacitance Cs to be detected is tens to hundreds of femtofarads, the offset due to this feedthrough cannot be ignored. In the above measurement,
-Va0 = -Va + Vk
Is a voltage proportional to the detection target capacitance Cs, but the measured voltage is Va, and this voltage Va includes an error Vk due to an offset.
Va = Va0 + Vk

Therefore, in this embodiment, the voltage Vb at the time of discharging the detection target capacitor Cs is also measured. Here, the voltage Vb0 is as follows:
Vb0 = Vb-Vk
Is a voltage proportional to the capacitance Cs, and the measured voltage is Vb = Vb0 + Vk
It becomes. These measurement voltages Va and Vb are sequentially held by the sample and hold circuit 7, and then the held voltage is A / D converted by the A / D converter 9 for each of the measurement voltages Va and Vb. Store in the memory. In the decoding arithmetic circuit 10,
d = Vb-Va = (Vb0 + Vk)-(Vk + Va0) = Vb0-Va0
As a result, a measurement value not including an offset error, that is, measurement data d corresponding to the multiplexed capacitance value is obtained.

  As described above, the decoding arithmetic circuit 10 determines the difference between the output signal of the charge amplifier circuit 6 when the potential of the column wiring is raised and when the potential of the column wiring rises and falls at the rise and fall of a predetermined drive pulse in the drive pulse train. By taking this, the capacitance value of the sensor element can be measured in a state where there is no influence of feedthrough. Further, by providing the selector, the charge amplifier circuit 6 that requires measurement time can be measured in parallel in each column wiring, and the measurement speed of the entire sensor can be increased.

  Next, at time t2 (corresponding to the measurement in the drive pulse P2 after 1-bit shift in FIG. 12; time before the rise of the drive pulse P2 in (f)), the timing control circuit 11 Output a clock. As a result, in the code generation unit 1, the shift register 21 shifts by one bit to generate “1” and outputs it to the storage shift register 23. The storage shift register 23 synchronizes with the clock and stores the stored PN code bit string {1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0. , 0, 1} are shifted by one bit, and data “1” input from the shift register 21 is written to the register 231. As a result, the data “1” stored in the register 2315 protrudes from the storage shift register 23 and disappears, and the data “1” stored in the register 2314 is newly written in the register 2315.

  For this reason, as shown in FIG. 13, each of the registers 2315, 2314, 2313, 2312, 2311, 2310, 239, 238, 237, 236, 235, 234, 233, 232, 231 of the storage shift register 23 is stored. The data thus obtained is a bit string {1, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1}. Each output of each register of the shift register 22 is supplied to driver circuits 515, 514, 513, 512, 511, 510, 59, 58, 57, 56, 55, 54, 53, 52, 51 in the column wiring drive unit 5. Supplied to each. Therefore, when the time t2 ends, the PN code bit string {1 (MSB), 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1 (LSB) } Is 1 bit out of phase with respect to the time t1, that is, when the capacitance values of the plurality of sensor elements are multiplexed by the previous drive pulse train P1 (the bit arrangement of the PN code is 1 bit) The PN code is supplied to the driver circuits 515, 514, 513, 512, 511, 510, 59, 58, 57, 56, 55, 54, 53, 52, and 51 in the column wiring drive unit 5, respectively. .

  Next, at time t2, the column wiring drive unit 5 causes the driver circuits 515, 514, 513, 512, 511, 510, 59, 58, 57, 56, 55, 54, 53, 52, 51 to correspond to the corresponding columns. The wirings C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, and C1 are driven on the basis of the clock pulse output from the timing control circuit 11 (1 Driving is performed by a driving pulse having a predetermined constant width in the driving pulse train P2) after the bit shift (see FIGS. 11D and 12F). At the time t2, the column wirings C1, C2, C6, C9, C10, C12, C14, and C15 are driven (FIG. 13). The state at time t2 corresponds to the time t1 already described.

Then, at time t2 (that is, in the vicinity of time t2), the operation from time td1 to time td5 already described in FIG. 11 is repeated, and a plurality of column wirings are driven in a state where the bit string of the PN code is shifted by 1 bit. Then, the capacitance values of the plurality of sensor elements are multiplexed, and a measurement voltage obtained by converting the multiplexed capacitance into a voltage value is obtained.
The processing described at time t1 and t2 described above is repeated from time td1 to time td5 shown in FIG. 11 at each timing corresponding to time t3 to time t15 (FIG. 14 shows the storage shift at each time. The bit arrangement of the PN code of the register 23 is shown), and the fingerprint acquisition process is performed by repeating the bit shift of the PN code, the driving of the column wiring, and the acquisition of the measurement voltage over one period.

The capacitance detection circuit 100 drives the plurality of column wirings of the column wiring group 2 by each of the drive pulse trains P1 to P15, and performs the above-described measurement processing every time the 15-bit PN code is sequentially shifted by 1 bit. Fifteen measurement voltages Vd whose phases are shifted by 1 bit are obtained for each row wiring in time series. This measurement voltage Vd is converted to measurement data Vd in time series by the A / D converter 9, and a data string {d1, d2,..., D15} of measurement data multiplexed by a PN code is obtained.
As the measurement data in which the phase of the PN code differs by 1 bit for each row wiring, it is stored in the memory inside the decoding arithmetic circuit 10 as the following data.
d1 = Vs1 + Vs5 + Vs8 + Vs9 + Vs11 + Vs13 + Vs14 + Vs15
d2 = Vs1 + Vs2 + Vs6 + Vs9 + Vs10 + Vs12 + Vs14 + Vs15
d3 = Vs1 + Vs2 + Vs3 + Vs7 + Vs10 + Vs11 + Vs13 + Vs15
d4 = Vs1 + Vs2 + Vs3 + Vs4 + Vs8 + Vs11 + Vs12 + Vs14
・
・
・
d15 = Vs4 + Vs7 + Vs8 + Vs10 + Vs12 + Vs13 + Vs14 + Vs15

Here, Vs is voltage data (digital value) obtained by converting each capacitance of the sensor element at the intersection of each driven column wiring and row wiring into a voltage, and each measurement data d is driven based on the PN code. Multiplexed by the capacitance of the sensor element corresponding to the column wiring.
When considered as a general formula, the following formula (1) is obtained.

In this equation, about half (eight) in the column wiring group 2 are simultaneously driven based on the PN code, so that the integrated value of the voltage data Vsj corresponding to the capacitance Csj of the sensor elements at about half of the intersections. Is obtained as measurement data di. Here, “j” is the number of the column wiring C, “i” is the number of the measurement data (corresponding to the order in which the phase is shifted by 1 bit), and i = 1, 2, 3,. j = 1, 2, 3,...
Then, the decoding arithmetic circuit 10 obtains the voltage data Vs of each sensor element by the following equation (2) from the multiplexed measurement data and the PN code used for multiplexing.

As described above, the time-series measurement data d obtained by sequentially shifting the PN code in bit units is calculated by the product-sum operation of the PN code and the measurement data d according to the above equation (2). The voltage data ds corresponding to the capacitance of the sensor element at the intersection with the driven column wiring, that is, voltage data Vs can be separated.
In this equation (2), when the bit data of the PN code is PNi = 1, the polarity code PNs (i) = + 1, and when PNi = 0, the polarity code PNs (i) = − 1. To do.
The decoding operation circuit 10 performs an operation of separation (that is, decoding) from the measurement data d to the voltage data ds using the equation (2).

  That is, when obtaining the voltage data ds for each sensor element, that is, the voltage data {ds15, ds14, ds13,..., Ds2, ds1}, the voltage data ds is multiplexed by the PN code in units of row wiring, and the data of the measurement data is obtained. Since the sequence {d15, d14, d13,..., D2, d1} is obtained, first, the bit sequence {1 (MSB), 1, 1, 1, 0, 1, 0, 1 of the PN code for each measurement data dj , 1, 0, 0, 1, 0, 0, 0 (LSB)} is multiplied by the polarity code corresponding to the data PNi of each bit. Here, at the time of measurement, when a drive signal is applied to the column wiring based on a predetermined PN code, the order of the bit strings sequentially corresponds to the order of each column wiring. For example, the LSB bit corresponds to the column wiring C1. The MSB bit corresponds to the column wiring C15. Next, the voltage data ds1 corresponding to the intersection of the column wiring C1 is a PN code bit string (no shift), {1 (MSB), 1,1,1,0,1,0,1,1,0, 0, 1, 0, 0, 0 (LSB)}, the polarity code corresponding to the data PNi of each bit of this bit string is multiplied for each measurement data dj and integrated over one period. That is, the column wiring C1 is driven corresponding to the LSB bit data of the PN code at the time t1, as can be seen from the PN code bit data of the LSB column in the table of FIG. Since the second bit at time t2,..., And the MSB bit data are driven at time t15, the polarity code corresponding to the bit data of the corresponding PN code is also multiplied in the product-sum operation. Will be added.

  Similarly, the voltage data dS2 corresponding to the intersection of the column wiring C2 is obtained by converting the bit string of the PN code into the data of the PN code at each time in the second bit column in the table of FIG. Since the one bit shifted (circulated in the right direction) is used to drive the column wiring C2, the bit string {0 (LSB), 1, 1, 1, 1, 0, 1, 0, 1, 1 , 0, 0, 1, 0, 0 (MSB)}, the data PNi of each bit of this bit string is multiplied as a coefficient for each measurement data dsj and integrated over one period. This process corresponds to a product-sum operation for the PN code. As shown below, the voltage data dsj corresponding to each intersection is obtained by measuring the measured data di and the bit string obtained by shifting the bit string of the PN code by a predetermined bit string. It is obtained by a product-sum operation with the polarity code corresponding to each data PNi.

In this case, in the product-sum operation at the time of decoding, the PN code in the initial state is used for the row wiring R1, and the PN code shifted by 1 bit for each column wiring in the order of measurement is used.
That is, in the product-sum operation at the time of decoding, for each measurement data measured at each time, the number of the column wiring of the intersection to be obtained and the bit array of the PN code used at the time corresponding to this number Each number (order) of bit data is multiplied by the polarity code corresponding to the data and integrated (ie, the PN code used when driving the corresponding column wiring at each time during measurement) The bit data and the polarity code corresponding to the data of the same value are multiplied).

PN code bit string {1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0, 0} corresponding to 15 column wirings in this embodiment In this case, the decoding arithmetic circuit 10 is based on the equation (2):
ds1 = + d1 + d2 + d3 + d4-d5 + d6-d7 + d8 + d9-d10-d11 + d12-d13-d14-d15
ds2 = -d1 + d2 + d3 + d4 + d5-d6 + d7-d8 + d9 + d10-d11-d12 + d13-d14-d15
ds3 = -d1-d2 + d3 + d4 + d5 + d6-d7 + d8-d9 + d10 + d11-d12-d13 + d14-d15
ds4 = -d1-d2-d3 + d4 + d5 + d6 + d7-d8 + d9-d10 + d11 + d12-d13-d14 + d15
・
・
・
ds15 = + d1 + d2 + d3-d4 + d5-d6 + d7 + d8-d9-d10 + d11-d12-d13-d14 + d15
And the voltage data dsj corresponding to the capacitance value of each sensor element is separated from the data string of the measurement data di.

As described above, in the first embodiment, the column wiring group 2 is divided into a plurality of column wiring groups composed of adjacent column wirings, and each of the column wiring groups is divided into time t1 to time t15. , The measurement is performed by multiplexing the column wirings while changing the phase of the PN code, and this process is repeated for all the column wiring group units to measure all the column wirings. By performing a product-sum operation process with the PN code, the influence from the intersection capacitance with other column wirings is almost averaged, and at the same time, the sensor element (capacitance sensor) at the intersection with the target column wiring is obtained. It is possible to extract only information on charges charged and discharged.
In the first embodiment, there are several types of PN codes in addition to the M sequence. However, when an M sequence having excellent autocorrelation is decoded on the detection side, the influence on adjacent column wirings is uniform. Therefore, there is an effect of reducing the influence of crosstalk between column wirings. An example other than the M sequence is an 11-bit length Barker sequence {1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0}.

  Furthermore, the capacitance detection circuit of the first embodiment is multiplexed at time t1 when the decoding arithmetic circuit 10 multiplexes and measures the column wiring for each column wiring group in the measurement of each column wiring group described above. It is detected whether the measured voltage exceeds the preset reference voltage. If it is detected that the measured voltage exceeds the reference voltage, the measurement of this wiring group is continued, while the measured voltage is When it is detected that the voltage is not exceeded, the measurement of this wiring group is stopped, all the measurement data d1 to d15 are set to “0”, and the measurement is transferred to the next column wiring group. Measurement of column wiring groups that are not in contact with each other and need not be subjected to capacitance detection is eliminated, the entire measurement process can be made more efficient, and the load of the capacitance detection process can be reduced.

Further, as the timing of switching the column wiring group, in the above-described measurement operation, the measurement target is transferred to the next column wiring group when one cycle from time t1 to time t15 ends for each column wiring group.
However, as shown in FIG. 15, the column wiring groups of the column wiring group 41 to the column wiring group 4M are sequentially switched by the bit arrangement of the PN code at time t1, and the phase of the bit arrangement of the PN code is changed after the group switching is completed. In addition, a measurement process for sequentially switching the column wiring groups of the column wiring group 41 to the column wiring group 4M is performed, and measurement data for each column wiring group is sequentially measured.
Here, the process in which the decoding operation circuit 10 obtains the voltage data dsj of each capacitor from the measurement data of each column wiring group in each column wiring group unit is the same as the decoding process already described.

Next, FIG. 16 is a block diagram showing a configuration example when this embodiment is used for a line sensor.
In the sensor unit 4B of this line sensor, a line type sensor is configured by arranging the row wiring to be detected in one column.
Each configuration of the capacitance detection circuit is the same as that of the already described area type sensor except that the selector circuit 8 for selecting the row wiring for detecting the capacitance is not provided. .
This line type sensor has a smaller circuit scale than an area type sensor, and can reduce power consumption and cost.
When this line type sensor is used as a fingerprint sensor, the finger is swept at an angle substantially perpendicular to the row wiring, the timing control circuit 11 outputs each signal for measurement processing at a predetermined period, and the decoding arithmetic circuit 10 Detects the two-dimensional fingerprint data by connecting the measurement data in units of row wirings inputted every predetermined period.

Next, a capacitance detection circuit according to the second embodiment of the present invention will be described with reference to FIG.
The configuration of the capacitance detection circuit of the second embodiment is the same as that of the capacitance detection circuit of the first embodiment. The second embodiment differs from the first embodiment in that when the column wiring group 2 is divided (assigned) into a plurality of, for example, M column wiring groups 41 to 4M, the column wiring group is divided by adjacent column wirings. 17 as shown in FIG. 17, it is constituted by column wirings of a predetermined interval (a predetermined number apart).

For example, when the column wiring portion 2 is composed of 255 column wirings, if 15 columns are provisionally divided into 15 groups, and the first column wiring of each group is combined into a column wiring group, 15 columns are obtained. Each column wiring is grouped into 17 column wiring groups.
Note that the measurement data measurement process and effects performed for each column wiring group in the second embodiment are the same as those in the first embodiment.

Next, a capacitance detection circuit according to the third embodiment of the present invention will be described with reference to FIG.
The configuration of the capacitance detection circuit of the third embodiment is the same as that of the capacitance detection circuit of the second embodiment. The third embodiment is different from the second embodiment in that a code generation unit 1A is provided with a pulse generation circuit 30 instead of the storage shift register 23 in the code generation unit 1, as shown in FIG. In addition, a column wiring selector 13A is provided in place of the column wiring selector 13.

  For example, when the column wiring group 2 is composed of 255 column wirings and the PN code is 15 bits, the pulse generation circuit 30 has 15 column wirings per column wiring group. Input the bit array {1 (MSB), 1,1,1,0,1,0,1,1,0,0,0,1,0,0,0 (LSB)} of the generated PN code, Drive bit array {1, <16-bit 0>, 1, <16-bit 0>, 1, <16-bit 0>, 1, <16-bit 0>, 0, <16-bit 0>, 1, <16-bit 0>, 0, <16-bit 0>, 1, <16-bit 0>, 1, <16-bit 0>, 0, <16-bit 0 >, 0, <16-bit 0>, 1, <16-bit 0>, 0, <16-bit 0>, 0, <16-bit 0> 0, and outputs a} <0 16-bit>. Here, <16-bit 0> is a bit array {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 in which data “0” continues 16 bits. , 0, 0}.

That is, the pulse generation circuit 30 inserts <16-bit 0> between each bit in the bit array of the PN code so that one column wiring is driven for every 17-bit column wiring. One bit is output to the wiring selector 13A for each multiplexed measurement.
The column wiring selector 13A is a shift register including registers corresponding to the column wirings C1 to C255 of the column wiring group 2, and every time one bit of the driving bit array in which the data “0” is inserted is input, Data is shifted bit by bit in the direction of the arrow (to the right in FIG. 18).
As a result, the column wiring selector 13A uses one column wiring for every predetermined number, for example every 17 lines, through the buffers 51 to 5255 of the column wiring driving unit, depending on the data in each register of the shift register, that is, The column wiring is driven in a column wiring group unit composed of column wirings separated by a predetermined number.

Next, an operation example of the capacitance detection circuit 100 having the above-described configuration according to the fourth embodiment of the present invention will be described with reference to FIG. This fourth embodiment is different from the first to second embodiments except that orthogonal codes are used instead of the PN codes in the first to second embodiments for multiplexing of measurement data. There is no difference in operation. Here, in order to simplify the explanation, a 15-bit length orthogonal code generated from an orthogonal code reading circuit 220 to be described later will be described as an example, and only operations different from those in the first embodiment will be described.
It is assumed that the decoding operation circuit 10 has received a signal from the outside to start capacity detection, that is, a fingerprint collection by the fingerprint sensor (sensor unit 4).
As a result, the decoding arithmetic circuit 10 outputs a start signal that instructs the timing control circuit 11 to start detection. Next, the timing control circuit 11 outputs a clock signal and a reset signal to the code generator 1B.
Then, the code generator 1B initializes each register of the internal address counter 222 and the orthogonal code reading circuit 220 (FIG. 19) via the orthogonal code reading circuit 220 by the reset signal, and synchronizes with the clock. Then, the orthogonal codes are sequentially read from the code memory 221 and output.

Here, the code generation unit 1B stores an orthogonal code created in advance in the internal code memory 221. Each time a clock is sequentially input, the code generation unit 1B applies a data string having orthogonality to the column wiring drive unit 5B. Output to.
The Walsh code, which is a typical orthogonal code, is generated in the order shown in FIG. As a basic structure, a basic unit of 2 (rows) × 2 (columns) is formed, but the upper right, upper left, and lower left bits are the same, and the lower right is an inversion of these bits.
Next, four 2 × 2 basic units described above are combined as blocks in the upper right, upper left, lower right, and lower left to create a code of a bit array of 4 (rows) × 4 (columns). Here, as in the creation of the 2 × 2 basic unit, the lower right block is bit-inverted. In the same procedure, the number of bits of the bit arrangement of the code (corresponding to the number of columns) and the number of codes (the number of rows) are set as 8 (row) × 8 (column), 16 (row) × 16 (column). Response).

In the second embodiment, the measurement data can be multiplexed on the first row and the first column, all of which are logic “0”, that is, all the bit data is “0”, without driving the columns. Because it was not, it was excluded from the code. In FIG. 20, for example, a 15 × 15 bit matrix is used as an orthogonal code.
As described above, a Walsh code can be generated similarly for a code having a long code length, and the generated Walsh code can be applied to multiplexing in capacity measurement described below.
In this embodiment, for example, the column wiring group 2 is composed of 15 wirings C1 to C15, and orthogonal codes represented by a matrix of 15 × 15 bits are used for multiplexing at the time of capacitance measurement.

In the code memory (code memory 221 in FIG. 19) in the code generator 1B, the orthogonal code data represented by the 15 × 15 matrix is stored in the data format shown in the table of FIG. Each row is stored in order in association with the addresses t1 to t15.
Here, for example, the Walsh code in the row of the address t1 is {1 (LSB), 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 (MSB)}. And the Walsh code of the row at address t15 is {1 (LSB), 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0 (MSB)} It has become.

When the start signal is input, the timing control circuit 11 outputs a measurement start signal to the code generator 1B.
In FIG. 19, when the measurement start signal is input, the orthogonal code reading circuit 220 resets the address counter 222 and the storage register 23 and sets the count value of the address counter 222 to “0”.

Next, after setting the initial state, the orthogonal code reading circuit 220 outputs the count signal to the address counter every time the clock output from the timing control circuit 11 is input in time series when measuring the capacitance at the intersection. It outputs to 222.
Then, the address counter 222 counts the input count signal and outputs addresses t 1, t 2,..., T 15 to the code memory 221 corresponding to the count values.
As a result, the code memory 221 outputs the orthogonal code data (row bit arrangement) corresponding to the input addresses t 1, t 2,..., T 15 to the orthogonal code reading circuit 220.

The orthogonal code reading circuit 220 writes the LSB to MSB bit array of the bit string of the orthogonal code to each of the registers 2231 to 22315 of the storage register 223 by the clock of the timing control circuit 11.
When the orthogonal code is input to the storage register 223, the data array {1 (LSB), 0, 1, 0 is stored in each of the registers 2231, 2232, 2233, 2234, 2235, ..., 22314, 22315 of the storage register 223. , 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 (MSB)} is input.
As a result, the column wiring drive unit 5 performs the corresponding predetermined bit data in the bit array of the orthogonal code input in the column wiring group selected by the column wiring selector 13 as in the first embodiment. Controls driving of the column wiring.

  Similar to the capacity detection processing described in the first embodiment, the processing from time td1 to time td5 shown in FIG. 11 is repeated at each timing corresponding to time t1 to time t15 (FIG. The bit sequence of the orthogonal code of the storage register 223 is shown), reading from the code memory 221 of the orthogonal code, driving of the column wiring, and acquisition of the measurement voltage over one cycle from the memory address t1 to t15 Is repeated, and fingerprint acquisition processing is performed.

The capacitance detection circuit 100 sequentially reads out the 15-bit orthogonal code in the above-described measurement process corresponding to the time from the code memory 221 when driving the drive pulse P at each time, and the column wiring drive unit 5 At each time, a predetermined column wiring corresponding to the orthogonal code in the column wiring group is driven.
As a result, the capacitance detection circuit 100 obtains 15 measurement voltages Vd different for each address t1 to t15 corresponding to each time for each row wiring in time series. The A / D converter 9 converts this measurement voltage Vd into measurement data d in time series, and a data string {d1, d2,..., D15} of measurement data multiplexed with orthogonal codes is obtained.
Measurement data different for each of the 15 orthogonal codes for each row wiring is stored as data shown below (measured using the orthogonal codes in the table of FIG. 21) in the memory inside the decoding arithmetic circuit 10.
d1 = Vs1 + Vs3 + Vs5 + Vs7 + Vs9 + Vs11 + Vs13 + Vs15
d2 = Vs2 + Vs3 + Vs6 + Vs7 + Vs10 + Vs11 + Vs14 + Vs15
d3 = Vs1 + Vs2 + Vs5 + Vs6 + Vs9 + Vs10 + Vs13 + Vs14
d4 = Vs4 + Vs5 + Vs6 + Vs7 + Vs12 + Vs13 + Vs14 + Vs15
・
・
・
d15 = Vs1 + Vs2 + Vs4 + Vs7 + Vs8 + Vs11 + Vs13 + Vs14

Here, Vs is voltage data (digital value) obtained by converting each capacitance of the sensor element at the intersection of each driven column wiring and row wiring into a voltage, and each measurement data d is driven based on an orthogonal code. Multiplexed by the capacitance of the sensor element corresponding to the column wiring.
When considered as a general formula, the following formula (3) is obtained.

In this equation (3), about half (eight) in the column wiring group 2 are simultaneously driven based on the orthogonal code, so that the integration of the voltage data Vsj corresponding to the capacitance Csj of the sensor elements at about half of the intersections. The obtained value is obtained as measurement data di. Here, “j” is the number of the column wiring C, “i” is the number of the measurement data (corresponding to the order of each address ti), i = 1, 2, 3,..., N, j = 1, 2, 3, ..., N. That is, the code CD (i, j) in the equation (1) indicates the code of the j-th element in the i-th code used at the time ti.
Then, the decoding arithmetic circuit 10 obtains the voltage data Vs of each sensor element by the following equation (4) from the multiplexed measurement data and the orthogonal code used for multiplexing.

As described above, the orthogonal codes are sequentially read from the code memory 221, and the obtained time-series measurement data d is obtained by performing the product sum operation of the orthogonal codes and the measurement data d by the above equation (4). And voltage data ds corresponding to the capacitance of the sensor element at the intersection of the driven column wiring and the voltage data Vs.
In this equation (4), when the bit data of the orthogonal code is CD (i, j) = 1, the polarity code CDs (i, j) = + 1 and CD (i, j) = 0. At this time, the polarity code CDs (i, j) = − 1.
The decoding operation circuit 10 performs an operation of separation from the measurement data d to the voltage data ds using the equation (4).

  That is, when obtaining the voltage data ds for each sensor element, that is, the voltage data {ds1, ds2, ds3,..., Ds14, ds15}, the voltage data ds is multiplexed with the orthogonal code in units of row wiring, and the data of the measurement data is obtained. Since the sequence {d1, d2, d3,..., D14, d15} is obtained, first, the bit sequence {1 (LSB), 0, 1, 0, 1, 0, 1, 0 of the orthogonal code for each measurement data di. , 1, 0, 1, 0, 1, 0, 1 (MSB)} is multiplied by the polarity code corresponding to the data CD (i, j) of each bit.

  Here, the order of the bit columns sequentially corresponds to the order of the column wirings of each column wiring group. For example, the LSB bit corresponds to the column wiring C1, and the MSB bit corresponds to the column wiring C15. Next, the voltage data ds1 corresponding to the intersection of the column wiring C1 is the LSB bit string {1 (t1), 0 (t2), 1 (t3), 0 ( t4), 1 (t5), 0 (t6), 1 (t7), 0 (t8), 1 (t9), 0 (t10), 1 (t11), 0 (t12), 1 (t13), 0 ( t14), 1 (t15)}, the polarity code corresponding to the data CD (i, j) of each bit of this bit string is multiplied for each measurement data di and integrated over one period.

  That is, the column wiring C1 is driven by the LSB (first bit) data of the orthogonal code at the address t1 at time t1, and is driven by the LSB data of the orthogonal code at the address t2 at time t2,. Since the data is driven by the LSB bit data of the orthogonal code at the address t15, the polarity code corresponding to the used orthogonal code bit data is multiplied and added also in the product-sum operation.

Similarly, the voltage data dS2 corresponding to the intersection of the column wiring C2 is driven corresponding to the second bit data of the orthogonal code at the address t1 at the time t1, and the second bit of the orthogonal code at the address t2 at the time t2. ..,..., And is driven in correspondence with the second bit data of the orthogonal code at the address t15 at time t15. The corresponding polarity codes are multiplied and added.
That is, the voltage data ds2 is a bit string {0 (t1), 1 (t2), 1 (t3), 0 (t4), 0 (t5) consisting of the second bit of the bit arrangement of each orthogonal code at addresses t1 to t15. , 1 (t6), 1 (t7), 0 (t8), 0 (t9), 1 (t10), 1 (t11), 0 (t12), 0 (t13), 1 (t14), 1 (t15) }, The polarity code corresponding to the data CD (i, j) of each bit of this bit string is multiplied for each measurement data di and integrated over one period.

As described above, the voltage corresponding to the capacitance at each intersection corresponds to the data CD (i, j) of each bit of the bit string corresponding to the data applied to the corresponding column wiring at time t1 to t15. The polarity code is multiplied for each measurement data di and integrated over one period. This processing corresponds to a product-sum operation on the orthogonal code. As shown below, the voltage data dsj corresponding to each intersection is measured data di and each bit arrangement of the orthogonal code stored in the code memory 21. Is obtained by a product-sum operation with the polarity code corresponding to the data.
That is, in the product-sum operation at the time of decoding, for each measurement data measured at each time, the measurement data of the column wiring number of the intersection to be obtained and the orthogonal code used at the above time corresponding to this number Each number sign (order) in the bit array is multiplied by the polarity code corresponding to the bit data (ie, used to drive the corresponding column wiring at each time during measurement). The bit data of the orthogonal code and the polarity code corresponding to the data of the same value are multiplied).

In the orthogonal code shown in FIG. 21 stored in the code memory 221 and corresponding to the 15 column wirings in the present embodiment, the decoding arithmetic circuit 10 uses (4) the bit arrangement of the orthogonal codes of the addresses t1 to t15. Based on the formula
ds1 = + d1-d2 + d3-d4 + d5-d6 + d7-d8 + d9-d10 + d11-d12 + d13-d14 + d15
ds2 = -d1 + d2 + d3-d4-d5 + d6 + d7-d8-d9 + d10 + d11-d12-d13 + d14 + d15
ds3 = + d1 + d2-d3-d4 + d5 + d6-d7-d8 + d9 + d10-d11-d12 + d13 + d14-d15
ds4 = -d1-d2-d3 + d4 + d5 + d6 + d7-d8-d9-d10-d11 + d12 + d13 + d14 + d15
・
・
・
ds15 = + d1 + d2-d3 + d4-d5-d6 + d7 + d8-d9-d10 + d11-d12 + d13 + d14-d15
And the voltage data dsj corresponding to the capacitance value of each sensor element is separated from the data string of the measurement data di.

  As described above, in the fourth embodiment, an orthogonal code is used for each column wiring group obtained by dividing the column wiring group 2 using an orthogonal code, for example, a Walsh code, instead of the PN code of the first embodiment. The column wiring corresponding to each bit data is driven, the measurement value of each column wiring group is multiplexed to obtain measurement data, and the orthogonal code of the address corresponding to the time is read from the code memory 221 at the next timing. The operation of performing the above measurement is repeated, and on the other hand, the measurement data obtained in time series on the detection side is subjected to the product-sum operation processing with the orthogonal code, so that the influence from the intersection capacitance with the other column wiring is reduced. At the same time, it is possible to extract only information on the charge / discharge of the sensor element (capacitance sensor) at the intersection with the target column wiring.

In the first to fourth embodiments, the decoding operation in the decoding operation circuit 10 may be performed on the sensor side, or may be performed on the host after transmitting measurement data to the host.
Further, the detection target is not limited to the capacitance, and can be used for measurement of other physical quantities such as a resistance value.
Furthermore, in the first to fourth embodiments, the column wiring and the row wiring are crossed, and one is a drive line (column wiring) and the other is a detection line (row wiring). Similar effects can be obtained in other driving and detection methods.

In the first to fourth embodiments, the description has been made of the multiplexed measurement of the capacitance of the sensor element formed at the intersection of the column wiring and the row wiring as shown in FIG. However, in the fifth embodiment, a configuration when applied to the sensor unit 4C which is an active matrix sensor shown in FIG. 22 will be described.
A bit string of a predetermined PN code is input from the code generator 1 to the column wiring drive circuit 5, and the column wiring group 2 is divided into a plurality of column wiring groups (41-4M), and a plurality of column wirings are provided for each column wiring group. The fifth embodiment is the same as the first to fourth embodiments in that the capacitor of the unit capacity cell 70 (sensor element) is multiplexed on a row wiring basis. The capacitance detection circuit 200 is similar in configuration and operation to the first to fourth embodiments, but the charge amplifier circuit 6 is replaced with the charge amplifier circuit 72 shown in FIG. The capacitance detection circuit 200 has the same configuration except that the charge amplifier circuit is replaced.

The charge amplifier circuit 72 has the configuration shown in FIG. 23, and the same reference numerals are given to the same configurations as those of the charge amplifier circuit 6. Since the measurement method of the active matrix sensor is slightly different, only the measurement operation in which the charge amplifier circuit 72 is different from the charge amplifier circuit 6 will be described.
Before measuring the fingerprint data, the switch 73 is turned off, the switch 74, the switch 124, and the cell selection switch 71 connected to the plurality of column wirings corresponding to the bit 1 are turned on, and the unit capacity cell 70 (detection capacity Cs ) And the parasitic capacitance Cp is accumulated until the voltage Vc reaches the voltage Vc, and all the switches are temporarily turned off.

  In the measurement of fingerprint data, when the switch 73 and the cell selection switch 71 are turned on at the same time while the switch 74 and the switch 124 are kept in the off state, each unit capacity cell 70 is placed on the sensor unit 4C. Therefore, a voltage corresponding to the sum of charges generated by the voltage difference between the voltage Vc and the reference voltage Vref (total value due to multiplexing of the column wiring groups) is generated at the output terminal of the operational amplifier 121. This is stored in the internal memory of the decoding arithmetic circuit 10 as measurement data d. Multiplexed measurement data strings di are obtained by repeating this sequence of charge accumulation and detection voltage measurement. Then, the decoding operation circuit 10 obtains voltage data ds corresponding to the capacity Cs of each unit capacity cell 70 from the data string of the measurement data d stored in the internal memory by the operation of the decoding process already described.

  In the first to fifth embodiments, the PN code or the orthogonal code is used over one period, the column wiring to be measured is multiplexed, and the voltage data at each intersection is decoded. However, measurement may be performed over a plurality of periods, measurement data of a plurality of periods may be added, and decoding may be performed from the addition result. Thereby, random noise superimposed on the measurement signal in the row wiring can be canceled, and the measurement accuracy can be further improved.

  The program for realizing the function of the processing unit in FIG. 1 is recorded on a computer-readable recording medium, and the program recorded on the recording medium is read into the computer system and executed, thereby executing the first to first programs. The configuration of the fifth embodiment may be controlled. Here, the “computer system” includes an OS and hardware such as peripheral devices. The “computer system” includes a WWW system having a homepage providing environment (or display environment). The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. Further, the “computer-readable recording medium” refers to a volatile memory (RAM) in a computer system that becomes a server or a client when a program is transmitted via a network such as the Internet or a communication line such as a telephone line. In addition, those holding programs for a certain period of time are also included.

  The program may be transmitted from a computer system storing the program in a storage device or the like to another computer system via a transmission medium or by a transmission wave in the transmission medium. Here, the “transmission medium” for transmitting the program refers to a medium having a function of transmitting information, such as a network (communication network) such as the Internet or a communication line (communication line) such as a telephone line. The program may be for realizing a part of the functions described above. Furthermore, what can implement | achieve the function mentioned above in combination with the program already recorded on the computer system, and what is called a difference file (difference program) may be sufficient.

It is a block diagram which shows the structure of the fingerprint sensor using the capacity | capacitance detection circuit by the 1st Embodiment of this invention. It is a conceptual diagram which shows the structural example of the sensor part 4 in FIG. It is a conceptual diagram explaining the measurement of the fingerprint data using the sensor part 4 in FIG. 5 is a conceptual diagram illustrating a configuration example of a sensor element 55 formed at each intersection of a column wiring of the column wiring group 2 and a row wiring of the row wiring group 3 in the sensor unit 4 of the area sensor type. FIG. FIG. 2 is a conceptual diagram illustrating a configuration example of a sensor unit 4 and a charge amplifier circuit 6 in FIG. 1. FIG. 2 is a conceptual diagram illustrating a configuration example of a code generation circuit 20 in the code generation unit 1 of FIG. 1. It is a conceptual diagram explaining the autocorrelation for every period of the arrangement | sequence of a bit string in the phase change by the bit shift of the bit string in a PN code. FIG. 3 is a conceptual diagram illustrating an operation example in which the column wiring selector 13 in FIG. 1 sets the column wiring group 2 as a plurality of column wiring groups and selects a measurement target from these column wiring groups. FIG. 9 is a conceptual diagram illustrating a capacitance measurement operation in which the column wiring selector 13 in FIG. 8 selects a predetermined column wiring group and multiplexes column wirings included in the column wiring group. In the capacity detection circuit of the present invention, the column wiring group 2 is divided into column wiring groups, and is a conceptual diagram showing the measurement order of capacitance measurement in each column wiring group. 5 is a timing chart for explaining the detection signal and the operation of the charge amplifier circuit 6 in the first embodiment. 6 is a timing chart for explaining the operation of controlling the selector and the column wiring in the first embodiment. FIG. 9 is a conceptual diagram illustrating a capacitance measurement operation in which the column wiring selector 13 in FIG. 8 selects a predetermined column wiring group and multiplexes column wirings included in the column wiring group. 4 is a table showing data stored in each register of the storage shift register 23 at each time (t1 to t15). FIG. 9 is a conceptual diagram illustrating a capacitance measurement operation in which the column wiring selector 13 in FIG. 8 selects a predetermined column wiring group and multiplexes column wirings included in the column wiring group. It is a block diagram which shows the structural example at the time of using the 1st-4th embodiment for a line sensor. In the 2nd Embodiment of this invention, it is a conceptual diagram explaining the combination of the column wiring which divides the column wiring group 2 into a column wiring group. It is a conceptual diagram which shows the drive of the column wiring in each column wiring group by PN code (or orthogonal code) using the column wiring selector 13A of 3rd Embodiment. In the fourth embodiment, for each column wiring group selected by a column wiring selector, a conceptual diagram illustrating multiplexed driving of column wirings included in this column wiring group with orthogonal codes. It is a conceptual diagram explaining the procedure which produces | generates the Walsh code which is an orthogonal code in 4th Embodiment. It is a figure which shows the table of the Walsh code memorize | stored in the code memory 221 in FIG. It is a conceptual diagram which shows the structural example of the active matrix type sensor in 5th Embodiment. FIG. 10 is a block diagram showing a configuration of a charge amplifier circuit 72 in a fifth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1A, 1B ... Code generation part 2 ... Column wiring group 3 ... Row wiring group 4, 4B, 4C ... Sensor part 5 ... Column wiring drive part 6 ... Charge amplifier circuit 7, 72 ... Sample hold circuit 8 ... Selector circuit 9 A / D converter 10 Decoding operation circuit 11 Timing control circuit 13, 13A Column wiring selector 20 Code generation circuit 21 Shift register 22 EXOR (exclusive OR)
23 ... Shift register for storage 50 ... Substrate 51 ... Insulating film 52 ... Air gap 54 ... Film 100, 200 ... Capacitance detection circuit 220 ... Orthogonal code reading circuit 221 ... Code memory 222 ... Address counter 223 ... Storage register

Claims (9)

It is a capacitance detection circuit that detects a change in capacitance at a crossing portion of a column wiring and a row wiring as a voltage value by intersecting a row wiring with respect to a plurality of column wirings,
Code generating means for generating a code having orthogonality in time series;
Column wiring group selection means for dividing the plurality of column wirings into column wiring groups made up of a predetermined number of column wirings and selecting a column wiring group to be measured;
Column wiring driving means for driving a plurality of column wirings on the basis of the reference symbols for each column wiring group selected in sequence;
Capacitance measuring means for outputting a sum of current values corresponding to the capacitance of the intersections of the row wiring and the plurality of driven column wirings as a measurement voltage;
A capacitance detection circuit comprising: a decoding operation unit that performs a product-sum operation on the column wiring groups using the measurement voltage and the sign to obtain a voltage value corresponding to the capacitance of each intersection.   2. An area-type sensor in which a plurality of the row wirings are arranged for the plurality of column wirings and the intersections are arranged in a matrix, and the capacitance of the intersections is measured. The capacitance detection circuit described.   2. The line-type sensor in which one row wiring is arranged for the plurality of column wirings and the intersections are arranged in series, and the capacitance of the intersections is measured. The capacitance detection circuit described.   4. The capacitance detection circuit according to claim 1, wherein the column wiring group is formed by a predetermined number of adjacent column wirings. 5.   4. The capacitance detection circuit according to claim 1, wherein the column wiring group is formed by column wirings having a predetermined interval.   The code generation means generates a PN code having autocorrelation, sequentially shifts a bit arrangement of the PN code, and outputs the code as a PN code having a phase different in time series. The capacitance detection circuit according to claim 1.   6. The capacitance detection circuit according to claim 1, wherein the code generation means generates Walsh orthogonal codes having different bit arrangements in time series and outputs the codes as the codes.   A fingerprint sensor comprising the capacitance detection circuit according to claim 1. A row detection method is a capacitance detection method for detecting a change in capacitance at a crossing portion of a column wiring and a row wiring as a voltage value by intersecting a row wiring with respect to a plurality of column wirings.
A code generation process for generating a code having orthogonality in time series;
Dividing the plurality of column wirings into column wiring groups made up of a predetermined number of column wirings, and selecting a column wiring group to be measured;
For each column wiring group selected in sequence, a column wiring driving process for driving a plurality of column wirings based on the sign,
A capacitance measuring process for outputting a sum of current values corresponding to the capacitance of the intersections of the row wiring and the plurality of driven column wirings as a measurement voltage;
A capacitance detection method comprising: performing a product-sum operation on the column wiring groups by the measurement voltage and the sign to obtain a voltage value corresponding to the capacitance of each intersection.

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