JP2005084120A - Cross talk correction method of electro-optical device, its correction circuit, electro-optical device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a cross talk correction method of an electro-optical device capable of highly accurately correcting voltage applied to pixels. <P>SOLUTION: A correction circuit 600 is added to an electro-optical device 10. When a positive selection voltage +V<SB>S</SB>, for instance, is applied to a scanning line 312 in the latter period of one horizontal scanning period, the correction circuit 600 detects a spike due to change-over from a voltage -V<SB>D</SB>/2 to a voltage +V<SB>D</SB>/2 in a data line 212 in the former half period, discriminates whether the magnitude of the detected spike is equal to the threshold value or greater and, on the other hand, applies a pulse to a selective voltage supply line 511 in the latter half period which follows the former half period. Therein, the pulse has a pulse width according to the time length of discriminated detection period during which the magnitude of the spike is discriminated to be equal to the threshold value or greater and at the same time has the same polarity with the spike's polarity. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a crosstalk correction method for an electro-optical device for suppressing the occurrence of so-called lateral crosstalk, a correction circuit therefor, an electro-optical device, and an electronic apparatus.

In an electro-optical device that performs display by an electro-optical change of an electro-optical material such as a liquid crystal, horizontal crosstalk that a difference in display quality occurs in the horizontal (row) direction is regarded as a problem. It is considered that the cause of the horizontal crosstalk is that a spike generated when the voltage of the data line (segment electrode) is switched fluctuates the effective voltage value applied to the pixel.
As a technique for suppressing the occurrence of such horizontal crosstalk, for example, a technique for correcting a voltage applied to a pixel by reducing the pulse width of a scanning signal in accordance with the number of segment electrodes whose voltage is switched (for example, a patent) Refer to Document 1. This is referred to as technology (A)), and a technology for detecting a distortion (spike) of a drive signal and adding a correction signal to a data signal or the like (see, for example, Patent Document 2. This technology (B). ) And)).
Japanese Patent Laid-Open No. 11-52922 (refer to FIG. 1, FIG. 2, paragraph 0027, etc.) JP 2000-56292 A (see FIG. 1, paragraph 0017, etc.)

However, in the above technique (a), since the spike itself is not detected, the correction accuracy of the applied voltage is not necessarily high. In the technique (b), although a spike is detected, a correction signal is generated via a filter, an amplifier circuit, etc., so that there is a considerable operational delay. For this reason, a correction signal for canceling the spike is added immediately after the spike, and the applied voltage to the pixel changes significantly. Therefore, particularly when the pixel has a capacitance as in a liquid crystal device, the effective voltage value The correction accuracy is not necessarily high.
The present invention has been made in view of such circumstances, and an object of the present invention is to correct crosstalk of an electro-optical device capable of correcting an effective voltage value applied to a pixel with high accuracy. A method, a correction circuit thereof, an electro-optical device, and an electronic apparatus are provided.

In order to achieve the above object, a crosstalk correction circuit according to the present invention includes a pixel provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines, and the scanning lines for each horizontal scanning period. A scanning line driving circuit that sequentially selects and applies a selection voltage to the selected scanning line over the latter half period of the one horizontal scanning period, and one data line among the first half period of the one horizontal scanning period, While the non-lighting voltage is applied for the period corresponding to the gray level of the pixel corresponding to the intersection of the data line and the selected scanning line, and the lighting voltage is applied for the remaining period, the pixel of the latter half period is applied. Crosstalk generated in an electro-optical device having a data line driving circuit that applies a lighting voltage over a period according to the gray level and a non-lighting voltage over the remaining period is corrected. A detection circuit that detects a spike associated with switching from one of the lighting voltage or the non-lighting voltage to the other during the first half of one horizontal scanning period, and a magnitude of the spike detected by the detection circuit A discriminating circuit for discriminating whether or not the threshold value is equal to or greater than a threshold value, and adding to the selection voltage based on a time length of a detection period in which the magnitude of the spike is determined by the discriminating circuit to be equal to or greater than the threshold value An additional pulse specifying circuit for generating a pulse specifying signal indicating a pulse to be performed, and a pulse having the same polarity as the spike detected by the detection circuit based on the pulse specifying signal generated by the additional pulse specifying circuit, And an additional circuit for adding to the selection voltage in the second half period following the first half period. The present invention can also be implemented as a crosstalk correction method.
The lighting voltage (ON voltage) in the present invention is a voltage of a data signal applied to a data line when a certain scanning line (hereinafter referred to as “target scanning line”) is focused. In this period, a voltage having a polarity opposite to the selection voltage applied to the scanning line of interest is referred to. On the other hand, the non-lighting voltage (off voltage) is the same polarity as the selection voltage applied to the target scanning line during the period of the voltage of the data signal applied to the data line during the period when the target scanning line is selected. Voltage.
When the voltage of the data line is switched from one of the lighting voltage and the non-lighting voltage to the other in the first half period of one horizontal scanning period, the same number of data lines are turned on or off in the latter half period when the selection voltage is applied. Therefore, a spike having a polarity opposite to that of the first half period and substantially the same magnitude is generated. Using this fact, the correction circuit according to the present invention suppresses the occurrence of lateral crosstalk. That is, according to the correction circuit of the present invention, if a spike associated with voltage switching is detected in the first half period and it is determined that the magnitude is greater than or equal to the threshold value, a pulse having the same polarity as that spike is Since it is added in the latter half period, the reverse polarity spike in the latter half period in which the selection voltage is applied is canceled.
By the way, as a configuration for canceling the spike generated in the selection voltage in the second half period, a pulse having a pulse width corresponding to the time length determined by the determination circuit as being larger than the threshold value is added to the selection voltage as it is. Configuration is also conceivable. However, depending on the relationship between the size of the spike and the time length of the detection period, the pulse added to the selection voltage may be excessive, or the pulse added to the selection voltage may be insufficient to cancel the spike. . On the other hand, according to the present invention, the pulse specification for specifying the pulse to be added to the selected voltage based on the time length of the detection period in which the size of the spike is determined to be greater than or equal to the threshold value by the determination circuit. Since a signal is generated, an appropriate pulse can be added to the selected voltage regardless of the relationship between the magnitude of the spike and the time length of the detection period.

  For example, the time length of the detection period may change exponentially according to the change in the size of the spike. In such a case, if a pulse having a pulse width corresponding to the time length of the detection period is added to the selection voltage as it is, the pulse added to the selection voltage becomes excessive, especially when the detection period is long, and instead the selection voltage is set. It can also cause distortion. Therefore, it is desirable that the additional pulse specifying circuit generate the pulse specifying signal so that the pulse width indicated by the pulse specifying signal changes linearly with respect to the change in the time length of the detection period. According to this configuration, a pulse having an appropriate magnitude (pulse width or voltage level) is added to the selected voltage, so that the spike generated in the selected voltage is effectively canceled and the selected voltage is maintained at an intended value. can do.

  In another aspect, the determination circuit outputs a pulse signal having a pulse width corresponding to the time length of the detection period, and the additional pulse specifying circuit outputs a pulse width of the pulse signal output from the determination circuit. The detection circuit generates detection pulse data indicating the detection pulse data, and converts the detection pulse data generated by the encoding circuit into additional pulse data indicating a pulse width of a pulse to be added to the selection voltage. A conversion circuit that outputs the pulse specifying signal. In a further preferred aspect, the conversion circuit has a table in which a time length of a detection period and a pulse width of a pulse to be added to the selection voltage are associated with each other, and based on the contents of the table, the detection pulse The additional pulse data is generated from the data. According to this configuration, for example, the additional pulse data can be obtained quickly with a simpler configuration as compared with the configuration in which the additional pulse data is generated by performing an operation on the detection pulse data. Of course, the additional pulse data may be generated by performing a predetermined calculation on the detected pulse data.

In another aspect of the present invention, the additional circuit adds the pulse at a timing at which switching is performed from the other of the lighting voltage or the non-lighting voltage in the second half period. According to this aspect, the spike generated in the selection voltage in the second half period can be accurately canceled by adding a pulse having the same polarity as the spike generated in the first half period.
Further, in another aspect of the present invention, the data line driving circuit has, for one data line, an elapsed time from the start of the first half period to switching to the other of the lighting voltage or the non-lighting voltage, The elapsed time from the start of the second half period following the first half period to the switching to one of the lighting voltage or the non-lighting voltage is made substantially the same, and the additional circuit sets a spike that is equal to or greater than the threshold value to 1 There is a delay circuit that delays by half the length of the horizontal scanning period and outputs the delayed pulse. According to this aspect, it becomes easy to simplify the configuration.
Further, when the electro-optical device adopts AC driving as in the liquid crystal device, the scanning line driving circuit reverses the polarity of the selection voltage around an intermediate voltage between the lighting voltage and the non-lighting voltage, and detects the detection A configuration in which two systems each having a circuit, the determination circuit, the additional pulse specifying circuit, and the additional circuit are provided for the positive electrode and the negative electrode, respectively, is also desirable. According to this configuration, the spike of the selection voltage is canceled in both the positive electrode and the negative electrode in AC driving.

  In another aspect of the present invention, the detection circuit includes a first capacitor having one end connected to a specific voltage supply line. According to this aspect, it is possible to detect spikes associated with voltage switching in the first half period with a simple configuration. In yet another aspect, the scanning line driving circuit includes a switch that connects a power supply line that supplies the selection voltage to the selected scanning line in a second half period, and the additional circuit is connected to the power supply line. It includes a second capacitor connected at one end. According to this aspect, adding a pulse having the same polarity as that of the first half period to the selection voltage in the second half period is realized by a simple configuration.

  In order to achieve the above object, an electro-optical device according to the present invention includes the correction circuit. More specifically, the electro-optical device according to the present invention sequentially selects pixels provided corresponding to intersections of a plurality of scanning lines and a plurality of data lines, and the scanning lines every horizontal scanning period. In addition, a scanning line driving circuit that applies a selection voltage to the selected scanning line over the latter half of the one horizontal scanning period, and the data line in the first half of the one horizontal scanning period for one data line. And applying a non-lighting voltage over a period corresponding to the gray level of the pixel corresponding to the intersection of the selected scanning line and a lighting voltage over the remaining period, while the gray level of the pixel during the latter half period. A data line driving circuit that applies a lighting voltage over a period corresponding to the non-lighting voltage over the remaining period, and either the lighting voltage or the non-lighting voltage in the first half of one horizontal scanning period. A detection circuit for detecting a spike associated with switching to the other, a determination circuit for determining whether the magnitude of the spike detected by the detection circuit is greater than or equal to a threshold value, and the magnitude of the spike by the determination circuit An additional pulse specifying circuit for generating a pulse specifying signal for specifying a pulse to be added to the selection voltage based on a time length of a detection period determined to be equal to or greater than the threshold; and the additional pulse specifying And an additional circuit for adding a pulse having the same polarity as the spike detected by the detection circuit to the selection voltage in a second half period following the first half period based on a pulse specifying signal generated by the circuit. According to this electro-optical device, similarly to the correction circuit, the reverse polarity spike in the second half period is canceled, and a pulse having an appropriate magnitude can be added to the selection voltage in order to cancel the spike. In addition, since the electronic apparatus according to the present invention includes the electro-optical device as a display device, high-quality display with reduced occurrence of crosstalk becomes possible.

  According to the present invention, since the effective voltage value applied to the pixel is corrected with high accuracy, the occurrence of lateral crosstalk is effectively suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings shown below, the dimensions and ratios of the components are appropriately different from the actual ones in order to make the components large enough to be recognized on the drawings.

  FIG. 1 is a block diagram illustrating a configuration of an electro-optical device according to an embodiment of the invention. As shown in this figure, the electro-optical device 10 includes a liquid crystal panel 100, a control circuit 400, a voltage generation circuit 500, and a correction circuit 600. Among them, in the liquid crystal panel 100, a plurality of data lines (segment electrodes) 212 are formed extending in the column (Y) direction, while a plurality of scanning lines (common electrodes) 312 are extended in the row (X) direction. Is formed. Pixels 116 are formed at points where the data lines 212 and the scanning lines 312 intersect. Each pixel 116 includes a TFD (Thin Film Diode) 220 which is an example of a two-terminal switching element, and a liquid crystal capacitor 118 connected in series to the TFD 220. Among these, the liquid crystal capacitor 118 has a configuration in which a liquid crystal, which is an example of an electro-optical material, is sandwiched between a scanning line 312 and a rectangular pixel electrode, as will be described later. In the present embodiment, for convenience of explanation, the total number of scanning lines 312 is 320, the total number of data lines 212 is 240, and the description will be made as a matrix type display device having 320 rows by 240 columns. However, the present invention is not limited to this.

  Next, the scanning line driving circuit 350 is a circuit that supplies the scanning signals Y1, Y2, Y3,..., Y320 to the scanning lines 312 in the first, second, third,. is there. Specifically, the scanning line driving circuit 350 selects 320 scanning lines 312 one by one as will be described later, and selects a selected voltage for the selected scanning line 312 and a non-selected voltage for the other scanning lines 312. Are supplied respectively. Further, the data line driving circuit 250 applies data signals X1, X2, X3,..., X240 corresponding to display contents (gradation) to the pixels 116 located on the scanning line 312 selected by the scanning line driving circuit 350. Are supplied via the data lines 212 in the first, second, third,..., 240th columns, respectively. Note that detailed configurations of the data line driving circuit 250 and the scanning line driving circuit 350 will be described later.

  On the other hand, the control circuit 400 supplies various control signals and clock signals for horizontally scanning the liquid crystal panel 100 to the data line driving circuit 250, while providing the liquid crystal panel 100 to the scanning line driving circuit 350. This circuit supplies various control signals and clock signals for vertical scanning. Further, the control circuit 400 supplies 3-bit gradation data Dn indicating the gradation of the pixel 116 in eight stages from “0” to “7” in synchronization with the vertical scanning and the horizontal scanning. Here, as a premise of this embodiment, the brightest white display is instructed when the 3-bit gradation data Dn is (000), and the luminance gradually decreases as the 3-bit decimal value increases. When the gradation data Dn is (111), the darkest black display is instructed. Further, assume that the liquid crystal panel 100 is in a normally white mode in which white display is performed when no voltage is applied. As described above, the lighting voltage refers to the voltage of the data signal having the opposite polarity to the selection voltage. Therefore, it should be noted that in the normally white mode, the pixel becomes dark when the lighting voltage is applied.

Next, the voltage generation circuit 500 is a circuit that generates a voltage ± V _S and a voltage ± V _D / 2 used for the liquid crystal panel 100, respectively. Of these, the voltage ± V _S is used as a selection voltage in the scanning signal. The voltage + V _S is supplied to the scanning line driving circuit 350 through the resistor R1 and the supply line 511, and the voltage −V _S is supplied through the resistor R4 and the supply line 514, respectively. On the other hand, the voltage ± V _D / 2 is a non-selection voltage in the scanning signal, the voltage + V _D / 2 is supplied via the resistor R2 and the supply line 512, and the voltage −V _D / 2 is supplied via the resistor R3 and the supply line 513. Each is supplied to the scanning line driving circuit 350. Further, the voltage ± V _D / 2 is also used as the data voltage of the data signal, and thus is supplied to the data line driving circuit 250 respectively. The voltage −V _D / 2 is also supplied to the correction circuit 600, which will be described later.

  Next, FIG. 2 is a perspective view showing the overall configuration of the liquid crystal panel 100. FIG. 3 is a cross-sectional view showing a configuration when the liquid crystal panel 100 is broken along the X direction. As shown in these drawings, the liquid crystal panel 100 includes an element substrate 200 located on the back side and a counter substrate 300 facing the element substrate 200 on the observation side. The counter substrate 300 is slightly smaller than the element substrate 200. The element substrate 200 and the counter substrate 300 are bonded to each other with a certain gap by a sealing material 110 mixed with conductive particles 114 that also serve as spacers. For example, a TN (Twisted Nematic) type liquid crystal 160 is sealed in a space surrounded by the element substrate 200 and the counter substrate 300 and the sealing material 110. As shown in FIG. 2, the sealing material 110 is formed in a frame shape along the inner peripheral edge of the counter substrate 300, but a part of the sealing material 110 is opened to enclose the liquid crystal 160. The opening is sealed by the sealing material 112 after the liquid crystal 160 is sealed.

  On the surface of the counter substrate 300 facing the element substrate 200, there is an alignment film 308 that is rubbed in a certain direction, in addition to the scanning lines 312 that are strip-shaped electrodes formed extending in the row (X) direction. Is formed. Here, as shown in FIG. 3 in particular, one end of the scanning line 312 is extended to a region where the sealing material 110 is formed. Further, a polarizer 131 is attached to the outer side (observation side) of the counter substrate 300 (not shown in FIG. 2), and the direction of the absorption axis is selected according to the direction of the rubbing treatment to the alignment film 308. Yes.

  On the other hand, a rectangular pixel electrode 234 is formed on the surface of the element substrate 200 facing the counter substrate 300 adjacent to the data line 212 formed extending in the Y (column) direction, and is constant. An alignment film 208 that is rubbed in the direction is formed. Further, the element substrate 200 is provided with wirings 342 in one-to-one correspondence with the scanning lines 312. Specifically, one end of the wiring 342 is formed so as to face one end of the corresponding scanning line 312 in the region where the sealing material 110 is formed, as particularly shown in FIG. Here, the conductive particles 114 are dispersed in the sealing material 110 at a ratio such that at least one or more conductive particles 114 are interposed in a portion where one end of the scanning line 312 and one end of the wiring 342 face each other. With this configuration, the scanning line 312 formed on the counter substrate 300 is connected to the wiring 342 on the counter surface of the element substrate 200 through the conductive particles 114.

  In addition, one end of the data line 212 formed on the element substrate 200 has a configuration in which it is drawn out of the sealing material 110 formation region as it is. Further, a polarizer 121 is attached to the outside (back side) of the element substrate 200 (not shown in FIG. 2), and the direction of the absorption axis is selected according to the direction of the rubbing treatment to the alignment film 208. Yes. The liquid crystal panel 100 according to the present embodiment is a transmissive liquid crystal panel that performs display (transmissive display) by transmitting incident light from the back side to the observation side. Accordingly, a backlight unit that uniformly irradiates light is provided on the back side of the element substrate 200, but is not shown because it is not directly related to the present case.

  Next, the configuration outside the display area in the liquid crystal panel 100 will be described. As shown in FIG. 2, a data line driving circuit 250 for driving the data line 212 and a scanning line for driving the scanning line 312 are provided on two sides of the element substrate 200 protruding from the counter substrate 300. The drive circuits 350 are each mounted by COG (Chip On Glass) technology. Therefore, the data line driving circuit 250 directly supplies a data signal to the data line 212, while the scanning line driving circuit 350 indirectly supplies the scanning signal to the scanning line 312 through the wiring 342 and the conductive particles 114. Supply. In addition, one end of an FPC (Flexible Printed Circuit) substrate 150 is joined in the vicinity of the outside of the region where the data line driving circuit 250 is mounted. Note that the other end of the FPC board 150 is connected to the control circuit 400, the voltage generation circuit 500, and the correction circuit 600 in FIG.

  Note that, unlike FIG. 2, the data line driving circuit 250 and the scanning line driving circuit 350 in FIG. 1 are respectively located on the left side and the upper side of the liquid crystal panel 100. This will explain the electrical configuration. It is just a measure for convenience. In addition, instead of COG mounting the data line driving circuit 250 and the scanning line driving circuit 350 on the element substrate 200, for example, TCP (Tape Automated Bonding) technology is used to mount each driver and power supply circuit TCP ( Tape Carrier Package) may be electrically and mechanically connected by an anisotropic conductive film.

  Next, a detailed configuration of the pixel 116 in the liquid crystal panel 100 will be described. FIG. 4 is a perspective view showing the structure. In this figure, for convenience of explanation, the alignment films 208 and 308 and the polarizers 121 and 131 in FIG. 3 are omitted. As shown in FIG. 4, rectangular pixel electrodes 234 made of a transparent conductor such as ITO (Indium Tin Oxide) are arranged in a matrix on the surface of the element substrate 200 facing the counter substrate 300. Of these, the pixel electrodes 234 arranged in the same column are commonly connected to one data line 212 via the TFD 220. Here, when viewed from the substrate side, the TFD 220 is formed of a tantalum simple substance, a tantalum alloy, or the like, and is branched from the data line 212 in a T shape, and the first conductor 222 It is composed of an anodized insulator 224 and a second conductor 226 such as chromium, and has a conductor / insulator / conductor sandwich structure. Therefore, the TFD 220 has a diode switching characteristic in which the current-voltage characteristic is nonlinear in both positive and negative directions.

  In FIG. 4, the pixel electrode 234, the data line 212, and the like are formed directly on the surface of the element substrate 200 that faces the counter substrate 300, but a transparent insulator is formed on the element substrate 200. A configuration in which the pixel electrode 234, the data line 212, and the like are formed on the upper surface is preferable. The reason why it is better to form such an insulator is to prevent the first conductor 222 from being peeled off by heat treatment after the deposition of the second conductor 226 and to the first conductor 222 as an impurity. This is to prevent diffusion.

  On the other hand, on the surface of the counter substrate 300 facing the element substrate 200, a plurality of scanning lines 312 made of ITO or the like extend in the row direction perpendicular to the data lines 212 and form a plurality of columns in the row direction. It faces the pixel electrode 234. Accordingly, the scanning line 312 functions as a counter electrode of the pixel electrode 234. Accordingly, the liquid crystal capacitor 118 in FIG. 1 is constituted by the liquid crystal 160 sandwiched between the scanning line 312 and the pixel electrode 234 at the intersection of the data line 212 and the scanning line 312.

In such a configuration, when either the selection voltage + V _S or −V _S forcing the TFD 220 to be in a conductive state (on) is applied to the scanning line 312, regardless of the data voltage applied to the data line 212. The TFD 220 corresponding to the intersection of the scanning line 312 and the data line 212 is turned on, and charges corresponding to the difference between the selection voltage and the data voltage are accumulated in the liquid crystal capacitor 118 connected to the turned on TFD 220. . Even if the non-selection voltage is applied to the scanning line 312 after the charge is accumulated to turn off the TFD 220, the accumulation of the charge in the liquid crystal capacitor 118 is maintained. In the liquid crystal capacitor 118, the alignment state of the liquid crystal 160 changes according to the amount of accumulated charge, and the amount of light passing through the polarizers 121 and 131 changes according to the amount of accumulated charge. Therefore, if it is assumed that the selection voltage does not fluctuate, the accumulation amount of charges in the liquid crystal capacitor 118 is controlled for each pixel 116 according to the data voltage when the selection voltage is applied, so that a predetermined gradation is obtained. Display is possible.

Here, various signals generated by the control circuit 400 in FIG. 1 will be described. First, signals used on the Y (vertical scanning) side will be described. First, the start pulse DY is a pulse output at the beginning of one vertical scanning period (1F), as shown in FIG. Second, the clock signal YCK is a Y-side reference signal and has a period of one horizontal scanning period (1H) as shown in FIG. Third, the polarity instruction signal POL is a signal for designating the polarity of the selection voltage to be applied when the scanning line 312 is selected. For example, if it is at the H level, the polarity selection signal + V _S is set to L If the level, a negative selection voltage -V _S is specified. As shown in the figure, the polarity instruction signal POL has its logic level inverted every horizontal scanning period (1H) within one vertical scanning period, and the same in the vertical scanning period that is temporally changed. In the horizontal scanning period in which the scanning line 312 is selected, the logic level is inverted. Fourth, the control signal INH is a signal for defining a selection voltage application period in one horizontal scanning period (1H). As will be described later, in this embodiment, since the selection voltage is applied in the latter half of one horizontal scanning period (1H), the control signal INH becomes H level in the latter half.

Next, signals used on the X (horizontal scanning) side will be described. First, the latch pulse LP is a pulse output at the beginning of one horizontal scanning period (1H) as shown in FIG. Secondly, as shown in the figure, the reset signal RES is a pulse output at the beginning of the first half period and at the beginning of the second half period of one horizontal scanning period (1H). Third, the AC drive signal MX is a signal for AC driving the pixel 116 on the data line side, and as shown in the figure, the phase is advanced by 90 degrees from the polarity instruction signal POL on the Y side. It is in. In other words, in one horizontal scanning period (1H) in which the positive voltage + V _S is designated as the selection voltage, the AC drive signal MX becomes the H level in the first half period and becomes the L level in the second half period. In the one horizontal scanning period (1H) in which the negative voltage −V _S is designated, the L level is set in the first half period and the H level is set in the second half period. Fourth, as shown in the figure, the gradation code pulse GCP has gray gradations (gradation data (110), excluding white or black) in each of the first half period and the second half period of one horizontal scanning period. This pulse is output at a timing corresponding to (101), (100), (011), (010), (gradation indicated by (001)). In the figure, the position where the gradation code pulse GCP is arranged is actually selected in consideration of the applied voltage-density (transmittance) characteristic (VT characteristic) of the pixel 116. Each pulse is not equally spaced.

Next, the scanning line driving circuit 350 will be described. FIG. 5 is a block diagram showing a configuration of the scanning line driving circuit 350.
In this figure, a shift register 352 has a number of stages of 320 bits corresponding to the total number of scanning lines 312 and sequentially shifts a start pulse DY supplied at the beginning of one vertical scanning period by a clock signal YCK, thereby transferring a transfer signal. Ys1, Ys2, Ys3,..., Ys320. The transfer signals Ys1, Ys2, Ys3,..., Ys320 correspond to the scanning lines 312 of the first row, the second row, the third row,. That is, when one of the transfer signals becomes H level, it is instructed that the horizontal scanning period (1H) in which the corresponding scanning line 312 is to be selected.

Subsequently, the voltage selection signal forming circuit 354 outputs voltage selection signals a, b, c, and d that specify the voltage applied to the scanning line 312 of each row based on the transfer signal, the polarity instruction signal POL, and the control signal INH. To do. The voltage selection signals a, b, c and d are at the active level (H level) exclusively. Here, when the voltage selection signal a becomes H level, the selection of + V _S (positive polarity selection voltage) is instructed. Similarly, when the voltage selection signals b, c, and d become H level, + V _D / 2 (positive polarity non-selection voltage), −V _D / 2 (negative polarity non-selection voltage), and −V _S (negative polarity selection), respectively. Voltage) selection is instructed.

In this embodiment, as described above, the period during which the selection voltage + V _S or −V _S is applied is 0.5H (denoted as “1 / 2H”) in the second half of one horizontal scanning period (1H). . The non-selection voltage is + V _D / 2 after the selection voltage + V _S is applied, and is −V _D / 2 after the selection voltage −V _S is applied. It is fixed. The voltage selection signal forming circuit 354 outputs the voltage selection signals a, b, c, and d for the scanning lines 312 in each row so that the voltage levels of the scanning signals have the following relationship. That is, any one of the transfer signals Ys1, Ys2,..., Ys320 becomes H level, it is specified that it is a horizontal scanning period in which the corresponding scanning line 312 is to be selected, and further, the control signal INH becomes H level. When the second half of the horizontal scanning period is indicated, the voltage selection signal forming circuit 354 first sets the voltage level of the scanning signal to the scanning line 312 to the signal level of the polarity instruction signal POL. Second, when the second half period ends, the voltage selection signal is generated so that the selection voltage becomes the non-selection voltage corresponding to the selection voltage.

Specifically, the voltage selection signal forming circuit 354, the control in a period in which the signal INH is at H level, the polarity indicating signal POL is the second half of the voltage selection signal a to select the positive polarity selection voltage + V _S if H level When the second half period ends and the control signal INH transitions to the L level, the voltage selection signal b for selecting the positive non-selection voltage + V _D / 2 is output as the H level. In the latter half period in which the signal INH is at the H level, if the polarity instruction signal POL is at the L level, the voltage selection signal d for selecting the negative selection voltage −V _S is set to the H level in the period, and then the control signal INH is When transitioning to the L level, the voltage selection signal c for selecting the negative polarity non-selection voltage −V _D / 2 is output as the H level.

  The selector group 358 has four switches 3581 to 3584 for each scanning line 312. One ends of these switches 3581 to 3584 are connected to supply lines 511 to 514, respectively, and the other ends of the switches 3581 to 3584 are commonly connected to corresponding scanning lines 312. Voltage selection signals a, b, c, and d are supplied to the gates of the switches 3581 to 3584, respectively. Each of the switches 3581 to 3584 becomes conductive between one end and the other end when the voltage selection signals a, b, c, and d inputted to the gate become H level. Accordingly, each scanning line 312 is connected to any one of the supply lines 511 to 514 via the one of the switches 3581 to 3584 that is turned on.

Next, the voltage waveform of the scanning signal supplied by the scanning line driving circuit 350 will be described.
First, as shown in FIG. 6, the start pulse DY is sequentially shifted by the shift register 352 in accordance with the clock signal YCK every horizontal scanning period (1H), and these are transferred as transfer signals Ys1, Ys2,. Is output. Here, when the latter half period (1 / 2H) arrives in one horizontal scanning period in which the transfer signal corresponding to a certain scanning line 312 is at the H level, according to the logic level of the polarity instruction signal POL in the latter half period. Thus, the selection voltage to the scanning line 312 is determined.

Specifically, the voltage of the scanning signal supplied to a certain scanning line 312 is such that the polarity instruction signal POL is, for example, H during the latter half period (1 / 2H) of one horizontal scanning period in which the scanning line 312 is selected. If it is level, it becomes a positive polarity selection voltage + V _S , and then holds a positive polarity non-selection voltage + V _D / 2 corresponding to the selection voltage. When one vertical scanning period (1F) elapses, in the latter half of one horizontal scanning period, the polarity instruction signal POL is inverted and becomes L level, so the voltage of the scanning signal supplied to the scanning line 312 is , The negative selection voltage −V _S , and then the negative non-selection voltage −V _D / 2 corresponding to the selection voltage is held.

Therefore, the scanning signal Y1 to the scanning line 312 in the first row in a certain vertical scanning period has a positive polarity corresponding to the H level of the polarity instruction signal POL in the latter half of one horizontal scanning period, as shown in FIG. sexual selection voltage + _{V S,} and the hold then a positive polarity non-selection voltage _{+ V} D / 2. In the second half of the next one horizontal scanning period corresponding to the scanning line 312, the level of the polarity instruction signal POL becomes an L level logically inverted from the previous selection, so that the scanning signal Y1 to the scanning line 312 is The negative selection voltage −V _{S is obtained} , and then the negative non-selection voltage −V _D / 2 is maintained. This cycle is repeated thereafter. In addition, since the logic level of the polarity instruction signal POL is inverted every horizontal scanning period (1H), the scanning signal supplied to each scanning line 312 is changed every horizontal scanning period (1H), that is, the scanning line. The polarity is alternately inverted every line 312. For example, in a certain vertical scanning period, if the selection voltage of the scanning signal Y1 in the first row is the positive selection voltage + V _S , the selection voltage of the scanning signal Y2 in the second row is selected as the negative polarity after the lapse of one horizontal scanning period. The voltage is −V _S.

  Next, the data line driving circuit 250 will be described. FIG. 7 is a block diagram showing a configuration of the data line driving circuit 250. In this figure, an address control circuit 252 is a circuit for generating a row address Rad used for reading gradation data, and resets the row address Rad by a start pulse DY supplied at the beginning of one vertical scanning period. In this configuration, stepping is performed by a latch pulse LP supplied every horizontal scanning period. A display data RAM (Random Access Memory) 254 is a dual port RAM having a storage area corresponding to the pixels 116 of 320 rows × 240 columns. On the write side, the display data RAM (Random Access Memory) 254 is supplied from the control circuit 400 in FIG. The tone data Dn is written to the address specified by the write address Wad from the control circuit 400, while on the reading side, 240 pieces of gradation data Dn at the address specified by the row address Rad are batched. Read out.

Next, the decoder 256 resets the voltage selection signals e and f for selecting the data voltages of the data signals X1, X2,..., X240 according to the read 240 gradation data Dn. This is a circuit exclusively generating from the signal RES, the AC drive signal MX, and the gradation code pulse GCP. Here, the voltage selection signal e instructs selection of + V _D / 2, and the voltage selection signal f instructs selection of −V _D / 2, respectively. More specifically, the decoder 256 generates the following voltage selection signal when paying attention to the gradation data Dn of a specific column among the 240 read out data.

  In other words, the decoder 256 is not limited as long as the gradation data Dn specifies an intermediate gradation other than white (000) and black (111) in one horizontal scanning period (1H) in which the polarity instruction signal POL is at the H level. First, the reset signal RES supplied at the beginning of the first half period (1 / 2H) of one horizontal scanning period is reset to a level opposite to the level of the AC drive signal MX, and second, the gradation code At the falling edge of the pulse GCP corresponding to the gradation data Dn, it is set to the same level as the AC drive signal MX, and thirdly, supplied at the beginning of the second half period (1 / 2H) of one horizontal scanning period. And fourth, the same level as the AC drive signal MX at the falling edge of the grayscale code pulse GCP corresponding to the grayscale data Dn. Generating a voltage selection signal so as to re-set. However, in the one horizontal scanning period (1H) in which the polarity instruction signal POL is at the H level, the decoder 256 is at a level obtained by inverting the AC drive signal MX if the gradation data Dn is white (000). If the gradation data Dn is black (111), the voltage selection signals e and f are generated so as to be at the same level as the AC drive signal MX.

  In addition, the decoder 256 is configured such that in one horizontal scanning period (1H) in which the polarity instruction signal POL is at the L level, a voltage in which the voltage is exchanged is different from that in the one horizontal scanning period (1H) in which the polarity instruction signal POL is at the H level. Selection signals e and f are generated. The decoder 256 generates such a voltage selection signal using each of the 240 gradation data Dn read out.

  The selector group 358 has two switches 2581 and 2582 for one column of data lines 212. One ends of these switches 2581 and 2582 are connected to supply lines 512 and 513, respectively, while the other ends are commonly connected to corresponding data lines 212. Voltage selection signals e and f are supplied to the gates of the switches 2581 and 2582, respectively. Each of switches 2581 and 2582 becomes conductive between one end and the other end when voltage selection signals e and f inputted to the gate are in an active level. Accordingly, each data line 212 is connected to either the supply line 512 or 513 through the switch 2581 and 2582 that is turned on.

  FIG. 8 is a diagram showing the relationship between the binary number display of the gradation data Dn input to the decoder 256 and the data signal Xj obtained by decoding it. FIG. 9 shows a scanning signal Yi for the i-th scanning line 312, a scanning signal Yi + 1 for the scanning line 312 one row lower than this, and a data signal Xj for the j-th data line 212. It is a figure which shows each signal waveform in. For this data signal Xj, the scanning lines 312 in the i-th row and the (i + 1) -th row and the pixels 116 located in the data line 212 in the j-th column are set to white display, black display, and intermediate gray display. Each case is shown.

As shown in these figures, one horizontal scanning period (1H) is divided into two to be divided into a first half period and a second half period, and the scanning signals Yi and Yi + 1 have a selection voltage applied over the second half period (1 / 2H). In other words, the period during which the data signal Xj takes the lighting voltage becomes longer as the gradation of the pixel 116 becomes darker. Here, the lighting voltage is negative data voltage −V _D / 2 when the selection voltage is positive + V _S , and is positive data when the selection voltage is negative −V _S. Voltage + V _D / 2. On the other hand, the data signal in the first half period prior to the second half period has a relationship in which the voltage is reversed from that of the data signal in the second half period. Therefore, focusing on one horizontal scanning period (1H), the data signal Xj takes the voltage + V _D / 2 and −V _D / 2 at a ratio of 50%. For this reason, even if the gradation of the pixel 116 continues in any pattern, in one vertical scanning period (1F), the total of the period in which the data signal Xj takes the voltage −V _D / 2 and the voltage + V _D / 2 are taken. The cumulative period is the same as each other. This means that the effective voltage value applied to the pixels 116 in the non-selection period is the same across all the pixels 116. According to this configuration, a column (vertical) generated when displaying a checkered pattern in which white pixels and black pixels are alternately arranged in rows and columns, a zebra pattern in which the white pixels and black pixels are inverted for each row, or the like. Directional crosstalk is reduced. This vertical crosstalk is also described in FIG. 10 of Japanese Patent Application Laid-Open No. 2001-147671, for example.

By the way, in this embodiment, since the scanning line 312 is formed of a metal having a relatively high resistivity such as ITO, the scanning line 312 in the i-th row is taken as an example, as shown in FIG. Line 312 is capacitively coupled to all data lines 212 from the first column to the 240th column. In addition, not only the scanning lines 312 but also all wirings and signal lines in the liquid crystal panel 100 are similarly capacitively coupled to all the data lines 212. In particular, since the supply lines 511 to 514 are partially formed on the substrates 200 and 300, the degree of coupling with the data line 212 is large. When the data signal on the data line 212 is switched from one of the voltages + V _D / 2 and −V _D / 2 to the other, a spike (differential waveform noise) appears on the scanning line 312, the wiring, and the supply line. Here, in the display image of the liquid crystal panel 100, when the correlation between the gradations of the pixels is low (for example, when displaying a natural image), the voltage switching timing of the data signal is distributed over a large number of data lines 212. Because the spike itself is small, the effect can be almost ignored. On the other hand, in the display image of the liquid crystal panel 100, when the correlation between the gradations of adjacent pixels is high (for example, when displaying a data image), the voltage switching timing of the data signal is set to each data line. Concentrate over 212. Therefore, in this case, although the number of spikes is small, the spike itself becomes large, so the influence cannot be ignored. In particular, when the average value during the application period of the selection voltage varies due to the spike, the effective voltage value applied to the liquid crystal capacitor 118 changes, so that a gradation different from the intended original gradation is displayed.

  For example, as shown in FIG. 11A, consider a case where a rectangular white area is displayed in a window with a gray background in the display area 100a of the liquid crystal panel. In this case, as shown in FIG. 11B, the image actually displayed is different from the white areas B-E and the areas B-D and B-F adjacent in the row (lateral) direction. The gray areas A-D, A-E, A-F, C-D, CE, and C-F become brighter. Since this display difference occurs in the row direction, it is particularly called horizontal crosstalk in order to distinguish it from the above-described vertical crosstalk.

This lateral crosstalk will be examined with a signal waveform applied to the liquid crystal capacitor 118. In FIG. 11B, when the scanning line 312 belonging to the row range A or the row range C is selected, the gradations of the pixels located on the scanning line 312 are all gray in the background. For this reason, as shown in FIG. 12A, the voltages of all the data signals are the first in one horizontal scanning period (1H) if a positive selection voltage is applied to the scanning line 312. It changes simultaneously in the middle of the first half period and in the middle of the second half period. Accordingly, relatively large spikes S0, S1, and S3 appear in the scanning signal in the direction in which the voltage is switched. Among these, spikes S0 and S1 appear during a period in which the scanning signal is a non-selection voltage, and thus have little influence on the effective voltage value. However, the spike S3 is so appears during a period in which the scanning signal is selected voltage, the selection voltage + V _S is large fluctuation, the voltage waveform applied to the pixel 116 indicated by the difference between the scan signal and the data signal, in FIG. As shown in the part P, it is greatly distorted. In FIG. 12A, one horizontal scanning period in which the positive selection voltage + V _S is obtained in the latter half period has been described. However, in the one horizontal scanning period in which the negative selection voltage −V _S is obtained, the waveform shown in FIG. Since the polarity is inverted around the voltage reference point, the voltage waveform applied to the pixel 116 is also greatly distorted. Therefore, in the pixels 116 belonging to the row range A and the row range C (the pixels 116 belonging to the regions AD, AE, AF, CD, CE, and CF), the applied voltage is the target. Therefore, it will be brighter in the normally white mode.

On the other hand, in FIG. 11B, when the scanning line 312 belonging to the row range B is selected, the pixels 116 positioned on the scanning line 312 are of two types, gray and white of the background color. For this reason, as shown in FIG. 12B, the data signal is a data line belonging to the column ranges D and F related to the background if a positive selection voltage + V _S is applied to the scanning line 312. And those supplied to the data lines belonging to the column range E relating to the white region. In other words, if the scanning line 312 belonging to the row range A or the row range C is selected, all the data signals correspond to the same gray, whereas the scanning line belonging to the row range B If 312 is selected, the number of data signals corresponding to the gray is approximately halved. Therefore, spikes S0, S1, and S3 that appear when the scanning line 312 belonging to the row range B is selected are smaller than when the scanning line 312 that belongs to the row range A or the row range C is selected. For this reason, the spike S3 appearing in the second half period does not fluctuate the selection voltage + V _S taken by the scanning signal so much, and the applied voltage waveform to the pixel 116 is also less distorted as shown by the portion Q in the figure. . The same applies to one horizontal scanning period in which a negative selection voltage -V _S is taken. Therefore, the gradation of the pixels 116 in the regions BD and BF is only slightly brighter.

  As a result, the pixels 116 belonging to the regions AD, AE, AF, CD, CE, and CF, which should have the same gradation, and the pixels in the regions BD and BF With 116, the gradation of the pixel 116 belonging to the former area becomes brighter than the gradation of the pixel 116 belonging to the latter area, and this is visually recognized as a horizontal cross-roke. As described above, the cause of the horizontal crosstalk is that a difference occurs in the degree of spike depending on the number of data lines (data signals) whose voltage changes at the same timing. As a result, each time the scanning line 312 is selected, This is considered to be because the average values during the application period differ. In addition, the point that the voltage applied to the pixels 116 belonging to the row range A and the row range C is insufficient is irrelevant to whether or not the white region is displayed. Similarly, it is considered that the voltage applied to the pixel 116 is insufficient. However, when displaying the same gray color on the entire surface, the influence of the spike S3 acts uniformly on all the pixels 116, so that it is not visually recognized as a difference in brightness, and thus the problem of lateral crosstalk does not become apparent. . However, this is a problem in that the target voltage is not correctly applied to the pixel 116.

The correction circuit 600 shown in FIG. 1 is a circuit for suppressing the occurrence of this lateral crosstalk. FIG. 13 is a block diagram showing the configuration of the correction circuit 600. As shown in the figure, one end of the coupling capacitor 602 is connected to a supply line 513 that supplies a negative data voltage (and non-selection voltage) −V _D / 2. On the other hand, the other end of the coupling capacitor 602 is connected to a terminal in which is an intermediate point between the resistors 604 and 606 connected in series between the supply line of the power supply voltage Vdd and the ground line Gnd. The resistance values of the resistors 604 and 606 are selected so that the potential of the terminal “in” becomes zero, which is an intermediate value of the voltage ± V _D / 2. In the present embodiment, the potential of the ground line Gnd is not zero but a negative value (for example, −V _D / 2).

As described above, the supply line 513 is capacitively coupled to the data lines 212 from the first column to the 240th column, similarly to the scanning line 312. For this reason, when the data line 212 is switched from one of the voltages + V _D / 2 and −V _D / 2 to the other, spikes in the switching direction are supplied to the supply line 513, and the data having the same switching timing is used. It appears in a size corresponding to the number of lines 212. At this time, the coupling capacitor 602 cuts ± V _D / 2, which is the DC component of the supply line 513, and passes the spike, which is an AC component, so that a spike with reference to zero potential appears at the terminal in. (See FIG. 18). In other words, the coupling capacitor 602 functions as a detection circuit that detects a spike that is generated when the voltage of the data signal is switched.

  On the other hand, the terminal in is connected to the positive input terminal (+) of the comparator 612. A threshold voltage Vth1 adjusted by a resistor 614 is supplied to the negative input terminal (−) of the comparator 612. The terminal in is also connected to the negative input terminal (−) of the comparator 622, and the threshold voltage Vth <b> 2 adjusted by the resistor 624 is supplied to the positive input terminal (+) of the comparator 622. Comparators 612 and 622 respectively output signals Cmp1 and Cmp2 that become H level when the voltage supplied to the positive input terminal (+) becomes equal to or higher than the voltage supplied to the negative input terminal (−). That is, the comparator 612 (622) is at the H level only during a period when the spike is greater than the absolute value of the threshold voltage Vth1 (Vth2), and greater than the absolute value of the threshold voltage Vth1 (Vth2). The signal Cmp1 (Cmp2) is output. In this manner, the comparators 612 and 622 function as a determination circuit that determines whether or not the spike detected by the coupling capacitor 602 is equal to or greater than a threshold value. The threshold voltages Vth1 and Vth2 have a relationship of Vth1> 0> Vth2 and Vth1≈−Vth2.

The pulse addition circuit 650 is a circuit that adds a pulse having the same polarity as the spike detected by the coupling capacitor 602 in the first half period of one horizontal scanning period to the selection voltage in the second half period following the first half period. The pulse addition circuit 650 includes a conversion / delay circuit 660, buffers 672 and 682, and coupling capacitors 674 and 684. Among them, the conversion / delay circuit 660 specifies a pulse to be added to the selection voltage based on the signal Cmp1 output from the comparator 612 or the signal Cmp2 output from the comparator 622, and the specified pulse is set to 1 This circuit outputs the signal P1 or P2 after being delayed by a period of / 2H. The buffer 672 multiplies the signal P1 by a coefficient a. One end of the coupling capacitor 674 is connected to the output terminal of the buffer 672, the other end of the coupling capacitor 674 is connected to the supply line 511 of the positive polarity selection voltage + V _S. Further, the buffer 682 inverts the polarity by multiplying the signal P2 by a coefficient (−a). One end of the coupling capacitor 684 is connected to the output end of the buffer 682, while the other end of the coupling capacitor 684 is connected to the supply line 514 of the negative selection voltage −V _S. With this configuration, the pulse of the signal P1 or P2 output from the conversion / delay circuit 660 is output to the supply line 511 or 514 via the coupling capacitor 674, so that the supply line 511 or 514 includes A spike that is a differential waveform of the pulse of the signal P1 or P2 appears. By superimposing the spike on the selection voltage of the scanning signal, the variation in the selection voltage due to the spike accompanying the variation in the level of the data signal can be suppressed.

  Next, the configuration of the conversion / delay circuit 660 will be described. FIG. 14 is a block diagram showing the configuration of the conversion / delay circuit 660. In this figure, only one system from the signal Cmp1 by the comparator 612 to the output of the signal P1 is shown. The conversion / delay circuit 660 also includes a system from the signal Cmp2 to the signal P2 output by the comparator 622, but is not shown because it has the same configuration as the system from the signal Cmp1 to the signal P1. ing.

  In FIG. 14, the selector 661 outputs the gradation code pulse GCP to the output terminal A in the first half of one horizontal scanning period in which the control signal INH is at L level, while in the second half period in which the control signal INH is at H level. Output to the output terminal B. The delay unit 662 delays the gradation code pulse GCP supplied from the output terminal A of the selector 661 by a time d and outputs it as a gradation code pulse GCPa. The writer 663 defines the writing timing of data (hereinafter referred to as “additional pulse data”) output from the additional pulse specifying circuit 700 described later by the falling timing of the gradation code pulse GCPa. Further, the reader 664 defines the read timing of the additional pulse data by the falling timing of the gradation code pulse GCPb supplied from the output terminal B of the selector 661.

  On the other hand, of the pulses included in the signal Cmp1, the remover 665 has a timing at which the latch pulse LP is output (that is, the start timing of one horizontal scanning period) and a period during which the control signal INH is at the H level (that is, one horizontal). This is a circuit that removes pulses included in the second half of the scanning period) and outputs them as a signal C1. Hereinafter, a pulse appearing in the signal C1 in the first half of one horizontal scanning period, that is, a pulse remaining in the signal C1 without being removed by the remover 665 will be referred to as a “detection pulse”. When the detection pulse appears in the signal C1, the additional pulse specifying circuit 700 is added to the selection voltage based on the pulse width (that is, the time length during which the spike appearing on the supply line 513 exceeds the threshold value). A power pulse (hereinafter referred to as “additional pulse”) is specified, and data indicating the pulse width of this additional pulse is output as additional pulse data.

  The memory 667 is a FIFO (First-In First-Out) type memory. The memory 667 sequentially stores the additional pulse data output from the additional pulse specifying circuit 700 at the timing specified by the writer 663 and sequentially reads at the timing specified by the reader 664. When the additional pulse data is read from the memory 667, the decoder 668 decodes the pulse having the width indicated by the additional pulse data only when the additional pulse data is changed, and outputs the pulse as the signal P1. It is.

  By the way, as described above, spikes having different sizes appear at the terminal in depending on the number of data lines (data signals) whose voltage changes at the same timing. FIG. 15 is a graph showing a relationship between a plurality of types of spikes having different sizes (that is, voltage levels at peak points) and the threshold value Vth1. In the figure, the horizontal axis indicates time and the vertical axis indicates voltage. Since the signal Cmp1 output from the comparator 612 becomes H level when the voltage input to the positive input terminal (+) becomes equal to or higher than the threshold voltage Vth1 supplied to the negative input terminal (−), it is removed. In the signal C1 output from the detector 665, a detection pulse having a width corresponding to the length of time when the detected spike becomes equal to or higher than the threshold voltage Vth1 appears. Therefore, the pulse width of this detection pulse differs depending on the detected spike size. Specifically, as shown in 15, the pulse width of the detection pulse Pa that appears in the signal C1 when the spike Sa occurs is “Ta”, and the detection pulse Pb that appears in the signal C1 when the spike Sb occurs The pulse width is “Tb”. On the other hand, since the attenuation characteristic of the spike depends on the time constant of the circuit composed of a resistor and a capacitor, the pulse width of the detection pulse appearing in the signal C1 varies exponentially with respect to the magnitude (height) of the spike. It becomes. For example, taking FIG. 15 as an example, the size of the spike Sd is about twice the size of the spike Sb, but the pulse width “Td” of the detection pulse Pd corresponding to the spike Sd corresponds to the spike Sb. This is about four times the pulse width “Tb” of the detection pulse Pb.

  Here, as a configuration for adding a pulse to the selected voltage, the detection pulse appearing in the signal C1 output from the remover 665 is delayed by the memory 667 while maintaining its pulse width, and then added as an additional pulse. A configuration for adding to the selection voltage is also conceivable. However, as described above, since the pulse width of the detection pulse appearing in the signal C1 changes exponentially with respect to the magnitude of the spike, the spike superimposed on the selected voltage may be excessive under this configuration. is there. For example, even when the distortion of the selection voltage is appropriately corrected when the detection pulse Pa appears in the signal C1, when the detection pulse Pd appears, the selection voltage exceeds the range sufficient to compensate the distortion. In some cases, the spikes are superimposed and the selected voltage is distorted. In addition, although the signal C1 was mentioned here as an example, the same malfunction may arise also about the signal C2 which has a pulse of reverse polarity to this.

  In order to solve these problems, the additional pulse specifying circuit 700 according to the present embodiment selects the selection voltage based on the pulse width of the detection pulse that appears in the signal C1 (that is, the time length during which the spike is greater than or equal to the threshold value). The pulse width of the additional pulse to be added to is specified. FIG. 16 is a block diagram showing a specific configuration of the additional pulse specifying circuit 700. As shown in the figure, the additional pulse specifying circuit 700 includes an encoder 710 and a conversion circuit 720.

  Among these, the encoder 710 is a circuit that outputs data indicating the pulse width of the detection pulse (hereinafter referred to as “detection pulse data”) when a detection pulse is generated in the signal C1. Specifically, the encoder 710 includes a counter 711, an inverter 712, and a latch circuit 713. The signal C1 output from the remover 665 is input to the counter 711 and the inverter 712. The counter 711 counts the rise of the clock signal CLK and outputs the count value, while resetting the count value at the timing when the signal C1 rises. The clock signal CLK is a signal supplied from the control circuit 400 and has a period sufficiently shorter than the pulse width of the detection pulse appearing in the signal C1. On the other hand, the inverter 712 inverts the level of the signal C1 and outputs it to the latch circuit 713. The latch circuit 713 is a circuit that latches the count value of the counter 711 as detection pulse data at the timing when the output signal from the inverter 712 rises, that is, when the signal C1 falls. That is, a count value corresponding to the pulse width of the detection pulse appearing in the signal C1 is output as detection pulse data. In this configuration, when a detection pulse is generated in the signal C1, a time longer than the pulse width is required from the rising edge to the determination of the pulse width.

  On the other hand, the conversion circuit 720 is a circuit that outputs additional pulse data corresponding to the detected pulse data based on a conversion table 721 set in advance. As shown in FIG. 17, the conversion table 721 is a table in which the pulse width of the detection pulse (that is, the time length during which the spike is equal to or greater than the threshold) and the pulse width of the additional pulse are associated with each other. When the detection pulse data is supplied from the encoder 710, the conversion circuit 720 specifies the pulse width of the additional pulse associated with the pulse width indicated by the detection pulse data in the conversion table 721, and uses the specified pulse width. The indicated data is output as additional pulse data. This output signal corresponds to the “pulse specific signal” in the present invention. As shown in FIG. 17 and FIG. 15, the conversion table 721 associates both pulse widths such that the pulse width of the additional pulse increases as the pulse width of the detection pulse increases. However, the content of the conversion table 721 is that the pulse width of the additional pulse corresponds to the change in the pulse width of the detection pulse appearing in the signal C1, that is, the change in the time length of the period in which the magnitude of the spike is determined to be greater than or equal to the threshold value. Is selected to change linearly (linearly). For example, in FIG. 15, focusing on the spike Sb and a spike Sd having a size about twice that of the spike Sb, the pulse width of the additional pulse Pd ′ specified when the spike Sd is generated is specified when the spike Sb is generated. This is about twice the pulse width of the additional pulse Pb ′.

  The contents of the conversion table 721 can be appropriately changed according to a command given from the outside. An interface 731 shown in FIG. 16 is a circuit that receives this command and supplies it to the register 730. The command input from the outside includes a command for designating the content of the change to the conversion table 721 and a command for instructing to reflect the content of the change in the conversion table 721 of the conversion circuit 720. When a command for designating change contents is supplied from the interface 731, the register 730 stores the change contents. On the other hand, when a command instructing the reflection of the change content is supplied from the interface 731, the change content stored in the register 730 at that time is overwritten in the conversion table 721.

Next, the operation of the correction circuit 600 will be described. 18 and 19 are timing charts for explaining the operation of the correction circuit 600. FIG.
As described above, when the data line 212 is switched from one of the voltages + V _D / 2 and −V _D / 2 to the other, the supply line 513 corresponds to the number of data lines having the same switching timing. A spike of size appears. At this time, the coupling capacitor 602 passes spikes that are alternating current components. Accordingly, as shown in FIG. 18, when the data signal is switched from the voltage −V _D / 2 to + V _D / 2, the positive spike appears at the terminal in (see FIG. 13), and the data signal is When switching from + V _D / 2 to -V _D / 2, a negative spike appears.

  Since the comparator 612 outputs the signal Cmp1 that is at the H level when the voltage at the terminal “in” becomes equal to or higher than the threshold voltage Vth1, among the positive spikes, the voltage is equal to or higher than the threshold voltage Vth1. Is replaced with a pulse that is at the H level only during a period when the threshold voltage Vth1 or higher is reached, and is output as a signal Cmp1. Similarly, the comparator 622 replaces a negative spike whose voltage is equal to or lower than the threshold voltage Vth2 with a pulse that becomes H level only during a period when the voltage is equal to or lower than the threshold voltage Vth2, and generates the signal Cmp2. Output. On the other hand, among the pulses included in the signal Cmp1, those output in the start timing of one horizontal scanning period (1H) and in the latter half period (1 / 2H) are removed by the remover 665 as shown in FIG. Is done. The pulses included in the signal Cmp2 are similarly removed by a system remover not shown in FIG. Therefore, as shown in FIG. 18, the output signal C1 (C2) from the remover 665 is output in the first half period (except for the start timing) of one horizontal scanning period among the pulses included in the signal Cmp1 (Cmp2). Only things.

  Next, the encoder 710 of the additional pulse specifying circuit 700 outputs detection pulse data indicating the pulse width of the detection pulse appearing in the signal C1. The conversion circuit 720 searches the detection pulse width of the conversion table 721 for the pulse width indicated by the detection pulse data, and outputs additional pulse data indicating the additional pulse width associated therewith. For example, taking FIG. 17 as an example, if the pulse width indicated by the detection pulse data is “80”, the conversion circuit 720 outputs additional pulse data indicating the pulse width “40”.

  By the way, as described above, when a detection pulse is generated in the signal C1, it takes time until the pulse width is determined from the rising edge. In FIG. 19, in the first half period (1 / 2H) of one horizontal scanning period, after the pulse S1a is generated (when the signal C1 rises), the additional pulse data S1b corresponding to the pulse width is output slightly. There is a time delay. Since the voltage switching of the data signal occurs at the fall of the gradation code pulse GCP, ideally, the timing at which the pulse S1a rises coincides with the timing at which the gradation code pulse GCP falls. However, in reality, the comparators 612 and 622 have an operation delay, so the timings of the two do not match.

  On the other hand, in the first half period (1 / 2H) of one horizontal scanning period, since the control signal INH is at the L level, the output terminal A is selected by the selector 661, and the gradation code pulse GCPa is more than the gradation code pulse GCP. Output is delayed by time d. At the fall timing of the delayed gradation code pulse GCPa, additional pulse data is written into the memory 667. The reason for designating the write timing of the memory 667 in this way by the fall of the delayed gradation code pulse GCPa is that the operation delay of the comparators 612 and 622 occurs as described above, and the pulse S1a This is because a time delay is generated after the generation of the additional pulse data S1b corresponding to the pulse width is output, and the write timing of the memory 667 coincides with the generation of the pulse S1a. This is because if the configuration is specified by the trailing edge of the key code pulse GCP, the width of the additional pulse is written in an undetermined state.

Next, in the second half period (1 / 2H) of one horizontal scanning period, the control signal INH becomes H level. Therefore, the selector 661 selects the output terminal B, and the gradation code pulse GCP is output as it is as the gradation code pulse GCPb. Then, the additional pulse data written in the memory 667 is sequentially read at the falling timing of the gradation code pulse GCPb. Only when there is a change in the additional pulse data, the decoder 668 decodes the pulse having the width indicated by the additional pulse data. For example, as shown in FIG. 18 or FIG. 19, the pulse of the signal C1 in the first half period The pulse S1d obtained by converting S1a based on the conversion table 721 is delayed from the pulse S1a by approximately half a period (0.5H) of one horizontal scanning period, and is output as the signal P1. That is, as shown in FIG. 18, the spike S1 generated when the data signal is switched from the voltage −V _D / 2 to + V _D / 2 in the first half period is replaced with the detection pulse S1a by the comparator 612. After the additional pulse S1d obtained by converting is delayed, the data signal is output at the timing of switching from the voltage + V _D / 2 to −V _D / 2 in the second half period.

Since the pulse S1d included in the signal P1 is output to the supply line 511 via the buffer 672 and the coupling capacitor 674, a positive spike that is a differential waveform of the pulse S1d appears on the supply line 511. As described above, the scanning line driving circuit 350 turns on the switch 3581 corresponding to the selected scanning line 312 in the second half period and connects the supply line 511 to the scanning line 312, so that the scanning line 312 has a positive polarity. Therefore, a positive spike, which is a differential waveform of the pulse S1d, is directly superimposed on the scanning signal. In the scanning line 312, a negative spike S3 appears at the timing when the data signal switches from the voltage + V _D / 2 to −V _D / 2 in the latter half period, but a positive spike also appears at the same timing. As a result, both cancel each other. Therefore, the selection voltage + V _S is kept substantially constant regardless of the voltage switching of the data signal.

The above operation, one horizontal scanning period the polarity indicating signal POL is at the H level, i.e., was the operation for one horizontal scanning period including a period late for applying a voltage + V _S as the selection voltage, the polarity indicating signal POL is Even during the period of the L level, the selection voltage −V _S is kept substantially constant by processing the detection pulse included in the signal C2 in the same manner. Specifically, in the second half of one horizontal scanning period in which the polarity instruction signal POL is at the L level, the data signal is switched from the voltage −V _D / 2 to + V _D / 2, so that the spike appearing at that timing is positive. . On the other hand, the additional pulse included in the signal P2 is positive, but after being inverted in polarity by the buffer 682, it is output to the supply line 514 via the coupling capacitor 684. A negative spike that is a differential waveform appears. Therefore, both spikes cancel each other even in the latter half of one horizontal scanning period in which the polarity instruction signal POL is at the H level, and the selection voltage −V _S is kept substantially constant.

As described above, the correction circuit 600 is replaced with the additional pulse having a width corresponding to the magnitude of the spike accompanying the voltage switching of the data signal in the first half period, and then delayed by the memory 667 and added in the second half period. Regardless of the size, the spike can be counteracted. For example, in FIG. 12A described above, since the spike S1 appearing in the first half period and the spike S3 appearing in the second half period are relatively large, the width of the detection pulse obtained by converting the spike appearing in the first half period is widened and output. The width of the additional pulse included in the signal P1 is also relatively wide. For this reason, as shown in FIG. 20 (a), the spike S1e superimposed on the scanning signal also increases, so that the selection voltage + V _S of the scanning signal is kept substantially constant, and as a result, the waveform of the voltage applied to the pixel 116 Can be almost eliminated.

In FIG. 12B, the spike S1 appearing in the first half period and the spike S3 appearing in the second half period are relatively small, so that the width of the detection pulse converted from the spike appearing in the first half period is also reduced, resulting in an output. The width of the additional pulse included in the signal P1 is also relatively narrow. For this reason, as shown in FIG. 20B, the spike S1e superimposed on the scanning signal is also reduced. In this case as well, the selection voltage + V _{S of the} scanning signal is kept substantially constant. Distortion of the applied voltage waveform to can be almost eliminated. For this reason, the pixel 116 belonging to the areas A-D, A-E, A-F, C-D, CE, and C-F and the areas B-D and B-F shown in FIG. Since the voltages applied to the pixel 116 to which it belongs are substantially equal to each other, it is possible to suppress lateral crosstalk. Furthermore, since the applied voltage of the pixels 116 belonging to these regions is substantially the target voltage, the display image also substantially coincides with the target image shown in FIG. Even if the same gray color is displayed on the entire surface, the voltage applied to the pixel 116 is not insufficient and the density is not lowered.

  As described above, according to the present embodiment, the spike that appears in the first half period is detected, and the spike that appears in the selection voltage in the second half period is canceled using this spike. Therefore, since the comparators 612 and 622 and the like are not required to operate at high speed, the power consumed in each unit can be suppressed.

  Further, according to the present embodiment, the pulse width of the detection pulse obtained from the spike is changed by the conversion circuit 720, and the spike of the selected voltage is canceled by the additional pulse after the change. Even in a configuration in which the pulse width of the detection pulse changes exponentially according to the change in the length, an appropriate pulse can always be added to the selection voltage. Moreover, in the present embodiment, the contents of the conversion table 721 can be appropriately changed by inputting a command. Therefore, after displaying the image as shown in FIG. 11, the user inputs a command appropriately while confirming this image, so that the conversion table 721 can effectively suppress the lateral crosstalk. The contents of can be adjusted.

  In the above embodiment, when the selection voltage is applied, the lighting voltage is applied while being moved backward in time, so that the data line driving circuit 250 applies the data line 212 to the data line 212 during the selection voltage application period. The supplied data signal was switched from the non-lighting voltage to the lighting voltage. However, the present invention is not limited to this, and the lighting voltage may be applied while being moved forward in time. In this configuration, the data line driving circuit 250 switches the data signal supplied to the data line 212 from the lighting voltage to the non-lighting voltage, contrary to the embodiment, during the selection voltage application period. In the embodiment, the correction circuit 600 is configured to detect spikes in the supply line 513. This is because the potential of the supply line 513 is the potential of the ground line Gnd, that is, the ground potential, which is most stable. Because. Therefore, another supply line, wiring, or the like may be used as long as the potential is stable.

  In the above embodiment, the configuration in which the pulse width of the additional pulse is specified so as to change linearly with respect to the change in the magnitude of the spike is exemplified. However, the relationship between the magnitude of the spike and the pulse width of the additional pulse is exemplified. Is not limited to this. In short, it is sufficient if the configuration is such that a pulse having a magnitude (pulse width or voltage level) that can effectively cancel the spike is specified based on the time length of the period in which the magnitude of the spike is equal to or greater than the threshold value.

  In the above-described embodiment, the correction circuit 600 is independent from the other components. However, for example, the correction circuit 600 may be integrated with one or both of the data line driving circuit 250 and the scanning line driving circuit 350. Further, the correction circuit 600 does not necessarily have to be configured as an integrated circuit in which all the components (the respective parts shown in FIGS. 13 and 14) are integrated, and these components are partially separated. It may be configured as an integrated circuit.

  The present invention is not limited to a transmissive display device, but is a reflective display device that performs display (reflective display) by reflecting incident light from the observation side to the observation side, and both transmissive and reflective displays. The present invention can also be applied to a transflective display device capable of achieving the above. Further, the number of gradations is not limited to “8”, and may be any other number of gradations (for example, 4, 16, 32, 64 gradations, etc.). A configuration may be adopted in which one dot is constituted by three pixels assigned to the respective colors R (red), G (green), and B (blue) to display a color image.

  In the above-described embodiment, the active matrix type liquid crystal panel 100 using the TFD 220 as an active element is illustrated. However, the passive matrix type electro-optical device in which the liquid crystal 160 is sandwiched by the intersection of the strip electrodes without using the active element. The present invention can also be applied. In the embodiment, the TFD 220 is connected to the data line 212 and the liquid crystal capacitor 118 is connected to the scanning line 312. Conversely, the TFD 220 is connected to the scanning line 312 and the liquid crystal capacitor 118 is connected to the data line 212. A configuration in which the lines 212 are connected to each other may be employed. Furthermore, the TFD 220 is only an example of a two-terminal switching element, and an element using a ZnO (zinc oxide) varistor, MSI (Metal Semi-Insulator), or two of these elements are connected in series in opposite directions. Alternatively, those connected in parallel can be used as a two-terminal switching element.

  In the above embodiment, a liquid crystal device using a TN type liquid crystal is exemplified, but STN (Super Twisted Nematic) type liquid crystal and anisotropy of visible light absorption in the major axis direction and the minor axis direction of the molecule are shown. A guest-host type liquid crystal in which a dye (guest) having a dye molecule is dissolved in a liquid crystal (host) having a certain molecular arrangement and the dye molecules are arranged in parallel with the liquid crystal molecules may be used. In addition, the liquid crystal molecules are aligned vertically with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned horizontally with respect to both substrates when a voltage is applied. Alternatively, liquid crystal molecules are aligned horizontally with respect to both substrates when no voltage is applied, while liquid crystal molecules are aligned vertically with respect to both substrates when voltage is applied (homogeneous alignment). It is good also as a structure of. Thus, in the present invention, various liquid crystal and alignment methods can be used.

  The present invention can also be applied to electro-optical devices other than liquid crystal devices. That is, the present invention can be applied to any device that displays an image using an electro-optical material that converts an electrical action such as supply of current or application of voltage into an optical action such as change in luminance or transmittance. For example, an EL display device using EL (Electro Luminescent) as an electro-optical material, an electrophoretic display device using microcapsules containing a colored liquid and white particles dispersed in the liquid as an electro-optical material, Twisted ball display using twisted balls painted in different colors for areas of different polarity as electro-optical materials, toner display using black toner as electro-optical materials, or electro-optics of high-pressure gas such as helium or neon The present invention is applied to various electro-optical devices such as a plasma display panel (PDP) used as a substance.

  Next, an electronic apparatus having the electro-optical device according to the above-described embodiment as a display device will be described. FIG. 21 is a perspective view showing a configuration of a mobile phone using the electro-optical device 10 according to the embodiment. As shown in this figure, the cellular phone 1200 includes the liquid crystal panel 100 described above together with a plurality of operation buttons 1202, an earpiece 1204, and a mouthpiece 1206. Note that components other than the liquid crystal panel 100 in the electro-optical device 10 are built in the housing, and thus do not appear on the appearance of the mobile phone 1200.

  FIG. 22 is a perspective view showing a configuration of a digital still camera in which the liquid crystal panel 100 is applied to a viewfinder. The silver salt camera sensitizes the film with the optical image of the subject, while the digital still camera 1300 generates and stores an imaging signal by photoelectrically converting the optical image of the subject with an imaging device such as a CCD (Charge Coupled Device). To do. Here, the liquid crystal panel 100 described above is provided on the back surface of the main body 1302 of the digital still camera 1300. Since the liquid crystal panel 100 performs display based on the imaging signal, it functions as a finder that displays the subject. A light receiving unit 1304 including an optical lens, a CCD, and the like is provided on the front side (the back side in FIG. 24) of the main body 1302. When the photographer confirms the subject image displayed on the liquid crystal panel 100 and presses the shutter button 1306, the CCD image pickup signal at that time is transferred and stored in the memory of the circuit board 1308. In the digital still camera 1300, a video signal output terminal 1312 for performing external display and an input / output terminal 1314 for data communication are provided on the side surface of the case 1302.

  Note that examples of the electronic apparatus in which the electro-optical device 10 can be used as a display device include a laptop computer, a liquid crystal television, and a viewfinder type in addition to the mobile phone shown in FIG. 21 and the digital still camera shown in FIG. (Or a monitor direct-view type) video recorder, car navigation device, pager, electronic notebook, calculator, word processor, workstation, videophone, POS terminal, device equipped with a touch panel, and the like. In any electronic device, high-quality display with reduced horizontal crosstalk can be realized with a simple configuration.

1 is a block diagram illustrating a configuration of an electro-optical device according to an embodiment of the invention. FIG. It is a perspective view which shows the structure of the same electro-optical apparatus. FIG. 3 is a cross-sectional view illustrating a configuration of a liquid crystal panel in the same electro-optical device. FIG. 2 is a partially broken perspective view showing a configuration of a pixel in the electro-optical device. FIG. 3 is a block diagram illustrating a configuration of a scanning line driving circuit in the electro-optical device. It is a figure which shows the waveform of the scanning signal by the scanning line drive circuit. FIG. 3 is a block diagram illustrating a configuration of a data driving circuit in the electro-optical device. It is a figure which shows the waveform of the data signal by the data line drive circuit. It is a figure which shows the waveform of the signal applied to the pixel in the same electro-optical device. It is a figure which shows the equivalent circuit of the scanning line etc. of i row, and each data line. It is a figure which shows the example of generation | occurrence | production of the horizontal crosstalk in the same electro-optical apparatus. It is a figure for demonstrating the cause of horizontal crosstalk. 2 is a block diagram illustrating a configuration of a correction circuit in the electro-optical device. FIG. It is a block diagram which shows the structure of the conversion / delay circuit in the same correction circuit. It is a figure which shows the relationship between the spike which generate | occur | produces in a supply line, a detection pulse, and an additional pulse. It is a block diagram which shows the structure of the additional pulse specific circuit in the correction circuit. It is a figure which shows the content of the conversion table used in the additional pulse specific circuit. It is a timing chart for explaining operation of the correction circuit. It is a timing chart for explaining operation of the correction circuit. It is a figure for demonstrating the correction | amendment operation | movement by the correction circuit. It is a perspective view which shows the structure of the mobile telephone using the same electro-optical apparatus. FIG. 2 is a perspective view illustrating a configuration of a digital still camera using the same electro-optical device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Liquid crystal panel, 116 ... Pixel, 212 ... Data line, 250 ... Data line drive circuit, 312 ... Scan line, 350 ... Scan line drive circuit, 400 ... Control circuit, 500 ... Voltage generation circuit, 600 ... Correction circuit, 602 604, coupling capacitor, 612, 622, comparator, 650, pulse addition circuit, 660, conversion / delay circuit, 667, memory, 700, additional pulse specifying circuit, 710, encoder, 720, conversion circuit, 721 ...... Conversion table.

Claims (7)

Pixels provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines;
A scanning line driving circuit that sequentially selects the scanning lines for each horizontal scanning period, and applies a selection voltage to the selected scanning lines over the latter half of the horizontal scanning period;
For one data line
During the first half of one horizontal scanning period, a non-lighting voltage is applied over a period corresponding to the gray level of the pixel corresponding to the intersection of the data line and the selected scanning line, and a lighting voltage is applied over the remaining period. on the other hand,
In the latter half period, the crosstalk generated in the electro-optical device having the data line driving circuit for applying the lighting voltage over the period corresponding to the gradation of the pixel and the non-lighting voltage over the remaining period is corrected. A circuit that
A detection circuit that detects a spike associated with switching from one of the lighting voltage or the non-lighting voltage to the other in the first half of one horizontal scanning period;
A determination circuit for determining whether the magnitude of the spike detected by the detection circuit is equal to or greater than a threshold;
An additional pulse specifying circuit that generates a pulse specifying signal indicating a pulse to be added to the selection voltage based on a time length of a detection period in which the size of the spike is determined to be greater than or equal to the threshold value by the determination circuit When,
An additional circuit for adding a pulse having the same polarity as the spike detected by the detection circuit to the selection voltage in the second half period following the first half period based on the pulse identification signal generated by the additional pulse identification circuit. A crosstalk correction circuit for an electro-optical device. The additional pulse specifying circuit generates the pulse specifying signal such that a pulse width indicated by the pulse specifying signal changes linearly with respect to a change in time length of the detection period. Item 4. The crosstalk correction circuit of the electro-optical device according to Item 1. The discrimination circuit outputs a pulse signal having a pulse width corresponding to the time length of the detection period,
The additional pulse specifying circuit includes:
An encoding circuit that generates detection pulse data indicating a pulse width of the pulse signal output from the determination circuit;
A conversion circuit that converts detection pulse data generated by the encoding circuit into additional pulse data indicating a pulse width of a pulse to be added to the selection voltage, and outputs the additional pulse data as the pulse specifying signal. The crosstalk correction circuit for an electro-optical device according to claim 1 or 2. The conversion circuit has a table in which a time length of a detection period and a pulse width of a pulse to be added to the selection voltage are associated with each other, and based on the contents of the table, the additional pulse is extracted from the detection pulse data. The crosstalk correction circuit of the electro-optical device according to claim 3, wherein data is generated. Pixels provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines;
A scanning line driving circuit that sequentially selects the scanning lines for each horizontal scanning period, and applies a selection voltage to the selected scanning lines over the latter half of the horizontal scanning period;
For one data line
During the first half of one horizontal scanning period, a non-lighting voltage is applied over a period corresponding to the gray level of the pixel corresponding to the intersection of the data line and the selected scanning line, and a lighting voltage is applied over the remaining period. on the other hand,
In the latter half period, the crosstalk generated in the electro-optical device having the data line driving circuit for applying the lighting voltage over the period corresponding to the gradation of the pixel and the non-lighting voltage over the remaining period is corrected. A way to
A spike associated with switching from one of the lighting voltage or the non-lighting voltage to the other in the first half of one horizontal scanning period;
Determine whether the detected spike size is greater than or equal to the threshold,
Based on the time length of the detection period in which the magnitude of the spike is determined to be greater than or equal to the threshold value, a pulse specifying signal indicating a pulse to be added to the selection voltage is generated,
A crosstalk correction method for an electro-optical device, wherein a pulse having the same polarity as the detected spike is added to the selection voltage in a second half period following the first half period based on the generated pulse specifying signal. Pixels provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines;
A scanning line driving circuit that sequentially selects the scanning lines for each horizontal scanning period, and applies a selection voltage to the selected scanning lines over the latter half of the horizontal scanning period;
For one data line
During the first half of one horizontal scanning period, a non-lighting voltage is applied over a period corresponding to the gray level of the pixel corresponding to the intersection of the data line and the selected scanning line, and a lighting voltage is applied over the remaining period. on the other hand,
A data line driving circuit that applies a lighting voltage over a period according to the gray level of the pixel in the latter half period and a non-lighting voltage over the remaining period;
A detection circuit that detects a spike associated with switching from one of the lighting voltage or the non-lighting voltage to the other in the first half of one horizontal scanning period;
A determination circuit for determining whether the magnitude of the spike detected by the detection circuit is equal to or greater than a threshold;
An addition for generating a pulse specifying signal for specifying a pulse to be added to the selection voltage based on a time length of a detection period in which the size of the spike is determined to be greater than or equal to the threshold value by the determination circuit A pulse identification circuit;
An additional circuit for adding a pulse having the same polarity as the spike detected by the detection circuit to the selected voltage based on a pulse specifying signal generated by the additional pulse specifying circuit in a second half period following the first half period; An electro-optical device comprising:   An electronic apparatus comprising the electro-optical device according to claim 6 as a display device.

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