JP2003044015A - Electro-optical device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the configuration and reduce the power consumption of an electro-optical device, and thereafter realize a multi-gradation displaying thereof. SOLUTION: A control circuit 400 outputs 11 gradation control pulses at regular intervals over a period in which a selection voltage is applied, and a converter circuit 500 converts 14 pieces among density data Dpix for indicating gradations of a pixel 116 except the lowest and highest values so that the 14 pieces correspond to each of the 11 gradation control pulses and the difference between the gradations indicated by the density data and those of the pixel actually displayed by the gradation data is eliminated, to the noted pixel.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to simplification of construction,
The present invention relates to an electro-optical device and electronic equipment capable of multi-gradation display while achieving low power consumption.

[0002]

2. Description of the Related Art In recent years, electro-optical devices that display by means of electro-optical changes in liquid crystal display, which are thin, compact, and have low power consumption, are alternatives to cathode ray tubes (CRTs).
It is being widely used as a device in various electronic devices and televisions. This electro-optical device can be roughly classified into an active matrix type in which pixels are driven by switching and a passive matrix type in which pixels are driven without using a switching element, when classified according to a driving method or the like.

Among them, the active matrix type further includes a type using a three-terminal type switching element such as a thin film transistor (TFT) and a thin film diode (TFD) depending on the type of the switching element. 2-terminal switching element, specifically, for example, MIM (Metal Insulator M
It can be roughly classified into a type using an (etal) element. Here, when comparing a type using a three-terminal switching element and a type using a two-terminal switching element, the type using a two-terminal switching element does not have a crossing portion of the wiring, so It is considered to be more advantageous than the type using a three-terminal type switching element in that a short-circuit failure does not occur in principle, the film forming process and the photolithography process can be shortened, and the power consumption is reduced. ing. On the other hand, since the passive matrix type does not have a switching element in the first place, it has a simple structure and can be easily reduced in cost.
It is considered to be more advantageous than the active matrix type.

Although there are some differences in details regarding the driving of pixels between such a passive matrix type electro-optical device and an active matrix type electro-optical device using a two-terminal type switching element, there are some differences in details. , As described below, are generally common.

For example, when a pixel of interest corresponding to the intersection of a certain scanning line (common electrode) and a certain data line (segment electrode) is displayed in black (on in normally white mode), a scanning line drive circuit is used. When the scanning line corresponding to the target pixel is selected and the selection voltage is applied, the data line driving circuit applies the lighting voltage for making the pixel black to the data line corresponding to the target pixel over the entire selection period. To do. On the other hand, when the target pixel is displayed in white (OFF in normally white mode), when the scanning line driving circuit applies a selection voltage to the scanning line corresponding to the target pixel, the data line driving circuit corresponds to the target pixel. A non-lighting voltage that makes the pixel white is applied to the data line for the entire selection period. Further, in the case where the pixel of interest is an intermediate gray of black and white, when the scanning line drive circuit applies a selection voltage to the scanning line corresponding to the pixel of interest, the data line drive circuit corresponds to the pixel of interest. The lighting voltage is applied to the data line only during the gray period of the selected period.

Here, in order to apply the lighting voltage only in the grayscale period of the selection period, in the period in which the selection voltage is applied, a pulse (grayscale) is associated with each value that can be taken as an intermediate grayscale. A configuration is known in which a control pulse) is supplied to the data line driving circuit. For example, the data line driving circuit counts the gradation control pulses in the selection period, and when the count result reaches a value corresponding to the gradation of the pixel of interest, the voltage applied to the data line is changed from the non-lighting voltage. The lighting voltage is switched to, or the lighting voltage is switched to a non-lighting voltage.

[0007]

However, it should be noted that in the liquid crystal device, there is no linear relationship between the period in which the lighting voltage is applied during the selection period and the actual gray scale of the pixel due to the period. For example, even if the period during which the lighting voltage is applied during the selection period is doubled, the pixel density does not double (normally white). For this reason,
A configuration is required in which the gradation control pulses supplied in the selection period are supplied at unequal intervals according to the gradation characteristics of the pixels in the applied liquid crystal device. Such a structure is described below. This not only complicates the configuration, but also hinders low power consumption.

For example, in order to supply the gradation control pulses to be supplied in the selection period at unequal intervals according to the gradation characteristics of the pixel, the source clock signal having an extremely high frequency is counted over the selection period. The gradation control pulse may be output each time the count result reaches each of the possible values of the intermediate gradation. However, in such a configuration, in addition to the counter, a comparator and a circuit for sequentially supplying a reference value for the comparison are required, which not only complicates the configuration but also increases the frequency. Since the clock signal is used, the power consumption due to the capacitive load cannot be ignored.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to reduce the power consumption while simplifying the structure, and to provide an electric display capable of multi-gradation display. An object is to provide an optical device and an electronic device.

[0010]

In order to achieve the above object, an electro-optical device according to an embodiment selects a pixel provided corresponding to the intersection of a scanning line and a data line and one scanning line. Then, a scanning line drive circuit that applies a selection voltage to the selected scanning line, a pulse generation circuit that outputs a gradation control pulse at a constant cycle over the period in which the selection voltage is applied, and a gradation of a pixel are displayed. The grayscale data corresponding to each of the grayscale control pulses is assigned to the designated grayscale data, and the grayscale designated by the grayscale data for the pixel of interest and the grayscale of the pixel actually displayed by the grayscale data. The conversion circuit for converting in the direction of eliminating the difference and the gradation of the pixel at the intersection of the selected scanning line and the data line in the period in which one scanning line is selected and the selection voltage is applied. Gradation system corresponding to data While the pulse is a start or end timing supplied, it is characterized in configuration to and a data line driving circuit for applying lighting voltage to be turned on display the pixels. According to this configuration, the pulse generation circuit only needs to arrange and output the grayscale control pulses at a constant cycle, which simplifies the circuit configuration and lowers the operating frequency. Furthermore, since the gradation of the pixel is corrected by the converted gradation data, skip of gradation display is prevented. Note that the lighting voltage in this case means a data signal voltage having a polarity opposite to that of the selection voltage applied in a certain scanning line when the period is selected.

Here, as the contents of conversion by the conversion circuit, the conversion circuit sets a plurality of differences between the gradations designated by the density data of the pixel of interest and the gradations of the pixels actually displayed by the gradation data. Taking the vertical scanning period as a unit,
In addition to the aspect of performing conversion in the direction of elimination, the difference between the gradation indicated by the density data of the pixel of interest and the gradation of the pixel actually displayed by the gradation data is considered to be in the direction of elimination in units of multiple pixels. A mode in which conversion is performed can be considered.
It should be noted that, with respect to the pixel of interest, a process of converting the difference between the grayscale indicated by the density data and the grayscale of the pixel actually displayed by the grayscale data in the direction of eliminating the grayscale in units of a plurality of vertical scanning periods. A frame rate control method can be cited as an example, and an area gradation method such as a dither method can be cited as a processing for converting the difference in a direction of eliminating it by taking a plurality of pixels including the pixel as a unit. Of course,
You may use these together.

Further, in order to achieve the above object, the electro-optical device according to the embodiment selects a pixel provided corresponding to an intersection of a scanning line and a data line and one scanning line, and performs the selection. And a scanning line driving circuit for applying a selection voltage to the scanning line, and a gradation control pulse is added at intervals of 1, 2, 4 or 8 times the constant period over the period in which the selection voltage is applied. A pulse generation circuit for outputting and a floor corresponding to gray scale data of a pixel at a crossing position between the selected scanning line and the data line in a period in which one scanning line is selected and the selection voltage is applied. The data line driver circuit is characterized by including a data line driving circuit for applying a lighting voltage for turning on the relevant pixel during a period in which a timing at which the adjustment control pulse is supplied is set as a start point or an end point. According to this configuration, the pulse generation circuit only needs to output the gradation control pulse at an interval obtained by adding intervals of 1, 2, 4 or 8 times the constant period, so that the operating frequency can be low.

Further, since the electronic apparatus according to the embodiment has the electro-optical device as a display section, the configuration can be simplified and the power consumption can be reduced. Note that such electronic devices include personal computers and
Examples include digital still cameras and mobile phones.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

<Structure> First, the structure of the electro-optical device according to the embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of this electro-optical device. As shown in this figure, in the panel 100 of the electro-optical device, a plurality of data lines (segment electrodes) 212 are formed extending in the column (Y) direction, while a plurality of scanning lines (common electrodes) are formed. 312 are formed extending in the row (X) direction, and pixels 116 are formed corresponding to each intersection of the data line 212 and the scanning line 312. Here, each pixel 116
Is a liquid crystal capacitor 118 and a thin film diode (TFD) that is an example of a two-terminal switching element.
220 in series connection. Of these, the liquid crystal capacitance 11
As described below, the liquid crystal display device 8 has a configuration in which a liquid crystal, which is an example of an electro-optical material, is sandwiched between a scanning line 312 that functions as a counter electrode and a rectangular pixel electrode. In the present embodiment, for convenience of explanation, the total number of scanning lines 312 is 160 and the total number of data lines 212 is 120, and a matrix type display device of 160 rows × 120 columns will be described. The invention is not limited to this.

Next, the Y driver 350, which is generally called a scanning line driving circuit, has scanning signals Y1 and Y.
2, Y3, ..., Y160 in the first line, the second line,
The data is supplied to the scanning line 312 in the third row, ..., 160th row. More specifically, the Y driver 350 selects 160 scanning lines 312 one by one, as will be described later, a selected voltage for the selected scanning lines 312, and a non-selection voltage for the other scanning lines 312. Each is supplied.

The X driver 250 is generally called a data line drive circuit, and the Y driver 350.
Data signals X1, X2, X3, ..., X120 to the pixels 116 located on the scanning line 312 selected by
It is supplied via the corresponding data lines 212 according to the display contents. The detailed configurations of the X driver 250 and the Y driver 350 will be described later.

On the other hand, the control circuit 400 includes an X driver 25.
0 is supplied with various control signals and clock signals for defining horizontal scanning, while Y driver 350 is supplied with various control signals and clock signals for defining vertical scanning. is there. Further, the control circuit 400 sets the gradation of the pixel 116 to 16 from 0 to 15.
The 4-bit density data Dp designated at the stage is supplied in synchronization with vertical scanning and horizontal scanning. Next, the conversion circuit 5
00 is for converting the density data Dp shown in 16 steps into the gradation data Dpix shown in 13 steps as described later. For convenience of explanation, the density data Dp is 16 in the binary notation from (0000) to (1111).
It is assumed that the gradation data Dpix is expressed in 13 levels from (0000) to (1100) in binary value. Then, the voltage forming circuit 600
Is the voltage ± V _S and the voltage ± V _D / used in the panel 100.
2 and 2 are generated respectively. Here, in the present embodiment, the voltage ± V _S is used as a selection voltage in the scanning signal. Further, the voltage ± VD / 2 is configured to be shared by the non-selection voltage in the scanning signal and the data voltage in the data signal.

<Mechanical Structure> Next, the mechanical structure of the panel 100 will be described. FIG. 2 is a perspective view showing the overall configuration of the panel 100. 3 is a partial cross-sectional view showing the structure when the panel 100 is broken along the X direction, and FIG. 4 is a partial cross-sectional view showing the structure when the panel 100 is broken along the Y direction. It is a figure. As shown in these figures, the panel 100 includes an element substrate 200 located on the back side and an element substrate 2 located on the observation side.
The counter substrate 300, which is slightly smaller than 00, is adhered to the counter substrate 300 with a constant gap maintained by the sealing material 110 in which the conductive particles (conducting material) 114 also serving as a spacer are mixed, and for example, TN (Twisted Nemati).
The c) type liquid crystal 160 is enclosed. Note that the sealing material 110 is formed in a frame shape along the inner peripheral edge of the counter substrate 300 as shown in FIG.
A part is open to enclose 60. Therefore, after the liquid crystal is filled, the opening is sealed with the sealing material 112.

Now, on the facing surface of the facing substrate 300, the scanning line 3 which is a strip electrode formed extending in the row (X) direction.
In addition to 12, an alignment film 308 is formed and a rubbing process is performed in a fixed direction. Here, as shown in FIG. 3, one end of each scanning line 312 has a sealing material 1
It is extended to the formation region of 10. A polarizer 131 is attached to the outside (observation side) of the counter substrate 300 (not shown in FIG. 2), and its absorption axis has an alignment film 308.
Is set according to the direction of the rubbing process.

On the other hand, on the opposite surface of the element substrate 200, Y
A rectangular pixel electrode 234 is formed adjacent to the data line 212 formed extending in the (column) direction, an alignment film 208 is formed, and a rubbing process is performed in a fixed direction. Now, on the element substrate 200, wirings 342 are provided in one-to-one correspondence with the respective scanning lines 312. More specifically, one end of the wiring 342 is formed so as to face one end of the corresponding scanning line 312 in the region where the sealing material 110 is formed, as shown in FIG.
Here, the conductive particles 114 are dispersed in the sealing material 110 at such a ratio that at least one conductive particle 114 is present in a portion where one end of the scanning line 312 and one end of the wiring 342 face each other. Therefore, the scanning lines 31 formed on the counter substrate 300
2 is the element substrate 200 through the conductive particles 114.
In a state of being electrically connected to the wiring 342 on the opposite surface, the wiring is pulled out to the outside of the region where the sealing material 110 is formed. Further, one end of the data line 212 formed on the element substrate 200 is drawn out to the outside of the area where the sealing material 110 is formed as it is. Further, a polarizer 121 is attached to the outside (back side) of the element substrate 200 (not shown in FIG. 2), and its absorption axis is aligned with the alignment film 2.
It is set according to the direction of the rubbing process to 08.
Since the panel 100 according to the present embodiment is a transmissive type, a backlight unit that uniformly radiates light is provided on the back side of the element substrate 200, but since it is not directly related to the present case, it will be omitted here. Illustration is omitted.

Next, the outside of the display area of the panel 100 will be described. As shown in FIG. 2, the X for driving the data line 212 is provided on the two sides of the element substrate 200 which extend from the counter substrate 300. Driver 25
0 and a Y driver 350 for driving the scanning lines 312 are mounted by the COG (Chip On Glass) technique. Therefore, the X driver 250
While supplying the data signal directly to the data line 212,
The Y driver 350 includes the wiring 342 and the conductive particles 11.
4, the scanning signal is indirectly supplied to the scanning line 312 via the line 4.

An FPC (Flexible Printed Circuit) is provided near the outside of the area where the X driver 250 is mounted.
One end of the substrate 150 is joined. Here, an IC chip forming the voltage forming circuit 600 is mounted near the center of the FPC board 150 by COF (Chip On Film) technology. Although not shown in FIG. 2, the other end of the FPC board 150 is connected to the control circuit 400 and the conversion circuit 500 in FIG. That is, the control circuit 400 supplies various signals and clock signals to the X driver 250 and the Y driver 350, respectively, while the conversion circuit 500 supplies the gradation data Dpix to the X driver 250. There is.

The X driver 250 and the Y driver 350 in FIG. 1 are located on the left side and the upper side of the panel 100, respectively, unlike FIG.
This is merely a convenient measure for explaining the electrical configuration. Also, the X driver 250 and the Y driver 3
Instead of COG mounting each of the 50 on the element substrate 200, for example, a TAB (Tape Automated Bonding) technique is used to mount each driver and power supply circuit on the TCP.
The (Tape Carrier Package) may be electrically and mechanically connected by an anisotropic conductive film.

<Pixel Structure> Next, the detailed structure of the pixel 116 in the panel 100 will be described. FIG. 5 is a partially cutaway perspective view showing the structure. In addition, in this figure, the alignment film 20 in FIG.
8, 308 and the polarizers 121, 131 are omitted. As shown in FIG. 5, rectangular pixel electrodes 234 made of a transparent conductor such as ITO (Indium Tin Oxide) are arranged in a matrix on the opposing surface of the element substrate 200. Pixel electrodes 234 arrayed in
Are commonly connected to one data line 212 via the TFD 220. Here, the TFD 220 is
When viewed from the substrate side, a first conductor 222 formed of a single element of tantalum or a tantalum alloy and branched from the data line 212 in a T shape, and the first conductor 222.
Insulator 224 anodized with a second material such as chromium
And the conductor 226 of FIG. 3 to form a sandwich structure of conductor / insulator / conductor. Therefore, TF
D220 has a diode switching characteristic in which the current-voltage characteristic is non-linear in both positive and negative directions.

The insulator 201 formed on the upper surface of the element substrate 200 is transparent and has an insulating property. The reason why the insulator 201 is formed is that the second conductor 226 is deposited. In order to prevent the first conductor 222 from being separated by heat treatment performed later, and
This is to prevent impurities from diffusing into the conductor 222 of FIG. So if these are not a problem,
The insulator 201 can be omitted.

On the other hand, on the facing surface of the counter substrate 300, IT
Scanning lines 312 made of O or the like extend in the row direction orthogonal to the data lines 212 and are arranged at positions facing the pixel electrodes 234. Accordingly, the scanning line 312 is
The pixel electrode 234 functions as a counter electrode.
Therefore, the liquid crystal capacitor 118 in FIG. 1 has the scanning line 3 at the intersection of the data line 212 and the scanning line 312.
12, the pixel electrode 234, and the liquid crystal 160 sandwiched between the two.

In such a configuration, the data line 212
Regardless of the data voltage applied to the TFD22
When a selection voltage for forcibly turning 0 into a conductive state (ON) is applied to the scanning line 312, the TFD 220 corresponding to the intersection of the scanning line 312 and the data line 212 is turned on, and the liquid crystal connected to the turned-on TFD 220. Capacity 118
, The charge corresponding to the difference between the selection voltage and the data voltage is accumulated. After the charge accumulation, even if the TFD 220 is turned off by applying the non-selection voltage to the scanning line 312, the charge accumulation in the liquid crystal capacitor 118 is maintained. And
Depending on the amount of charge accumulated in the liquid crystal capacitor 118, the liquid crystal 16
Since the orientation state of 0 changes, the amount of light passing through the polarizers 121 and 131 changes according to the amount of accumulated charge.
Therefore, by controlling the amount of charge accumulated in the liquid crystal capacitor 118 for each pixel by the data voltage when the selection voltage is applied, it is possible to display a predetermined gradation.

<Driving Method> Next, in the panel 100 according to this embodiment, the pixels 116 are driven by a method called a four-value driving method (1 / 2H selection, 1H inversion). Since this driving method is not directly related to the present invention, a detailed description thereof will be omitted, but for simplification, one horizontal scanning period 1H is divided into two and divided into a first half period and a second half period. Among them, for example, while the selection voltage is applied to one scanning line in the latter half period, and the data voltage according to the display content of the pixel located on the scanning line is applied to the corresponding data line, in the first half period, the latter half This is a driving method in which a reverse polarity voltage of a voltage that will be applied during the period is applied to the data line in advance. In the present embodiment,
The polarity reference of the voltage applied to the scanning line 312 or the data line 212 is the data voltage ± VD applied to the data line 212.
It is based on the intermediate voltage of / 2. The control signals and clock signals necessary for executing the four-valued driving method and the specific configuration therefor will be described below.

<Control Circuit> First, various signals such as control signals and clock signals generated by the control circuit 400 in FIG. 1 will be described.

First, the signals used on the Y (vertical scanning) side will be described. First, the start pulse DY is a pulse output at the beginning of one vertical scanning period (1F), as shown in FIG. Secondly, the clock signal YCK
Is a reference signal on the Y side, and as shown in FIG.
It has a period of a horizontal scanning period (1H). Thirdly, the polarity instructing signal POL is a signal for instructing the polarity of the selection voltage in the scanning signal, and as shown in the figure, within the same vertical scanning period, it is a logic signal for every 1 horizontal scanning period (1H). The levels are inverted, and even if attention is paid to the same horizontal scanning period in adjacent vertical scanning periods, the logic levels are inverted. Fourthly, the control signal INH is a signal for defining the application period of the selection voltage in one horizontal scanning period 1H. As described above, in the present embodiment, since the selection voltage is applied to the scanning line in the second half period of one horizontal scanning period 1H, the control signal INH becomes H level in the second half period. Therefore, as a result, the control signal INH is obtained by shifting the phase of the clock signal YCK by 180 degrees.

Next, the signals used on the X (horizontal scanning) side will be described. First, as shown in FIG. 11, the start pulse DX is a pulse that is output at the supply start timing of the grayscale data Dpix for one row. Here, the gradation data Dpix is the density data Dp converted by the conversion circuit 500 (see FIG. 1) as described above. Secondly, the clock signal XCK is a reference signal on the X side, and its cycle corresponds to the period in which the gradation data Dpix for one pixel is supplied, as shown in FIG. Third, the latch pulse LP is a pulse that rises at the start of one horizontal scanning period (1H), and is a pulse that is output after the grayscale data Dpix for one row is supplied, as shown in FIG. Is. Fourthly, the reset signal RES is a pulse signal output at the beginning of the first half period and the beginning of the latter half period of one horizontal scanning period, as shown in FIG. Fifth, the gradation code pulse GCP is output by the pulse generation circuit 410 shown in FIG. 8, and is output at the timing when the reset signal RES is not output during the rising of the clock signal GCK. Is. Here, the clock signal GCK has a cycle of 1/32 with respect to the clock signal YCK. Then, in the present embodiment, the gradation control pulse GCP is, as shown in FIG. 9, a first half period or a second half period (1 / 2H) of one horizontal scanning period (1H).
When the reset signal RES is output at the first timing among the 16 timings divided into 16 times, 11 timings are output at the timings excluding the 1st to 5th timings, and are output at equal intervals. To be done. For convenience of description, the gradation control pulses GCP output in the first half period or the second half period will be represented as L11, L10, L9, ..., L1 in order when they are distinguished.

<Y Driver> Next, the details of the Y driver 350 will be described. FIG. 6 shows the Y driver 350.
3 is a block diagram showing the configuration of FIG. In this figure, the shift register 352 has 1 corresponding to the total number of scanning lines 312.
It is a 60-bit shift register. More specifically, the shift register 352 sequentially shifts the start pulse DY supplied at the beginning of one vertical scanning period according to the clock signal YCK, and transfers the transfer signals Ys1, Ys2, Ys3 ,.
It is sequentially output as Ys160. Here, the transfer signals Ys1, Ys2, Ys3, ..., Ys160 respectively correspond one-to-one to the scanning lines 312 of the first, second, third ,. When any one of the transfer signals becomes the H level, it is instructed that the horizontal scanning period (1H) in which the corresponding scanning line 312 should be selected is selected.

Then, the voltage selection signal forming circuit 354 is
In addition to these transfer signals, the voltage selection signals a, b, c, and d that determine the voltage to be applied to the scanning line 312 are exclusively obtained from the scanning line 3 based on the polarity instruction signal POL and the control signal INH.
It is output corresponding to every 12th. Here, in the present embodiment, the voltage of the scanning signal applied to the scanning line 312 is + VS (positive side selection voltage), + V as described above.
There are four values of D / 2 (non-selective voltage on the positive electrode side), -VS (non-selective voltage on the negative electrode side), and -VD / 2 (selective voltage on the negative electrode side), of which the selection voltage + VS or -VS is actually applied. The period to be performed is 1 / 2H in the latter half of one horizontal scanning period.
Further, the non-selection voltage is + VD / 2 after the selection voltage + VS is applied, and is −VD / 2 after the selection voltage −VS is applied, and is uniquely determined by the immediately preceding selection voltage. There is.

Therefore, the voltage selection signal forming circuit 354.
Generates the voltage selection signals a, b, c, d so that the voltage levels of the scanning signals have the following relationship. That is, any one of the transfer signals Ys1, Ys2, ..., Ys160 becomes the H level, and it is instructed that the horizontal scanning period in which the corresponding scanning line 312 should be selected is selected.
When NH becomes H level and it is informed that it is the second half period of the horizontal scanning period, the voltage selection signal forming circuit 35.
4 indicates the voltage level of the scanning signal to the scanning line 312,
First, a selection voltage having a polarity corresponding to the signal level of the polarity instruction signal POL is used. Secondly, when the control signal INH changes to the L level, in other words, when the selection state changes to the non-selection state, the selection voltage changes to the selection voltage. The voltage selection signal is generated so as to become the corresponding non-selected voltage.

Specifically, the voltage selection signal forming circuit 354.
Is the positive selection voltage + if the polarity instruction signal POL is at H level during the period when the control signal INH is at H level.
The voltage selection signal a for selecting VS is output during the period,
After that, when the control signal INH transitions to the L level, the voltage selection signal b for selecting the positive non-selection voltage + VD / 2 is output, while the polarity instruction signal POL changes during the period when the control signal INH is at the H level. If it is at the L level, the voltage selection signal d for selecting the negative-side selection voltage -VS is output in the period, and if the control signal INH subsequently transits to the L-level, the negative-side non-selection voltage -VD / 2 is selected. The voltage selection signal c to be output is output.

Next, the level shifter 356 expands the voltage amplitudes of the voltage selection signals a, b, c, d by the voltage selection signal forming circuit 354, respectively, and outputs a ', b', c ', d'.
Is output as. Then, the selector 358
Are voltage selection signals a ′, b ′, whose voltage amplitude is expanded,
The voltage indicated by c ′ and d ′ is actually selected and applied as a scanning signal to each of the corresponding scanning lines 312.

<Voltage Waveform of Scan Signal> Next, the voltage waveform of the scan signal supplied by the Y driver 350 having the above configuration will be examined. First, as shown in FIG. 7, the start pulse DY is sequentially shifted by the shift register 352 in accordance with the clock signal YCK every one horizontal scanning period 1H, and this is transferred signals Ys1, Ys2 ,.
It is output as Ys160. Here, in one horizontal scanning period in which a certain transfer signal is at the H level, the second half period 1 / 2H is selected by the control signal INH, and the second transfer signal is selected in accordance with the logical level of the polarity instruction signal POL in the second half period. The selection voltage for the corresponding scan line is defined.

More specifically, the voltage of the scanning signal supplied to a certain scanning line is the polarity designating signal P in the latter half period 1 / 2H of one horizontal scanning period 1H in which the scanning line is selected.
If the OL is, for example, at the H level, it becomes the positive-side selection voltage + VS, and then holds the positive-side non-selection voltage + VD / 2 corresponding to the selection voltage. Then, one vertical scanning period (1
In the latter half period of one horizontal scanning period after the passage of F), the polarity instruction signal POL is inverted and becomes L level. Therefore, the voltage of the scanning signal supplied to the scanning line is the negative polarity side selection voltage −VS. Then, the negative electrode side non-selection voltage −VD / 2 corresponding to the selected voltage is held.
For example, in a certain vertical scanning period, the scanning line 31 of the first row
As shown in FIG. 7, the scanning signal Y1 to 2 becomes the positive side selection voltage + VS corresponding to the H level of the polarity instruction signal POL in the latter half period of the horizontal scanning period, and then the positive side non-selection voltage. Hold + VD / 2. In the second half of the next one horizontal scanning period, the polarity indicating signal POL
Becomes the L level which is the logical inversion of the previous selection, the scanning signal Y1 to the scanning line becomes the negative polarity side selection voltage −VS, and then holds the negative polarity side non-selection voltage −VD / 2. Hereinafter, this cycle is repeated.

Further, since the logic level of the polarity designating signal POL is inverted every horizontal scanning period 1H, each scanning line 31.
The scanning signal supplied to 2 is the horizontal scanning period 1H every 1H.
That is, the polarity is alternately inverted for each scanning line 312. For example, in a certain frame, if the selection voltage of the scanning signal Y1 of the first row is the positive selection voltage + VS, the selection voltage of the scanning signal Y2 of the second row is the negative selection voltage −VS after the elapse of one horizontal scanning period. Becomes

<X Driver> Next, details of the X driver 250 will be described. FIG. 10 shows the X driver 25.
It is a block diagram which shows the structure of 0. In this figure, the shift register 25100 shows the grayscale data Dpix for one row.
Of the sampling control signals Xs1, Xs2, Xs are sequentially shifted at each rising edge of the clock signal XCK.
, ..., Xs120.

Subsequently, the register (Reg) 2520 is
The gradation data Dpix, which is provided in a one-to-one correspondence with the data lines 212, is sampled and held at the rising edge of the sampling control signal. Further, the latch circuit (L) 2530 is provided in one-to-one correspondence with the register 2520, and the grayscale data Dpix held by the register 2520 is supplied by the rising edge of the latch pulse LP supplied at the start of the horizontal scanning period. It is latched and output.

On the other hand, the counter 2540 sets (1101) corresponding to the maximum value of the gradation data as an initial value at the rising of the reset signal RES, and the initial value is set every time the gradation code pulse GCP rises. It counts down and outputs the counting result C.
Next, the comparator (CMP) 2550 is provided in a one-to-one correspondence with the latch circuit 2530, and the counter 254 is provided.
The count result C obtained by 0 is compared with the gradation data Dpix latched by the corresponding latch circuit 2530, and when the latter is equal to or higher than the former, a signal which becomes H level is output.

Further, the EX-OR circuit 2562 has an exclusive OR signal M of the polarity designating signal POL and the control signal INH.
X is obtained and the selection by the switch 2560 is controlled by this. Specifically, switch 2560
If the exclusive OR signal MX is at the H level, the data voltage + VD / 2 is set to the voltage supply line 2568, the data voltage −VD / 2 is set to the voltage supply line 2564, and the positions shown by the solid lines are taken. On the other hand, when the exclusive OR signal MX is at the L level, the data voltage + VD / 2 is supplied to the voltage supply line 2 at the position indicated by the broken line in the figure.
At 564, the data voltage −VD / 2 is applied to the voltage supply line 2568.
, Respectively.

The switch 2570 has a one-to-one correspondence with the comparator 2550, that is, the data line 2
12 and one-to-one correspondence with the comparator 25
According to the comparison result of 50, the voltage supply lines 2564, 2568
One of the two is selected. Specifically, switch 25
70 selects the voltage supply line 2564 as shown by the solid line in the figure if the signal indicating the comparison result by the comparator 2550 is at the L level, while it shows the dashed line in the figure if the signal is at the H level. As described above, the voltage supply line 2568 is selected, and the data voltage supplied to each selected voltage supply line is applied to the corresponding data line 212 as a data signal.

<Voltage Waveform of Data Signal> Next, the operation of the X driver 350 will be examined in order to explain the voltage waveform of the data signal. First, as shown in FIG.
When the start pulse DX rises to the H level, the gradation data Dpix corresponding to the pixels in the first column, the second column, the third column, ..., 120th column in any row are sequentially supplied.

Of these, the sampling control signal X output from the shift register 2510 at the timing when the gradation data Dpix corresponding to the pixels in the first column is supplied.
When s1 rises to the H level, the gradation data becomes 1
It is sampled by the register 2520 corresponding to the column number. Next, the gradation data Dpi corresponding to the pixels in the second column
When the sampling control signal Xs2 rises to the H level at the timing when x is supplied, the gradation data is sampled by the register 2520 corresponding to the second column. Similarly, in the third row, the fourth row, ...
The gradation data Dpix corresponding to the pixels in the 120th column are sampled by the registers 2520 corresponding to the 3rd column, the 4th column, ..., And the 120th column, respectively.

Subsequently, when the latch pulse LP is output (when its logic level rises to H level), the grayscale data Dpix sampled by the register 2520 in each column is latched by the latch circuit corresponding to that column. 2530 latches all at once. On the other hand, the counting result C shows the reset signal RES as shown in FIG.
The counter 25 is set to (1100) set by the rising edge of each time the gradation code pulse GCP rises.
The value is down-counted by 40. Therefore, in the comparator 2550, the grayscale data Dpix latched by the latch circuit 2530 and the counter 25
The counting result C obtained by 40 is compared for each data line in each of the first half period and the second half period of the horizontal scanning period defined by the latch pulse LP.

By the way, in the horizontal scanning period when the polarity instruction signal POL is at the H level, the exclusive OR signal MX.
Becomes H level in the first half period and becomes L level in the latter half period. Therefore, in the first half period of the horizontal scanning period, the voltage -VD / is applied to the voltage supply line 2564.
2 is applied and the voltage + VD / 2 is applied to the voltage supply line 2568, while the voltage application relationship is reversed in the latter half of the horizontal scanning period.

Here, in general, the latch circuit 25 in the j-th column
It is assumed that the grayscale data Dpix latched by 30 has the lowest value (0000). In this case, the gradation code pulse GC is output after the reset signal RES is output.
Even if 11 Ps are output, the counting result C does not become less than the latched (0000). Therefore, the output signal from the comparator 2550 in the j-th column maintains the L level in the first half period and the second half period of one horizontal scanning period defined by the latch pulse LP. However, since the application relationship of the voltages applied to the voltage supply lines 2564 and 2568 is reversed between the first half period and the second half period of the horizontal scanning period, the data signal Xj supplied to the j-th column data line 212 is As shown in FIG. 12, the voltage becomes −VD / 2 in the first half period of the horizontal scanning period, and becomes the voltage + VD / 2 in the second half period of the horizontal scanning period. Therefore, if the grayscale data Dpix is (0000), the lighting voltage having the opposite polarity to the selection voltage is not applied at all in the latter half period when the selection voltage is applied to the scanning line, and the latter half of the selection voltage is applied. The non-lighting voltage is applied over the entire period.

Next, in general, the latch circuit 253 of the j-th column
The gradation data Dpix latched by 0 is an intermediate value,
For example, the case of (1001) is assumed. in this case,
When three gradation code pulses GCP are output after the reset signal RES is output, that is, the pulse L
At the time when 9 is output, the counting result C becomes equal to or less than (1001) that is latched, so at that time, the output signal from the comparator 2550 in the j-th column transits from the L level to the H level. Therefore, the data line 21 of the jth column
As shown in FIG. 12, the data signal Xj supplied to the data signal 2 is reset signal REj in the first half period of the horizontal scanning period.
From the output of S to the output of three gradation code pulses GCP, the voltage becomes −VD / 2, and thereafter, the voltage + VD is output until the reset signal RES is output at the start of the latter half period of the horizontal scanning period. / 2. Further, when the reset signal RES is output at the start of the latter half period of the horizontal scanning period, the output signal from the comparator 2550 in the jth column returns to the L level, but at the same time, the voltage supply line 25
Since the application relationship of the voltages applied to 64 and 2568 is also reversed, the data signal Xj apparently maintains the voltage + VD / 2 immediately after the reset signal RES is output. Then, when three gradation code pulses GCP are output again, the data signal Xj transits to the voltage −VD / 2.

That is, the data signal Xj becomes the voltage −VD / 2 in the first 3/12 period of the first half period, becomes the voltage + VD / 2 in the remaining 9/12 period, and becomes the first half of the following second half period. The voltage continues to be + VD / 2 during the period of 3/12 and becomes -VD / 2 during the remaining period of 9/12. After all, the gradation data Dpi
When x is (1001), the lighting voltage is applied for 9/12 only in the latter half period of the selection voltage applied to the scanning line, while the non-lighting voltage is applied for the remaining 3/12. It will be. Note that the latched gradation data Dpix is
Even if it corresponds to an intermediate value other than (1000), it is the same except that the transition timing of the output signal by the comparator 2550 is different.

Therefore, the pulses L11, L10, L9, ..., L1 which are the gradation control pulses GCP sequentially supplied after the reset signal RES is output have the lighting voltage application period Pw of 11/12, respectively. 10/12, 9
/ 12, ..., 1/12 will be defined.

Further, generally, the latch circuit 25 of the j-th column
Assume that the grayscale data Dpix latched by 30 is (1100) corresponding to the highest value. In this case, when the reset signal RES is output, the count result C is immediately latched (1100), so the output signal from the comparator 2550 in the j-th column is
The H level is maintained in the first half period and the second half period of one horizontal scanning period defined by the latch pulse LP. However, since the application relationship of the voltages applied to the voltage supply lines 2564 and 2568 is reversed in the first half period and the second half period of the horizontal scanning period, the data line 2 in the j-th column is
The data signal Xj supplied to 12 has a voltage of + VD / 2 in the first half of the horizontal scanning period and has a voltage of −VD / 2 in the second half of the horizontal scanning period. Therefore,
If the gradation data Dpix is (1101), the lighting voltage is applied throughout the latter half period when the selection voltage is applied to the scanning line, and the non-lighting voltage is not applied at all.

Although the horizontal scanning period in which the polarity instruction signal POL is at H level has been described here, only the exclusive OR signal MX is logically inverted in the horizontal scanning period in which the polarity instruction signal POL is at L level. And the others are the same. That is, the polarity instruction signal POL is L
In the first half period of the level horizontal scanning period, the voltage + VD / 2 is applied to the voltage supply line 2564.
While the voltage −VD / 2 is applied to 68, the voltage −VD is applied to the voltage supply line 2564 in the latter half period of the horizontal scanning period.
/ 2 is applied and the voltage + VD / 2 is applied to the voltage supply line 2568.
Is only applied. Therefore, as shown in FIG. 12, the data signal Xj in the horizontal scanning period in which the polarity instruction signal POL is at the L level is the logical level of the data signal Xj inverted in the horizontal scanning period in which the polarity instruction signal POL is at the H level. Will be things. However, in any horizontal scanning period, the lighting voltage is common in that the lighting voltage is moved backward in time, and the application period Pw is also the same.

Further, as seen in one horizontal scanning period, a period in which the voltage is + VD / 2 in the data signal Xj and a voltage −
The period of VD / 2 is 50% each. Therefore, the effective value of the data voltage viewed from the non-selection voltage is constant across the data lines without depending on the display pattern, so that the occurrence of so-called crosstalk is prevented. Since it is not directly related to the present invention, further description will be omitted.

<Relationship between gradation control pulse and gradation> Here, in the panel 100, the application period Pw (pulse width) of the lighting voltage defined by the gradation control pulse GCP,
The relationship with the pixel gradation will be described with reference to FIG.
FIG. 24 defines the second half period (1 / 2H) of one horizontal scanning period as “255” (decimal notation) regarding the gradation change of the pixel when the application period of the lighting voltage is changed, and the floor thereof. The lowest gradation (white) of the tonal change is "0",
It is a figure which normalized and shows the highest gradation (black) as "15". As shown in this figure, the lighting voltage application period and the pixel gradation are not in a linear relationship.

On the other hand, in the X driver 250, the application period of the lighting voltage corresponding to the gradation data Dpix is determined by the count of the gradation control pulse GCP except the minimum value and the maximum value. Therefore, if there is no linear relationship between the lighting voltage application period and the pixel gray scale, 14 gray scale control pulses GCP are output corresponding to the intermediate gray scale, and the output interval is required. It is easy to think that it is sufficient to make them uneven according to the application period of the lighting voltage.
For example, in the case of the characteristics shown in FIG. 24, the lighting voltage application period (pulse width) required for each of the intermediate values excluding the minimum value “0” and the maximum value “15” is shown in FIG. On the street. For this reason, the first half / second half period (1 / 2H) of one horizontal scanning period is divided into 255, and "79", "26", "20" from the output of the reset signal RES,
If the configuration is such that the gradation control pulse GCP is output at each of the timings when "20", ..., "5" have elapsed,
The X driver 250 without converting the density data Dp
If it is directly supplied to, it should be possible to display 16 gradations immediately.

Here, in order to output the gradation control pulse GCP unevenly so as to match the characteristics of the pulse width / density, for example, the configuration shown in FIG. 26 is required. In this figure, the counter 430 is 1/25 for the first half or second half period (1 / 2H) of one horizontal scanning period.
The source oscillation clock signal Gck having a period of 5 is counted up each time it rises, and the count result is reset to zero when the OR signal by the OR circuit 435 transits to the H level. Next, the comparator 440 outputs one gradation control pulse GCP each time the count result supplied to the input terminal A and the threshold value supplied to the input terminal B match. On the other hand, the threshold value output circuit 450 outputs the threshold value “79” when the reset signal RES becomes H level, and thereafter, the threshold value “2” is output every time the gradation control pulse GCP is output.
6 "," 20 "," 20 ", ...," 5 "are output in order. Further, the OR circuit 435 obtains a logical sum signal of the reset signal RES and the gradation control pulse GCP. Therefore, as a result of counting by the counter 430, the reset signal RES is output, or
Each time the gradation control pulse GCP is output, it is reset to zero.

In this configuration, when the reset signal RES is supplied at the beginning of the first half or the second half of one horizontal scanning period, the count result by the counter 430 is reset to zero and the threshold value output circuit 450 sets the threshold value. The value “79” is output. Therefore, first, when the rise of the source oscillation clock signal Gck is counted 79 times, the gradation control pulse GCP is output. After that, the count result of the counter 430 is reset to zero again, and the threshold output circuit 45
The threshold value “26” is output from 0. Therefore, next, when the rise of the source oscillation clock signal Gck is counted 26 times, the gradation control pulse GCP is output. Similarly, the gradation control pulse GCP is output. Therefore, in the configuration shown in FIG. 26, the gradation control pulse GCP is "79", "26", "2" in the first half / second half period (1 / 2H) of one horizontal scanning period.
It is output at each timing when only "0", "20", ..., "5" have passed. Note that FIG. 27 shows
In the gradation control pulse GCP output in this configuration, the temporally rear part in the latter half period of one horizontal scanning period is extracted and shown.

However, the configuration shown in FIG.
The pulse generation circuit 410 in this embodiment (see FIG. 8)
In addition to being complicated, the source clock signal Gck is required to have a frequency much higher than the frequency of the clock signal GCK used in the present embodiment. Since the signal line for supplying the source clock signal Gck usually has some parasitic capacitance, extra power is consumed, resulting in a large factor that hinders low power consumption.

Therefore, in the present embodiment, the gradation control pulse GCP is output using the clock signal GCK having a low frequency as described above. Due to this relationship, the gradation control pulse GCP is irrelevant to the density characteristics of the pixel,
The data will be output at equal intervals (see FIG. 9). here,
Using the gradation control pulse GCP output at equal intervals,
The actual gradation (actual gradation) in the pixel is not only weakly related to the 16 gradations indicated by the original density data Dp, but also does not maintain a constant density difference. Specifically, it is as shown in FIG. 14 or FIG. For example, when the pulse width is short as defined by the gradation control pulses L1 and L2, the change in actual gradation becomes large. For this reason,
Even if an attempt is made to perform display in which the gradation gradually changes, for example, gradation display, the contour may be visually recognized due to the difference in the actual gradation. On the other hand, when the pulse width is long as defined by the gradation control pulses L10 and L11, the change in actual gradation is small, and therefore it may not be visually recognized as a density difference. Note that FIG. 14 is a table showing the actual gradation of the pixel when the gradation control pulse GCP output 11 times at equal intervals is used, and FIG. 15 shows the actual gradation as the density data Dp. In contrast to the gradation shown by
This is indicated by the mark ■.

In the first place, when 11 gradation output pulses GCP are output at equal intervals, the original density data Dp indicates the gradation of the pixel in 16 steps, whereas the gradation of the pixel is 13 steps. It can be changed only by three gradations, and the expression capability is reduced by three gradations.

Therefore, in this embodiment, the conversion circuit 500 is used.
As shown in FIG. 13, the conversion characteristics by
The grayscale data Dpix in units of one vertical scanning period is 1
Even in the case of three levels, the gradation that can be displayed by the pixel 116 is visually recognized in 16 levels which is the original density indicated by the density data Dp. For details, see FIG.
Is the lowest value of the density data Dp (0000)
Is converted into the lowest value of the gradation data Dpix (0000), and similarly, is the highest value of the density data Dp (11
11) is the maximum value of the gradation data Dpix (110)
0).

Next, if the difference between the gradation indicated by the density data Dp and the actual gradation by the gradation data Dpix is negligible, the density data Dp is directly converted to the gradation data Dpix. It For example, the density data Dp
(0011) indicates that the gradation of the pixel should be "3". However, since the actual gradation according to (0001) of the gradation data Dpix is "3.17", (001) of the density data Dp
1) is converted into (0001) of the gradation data Dpix. Further, for example, (0101) of the density data Dp indicates that the gradation of the pixel should be “5”, but the gradation data Dpi
Since the actual gradation according to (0010) of x is “5.22”, (0101) of the density data Dp is the gradation data Dpix.
Is converted to (0010). For the same reason, the density data Dp (1000), (1001), (101
0), (1011), (1100) and (1110)
Are (0100) and (01
01), (0110), (0111), (1000) and (1011).

On the other hand, if the difference between the gradation indicated by the density data Dp and the actual gradation indicated by the gradation data Dpix is not negligible (or the gradation indicated by the density data Dp is the gradation data If the density data Dp cannot be realized by Dpix), the density data Dp is distributed to the gradation data Dpix in which the actual gradation is located before and after the designated gradation at a frequency according to the gradation distance (frame rate control). Law). For example, (0001) of the density data Dp indicates that the gradation of the pixel should be "1", but there is no gradation data Dpix that realizes this gradation. However, before and after the gradation "1", (0000) of the gradation data Dpix that makes the actual gradation "0" and (0001) of the gradation data Dpix that makes the actual gradation "3.17". And exist. Therefore, (0001) of the density data Dp is (000) in 2 vertical scanning periods of 3 vertical scanning periods (frames).
0) and (0001) in the remaining one vertical scanning period are converted as grayscale data Dpix. In FIG. 13, the notation of the gradation data Dpix with respect to (0001) of the density data Dp means this conversion content.

As a result, the density data Dp is (000
In the pixel for which the gradation is designated as 1), the gradation data Dpix is (000
0), which is white, and an intermediate gradation with gradation data Dpix of (0001) in the remaining 1 vertical scanning period.
The gradation in units of three vertical scanning periods is "1.05", which can be made substantially equal to the gradation indicated by the density data Dp.

Similarly, the density data Dp of (001
0) is converted into gradation data Dpix into (0000) in one vertical scanning period of the three vertical scanning periods and into (0001) in the remaining two vertical scanning periods. Other density data Dp (0100), (0110),
Also for (0111) and (1101), the gradation data Dpix is converted according to the corresponding notation.

As described above, according to the conversion by the conversion circuit 500, even if the pixel 116 is capable of expressing the gradation only in 13 steps in one vertical scanning period, as shown by the symbol ⋄ in FIG. In terms of a plurality of vertical scanning periods, 16 of "0" to "15" depending on the density data Dp.
The gradation is visually recognized at a gradation almost equal to the gradation indicated in equal steps.

In the present embodiment, the gradation display instructed by the original density data Dp is made possible, and in addition to simplifying the structure for generating the gradation control pulse GCP, The required source clock signal can be of low frequency, so that power consumption can be reduced.

<Different Configuration of Conversion Circuit> In the above-described embodiment, the density data Dp is converted into the gradation data Dpix by the so-called frame control method, but the present invention is not limited to this, and various conversion algorithms may be applied. You can For example, the area gradation method may be used for conversion. FIG. 16 is a block diagram showing a conversion circuit 510 for converting the density data Dp into the gradation data Dpix by the area gradation method. In this area gradation method, for example, 3 × 3 pixels are assumed to be 1 pixel, and a new gradation of 1 pixel is instructed by a pattern of 3 × 3 pixels.

More specifically, the conversion circuit 510 has a 3 × 3 9 format.
Focusing on one pixel for each pixel, the density data Dp of the pixel of interest is converted into gradation data Dpix corresponding to nine pixels, and the gradation data Dpix is synchronized with vertical scanning and horizontal scanning. Will be supplied. At the time of this conversion, in order to specify the coordinates (row and column) of the pixel of interest,
The conversion circuit 510 includes data Col indicating the row of the pixel of interest.
And the data Row indicating the column are supplied. The control circuit 400 can generate the data Col by counting the clock signal YCK and the data Row by counting the clock signal XCK. Further, since the pixel of interest is not fixed and may be moved every vertical scanning period, the conversion circuit 510 is supplied with the data Fr indicating the number of frames. For the data Fr, the start pulse D
By counting Y, it can be generated by the control circuit 400.

Here, as shown in FIG. 17, if the density data Dp of the pixel of interest is (0001), the conversion circuit 510 causes 6 out of 9 pixels to be (0000).
, And the remaining 3 pixels are converted to (0001). For the contents of this conversion, FIG. 13 can be referred to. However, in FIG. 13, the density data Dp is (01
10), (0111), and (1101), the corresponding grayscale data Dpix is converted in units of 2, 5, and 2 vertical scanning periods, respectively, so here, 3 × 3 pixels (9 vertical scanning) are used. It is necessary to revise the contents in units of (period).

The area gradation method alone has a resolution of 1
It is desirable to use the above-mentioned frame rate control method together because it has a drawback such as a decrease to / 9. Needless to say, various patterns other than the 3 × 3 pattern can be applied in the area gradation. Further, the error at the time of conversion is allocated to the pixels located around the pixel, and when the peripheral pixels are converted, the allocated error is also taken into consideration, and the whole (1
A conversion (error diffusion method) that minimizes an error may be performed as a frame), or a random number may be added at the time of conversion to compare with a threshold value. Furthermore, the conversion methods may be combined appropriately.

<Other Configuration of Pulse Generation Circuit> In the above-described embodiment, the gradation control pulse GCP is generated using the clock signal GCK having a cycle of 1/32 with respect to the clock signal YCK. , But not limited to this. For example, the pulse generation circuit shown in FIG. 18 may be configured to output (14) gradation control pulses GCP. At first glance, this pulse generation circuit is common to the pulse generation circuit shown in FIG. 26, but the clock signal used and the threshold value output by the threshold value output circuit are changed.

When the pulse width / gradation characteristics are those shown in FIGS. 24 and 25 and the gradation control pulse GCP is generated by the pulse generation circuit shown in FIG. 26, the source clock signal Gck is high. As described above, the reduction in power consumption is hindered as a result of the required frequency. Therefore, in FIG. 25, attention is paid to the equivalence of pulse intervals (differences in pulse width), and this is approximated and replaced with the characteristics shown in FIG. That is, the pulse intervals (pulse width differences) shown in FIG. 20 are approximated to be multiples of all “2.5”. And the source clock signal G
The clock signal Gclk having a cycle of “2.5” times that of ck (see FIGS. 26 and 27) is counted by the counter 430 after the reset signal RES is supplied, and the count results are “32” and “10”. , "8", "8", ...
The gradation control pulse GCP is output at each of the timings when "2" has elapsed. With this configuration, although the configuration of the pulse generation circuit that generates the grayscale control pulse GCP cannot be simplified compared to the configuration shown in FIG. 26, the frequency of the clock signal Gck used for the counter 430 is 40% (2 / Since 5) is sufficient, low power consumption can be achieved. It should be noted that in FIG. 17, all the differences in pulse width are expressed at intervals obtained by appropriately adding 1, 2, 4, and 8 times the cycle to the clock signal Gclk. Therefore, the clock signal Gclk is set to 2, 4,
It is also possible to divide the frequency by 8 and decode the frequency-divided signal and the clock signal Gclk to output the gradation control pulse GCP.

<Summary of Embodiments> In the above-described embodiments, the case of displaying 16 gradations has been described, but the present invention is not limited to this, and it is also possible to realize 4 gradations of low gradation.
8 gradation display is also possible, 32 with higher gradation than this,
64, ..., And gradation may be used. In addition, R (red), G
Color display may be performed by forming one dot with three pixels of (green) and B (blue). Further, in the embodiment, the normally white mode in which the liquid crystal capacitance displays white when no voltage is applied has been described, but a normally black mode in which black display is displayed in the same state may be used.
In addition, in the embodiment, it is a transmissive type, but it may be a reflective type or a semi-transmissive / semi-reflective type in which both are used in combination.

Further, in the embodiment, when the selection voltage is applied, the lighting voltage is temporally moved backward and applied by the gradation control pulse supplied corresponding to the gradation data. Although the application start point of the lighting voltage is defined, the lighting voltage may be moved forward in time. With such a configuration that the lighting voltage is moved forward in time, the gradation control pulse supplied corresponding to the gradation data defines the application end point of the lighting voltage.

Further, in the present embodiment, one horizontal scanning period is divided into the first half period and the second half period, and the selection voltage is applied to any one of the scanning lines in the latter half period. A configuration may be used in which the selection voltage is applied during the period. Alternatively, the selection voltage may be applied to any of the scanning lines 312 over the one horizontal scanning period without dividing the one horizontal scanning period. Further, in the embodiment, the writing polarity of the liquid crystal capacitance is inverted every one vertical scanning period, but the present invention is not limited to this, and the configuration may be such that the inversion driving is performed in a cycle of two vertical scanning periods or more. .

On the other hand, the X driver 250 in the embodiment
9 has a configuration in which the counter result C by the counter 2540 is shared for each column as shown in FIG. 9, but it is also possible to provide a counter for each column and perform a comparison with the latched gradation data. good.

Further, T in the above-mentioned display device 100
The FD 220 is connected to the data line 212 side and the liquid crystal capacitor 118 is connected to the scanning line 312 side. On the contrary, the TFD 220 is connected to the scanning line 312 side and the liquid crystal capacitor 118 is connected to the data line 212 side. It may be configured to be connected to each side. Further, as the TFD 220, specifically, in addition to a MIM (Metal Insulator Metal) element, a silicon semiconductor, a ZnO (zinc oxide) varistor, an MSI (Meta
It is also possible to use, in addition to an element using a semi-insulator), two elements connected in series or in parallel in opposite directions.

Further, in the embodiment, the case where the liquid crystal is of the TN type or the STN type has been described, but a dye having anisotropy in absorption of visible light in the major axis direction and the minor axis direction of the molecule ( A guest-host type liquid crystal in which a dye) is arranged in parallel with liquid crystal molecules by dissolving a guest in a liquid crystal (host) having a certain molecular arrangement may be used. In addition, as a configuration of vertical alignment (homeotropic alignment), liquid crystal molecules are aligned vertically to both substrates when no voltage is applied, while liquid crystal molecules are aligned horizontally to both substrates when voltage is applied. The liquid crystal molecules are aligned horizontally with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned vertically with respect to both substrates when voltage is applied,
The configuration may be parallel (horizontal) orientation (homogeneous orientation). As described above, in the present invention, various types of liquid crystals and alignment methods can be used.

<Electronic Equipment> Next, examples in which the display device according to the above-described embodiment is used in electronic equipment will be described.

<Part 1: Mobile Personal Computer> First, an example in which the above-described display device 100 is applied to the display unit of a personal computer will be described. FIG. 21 is a perspective view showing the configuration of this personal computer. In the figure, a computer 1100 includes a main body portion 1104 having a keyboard 1102 and a display device 100 used as a display portion. When a transmissive liquid crystal device is used as the display device 100,
A backlight (not shown) is provided on the back surface to ensure visibility in the dark.

<Part 2: Mobile Phone> Further, an example in which the above-described display device 100 is applied to the display portion of a mobile phone will be described. FIG. 22 is a perspective view showing the configuration of this mobile phone. In the figure, a mobile phone 1200 includes a plurality of operation buttons 1202, an earpiece 1204, and a mouthpiece 12.
In addition to 06, the display device 100 described above is provided. When a liquid crystal device is used as the display device 100, in order to ensure visibility in a dark place, the backlight is a transmissive type or a semi-transmissive / semi-reflective type, and the front light is a reflective type. (Both are not shown).

<No. 3: Digital Still Camera> Next, a digital still camera using the above-mentioned display device as a finder will be described. FIG. 23 is a perspective view showing the back surface of this digital still camera. An ordinary silver salt camera exposes a film with a light image of a subject, whereas a digital still camera 1300 photoelectrically converts a light image of the subject by an image pickup device such as a CCD (Charge Coupled Device) to generate an image pickup signal. To do. Here, on the rear surface of the case 1302 in the digital still camera 1300, the display device 100 described above is provided.
Is provided, and display is performed based on the image pickup signal from the CCD. Therefore, the display device 100 is
It will function as a viewfinder that displays the subject. A light receiving unit 1304 including an optical lens and a CCD is provided on the front side (back side in FIG. 23) of the case 1302.

When the photographer confirms the subject image displayed on the display device 100 and presses the shutter button 1306, the image pickup signal of the CCD at that time is transferred / stored in the memory of the circuit board 1308. . In addition, in this digital still camera 1300, the case 1
On the side surface of 302, a video signal output terminal 1312 and an input / output terminal 131 for data communication are provided for external display.
And 4 are provided.

As the electronic equipment, in addition to the personal computer shown in FIG. 21, the mobile phone shown in FIG. 22, the digital still camera shown in FIG. 23, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, Car navigation system, pager, electronic organizer, calculator, word processor, workstation, videophone, P
Examples include OS terminals, devices equipped with a touch panel, and the like. It goes without saying that the above-mentioned display device can be applied as the display unit of these various electronic devices.

[0089]

As described above, according to the present invention, it is possible to perform multi-gradation display while simplifying the configuration and reducing power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of an electro-optical device according to an embodiment of the invention.

FIG. 2 is a perspective view showing a configuration of a panel in the electro-optical device.

FIG. 3 is a partial cross-sectional view showing the configuration when the panel is broken in the X direction.

FIG. 4 is a partial perspective view showing the configuration when the panel is broken in the Y direction.

FIG. 5 is a partially cutaway perspective view showing a pixel configuration of the panel.

FIG. 6 is a block diagram showing a configuration of a Y driver in the same electro-optical device.

FIG. 7 is a timing chart for explaining the operation of the Y driver.

FIG. 8 is a block diagram showing a configuration of a pulse generation circuit that generates a gradation control pulse in the same electro-optical device.

FIG. 9 is a timing chart showing an output state of a gradation control pulse by the pulse generation circuit.

FIG. 10 is a block diagram showing a configuration of an X driver in the electro-optical device.

FIG. 11 is a timing chart for explaining the operation of the X driver.

FIG. 12 is a timing chart for explaining the operation of the X driver.

FIG. 13 is a chart showing conversion contents of a conversion circuit in the electro-optical device.

FIG. 14 is a chart showing a relationship between a gradation control pulse and a pixel density in the electro-optical device.

FIG. 15 is a diagram showing the relationship between the gradation represented by the density data, the gradation actually displayed by the converted gradation data, and the gradation without conversion in the electro-optical device.

FIG. 16 is a block diagram showing an applied configuration of a conversion circuit in the electro-optical device.

FIG. 17 is a diagram for explaining conversion contents of the conversion circuit.

FIG. 18 is a block diagram showing an applied configuration of a pulse generation circuit in the electro-optical device.

FIG. 19 is a diagram showing an output state of the pulse generation circuit.

FIG. 20 is a diagram showing decoding characteristics of a decoder in the pulse generation circuit.

FIG. 21 is a perspective view showing a configuration of a personal computer as an example of an electronic apparatus to which the display device is applied.

FIG. 22 is a perspective view showing a configuration of a mobile phone which is an example of an electronic apparatus to which the display device is applied.

FIG. 23 is a perspective view showing a configuration of a digital still camera as an example of an electronic apparatus to which the display device is applied.

FIG. 24 is a diagram showing a relationship between a pulse width and a gradation of a pixel in the electro-optical device.

FIG. 25 is a diagram showing a relationship between gradation and output timing of a gradation control pulse in the conventional electro-optical device.

FIG. 26 is a block diagram showing a configuration of a pulse generation circuit that generates a gradation control pulse in a conventional electro-optical device.

FIG. 27 is a diagram showing an output state of a gradation control pulse by a conventional pulse generation circuit.

[Explanation of symbols]

100 ... Liquid crystal panel 116 ... Pixel 118: Liquid crystal capacity 200: Element substrate 212 ... Data line 220 ... TFD 234 ... Pixel electrode 250 ... Data line drive circuit 300 ... Counter substrate 312 ... Scan line 350 ... Scan line drive circuit 400 ... Control circuit 410 ... Pulse generation circuit 500 ... Conversion circuit 600 ... Drive voltage forming circuit

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) G09G 3/20 G09G 3/20 641P F Term (Reference) 2H093 NA16 NA41 NA51 NC12 NC34 NC37 ND06 ND39 NE04 5C006 AA15 BB17 BC03 BC12 BC16 BC20 BF14 BF22 BF46 FA41 FA47 FA56 5C080 AA10 BB05 DD22 DD26 EE29 FF11 JJ02 JJ04 JJ06

Claims (5)

[Claims] 1. A pixel provided corresponding to an intersection of a scanning line and a data line, a scanning line driving circuit for selecting one scanning line and applying a selection voltage to the selected scanning line, A pulse generation circuit that outputs a gradation control pulse at a constant cycle over a period in which a selection voltage is applied, and density data indicating the gradation of a pixel are converted into gradation data corresponding to each of the gradation control pulses. In addition, the conversion circuit for conversion and one scanning line are selected in the direction in which the difference between the gradation indicated by the density data of the pixel of interest and the gradation of the pixel actually displayed by the gradation data is eliminated. In the period in which the selection voltage is applied, the timing at which the gradation control pulse corresponding to the gradation data of the pixel at the intersection of the selected scanning line and the data line is supplied is defined as the start point or the end point. The period An electro-optical device, comprising: a data line driving circuit that applies a lighting voltage for turning on a pixel. 2. The conversion circuit eliminates the difference between the gray scale indicated by the density data of the pixel of interest and the gray scale of the pixel actually displayed by the gray scale data in units of a plurality of vertical scanning periods. The electro-optical device according to claim 1, wherein conversion is performed in the direction. 3. The conversion circuit eliminates the difference between the gradation indicated by the density data of the pixel of interest and the gradation of the pixel actually displayed by the gradation data in units of a plurality of pixels. The electro-optical device according to claim 1, which performs conversion. 4. A pixel provided corresponding to an intersection of a scanning line and a data line, a scanning line driving circuit for selecting one scanning line and applying a selection voltage to the selected scanning line, A pulse generation circuit that outputs a gradation control pulse at an interval obtained by adding intervals of 1, 2, 4 or 8 times a constant period over a period in which a selection voltage is applied, and one scanning line is selected. In the period in which the selection voltage is applied, the timing at which the gradation control pulse corresponding to the gradation data of the pixel at the intersection of the selected scanning line and the data line is supplied is set as the start point or the end point. An electro-optical device comprising: a data line driving circuit which applies a lighting voltage for turning on the pixel for a period. 5. An electronic apparatus comprising the electro-optical device according to claim 1 or 4 as a display unit.