JP2005051469A - Encoding device and encoding method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an encoding device and encoding method of which the circuit scale can be reduced; and to provide a program. <P>SOLUTION: An information bit storage memory 121 stores input data D121. The information bit storage memory 121 reads bits according to the parity check matrix of an LDPC code out of each bit of the stored input data D121 based on a control signal D125 supplied from a control signal generation section 124 and supplies the bits as information bits D122-1 to D122-7 to a computing unit 122. The computing unit 122 adds an one-bit parity bit D123 stored on a shift register 123 to the information bits D122-1 to D122-7 to obtain a new one-bit parity bit D124 responsible for the LDPC code for storage in the shift register 123. The present invention is applicable to the coding device conducting LDPC coding. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an encoding device, an encoding method, and a program, and more particularly, to an encoding device, an encoding method, and a program that perform low-density parity check encoding on predetermined information.

  In recent years, for example, the field of communication such as mobile communication and deep space communication and the field of broadcasting such as terrestrial or satellite digital broadcasting have been remarkably advanced. Research on coding theory is also actively conducted.

  As the theoretical limit of code performance, the Shannon limit given by the so-called Shannon (C. E. Shannon) channel coding theorem is known. Research on code theory is being conducted with the goal of developing codes that exhibit performance close to the Shannon limit. In recent years, encoding methods that exhibit performance close to the Shannon limit include so-called parallel concatenated convolutional codes (PCCC (Parallel Concatenated Convolutional Codes)) and tandem concatenated convolutional codes (SCCC (Serially Concatenated Convolutional Codes)). A technique called turbo coding has been developed.

  The column concatenated convolutional encoding is performed by an apparatus configured by connecting two convolutional encoders and an interleaver in a column. The decoding of the column concatenated convolutional code is performed by an apparatus configured by connecting two decoding circuits that output a soft-output in a column, and exchanges information between the two decoding circuits. A final decoding result is obtained.

  Further, as an application of this serially concatenated convolutional coding, repeat-accumulate code (RA coding) described in Non-Patent Document 1 is known. Further, Non-Patent Document 2 proposes an irregular repeat-accumulate code (IRA code) that is an extension of RA coding.

  FIG. 1 shows a configuration example of an encoding apparatus that performs IRA encoding.

  The encoding device 1 includes an encoding code unit 11, an interleaver 12, and an accumulator 13.

  The iterative encoding unit 11 performs a first code (hereinafter referred to as an outer code as appropriate) of the input data D11 to be encoded. Specifically, the repetitive encoding unit 11 repeats each bit of the input data D11 for an arbitrary number of times that is not constant, and supplies the same to the interleaver 12 as the first code D12. The interleaver 12 rearranges the order of the first code D12 supplied from the repetitive encoding unit 11, and supplies the rearranged data as data D13 to the accumulator 13. The accumulator 13 converts the data D13 into a second code (hereinafter referred to as an inner code as appropriate) and outputs a second code D14.

  In the encoding apparatus 1, a code sequence that combines the input data D11 and the second code D14 output from the accumulator 13 is output to the communication path as an IRA encoding result for the input data D11.

  FIG. 2 shows a configuration example of the interleaver 12 of FIG.

  The interleaver 12 includes an input data holding memory 31, a replacement data ROM (Read Only Memory) 32, a data replacement circuit 33, and an output data holding memory 34.

  The interleaver 12 is supplied with the first code D12 from the repetitive encoding unit 11, and the first code D12 is held in the input data holding memory 31. The input data holding memory 31 reads the held first code D12 and supplies it to the data replacement circuit 33. The replacement data ROM 32 stores position information for replacement for the first code D12 performed by the data replacement circuit 33. The data replacement circuit 33 reads the replacement position information stored in the replacement data ROM 32, and replaces the position (order) of the first code D12 supplied from the input data holding memory 31 based on the replacement position information. Sort). Then, the data replacement circuit 33 supplies the replacement result to the output data holding memory 34 to hold it. Then, the output data holding memory 34 reads the held replacement result of the first code D12 and outputs it as data D13 to the accumulator 13.

  That is, the interleaver 12 performs interleaving on the first code D12 supplied from the iterative encoding unit 11, and supplies the result to the accumulator 13 as data D13.

  FIG. 3 shows a configuration example of the accumulator 13 of FIG.

  In the accumulator 13, for example, seven consecutive data D13 supplied from the interleaver 12 is set as one set, a predetermined process is performed on the input of the set, and one data is output.

  The accumulator 13 includes an arithmetic unit 51 and a shift register 52. The calculator 51 is supplied with seven pieces of data D13 from the interleaver 12, and the data D13 is supplied to the calculator 51. The computing unit 51 adds the seven data D13 supplied from the interleaver 12 and the data supplied from the shift register 52 on GF (2) (calculates an exclusive OR), and the addition result Is output as the second code D14 and supplied to the shift register 52. The shift register 52 stores the second code D14 supplied from the calculator 51 and supplies the already stored data (the addition result added by the calculator 51 immediately before) to the calculator 51.

  The data D13 supplied to the computing unit 51 may be any number of continuous data instead of the seven continuous data.

  While these turbo codings have been developed, the use of low density parity check codes (hereinafter referred to as LDPC codes as appropriate), which is an encoding method that has been known for a long time, has been attracting attention.

  The LDPC code was first proposed in Non-Patent Document 3 by R. G. Gallager, and was later rediscovered by Non-Patent Document 4, Non-Patent Document 5, and the like.

  Recent studies have shown that LDPC codes can achieve performance close to the Shannon limit as the code length is increased, similar to turbo codes and the like. In addition, since the LDPC code has the property that the minimum distance is proportional to the code length, its characteristic is that the block error probability characteristic is good, and furthermore, the so-called error floor phenomenon observed in the decoding characteristic such as turbo code is observed. An advantage is that it hardly occurs.

  Hereinafter, such an LDPC code will be specifically described. Note that the LDPC code is a linear code and does not necessarily need to be binary, but will be described here as being binary.

  The LDPC code is characterized by the fact that the parity check matrix that defines the LDPC code is sparse. Here, the sparse matrix is configured so that the number of "1" of the matrix components is very small. If the sparse check matrix is represented by H, as such a check matrix, for example, As shown in FIG. 4, the hamming weight (number of “1” s) (weight) of each column is “3”, and the hamming weight of each row is “6”.

  Thus, an LDPC code defined by a parity check matrix H in which the Hamming weight of each row and each column is constant is referred to as a regular LDPC code. On the other hand, an LDPC code defined by a parity check matrix H in which the Hamming weight of each row and each column is not constant is referred to as an irregular LDPC code.

Such encoding into an LDPC code generates a generation matrix G based on a parity check matrix H, and generates a codeword c by multiplying the generation matrix G by binary information (message). It is realized with. Specifically, coding apparatus for coding to the LDPC code, first, between the transposed matrix H ^T of the parity check matrix H, calculates a generator matrix G which formula GH ^T = 0 is established. Here, when the generator matrix G is a k × n matrix, the encoding device multiplies the generator matrix G by an information word consisting of k bits, and a code word c (= uG) consisting of n bits. Is generated. The code word c generated by this encoding device is transmitted after being mapped such that the sign bit with the value "0" is "+1", the sign bit with the value "1" is "-1", etc. The data is received by the decoding device via a predetermined communication path.

  By the way, generally, when the code length is particularly large, it is not easy to obtain a generator matrix from a check matrix. Further, even if a generation matrix is obtained, it is often not reduced in density, and in this case, the amount of calculation for encoding becomes enormous. Therefore, when an LDPC code is configured by adding parity of 1 bit or more to information, the product of a check matrix H and a codeword c obtained by LDPC encoding information is 0 (0 vector). There is a method of performing LDPC encoding of information by obtaining the parity added to the information. Such LDPC encoding can be performed by the encoding device 1 of FIG.

D. Divsalar, H. Jin, RJMcEliece, “Coding Theorems for“ Turbo-Like ”Codes,” in Proc. 36th Allerton Conf.on Communication, Control, and Computing, Allerton, Illinois, USA, pp. 201-210, Sept. 1998 H.Jin, A.Khandekar, R.J.McEliece, “Irregular Repeat-Accumulate Codes,” in Proc. 2nd International Symposium on Turbo Codes & Related Topics, Brest, France, pp. 1-8, Sept. 2000 R. G. Gallager, “Low Density Parity Check Codes” Cambridge, Massachusetts: M. I. T. Press, 1963 D. J. C. MacKay, “Good error correcting codes based on very sparse matrices,” Submitted to IEEE Trans. Inf. Theory, IT-45, pp. 399-431, 1999 M. G. Luby, M. Mitzenmacher, M. A. Shokrollahi and D. A. Spielman, “Analysis of low density codes and improved designs using irregular graphs,” Available at http://www.icsi.berkeley.edu/luby/

  However, when the information is LDPC-encoded using the encoding device 1 of FIG. 1, the iterative encoding unit 11 repeats the input data D11 an arbitrary number of times, and the interleaver is used as the first code D12. In order to supply to 12, a memory for storing input data is required. Furthermore, in the interleaver 12, in order to rearrange the order of the first code D12 supplied from the iterative encoding unit 11, the input data holding memory 31 for storing the first code D12 and the rearranged first code An output data holding memory 34 that holds D12 is required. In particular, as the input data holding memory 31 and the output data holding memory 34 of the interleaver 12, a memory having a large storage capacity is required.

  Thus, since the encoding device 1 requires a memory with a large storage capacity, the circuit scale becomes large. Therefore, the encoding apparatus 1 has a problem that the cost is increased and the power consumption of the apparatus is increased.

  The present invention has been made in view of such a situation, and makes it possible to reduce the circuit scale of an encoding device.

  The encoding apparatus of the present invention includes a storage unit that stores one bit of parity of an LDPC code, a bit according to a parity check matrix of an LDPC code among each bit of information, and a 1-bit stored in the storage unit Computation means for obtaining a new 1-bit parity of the LDPC code by adding the parity and supplying the parity to the storage means is provided.

  The parity part of the parity check matrix corresponding to the parity of the LDPC code can have a stepped structure.

  The check matrix used in the arithmetic means is such that the parity part has a stepped structure by performing row replacement of the original check matrix or column replacement of the parity part of the original check matrix. can do.

  It is possible to further include information storage means for storing information and for reading each bit of the stored information at least once.

  It is possible to further comprise information storage means for storing information and for reading the stored information bit by bit.

  A thinning means for thinning out the calculation result calculated by the calculating means can be further provided.

  In the encoding method of the present invention, a storage step for storing one bit of parity of an LDPC code in the storage means, bits according to a parity check matrix of the LDPC code among each bit of information, and the storage means And calculating a new 1-bit parity of the LDPC code by adding the 1-bit parity and supplying the parity to the storage means.

  The program of the present invention includes a storage step for storing one bit of parity of the LDPC code in the storage means, a bit according to the parity check matrix of the LDPC code of each bit of information, and one bit stored in the storage means And calculating a new 1-bit parity of the LDPC code to be supplied to the storage means.

  In the present invention, 1 bit of parity of the LDPC code is stored, and by adding the bit according to the parity check matrix of the LDPC code and the stored 1-bit parity of each bit of information, A new 1-bit parity of the code is determined and stored.

  According to the present invention, it is possible to reduce the circuit scale of an encoding apparatus that performs LDPC encoding of predetermined information, thereby reducing costs and reducing power consumption of the apparatus.

  Embodiments of the present invention will be described below. Correspondences between constituent elements described in the claims and specific examples in the embodiments of the present invention are exemplified as follows. This description is to confirm that specific examples supporting the invention described in the claims are described in the embodiments of the invention. Therefore, even if there are specific examples that are described in the embodiment of the invention but are not described here as corresponding to the configuration requirements, the specific examples are not included in the configuration. It does not mean that it does not correspond to a requirement. On the contrary, even if a specific example is described here as corresponding to a configuration requirement, this means that the specific example does not correspond to a configuration requirement other than the configuration requirement. not.

  Further, this description does not mean that all the inventions corresponding to the specific examples described in the embodiments of the invention are described in the claims. In other words, this description is an invention corresponding to the specific example described in the embodiment of the invention, and the existence of an invention not described in the claims of this application, that is, in the future, a divisional application will be made. Nor does it deny the existence of an invention added by amendment.

  The encoding apparatus according to claim 1, a storage unit (for example, shift register 123 in FIG. 8) that stores one bit of parity of the LDPC code, and an inspection of the LDPC code of each bit of the information Arithmetic means (for example, FIG. 4) that obtains a new 1-bit parity of the LDPC code by adding the bit according to the matrix and the 1-bit parity stored in the storage means. 8 arithmetic units 122).

  The encoding device according to claim 4 is the encoding device according to claim 1, wherein the information is stored, and each bit of the stored information is read out at least once (for example, FIG. 8). The information bit storage memory 121) is further provided.

  The encoding device according to claim 5 is the encoding device according to claim 1, wherein the information is stored, and the stored information is read out bit by bit (for example, the information bit in FIG. 10). It further comprises a storage memory 141).

  An encoding apparatus according to a sixth aspect is the encoding apparatus according to the fifth aspect, further comprising a thinning-out means (for example, a puncture circuit 144 in FIG. 10) for thinning out the calculation result calculated by the calculation means. It is characterized by that.

  The encoding method according to claim 7 is an encoding method of an encoding device that encodes predetermined information into an LDPC (Low Density Parity Check) code, wherein one bit of the parity of the LDPC code is stored in a storage means. A storage step (for example, step S6 in FIG. 9) to be stored, a bit in each bit of the information according to the LDPC code check matrix, and a 1-bit parity stored in the storage means are added Thus, a calculation step (for example, step S5 in FIG. 9) of obtaining a new 1-bit parity of the LDPC code and supplying it to the storage means is included.

  A specific example of each step of the program described in claim 8 is also the same as the specific example in the embodiment of the invention of each step of the encoding method according to claim 7.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

  FIG. 5 shows an example of a parity check matrix H used for LDPC encoding.

  The parity check matrix H in FIG. 5 is a parity check matrix for encoding 60-bit information into a 90-bit LDPC code (coding rate 2/3, code length 90), and is 30 (rows) × 90 (columns). It is a matrix. In the parity check matrix of FIG. 5 (the same applies to FIG. 7 described later), 0 is represented by “.”.

  Here, the LDPC code obtained by encoding information using parity check matrix H in FIG. 5 is a systematic code in which all 60-bit information appears as it is among 90-bit codes. That is, LDPC encoding is performed by generating 30-bit parity from 60-bit information, and thus the LDPC code is composed of 60-bit information and 30-bit parity.

  Accordingly, the check matrix H is a matrix of 30 (rows) (from the first row to the 30th row) × 60 (columns) (from the first column to the 60th column) corresponding to 60-bit information of the LDPC code. A certain information part and a parity part which is a matrix of 30 (rows) (from the first line to the 30th line) × 30 (columns) (from the 61st column to the 90th column) corresponding to the 30-bit parity of the LDPC code And can be divided into

  In decoding the LDPC code, the information part is multiplied by the information (information bit) of the LDPC code, and the parity part is multiplied by the parity (parity bit) of the LDPC code.

  In the parity check matrix H in FIG. 5, each row of the information part corresponding to the information of the LDPC code is composed of seven “1” s and 53 “0” s. The parity part is a matrix having a lower triangular structure (lower triangular matrix).

  That is, the parity part of the parity check matrix H in FIG. 5 is a matrix in which the upper right corner of the diagonal line of the matrix is all “0”, and has a lower triangular structure.

By the way, as described above, an encoding device that performs encoding into an LDPC code calculates a generation matrix G in which the expression GH ^T = 0 holds between the transposed matrix H ^T of the parity check matrix H, and generates LDPC encoding is performed by multiplying the matrix G by an information word to generate a codeword c (= uG). Therefore, the encoding device can perform LDPC encoding of information by obtaining a codeword c that holds the expression Hc ^T = 0 (superscript ^T represents transposition) with the check matrix H. it can.

  Therefore, the encoding device may generate a codeword c in which the sum of the values of the codeword c corresponding to a certain position of “1” in each row of the check matrix H is 0 on GF (2). As shown in FIG. 5, LDPC encoding using parity check matrix H whose parity part has a lower triangular structure can be performed as follows.

  That is, in the first row of the parity check matrix H in FIG. 5, there are seven “1” s in the 1st to 60th columns as the information part, and “1” in the 61st column as the first column of the parity part. There is. Therefore, the encoding device has a value of the code word c corresponding to a certain position of “1” in the information part of the first row, that is, among information values (information bits) including 60 bits of the code word c. Calculate the sum (exclusive OR) on GF (2) of all information bits (seven information bits) corresponding to a position with “1” in the information part, and the value is 61 bits of code word c By using the parity of the eye, the sum on the GF (2) of the value of the code word c corresponding to a position where “1” is in the first row can be made zero.

  For example, when the sum on GF (2) of 7 information bits corresponding to a certain position of “1” in the information part in the first row is “1”, the encoding device determines that the code word c The parity of the 61st bit is set to “1”. In this case, the sum on GF (2) of 7 information bits corresponding to a position where “1” is in the information part of the first row is “1”, and the parity of the 61st bit of the code word c is Since it is “1”, the sum of the value of the code word c corresponding to a position of “1” in the first row of the parity check matrix on GF (2) becomes 0.

  In the second row of the parity check matrix H, there are seven “1” s in the first to 60th columns as the information part, and “1” in the 62nd column as the second column of the parity part. Therefore, the encoding apparatus calculates the sum on GF (2) of 7 information bits corresponding to a certain position of “1” in the information part of the second row, and calculates the sum as 62 bits of the code word c. By using the parity of the eye, the sum on the GF (2) of the value of the code word c corresponding to the position where “1” in the second row is present can be made zero.

  For example, when the sum on GF (2) of 7 information bits corresponding to a certain position of “1” in the information part in the second row is “0”, the encoding device determines that the code word c The parity of the 62nd bit is set to “0”. In this case, the sum on the GF (2) of 7 information bits corresponding to a position where “1” in the information part of the second row is “0”, and the parity of the 62nd bit is “0”. Therefore, the sum of the value of the code word c corresponding to the position at “1” in the second row of the parity check matrix on GF (2) is zero.

  In the third row of the check matrix H, there are seven “1” s in the 1st to 60th columns which are information parts, and the 61st and 63rd columns which are the first and third columns of the parity part. There is “1”. Therefore, the encoding apparatus has seven information bits corresponding to the position where “1” is present in the information part of the third row, and the value of the parity bit corresponding to the position where “1” is already obtained in the parity part. That is, the sum on the GF (2) of the parity value of the 61st bit of the code word c already obtained by the calculation in the first row is calculated, and this value is calculated as the 63rd bit parity of the code word c. By doing so, the sum on the GF (2) of the value of the codeword c corresponding to a position where “1” is in the third row can be made zero.

  For example, the sum on the GF (2) of 7 information bits corresponding to a certain position of “1” in the information part in the third row is “1”, and the parity of the 61st bit of the code word c When the value is “1”, the encoding apparatus sets the parity of the 63rd bit of the codeword c to “0”. In this case, the sum on GF (2) of 7 information bits corresponding to a position where “1” in the information part of the third row is “1”, and the parity of the 61st bit of the code word c is Since the parity of “1” and the 63rd bit is “0”, the sum of the value of the codeword c corresponding to the position of “1” in the third row of the parity check matrix on GF (2) is 0. Become.

  The encoding apparatus also has “1” for each row of the information part of the parity check matrix H in the 4th to 30th rows of the parity check matrix H, as in the 2nd and 3rd rows. Calculates the exclusive OR of the 7 information bits corresponding to the position and an arbitrary bit of the already calculated parity, that is, the parity bit corresponding to the position where “1” of the parity part already obtained for each row By doing so, the parity (bit) is obtained one bit at a time, and finally the 30-bit parity is obtained. Then, the encoding device generates a 90-bit code word c by combining the 60 information bits and the 30 parity bits, thereby using the check matrix H without using the generation matrix G. The information can be LDPC encoded.

  FIG. 6 shows a configuration example of an encoding apparatus that performs LDPC encoding of information using parity check matrix H of FIG. Although not shown (the same applies to FIGS. 8 and 10 to be described later), the codewords that are the encoding results are rearranged or mapped to transmission symbols in the subsequent stage of the encoding device. A device is provided.

  The encoding device 100 includes an information bit storage memory 101, a parity bit storage memory 102, a computing unit 103, and a control signal generation unit 104.

  The encoding device 100 receives 60-bit unit input data D101, which is information (bits) to be subjected to LDPC encoding, and the input data D101 is supplied to and stored in the information bit storage memory 101. The input data D101 is output as part of a codeword obtained by LDPC encoding.

  A control signal D105 is supplied from the control signal generation unit 104 to the information bit storage memory 101, and the information bit storage memory 101 receives the 60-bit input data D101 stored in FIG. 7 based on the control signal D105. In order from the first row of the information part of the parity check matrix H, input data (bits) corresponding to a position having “1” for each row is read, and 7 bits (the number of “1” s in each row of the information part) are 1 bit. Information bits D102-1 to D102-7 are supplied to the computing unit 103.

  The parity bit storage memory 102 is supplied with one parity bit D104 from the arithmetic unit 103, and the parity bit storage memory 102 stores the parity bit D104. Further, the control signal D106 is supplied from the control signal generation unit 104 to the parity bit storage memory 102, and the parity bit storage memory 102 is supplied from the arithmetic unit 103 and stored by the previous calculation based on the control signal D106. The parity bit D103 corresponding to the position where “1” is in the parity part for each row is read, and the parity bit D103 is supplied to the computing unit 103.

  The arithmetic unit 103 is supplied with seven (7-bit) information bits D102-1 to D102-7 from the information bit storage memory 101, and from the parity bit storage memory 102, “1” of the parity part for each row. A parity bit D103 corresponding to a certain position is supplied. The computing unit 103 uses 7 bits of information bits D102-1 to D102-7 and the GF (2) of the parity bit D103 corresponding to the position where “1” is stored in the parity part for each row obtained up to the previous computation. The above sum (exclusive OR) is calculated, and the calculation result is supplied to the parity bit storage memory 102 as a new 1-bit parity bit D104, and a part of the code word obtained by LDPC encoding the input data D101 Output as.

  The control signal generation unit 104 controls the information bit storage memory 101 so as to read the input data D101 corresponding to a position where “1” exists for each row in order from the first row of the information portion of the parity check matrix H. D105 is generated and supplied to the information bit storage memory 101. Further, the control signal generation unit 104 stores the parity bit so as to output a parity bit corresponding to the position where “1” is stored in the parity part for each row that is supplied from the arithmetic unit 103 until the previous calculation. A control signal D106 for controlling the memory 102 is generated and supplied to the parity bit storage memory 102.

  In the encoding apparatus 100 of FIG. 6, the arithmetic unit 103 repeats the calculation 30 times, thereby obtaining 30 parity bits D104. Then, the encoding apparatus 100 combines the 60-bit input data D101 and the 30-bit parity bit D104 obtained by the computing unit 103 to generate a 90-bit code word c, thereby generating a 60-bit input. Data D101 is LDPC encoded.

  FIG. 7 shows another example of parity check matrix H used for LDPC encoding.

  The parity check matrix H in FIG. 7 is a parity check matrix for encoding 60-bit information into a 90-bit LDPC code (coding rate 2/3, code length 90), as in FIG. It is a (row) × 90 (column) matrix.

  Here, the LDPC code obtained by encoding information using the parity check matrix H in FIG. 7 is a systematic code in which all 60-bit information appears as it is in a 90-bit code. That is, LDPC encoding is performed by generating 30-bit parity from 60-bit information, and thus the LDPC code is composed of 60-bit information and 30-bit parity.

  Therefore, the parity check matrix H in FIG. 7 is 30 (rows) (from the first row to the 30th row) × 60 (columns) (1) corresponding to the 60-bit information of the LDPC code, as in FIG. The information part which is a matrix of columns (from the 60th column to the 60th column) and 30 (row) (from the 1st row to the 30th row) corresponding to the 30-bit parity of the LDPC code × 30 (column) (from the 61st column) And a parity part which is a matrix of up to the 90th column).

  In decoding the LDPC code, the information part is multiplied by the information of the LDPC code, and the parity part is multiplied by the parity of the LDPC code.

  In the parity check matrix H in FIG. 7, each row of the information portion corresponding to the information of the LDPC code includes seven “1” s and 53 “0s”. The parity part is a matrix having a stepped structure.

  That is, the parity part of the parity check matrix H in FIG. 7 is a matrix in which the previous column of the unit matrix that is “1” in each row except the first row is also “1”. It has a step-like structure that falls to the right (upward to the left).

By the way, as described above, an encoding device that performs encoding into an LDPC code calculates a generation matrix G in which the expression GH ^T = 0 holds between the transposed matrix H ^T of the parity check matrix H, and generates LDPC encoding is performed by multiplying the matrix G by an information word to generate a codeword c (= uG). Therefore, the encoding device can perform LDPC encoding of information by obtaining a codeword c that holds the expression Hc ^T = 0 (superscript ^T represents transposition) with the check matrix H. it can.

  Therefore, the encoding device may generate a codeword c in which the sum of the values of the codeword c corresponding to a certain position of “1” in each row of the check matrix H is 0 on GF (2). As shown in FIG. 7, LDPC encoding using a parity check matrix H in which the parity part has a stepped structure can be performed as follows.

  That is, in the first row of the parity check matrix H in FIG. 7, there are seven “1” s in the 1st to 60th columns as the information part, and “1” in the 61st column as the first column of the parity part. There is. Therefore, the encoding device has a value of the code word c corresponding to a certain position of “1” in the information part of the first row, that is, among information values (information bits) including 60 bits of the code word c. Calculate the sum (exclusive OR) on GF (2) of all information bits (seven information bits) corresponding to a position with “1” in the information part, and the value is 61 bits of code word c By using the parity of the eye, the sum on the GF (2) of the value of the code word c corresponding to the position where “1” in the first row is present can be made zero.

  For example, when the sum on GF (2) of 7 information bits corresponding to a certain position of “1” in the information part in the first row is “1”, the encoding device determines that the code word c The parity of the 61st bit is set to “1”. In this case, the sum on GF (2) of 7 information bits corresponding to a position where “1” is in the information part of the first row is “1”, and the parity of the 61st bit of the code word c is Since it is “1”, the sum of the value of the code word c corresponding to a position of “1” in the first row of the parity check matrix on GF (2) becomes 0.

  In the second row of the check matrix H, there are seven “1” s in the 1st to 60th columns which are information parts, and the 61st and 62nd columns which are the first and second columns of the parity part. There is “1”. Therefore, the encoding apparatus performs the 7th information bit corresponding to a certain position of “1” in the information part of the second row and the 61st bit of the code word c already obtained by the calculation of the first row. The sum of the parity values on GF (2) is calculated, and the value is used as the parity of the 62nd bit of the code word c, so that the code word c corresponding to the position where “1” is in the second row The sum of the values on GF (2) can be made zero.

  For example, the sum of GF (2) of 7 information bits corresponding to a certain position of “1” in the information part of the second row is “0”, and the parity of the 61st bit of the code word c When the value is “1”, the encoding apparatus sets the parity of the 62nd bit of the codeword c to “1”. In this case, the sum on the GF (2) of 7 information bits corresponding to a position where “1” in the information part of the second row is “0”, and the parity of the 61st bit of the code word c is Since the parity of “1” and the 62nd bit is “1”, the sum of the value of the codeword c corresponding to the position of “1” in the second row of the parity check matrix on GF (2) is 0. Become.

  In the third to 30th rows of the parity check matrix H, the encoding apparatus 7 corresponds to a position where “1” exists for each row of the information part of the parity check matrix H as in the second row. By calculating the exclusive OR of each information bit and the parity bit obtained immediately before, the parity (bit) is obtained one bit at a time, and finally the 30-bit parity is obtained. Then, the encoding device generates a 90-bit code word c by combining the 60 information bits and the 30 parity bits, thereby using the check matrix H without using the generation matrix G. The information can be LDPC encoded.

  Note that the parity check matrix H in FIG. 7 is a lower triangular matrix in which the parity portion is all “0” in the upper right corner of the diagonal of the matrix, similar to the parity check matrix H in FIG. 5. Therefore, information can be LDPC-encoded according to the check matrix H of FIG. 7 using the encoding apparatus 100 of FIG.

  However, as described above, when the information is LDPC encoded according to the parity check matrix H in FIG. 7, the encoding apparatus is different from the case where the information is LDPC encoded according to the parity check matrix H in FIG. It is not necessary to calculate an exclusive OR using any bit of the calculated parity, that is, all parity bits corresponding to a position where “1” in the parity part of each row obtained until the previous time is used. A new parity bit can be obtained by calculating an exclusive OR using only the parity bit obtained in step (b). Accordingly, when information is LDPC encoded according to the parity check matrix H in FIG. 7, only the parity bit obtained immediately before needs to be stored, and it is not necessary to store all the parity obtained so far.

  FIG. 8 is a block diagram showing a configuration example of an embodiment of an encoding apparatus to which the present invention is applied.

  8 uses a shift register 123 that stores only the parity bit calculated immediately before, instead of the parity bit storage memory 102, and converts input data (information) according to the check matrix H of FIG. LDPC encoding.

  That is, the encoding device 120 includes an information bit storage memory 121, an arithmetic unit 122, a shift register 123, and a control signal generation unit 124.

  The encoding device 120 receives 60-bit input data D121, which is information (bits) to be subjected to LDPC encoding, and the input data D121 is supplied to and stored in the information bit storage memory 121. The input data D121 is output as part of a codeword obtained by LDPC encoding.

  The control signal D125 is supplied from the control signal generator 124 to the information bit storage memory 121. The information bit storage memory 121 receives the information part of the check matrix H from the stored input data D121 based on the control signal D125. In order from the first row, the input data corresponding to the position where “1” exists for each row is read, and seven (the number of “1” in each row of the information portion) of 1-bit information bits D122-1 to D122- 7 is supplied to the calculator 122.

  The arithmetic unit 122 is supplied with 7-bit information bits D122-1 to D122-7 from the information bit storage memory 121 and is also supplied with 1-bit parity bit D123 from the shift register 123. The arithmetic unit 122 calculates the addition of each of the 7-bit information bits D122-1 to D122-7 and the 1-bit parity bit D123, that is, an exclusive OR here. Then, the arithmetic unit 122 supplies the result of the operation as a new 1-bit parity (bit) D124 to the shift register 123 and outputs the input data D121 as a part of a codeword obtained by LDPC encoding.

  The shift register 123 is supplied with the 1-bit parity bit D124 calculated immediately before from the arithmetic unit 122, and the shift register 123 stores (holds) the parity bit D124. The shift register 123 supplies the already stored parity bit D123 to the arithmetic unit 122.

  The control signal generation unit 124 controls the information bit storage memory 121 so as to read the input data D121 corresponding to a position where “1” exists for each row in order from the first row of the information portion of the parity check matrix H. D125 is generated and supplied to the information bit storage memory 121.

  In the encoding device 120 of FIG. 8, the arithmetic unit 122 repeats the calculation 30 times, thereby obtaining 30 parity bits D124. Then, the encoding device 120 combines the 60-bit input data D121 and the 30-bit parity bit D124 obtained by the arithmetic unit 122 to generate a 90-bit codeword c, thereby generating a 60-bit input. Data D121 is LDPC encoded into a 90-bit codeword.

  As described above, in the encoding device 120, the shift register 123 stores only one parity bit that is the result of the calculation performed immediately before by the calculator 122. Compared to the parity bit storage memory 102 that stores parity bits (30 bits in FIG. 6), the circuit size can be reduced compared to the encoding device 100 of FIG. In particular, when encoding into a code having a long code length and a large number of parity bits, the memory capacity of the parity bit storage memory 102 for storing all the parity bits is increased, so that the circuit scale can be reduced. growing.

  The calculator 122 and the shift register 123 have the same configuration as the calculator 51 and the shift register 52 of the accumulator 13 shown in FIG. Therefore, the encoding device 120 can be configured by replacing the iterative encoding unit 11 and the interleaver 12 of the encoding device 1 of FIG. 1 with the control signal generation unit 124 and the information bit storage memory 121. As described above, the encoding device 120 is provided with the input data holding memory 31 and the output data holding memory 34 (FIG. 2) of the interleaver 12 by replacing the repetitive encoding unit 11 and the interleaver 12 of the encoding device 1. The storage capacity for storing data can be greatly reduced as compared with the encoding device 1. Thereby, in the encoding device 120, the circuit scale can be reduced as compared with the encoding device 1.

  FIG. 9 is a flowchart for describing the encoding process of the encoding device 120 of FIG. This encoding process starts when, for example, 60-bit input data D121, which is information (bits) to be subjected to LDPC encoding, is input to the encoding device 120.

  In step S1, the information bit storage memory 121 stores the input 60-bit input data D121, and proceeds to step S2.

  In step S2, the control signal generation unit 124 sets the first row of the information portion of the parity check matrix H as a processing target row (target row) based on the parity check matrix H of FIG. A control signal D125 for controlling to read input data D121 corresponding to a certain position is generated and supplied to the information bit storage memory 121.

  After the process of step S2, the process proceeds to step 3, and the information bit storage memory 121 uses the control data D125 supplied from the control signal generator 124 to obtain information on the check matrix H from the input data D121 stored in step S1. The input data D121 corresponding to a certain position of “1” in the target row of the part is read out, that is, seven (the number of “1” s in the target row of the information part) 1-bit information bits D122-1 to D122-7 Is supplied to the calculator 122. Then, the information bit storage memory 121 proceeds from step S3 to step S4.

  In step S4, the shift register 123 supplies the 1-bit parity bit D123 stored (stored) in step S6, which will be described later, to the computing unit 122, and proceeds to step S5. At the start of the encoding process, “0” is stored in the shift register 123 as an initial value. Accordingly, in the first step S 4, the shift register 123 supplies “0” to the calculator 122.

  In step S5, the arithmetic unit 122 adds a bit according to the parity check matrix H in FIG. 7 of each bit of the input data D121 and a 1-bit parity stored in the register 123 to obtain a new one. Obtain 1-bit parity. That is, the arithmetic unit 122 uses the seven 1-bit information bits D122-1 to D122-7 supplied from the information bit storage memory 121 and the 1-bit parity bit D123 supplied from the shift register 123. The exclusive OR of seven 1-bit information bits D122-1 to D122-7 and 1-bit parity bit D123 is calculated, and a new 1-bit parity bit D124, that is, the target row is the n-th row. In this case, the parity bit D124 of the nth bit is obtained. Then, the arithmetic unit 122 supplies a new 1-bit parity bit D124 to the shift register 123.

  After the processing in step S5, the process proceeds to step S6, and the shift register 123 stores (holds) the new 1-bit parity bit D124 supplied from the computing unit 122 by overwriting the previously stored parity bit. Then, the process proceeds to step S7. In step S7, the calculator 122 outputs a new 1-bit parity bit D124, which is the calculation result, and proceeds to step S8.

  In step S8, the control signal generation unit 124 determines whether all parity bits have been output. That is, the control signal generation unit 124 determines whether or not the control signal D125 has been generated with all rows of the check matrix H as target rows.

  In step S8, if the control signal generation unit 124 determines that all the parity bits are not output, the control signal generation unit 124 returns to step S2, and sets the next row after the current row as a new target row. The above processing is repeated. Therefore, the information bit storage memory 121 reads the input data D121 corresponding to a position where “1” in the information part of the parity check matrix H is at least once for each target row, and reads seven pieces (“1 in the target row of the information part). As the 1-bit information bits D122-1 to D122-7.

  In encoding apparatus 120, the above-described processing is repeated the number of rows of parity check matrix H (30 in the case of the parity check matrix in FIG. 7) times, and a total of 30 parity bits D124 are output.

  On the other hand, if the control signal generation unit 124 determines in step S8 that all parity bits have been output, the process ends. At this time, the encoding device 120 outputs a 90-bit code word c, which is a combination of the 60-bit input data D121 and the total 30-bit parity bits D124 output in step S7, as an encoding result. .

  The encoding process in FIG. 9 is repeated each time 60-bit input data D121 to be encoded next is supplied to the encoding apparatus.

  FIG. 10 shows a configuration example of another embodiment of an encoding apparatus to which the present invention is applied.

  10 uses the parity check matrix H of FIG. 7 to perform LDPC encoding on input data (information).

  In the encoding device 120 of FIG. 8, the arithmetic unit 122 obtains an exclusive OR of 7-bit input data and 1-bit parity bit by a single operation. In 140, the exclusive OR of the 7-bit input data and the 1-bit parity bit is obtained by sequentially calculating the exclusive OR of the two 1-bits. Therefore, in the encoding device 140 of FIG. 10, the seventh operation result of the exclusive OR of two 1-bit bits becomes a parity bit.

  That is, the exclusive OR of the first bit and the second bit of the seven 1-bit input data corresponding to the position of “1” in the first row of the information part of the check matrix H is calculated, and the calculation result Then, an exclusive OR of the third bit is calculated. Further, the operation result and the exclusive OR of the 4th bit are calculated. Thereafter, the exclusive OR of the 7-bit input data is calculated in the same manner to obtain the first parity bit. It is done. Next, the exclusive OR of the first bit of the parity bit of the first bit and seven 1-bit input data corresponding to the position where “1” in the second row of the information part of the check matrix H is calculated Then, the operation result and the exclusive OR of the second bit are calculated. Further, an exclusive OR of the calculation result and the third bit is calculated, and thereafter, in the same manner, at the position where the parity bit of the first bit and “1” in the second row of the information part of the check matrix H are present. By calculating an exclusive OR with corresponding 7-bit input data, a second parity bit is obtained. Other parity bits are obtained in the same manner.

  10, the encoding device 140 includes an information bit storage memory 141, an arithmetic unit 142, a shift register 143, a puncture circuit 144, and a control signal generation unit 145.

  The encoding device 140 receives 60-bit input data D141, which is information (bits) to be subjected to LDPC encoding, and the input data D141 is supplied to and stored in the information bit storage memory 141. The input data D141 is output as part of a codeword obtained by LDPC encoding.

  A control signal D146 is supplied from the control signal generation unit 145 to the information bit storage memory 141, and the information bit storage memory 141 uses the stored 60-bit input data D141 based on the control signal D146 in FIG. In order from the first row of the information part of the parity check matrix H, input data (bits) corresponding to a position having “1” for each row is read bit by bit and supplied to the computing unit 142 as information bits D142. The information bit storage memory 141 is composed of, for example, a RAM (Random Access Memory).

  The computing unit 142 is supplied with a 1-bit information bit D142 from the information bit storage memory 141 and is supplied with a 1-bit value D144 from the shift register 143. The calculator 142 uses the 1-bit information bit D142 and the 1-bit value D144 to calculate the addition of the 1-bit information bit D142 and the 1-bit value D144, that is, the exclusive OR here. Then, the computing unit 142 supplies the computation result to the shift register 143 and the puncture circuit 144 as a new 1-bit computation result D143.

  The shift register 143 is supplied with the 1-bit calculation result D143 calculated immediately before from the calculator 142, and the shift register 143 stores (holds) the calculation result D143. Further, the shift register 143 supplies the operation result D143 already stored to the calculator 142.

  The puncture circuit 144 is supplied with the calculation result D143 from the calculator 142. The puncture circuit 144 thins out the calculation result D143 of the first to sixth bits from the calculation result D143 every 7 bits supplied from the calculator 142, and outputs only the seventh bit of the calculation result D143 as the parity bit D145. .

  The control signal generation unit 145 controls the information bit storage memory 141 so that the input data D141 corresponding to the position where “1” exists for each row is read bit by bit in order from the first row of the information portion of the parity check matrix H. A control signal D146 is generated and supplied to the information bit storage memory 141.

  In the encoding device 140 of FIG. 10, the arithmetic unit 142 repeats the exclusive OR operation of two bits 30 × 7 times, thereby obtaining a 30-bit parity bit D145. Then, the encoding device 140 generates the 90-bit code word c by combining the 60-bit input data D141 and the 30-bit parity bit D145, thereby converting the 60-bit input data D141 into the 90-bit codeword. LDPC encoding is performed.

  In the encoding device 140, the shift register 143 stores only the 1-bit calculation result calculated immediately before by the calculator 142, so that the memory capacity of the shift register 143 is equal to all parity bits (30 bits in FIG. 6). ), The circuit scale can be reduced as compared with the encoding device 100 of FIG. In particular, when encoding into a code having a long code length and a large number of parity bits, the memory capacity of the parity bit storage memory 102 for storing all the parity bits is increased, so that the circuit scale can be reduced. growing.

  Further, the calculator 142 and the shift register 143 have the same configuration as the calculator 51 and the shift register 52 of the accumulator 13 shown in FIG. Therefore, the encoding device 120 is configured by adding the puncture circuit 144 in place of the control signal generation unit 145 and the information bit storage memory 141 in place of the repetitive encoding unit 11 and the interleaver 12 of the encoding device 1 of FIG. can do. As described above, the encoding device 140 is provided with the input data holding memory 31 and the output data holding memory 34 (FIG. 2) of the interleaver 12 by replacing the repetitive encoding unit 11 and the interleaver 12 of the encoding device 1. The storage capacity for storing data can be greatly reduced as compared with the encoding device 1. Thereby, in the encoding device 140, the circuit scale can be reduced as compared with the encoding device 1.

  FIG. 11 is a flowchart for describing the encoding process of the encoding device 140 of FIG. This encoding process starts when, for example, 60-bit input data D141 (information bits), which is information to be subjected to LDPC encoding, is input to the encoding device 140.

  In step S21, the information bit storage memory 141 stores the input 60-bit input data D141, and the process proceeds to step S22.

  In step S22, the puncture circuit 144 initializes the counter value K to 0, and proceeds to step S23. In step S23, the control signal generation unit 145 sets the first row of the information part of the parity check matrix H as a processing target row (target row) based on the parity check matrix H of FIG. A control signal D146 is generated for controlling the input data D141 corresponding to a certain position to be output bit by bit and supplied to the information bit storage memory 141.

  After the processing in step S23, the process proceeds to step S24, where the information bit storage memory 141 receives information on the check matrix H from the input data D141 stored in step S21 based on the control signal D146 supplied from the control signal generation unit 145. 1 bit of 7-bit input data D141 corresponding to a certain position of “1” in the target row of the part is read out and supplied to the computing unit 142 as 1-bit information bit D142. Proceed to S25.

  In step S25, the shift register 143 supplies the 1-bit calculation result D143 stored (stored) in step S27 described later to the calculator 142 as a value D144, and the process proceeds to step S26. At the start of the encoding process, “0” is stored in the shift register 143 as an initial value. Accordingly, the shift register 143 supplies “0” to the computing unit 142 in the process of the first step S25.

  In step S26, the arithmetic unit 142 uses the 1-bit information bit D142 supplied from the information bit storage memory 141 and the 1-bit value D144 supplied from the shift register 143 to use the information bit D142 and the value D144. And an operation result D143 is supplied to the shift register 143 and the puncture circuit 144.

  After the process of step S26, the process proceeds to step S27, and the shift register 143 stores (holds) the 1-bit operation result D143 supplied from the computing unit 142 in the form of overwriting the previously stored parity bit. The process proceeds to step S28. In step S28, the puncture circuit 144 acquires the calculation result D143 supplied from the calculator 142, and proceeds to step S29.

  In step S29, the puncture circuit 144 increments the counter value K by 1, and proceeds to step S30. In step S30, the puncture circuit 144 determines whether the counter value K is equal to or greater than the number N of “1” s in each row of the information part of the parity check matrix H (7 in the case of the parity check matrix in FIG. 7).

  In step S30, if the puncture circuit 144 determines that the counter value K is not equal to or greater than N, the puncture circuit 144 returns to step S23 and repeats the above-described processing. That is, in this case, the puncture circuit 144 does not output the calculation result of the calculator 142.

  On the other hand, if the puncture circuit 144 determines in step S30 that the counter value K is equal to or greater than N, the puncture circuit 144 proceeds to step S31 and outputs the operation result D143 obtained in step S28 as the parity bit D145. In other words, the puncture circuit 144 thins out the first to sixth bits of the 7-bit calculation result D143 sequentially supplied from the computing unit 142 by performing the loop processing from step S23 to step S30. When only the eye is represented as the parity bit D145, that is, when the target row is represented as the nth row, the nth parity bit D145 is output.

  After the process of step S31, the process proceeds to step S32, and the control signal generation unit 145 determines whether all parity bits have been output. That is, the control signal generation unit 145 determines whether or not the control signal D125 has been generated with all rows of the check matrix H as target rows.

  In step S32, if the control signal generation unit 145 determines that all the parity bits have not been output, the control signal generation unit 145 returns to step S22, and sets the next row after the current row as a new target row. The above processing is repeated. Therefore, the information bit storage memory 141 reads the input data D141 corresponding to a certain position of “1” in the information part of the check matrix H for each target row one or more bits at a time as one information bit D142. This is supplied to the calculator 142.

  In encoding apparatus 140, the number of rows of parity check matrix H (30 times in the case of the parity check matrix in FIG. 7) is repeated, and the above-described processing is repeated, and a total of 30 parity bits D145 are output.

  On the other hand, if the control signal generation unit 124 determines in step S32 that all parity bits have been output, the process ends. At this time, the encoding device 140 outputs a 90-bit code word c, which is a combination of the 60-bit input data D141 and the 30-bit parity bit D145 output in order in step S31, as an encoding result.

  In the above-described processing, the encoding apparatus encodes information in units of 60 bits into an LDPC code having a code rate of 2/3 and a code length of 90 using the parity check matrix H of FIG. As long as the parity part of parity check matrix H is a parity check matrix composed of stepped matrices, it can be encoded into an LDPC code of any code length and coding rate.

  Also, the parity check matrix H shown in FIG. 12 can be converted into the parity check matrix H of FIG. 7 having a stepped parity part by performing row replacement of the parity check matrix H and column replacement of the parity part of the parity check matrix H. it can. Therefore, when information is LDPC encoded using the parity check matrix shown in FIG. 12, encoding is performed using the parity check matrix of FIG. 7 obtained by converting the parity check matrix of FIG. 12 (original parity check matrix). Encoding can be performed by the encoding device of FIG. 8 or FIG. 10 simply by rearranging the resulting encoded sequences.

  That is, FIG. 12 shows a parity check matrix H obtained by subjecting the parity check matrix H of FIG. 7 to row replacement of equation (1) and column replacement of equation (2).

Line replacement: 6x + y + 1 line → 5y + x + 1 line
... (1)

Column replacement: 6s + t + 61st column → 5t + s + 61th column
... (2)

  However, in the formulas (1) and (2), x, y, s, and t are integers in the range of 0 ≦ x <5, 0 ≦ y <6, 0 ≦ s <5, 0 ≦ y <6, respectively. is there.

  According to the line replacement in equation (1), the first, seventh, thirteenth, nineteenth and twenty-fifth lines that divide by six and the remainder is one are divided by six on the first, second, third, fourth, and fifth lines, respectively. Thus, the second, eighth, eighth, ninth and tenth rows with a remainder of 2 are replaced with the sixth, seventh, eighth, ninth and tenth rows, respectively.

  Further, according to the column replacement of the formula (2), the 61st column, the 67th column, the 73th column, the 85th column with a remainder of 1 divided by 6 with respect to the 61st column and beyond (parity part) are respectively 61 , 62, 63, 64, and 65, the 62, 68, 74, 80, and 86 columns, which are divided by 6 and have a remainder of 2, are called 66, 67, 68, 69, and 70 columns, respectively. The replacement is performed accordingly.

  The parity check matrix H of FIG. 7 can be obtained by performing reverse permutation of row replacement of Expression (1) or reverse replacement of column replacement of Expression (2) on the parity check matrix H of FIG.

When the check matrix in FIG. 7 is multiplied by the code word sequence of the code represented by the check matrix in FIG. 12 and the inverse permutation of the column permutation in equation (2), the zero vector is output. That is obvious. That is, the parity check matrix of FIG. 12 is the matrix H, the parity check matrix of FIG. 7 is the matrix H ′, the codeword sequence of the code represented by the parity check matrix of FIG. Assuming that the row vectors c ′ obtained by performing the column substitution inverse permutation in (2) are represented respectively, Hc ^T (the superscript T represents transposition) is a 0 vector due to the nature of the parity check matrix. , H′c ′ ^T is naturally a zero vector.

  From the above, the check matrix of FIG. 7 is a code c ′ having a code word obtained by performing the reverse permutation of the column replacement of Expression (2) on the sequence of code words according to the check matrix of FIG. This is the check matrix.

  Therefore, when information is LDPC encoded using the parity check matrix shown in FIG. 12, encoding is performed using the parity check matrix of FIG. 7 obtained by converting the parity check matrix of FIG. The encoding can be performed by the encoding apparatus shown in FIG. 8 or FIG.

  Note that even if the code is not specified as an LDPC code, such as an IRA code, if the parity part of the parity check matrix H is composed of a stepped matrix, it is encoded by the encoding device of FIG. 8 or FIG. Can do.

  Next, the series of processes described above can be performed by hardware or software. When a series of processing is performed by software, a program constituting the software is installed in a general-purpose computer or the like.

  Therefore, FIG. 13 shows a configuration example of an embodiment of a computer in which a program for executing the series of processes described above is installed.

  The program can be recorded in advance on a hard disk 405 or a ROM 403 as a recording medium built in the computer.

  Alternatively, the program is stored temporarily on a removable recording medium 411 such as a flexible disk, a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto Optical) disk, a DVD (Digital Versatile Disc), a magnetic disk, or a semiconductor memory. It can be stored permanently (recorded). Such a removable recording medium 411 can be provided as so-called package software.

  The program is installed in the computer from the removable recording medium 411 as described above, or transferred from the download site to the computer wirelessly via a digital satellite broadcasting artificial satellite, LAN (Local Area Network), The program can be transferred to a computer via a network such as the Internet, and the computer can receive the program transferred in this way by the communication unit 408 and install it in the built-in hard disk 405.

  The computer includes a CPU (Central Processing Unit) 402. An input / output interface 410 is connected to the CPU 402 via the bus 401, and the CPU 402 operates the input unit 407 including a keyboard, a mouse, a microphone, and the like by the user via the input / output interface 410. When a command is input by the equalization, a program stored in a ROM (Read Only Memory) 403 is executed accordingly. Alternatively, the CPU 402 may be a program stored in the hard disk 405, a program transferred from a satellite or a network, received by the communication unit 408, installed in the hard disk 405, or a removable recording medium 411 installed in the drive 409. The program read and installed in the hard disk 405 is loaded into a RAM (Random Access Memory) 404 and executed. Thereby, the CPU 402 performs processing according to the above-described flowchart or processing performed by the configuration of the above-described block diagram. Then, the CPU 402 outputs the processing result from the output unit 406 configured with an LCD (Liquid Crystal Display), a speaker, or the like, for example, via the input / output interface 410, or from the communication unit 408 as necessary. Transmission and further recording on the hard disk 405 are performed.

  Here, in this specification, the processing steps for describing a program for causing a computer to perform various types of processing do not necessarily have to be processed in time series according to the order described in the flowchart, but in parallel or individually. This includes processing to be executed (for example, parallel processing or processing by an object).

  Further, the program may be processed by a single computer, or may be processed in a distributed manner by a plurality of computers. Furthermore, the program may be transferred to a remote computer and executed.

It is a figure which shows the structural example of the encoding apparatus of IRA encoding. It is a figure which shows the structural example of the interleaver of FIG. It is a figure which shows the structural example of the accumulator of FIG. 6 is a diagram illustrating an example of a check matrix H. FIG. 6 is a diagram illustrating an example of a check matrix H. FIG. It is a block diagram which shows the structural example of the encoding apparatus of LDPC encoding. 6 is a diagram illustrating an example of a check matrix H. FIG. It is a block diagram which shows the structural example of one Embodiment of the encoding apparatus of the LDPC encoding to which this invention is applied. It is a flowchart explaining the encoding process of the encoding apparatus of FIG. It is a block diagram which shows the structural example of other one Embodiment of the encoding apparatus of the LDPC encoding to which this invention is applied. It is a flowchart explaining the encoding process of the encoding apparatus of FIG. 6 is a diagram illustrating an example of a check matrix H. FIG. It is a block diagram which shows the structural example of one Embodiment of the computer to which this invention is applied.

Explanation of symbols

  120 encoding device, 121 information bit storage memory, 122 arithmetic unit, 123 shift register, 124 control signal generator, 140 encoding device, 141 information bit storage memory, 142 arithmetic unit, 143 shift register, 144 puncture circuit, 145 control Signal generation unit, 401 bus, 402 CPU, 403 ROM, 404 RAM, 405 hard disk, 406 output unit, 407 input unit, 408 communication unit, 409 drive, 410 input / output interface, 411 removable recording medium

Claims (8)

An encoding device that encodes predetermined information into an LDPC (Low Density Parity Check) code,
Storage means for storing one bit of parity of the LDPC code;
Of each bit of the information, by adding the bit according to the parity check matrix of the LDPC code and the 1-bit parity stored in the storage means, a new 1-bit parity of the LDPC code is obtained. An encoding device comprising: an arithmetic means for obtaining and supplying the storage means. The encoding device according to claim 1, comprising:
The parity unit of the parity check matrix corresponding to the parity of the LDPC code has a step-like structure. The encoding device according to claim 1, comprising:
The parity check matrix used in the computing means is such that the parity part has a stepped structure by performing row replacement of the original parity check matrix or column replacement of the parity part of the original parity check matrix. An encoding device characterized by being. The encoding device according to claim 1, comprising:
An encoding apparatus, further comprising: information storage means for storing the information and reading each bit of the stored information at least once. The encoding device according to claim 1, comprising:
An encoding apparatus, further comprising: information storage means for storing the information and reading the stored information bit by bit. The encoding device according to claim 5, wherein
An encoding apparatus, further comprising: thinning means for thinning out the calculation result calculated by the calculation means. An encoding method of an encoding device that encodes predetermined information into an LDPC (Low Density Parity Check) code,
A storage step of storing in the storage means 1 bit of parity of the LDPC code;
Of each bit of the information, by adding the bit according to the parity check matrix of the LDPC code and the 1-bit parity stored in the storage means, a new 1-bit parity of the LDPC code is obtained. And a calculating step for supplying to the storage means. A program for causing a computer to perform LDPC (Low Density Parity Check) encoding of predetermined information,
A storage step of storing in the storage means 1 bit of parity of the LDPC code;
Of each bit of the information, by adding the bit according to the parity check matrix of the LDPC code and the 1-bit parity stored in the storage means, a new 1-bit parity of the LDPC code is obtained. And a calculation step of supplying to the storage means.

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