JP2005025937A - Playback device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately detect pilot signals, which are included in playback signals and have a specific frequency, employing a smaller circuit scale. <P>SOLUTION: A playback device is provided with a playback means that reproduces analog signals, into which pilot signals having the specific frequency are superimposed and digital information is included, from a recording medium, an A/D converter which samples the analog signals reproduced by the playback means and converts the analog signals to digital data having a plurality of bits, a delaying means which delays the output of the A/D converter and an adding means which adds the output of the delaying means and the output of the A/D converter, obtains one bit of the most significant digit of the adding result and outputs the bit. Moreover, the playback device is provided with a pilot signal detecting means which detects the pilot signals from one bit data columns that are outputted from the adding means and a tracking control means which controls tracking operations of the reproducing means based on the pilot signals detected by the pilot signal detecting means. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a playback apparatus, and more particularly to tracking control.

  In recent years, consumer-use digital recording formats have been proposed and commercialized due to advances in magnetic recording / reproducing technology and advances in magnetic recording media. When reproducing this consumer digital recording format, a track formed in an oblique direction on a long tape using a rotary head is reproduced while tracking.

  In the reproduction system of this type of apparatus, the signal reproduced from the magnetic recording medium is an analog signal including digital information, and it is necessary to restore the digital information recorded from the analog signal. For example, automatic amplitude control (AGC) technology for controlling the amplitude of the reproduction signal, automatic phase control (APC) technology for detecting the phase of the reproduction signal and forming a clock synchronized with the reproduction signal, and the like. Therefore, an automatic tracking control (ATF) technique for detecting a pilot signal component included in the reproduced analog signal and performing tracking control based on the detected pilot signal is required.

  Further, in this type of digital VTR, since all processing after restoring digital information is performed by digital signal processing, the above-described AGC, APC, and ATF technologies are also performed by digital signal processing as much as possible. Realization is very advantageous in configuring the entire system.

In this background, the present applicant has already proposed a technique for digitizing each of the above techniques. For example, refer to Japanese Patent Application No. 6-200575 for digitizing AGC, Japanese Patent Application No. 6-166742 for digitizing APC, and Japanese Patent Application No. 6-277832 for digitizing ATF. Have made this kind of proposal.
JP-A-8-63888

  With the digitization of technologies such as AGC, APC, and ATF as described above, the reproduced signal is converted into digital data as an analog signal, and the obtained digital data is used for logical processing to perform the APC. Various determinations such as phase detection and amplitude detection for AGC are performed. However, if a DC offset is added to the output of the gain control amplifier of the playback signal due to temperature changes or changes over time, the phase detection, amplitude detection, and other determinations may not be accurate. Arise.

  In addition, when the ATF circuit is configured independently of these APC and AGC, the circuit scale becomes large. Therefore, a digital circuit that can reduce the circuit scale comprehensively and can be incorporated in an LSI. The construction of was awaited.

  Accordingly, an object of the present invention is to provide an apparatus capable of accurately detecting a pilot signal of a specific frequency contained in a reproduction signal with a smaller circuit scale.

  Under such a purpose, in the present invention, a pilot signal of a specific frequency is superimposed, a reproducing means for reproducing an analog signal including digital information from a recording medium, and the analog signal reproduced by the reproducing means is sampled to have a plurality of bits. An A / D converter for converting the digital data to the digital data, a delay means for delaying the output of the A / D converter, an output of the delay means and an output of the A / D converter are added, and the addition result Means for extracting and outputting the most significant 1 bit, pilot signal detecting means for detecting the pilot signal from the 1-bit data string output from the adding means, and the pilot signal detecting means And tracking control means for controlling tracking of the reproducing means based on a pilot signal.

  By configuring as described above, the pilot signal included in the reproduced analog signal can be digitally detected by a circuit having a very small circuit scale.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of a digital signal processing circuit as an embodiment of the present invention, and constitutes a part of a reproduction system of a digital VTR.

  In FIG. 1, a signal reproduced by a rotary head 101 from a magnetic tape (not shown) is amplified by a reproduction amplifier 103 and then applied to a reproduction integration equalizer 105. The integral equalizer 105 enhances the high frequency component attenuated by the magnetic recording / reproducing system and the low frequency component attenuated by the differential characteristic of the ring head. The integrated and equalized signal is input to the analog adder 107 for DC component shift.

  The analog adder 107 is an adder using an operational amplifier or the like, and removes a DC offset as will be described later by the other input. The signal from which the DC offset has been removed is input to the gain control amplifier 109 as binary eye pattern data. The gain control amplifier 109 adjusts the amplitude of the signal so as to be optimal with respect to the range of the A / D converter 111 in the subsequent stage by controlling the gain according to gain information to be described later. To enter.

  The A / D converter 111 converts the input analog signal into a multi-bit digital signal, and the digital signal is sent to the phase / amplitude detection circuit 113, the (1-2D) processing circuit 115, and the (1 + D) processing circuit 117. Supply. The phase / amplitude detection circuit 113 detects the phase and amplitude from the input digital signal, and inputs the detected phase information to the integration circuit 119 and the detected amplitude information to the subtraction circuit 121.

  Here, as for the operation of the phase / amplitude detection circuit 113, the ones introduced in Japanese Patent Application Nos. 6-200575 and 6-166742 can be applied, but will be briefly described below with reference to FIG. To do.

  In FIG. 2, the digital data after integration equalization input to the input terminal 301, that is, the output of the A / D converter 111 in FIG. 1, is delayed by one sampling period in the registers 303, 305, 307, and 309. Here, for convenience of explanation, as shown in the figure, the most significant bit (MSB) of the input / output data of each register is a, b, c, d, e, respectively.

  Data a, b, c, d, and e are input to the decoder 311, and signals s, h, and a are logically operated according to the logical expressions shown in the figure, the signal s is a switch 313, and the signal a is a register with a clock enable. 317 and a signal h are supplied to the register 315 with clock enable. On the other hand, the multi-bit output of the register 303 and the multi-bit output of the register 307 have a time difference of 2 clocks, but these are input to the subtracter 319 and subtracted, and one input terminal of the switch 313 and one of the switches 321 Are further input to the x (−1) multiplier 323. The x (−1) multiplier 323 inverts the sign of the input data and supplies it to the other input terminal of the switch 313 and the switch 321.

  The switch 313 outputs the multi-bit output of the subtracter 319 as it is when the data c is “0” according to the signal s from the decoder, that is, the data c, and the output of the subtractor 319 when the data c is “1”. Is input as the D input of the register 315 with a clock enable. The register 315 with clock enable latches the multi-bit data input as the D input when the signal h is “0” and the value output when the signal h is “1” in response to the signal h from the decoder 311. Is held, and the result is output to the output terminal 325 as phase information.

  On the other hand, the switch 321 selects and outputs the multi-bit output of the subtracter 319 and the multi-bit data whose sign is inverted by the x (−1) multiplier 323 according to the sign of the output of the subtractor 319. The absolute value of the output of the subtracter 319 is supplied to the D terminal of the register 317 with clock enable. The register 317 with a clock enable latches the multi-bit data input as the D input when the signal a is “0” and the value output when the signal a is “1” in response to the signal a from the decoder 311. Is held and the result is output to the output terminal 327 as amplitude information.

  Here, the phase information and amplitude information will be described. The input data is integral-equalized data. Data having a binary eye pattern is converted into a smooth waveform by the roll-off filter in the integral equalizer 105, and then A / D converted. It is input to the phase / amplitude detector 113.

  Assuming that the output of the register 305 in FIG. 2 is the center of time, the signal h output from the decoder 311 includes data before and after that, that is, data b and d indicating whether the output of the register 303 and the output of the register 307 are positive or negative. If the data a, c, e are not all the same, “0” is obtained. When the signal h becomes “0”, the data held in the register 315 is updated.

  For example, as shown in FIG. 3, it is assumed that five continuous data whose MSBs are “0”, “0”, “1”, “0”, “0” are input. The portion indicated by x in FIG. 3 is the sampling timing of the A / D converter 111. Here, if the input waveform and the sampling timing are in an ideal relationship, that is, sampling is performed at the timing of the peak value. If it does, as shown to Fig.3 (a), the difference value of the sample data before and behind will become substantially zero. On the other hand, when the sampling timing is delayed from the ideal timing as shown in FIG. 3B, there is a difference between the sample data k1 and k2 at the sampling timings j1 and j2 before and after that as shown in the figure. .

  As shown in FIG. 3B, this difference is advanced when the center data is positive and the sampling phase is delayed, and the difference value m (= k1−k2) is positive. In some cases, the data is negative. Further, the relationship between the positive / negative of the difference value and the phase advance / delay is reversed depending on whether the data c is “1” or “0”. Therefore, in the switch 313, the sign of the difference value output from the subtracter 319 is inverted according to the data c. MSB is “0”, “0”, “0”, “0”, “1” data, “1”, “0”, “0”, “0”, “1” data, “1”, “0”, “1”, “0”, “0” data, “1”, “1”, “1”, “1”, “0” data, etc., signal h becomes “0” 5 Even when two pieces of continuous data are input, at least the phase advance or delay can be detected as the difference value m for the same reason as described above.

  The difference value m obtained as described above is input to the integrating circuit 119 of FIG. 1 via the terminal 325 as phase information.

  Similarly, regarding the amplitude information, if the output of the register 305 in FIG. 2 is considered as the center of time, the signal “a”, that is, when the data b and d indicating the positive / negative of the output of the register 303 and the output of the register 307 do not match. When this signal a becomes “0”, the data held in the register 317 is updated. Here, when the data b and d do not match, there is a zero cross point before and after the output of the register 305, and the absolute value of the difference value between the output of the register 303 and the output of the register 307 at this time is It is proportional to the amplitude of the input signal.

  The amplitude information obtained in this way is input to the subtractor 121 in FIG. As is apparent from the above description, the timing for latching the phase information and the timing for sampling the amplitude information do not overlap. As a result, the phase / amplitude detection circuit 113 selects the phase information and the amplitude information. Will be output automatically.

  Returning to FIG. The phase information input to the integrating circuit 119 is averaged by the circuit 119 and the output is converted into an analog signal by the D / A converter 123. The analog signal output from the D / A converter 123 is used as a control input of a VCO (voltage controlled oscillator) 125, and the oscillation frequency of the VCO 125 is controlled based on the input voltage. The output of the VCO 125 is used as an operation clock for the A / D converter 111 and various circuits subsequent thereto. With the above configuration, it is possible to configure a PLL that controls the VCO 125 so that the clock has a predetermined phase.

  On the other hand, the subtractor 121 receives the amplitude information described above from the phase / amplitude detection circuit 113 and compares it with the amplitude value to be the control target stored in the register 127, and the difference between the current amplitude and the target amplitude. Is required. The output of the subtractor 121 is input to the integrating circuit 129, the amplitude error is averaged, and the result is input to the D / A converter 131. The D / A converter 131 uses the averaged digital data as an analog signal as a control input of a gain control amplifier (VCA) 109.

  With the above configuration, an AGC circuit that adjusts the gain of the gain control amplifier 109 so that the amplitude of the reproduction signal is fixed to a predetermined amplitude optimum for the A / D conversion range is configured.

  On the other hand, the digital data input to the (1-2D) processing circuit 115 is input to the Viterbi decoder 133 as a ternary waveform according to the partial response class 4 by subtracting the data two clocks before, and the Viterbi decoder is ternary. Maximum likelihood decoding is performed by using the likelihood of the waveform. The output of the Viterbi decoder 133 is supplied to the reproduction image processing circuit 135 as a reproduction digital signal. The reproduction image processing circuit 135 restores the reproduction image from the input digital data string by a well-known method and outputs the reproduction image signal to the output terminal 137. Output from.

  The data input to the (1 + D) processing circuit 117 calculates ternary data by adding the data one clock before and the current data, and then only the MSB of the ternary data is used for tracking control. This is supplied to an ATF tone signal detection circuit 139 and a low pass filter (LPF) 141. Here, the reason why the multi-bit data is reduced to 1 bit is to reduce the scale of the subsequent circuit as much as possible, and even when the multi-bit data is reduced to 1-bit data, tracking control and will be described later. This is because sufficient accuracy can be obtained for the control of the DC offset.

  For example, assuming that the clock rate is Fb and the tracking frequency is (Fb / 60), oversampling corresponding to about 6 bits is performed, and the tracking control data has sufficient accuracy. In FIG. 1, a portion surrounded by a dotted line indicates a digital signal processing portion constituted by the same LSI, and the output of the (1 + D) processing circuit 117 is output via a pin of the LSI, and a signal of a predetermined level. Is supplied to the analog LPF 141.

  Fig. 4 is a diagram showing an analog signal (Fig. 4a) input to the A / D converter 111, an amplitude range (Fig. 4b) when the analog signal is converted into digital data, and a histogram indicating the frequency of occurrence within that range. 4 shows. In the same figure, when the integrated equalization waveform is A / D converted and the converted data is data distributed in the vicinity of + A and −A as shown in FIG. 4C, the output data of the (1 + D) processing circuit 117 is As shown in FIG. 4d, ternary data is distributed in the vicinity of + 2A, 0, and -2A.

  Here, taking out only the most significant bit of the ternary data as shown in FIG. 4d is substantially equivalent to comparing this ternary data with 0, and the ternary waveform signal is As shown in FIG. 4, it has a distribution centered on zero. Here, the most significant bit is not greatly affected even when the amplitude −A to + A of the analog signal input to the A / D conversion circuit 111 slightly changes depending on the state of the tape or the reproducing head. When a DC offset exists in the analog signal input to the A / D conversion circuit 111, it is greatly affected. Specifically, in the case where the ternary signal is distributed centering around the value offset with respect to 0, the energy of a pilot signal component, which will be described later, included in one bit described above is reduced, and the tracking control accuracy is reduced. Decreases.

  FIG. 5A is a diagram showing the frequency characteristics of the signal output from the (1 + D) processing circuit 117. As is clear from FIG. 5, the (1 + D) processing circuit 117 passes a low-frequency component including a DC component. A signal having a frequency necessary for tracking control passes sufficiently. The 1-bit digital signal input to the ATF tone signal detection circuit 139 is processed by the circuit to detect the ATF tone signal. This ATF tone signal is supplied to an MPU (microprocessing unit) 143. The MPU 143 generates a tracking control signal based on the ATF tone signal and supplies it to the capstan control circuit 145. As is well known, the capstan control circuit 145 performs speed control and tracking control for controlling the rotational speed of a capstan (not shown), and operates so that the head 101 accurately follows the track.

  Here, details of the ATF tone signal detection circuit 139 will be described with reference to FIG. In this embodiment, it is assumed that tracking control is performed using two types of pilot signals f1 and f2 employed in a known digital VTR. That is, when reproducing a magnetic tape recorded in a format in which pilot signals having frequencies of f1 and f2 are alternately superimposed on a digital signal every other track, the rotating head moves a track on which no pilot signal is recorded. It is assumed that the f1 component and the f2 component contained in the rotary head are detected during reproduction, and the tracking control signal is obtained by comparing them.

  The 1-bit data output from the (1 + D) processing circuit 117 is input to the terminal 201, and the 1-bit data is supplied to the circuit blocks 213, 215, 217, and 219, respectively. Here, in FIG. 6A, the circuit blocks 213, 215, 217, and 219 have the same configuration, and only the input clock signal is different. Here, 211 is a tracking tone oscillator, which generates four types of signals shown in FIG. That is, the oscillator 211 supplies a sine wave of frequency f1 to the circuit 213, a cosine wave of frequency f1 to the circuit block 215, a sine wave of frequency f2 to the circuit block 217, and a cosine wave of frequency f2 to the circuit block 219. To do.

  In the circuit block 213, the 1-bit data is supplied to the multiplier 203, multiplied by a sine wave having the frequency f1, and the result is supplied to the integrator 205 and integrated over a predetermined period. The integration result is taken into the register 207 and held after the end of this period. Reference numeral 209 denotes a buffer, which is connected to the data bus of the MPU 143. The MPU 143 reads the value held in this buffer by releasing the output enable of the buffer 209.

  Here, each buffer in each of the circuit blocks 213, 215, 217, and 219 includes a sine wave having a frequency f1, a cosine wave having a frequency f1, a sine wave having a frequency f2, and the frequency included in the 1-bit data, that is, the reproduction signal. The cosine wave component of f2 is shown. The MPU 143 can detect the f1 component by taking the RMS (Root Mean Square) of the output of the circuit block 213 and the output of the circuit block 215, and by taking the RMS of the output of the circuit block 217 and the output of the circuit block 219. The f2 component can be detected.

  In the above description, RMS represents the square root of the sum of two input values that are squared. In the MPU 143, by comparing the f1 component and the f2 component, whether the rotating head being reproduced is shifted to the track side where the pilot signal of f1 or f2 is recorded with respect to the track where the pilot signal is not recorded. This result is supplied to the capstan control circuit 145 as a tracking control signal.

  Note that the multiplier (203, etc.) used here has only one input of one bit, so only two types of processing (x1) or (x-1) are selected. If the output is about binary (1 bit) or ternary (2 bits), it can be configured with a very simple logic circuit, and the integrator 205 can be configured with an up / down counter to dramatically increase the circuit scale. Can be reduced.

  Returning to FIG. 1, the MSB of the output of the (1 + D) processing circuit 117 is output from the terminal of the digital signal processing LSI, converted into a signal of a predetermined level, and then averaged by the LPF 141. The configuration of the LPF 141 is, for example, a low-pass circuit using a CR element shown in FIG. 7A, an integrator using an operational amplifier shown in FIG. 7B, and further shown in FIG. 7C. A circuit using a charge pump can be employed. Since these circuits themselves are well-known circuits, detailed description thereof will be omitted.

  The output of the LPF 141 is supplied to the analog adder 109 described above, and the DC offset of the reproduction signal is removed. As described above, if there is a DC offset in the analog signal input to the A / D converter 111, (1 + D) centering on level 0 of the signal ternarized by the adder in the processing circuit 117 The distribution is offset, and the occurrence probability of 1 and 0 in the MSB 1-bit data that is the output of the (1 + D) processing circuit 117 deviates from 50%. As a result, the AGC, APC, and ATF processes are seriously adversely affected.

  In the present embodiment, the deviation from the above 50% can be compensated by averaging in the external LPF 141 and adding the offset to the analog adder 107, and is sensitive to the offset of the integrated equalization waveform input as a result. Stable phase detection and amplitude detection operations can be stabilized. In addition, the accuracy of the tracking control can be improved.

  In the above-described embodiment, the DC offset is detected by adding adjacent sample data by the (1 + D) processing circuit 117. However, when the LSI gate speed is insufficient, FIG. The same effect can be obtained by adding adjacent samples by the (1 + 2D) processing circuit shown in FIG.

  In the above-described embodiment, an analog circuit is used as the LPF 141. However, for example, a digital circuit using an up / down counter is used, and an integration operation is performed in the digital signal processing LSI in FIG. In this case, the digital integration value obtained by the integration can be converted into an analog form via a D / A converter, a PWM circuit, or the like and fed back.

  As described above, according to the present embodiment, the specific frequency component included in the analog signal can be detected digitally by a circuit having an extremely small circuit scale.

It is a figure which shows the structure of the digital signal processing circuit as one Example of this invention. FIG. 2 is a block diagram illustrating a specific configuration example of a phase / amplitude detection circuit in the apparatus of FIG. 1. FIG. 3 is a diagram for explaining the operation of the phase / amplitude detection circuit shown in FIG. 2. It is a figure which shows the amplitude range at the time of converting the input analog signal and this analog signal into digital data, and also the histogram which shows the generation frequency in the range. It is a block diagram which shows the structure at the time of applying the digital signal processing apparatus of FIG. 1 to a digital disc reproducing | regenerating apparatus. It is a figure which shows the structural example of the processing circuit which can be applied to the apparatus of FIG. 1 and adds several samples. It is a figure which shows the specific structural example of the low-pass filter in the apparatus of FIG.

Claims (5)

Reproducing means for reproducing an analog signal containing digital information from a recording medium on which a pilot signal of a specific frequency is superimposed;
An A / D converter that samples the analog signal reproduced by the reproducing means and converts it into digital data of a plurality of bits;
Delay means for delaying the output of the A / D converter;
Adding means for adding the output of the delay means and the output of the A / D converter, and extracting and outputting the most significant bit of the addition result;
Pilot signal detecting means for detecting the pilot signal from a 1-bit data string output from the adding means;
A reproduction apparatus comprising: tracking control means for controlling tracking of the reproduction means based on a pilot signal detected by the pilot signal detection means.   2. The reproducing apparatus according to claim 1, wherein the delay means delays the output of the A / D converter by one sample.   The recording medium is a tape-shaped recording medium in which a large number of tracks are formed and two types of pilot signals are alternately superimposed every other track, and the tracking control means is a track on which the pilot signals are not recorded. 2. The reproducing apparatus according to claim 1, wherein a tracking control signal is obtained by comparing the two types of pilot signals detected by the pilot detecting means when the reproducing means is reproducing the signal.   2. The reproducing apparatus according to claim 1, further comprising restoring means for restoring the digital information based on an output of the A / D converter.   The pilot signal detection means includes a multiplier that multiplies the 1-bit data string output from the addition means and a signal having a frequency corresponding to the frequency of the pilot signal, and an integrator that integrates the output of the multiplier. The playback apparatus according to claim 1, further comprising:

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