JP2005019435A - Method of polishing wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of polishing wafer by which a wafer can be thinned without chipping or cracking the edge of the wafer even when the wafer is polished to an ultra-thin wafer having a finished thickness of ≤100 μm. <P>SOLUTION: The outer peripheral section 15 of the wafer 2 is removed by cutting the wafer 2 perpendicularly to the surface 3 of the wafer 2 along the boundary between the internal region 16 of the wafer 2 in which a semiconductor element or a circuit is formed, and the outer peripheral section 15 on the outside of the internal region 16. Then the surface 3 of the wafer 2 is stuck to a supporting member 10 having a larger surface dimension than the wafer 2 has. Thereafter, the thickness of the wafer 2 is reduced to a prescribed finished thickness by polishing the rear surface 30 of the wafer 2 while the surface 3 of the wafer 2 is supported by the supporting member 10. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wafer polishing method, and more particularly to a method for reducing the thickness of a wafer by polishing the back surface of the wafer.
[0002]
[Prior art]
In recent years, with the reduction in size and weight of devices typified by mobile phones, a stacked CSP (chip size package) in which a plurality of chips are stacked and accommodated in a package has been developed. In order to adapt to this stacked CSP, a wafer having semiconductor elements and circuits formed on the front surface is diced into chips, and the back surface of the wafer is polished to obtain the thickness of the wafer (this is referred to as “finished thickness”). The thickness of the chip is equal to or less than 200 μm, and further to 100 μm or less.
[0003]
For example, first, as shown in FIGS. 5 (a) (i) and 5 (b) (i), the protective tape 1 is attached to the surface 3 of the wafer 2 to be polished, and FIGS. 5 (a) (ii), After the back surface 30 of the wafer 2 is polished in a state where the front surface 3 of the wafer 2 is covered with the protective tape 1 as shown in FIGS. 5B and 5I, FIGS. 5A, 5I, and 5B are used. The protective tape 1 is peeled off from the surface 3 of the wafer 2 as shown in (iii), and then stretched on the metal carrier frame 4 as shown in FIGS. 5 (a) (iv), 5 (b) (iv). The back surface of the wafer 2 (the back surface after polishing is denoted by reference numeral 30 ') is attached to the dicing tape 5 thus obtained, and dicing is performed as shown in FIGS. 5 (a), 5 (v), 5 (b) and 5 (v). Is going. Thereby, the thin chip 20 suitable for the stacked CSP is obtained. In addition, as shown in FIG. 8, the protective tape 1 is provided with an acrylic adhesive material 12 on one side of a base material 13 such as ethylene vinyl acetate (EVA), polyolefin, polyethylene terephthalate (PET) or the like.
[0004]
Further, when the finished thickness of the wafer 2 is 200 μm or less, the wafer strength is lowered, so that it is necessary to avoid the risk of the wafer 2 being cracked due to the impact during the protective tape peeling process or the transfer between processes. Therefore, as shown in FIGS. 6 (a) (iii) and 6 (b) (iii), a dicing tape in which the back surface 30 'of the wafer 2 is stretched on the metal carrier frame 4 while the protective tape 1 is adhered. After being attached to 5, a method of peeling the protective tape 1 is performed as shown in FIGS. 6 (a), (iv), 6 (b), and (iv) (for example, Patent Document 1 (Japanese Patent Laid-Open No. Hei 7). -22358). 6 (a) (i) and 6 (b) (i) are the same as those shown in FIGS. 5 (a) (i), 5 (b) (i), and FIG. 6 (a). ) (Ii), FIG. 6 (b) (ii) are the back surface polishing steps of FIG. 5 (a) (ii), FIG. 5 (b) (ii), and FIG. 6 (a) (v), FIG. (B) The dicing process in (v) is the same as that in FIGS. 5 (a), 5 (v), 5 (b) and 5 (v).
[0005]
[Patent Document 1]
JP-A-7-22358 (first page, abstract)
[0006]
[Problems to be solved by the invention]
By the way, as shown in FIG. 7A and FIG. 7B in which the cross section taken along the line BB is partially enlarged, the semiconductor element and the circuit 9 are formed in the inner region 16 on the surface 3 of the wafer 2. A polyimide coat 14 having a thickness of about 3 μm to 10 μm is provided so as to cover it. As a result, a step A of about 3 μm to 10 μm is generated between the uppermost surface of the inner region 16 of the wafer 2 and the surface of the outer peripheral portion 15 outside thereof. Further, the wafer edge 8 which is the outermost periphery of the wafer 2 is chamfered (rounded) 6.
[0007]
Here, when the finished thickness of the wafer 2 becomes ultra-thin such as 100 μm or less, as shown in FIG. The wafer strength is extremely lowered. Since the wafer edge 8 is not bonded to the protective tape 1 and is not physically supported, the wafer edge 8 is affected by the step A between the inner region and the outer peripheral portion. As a result, minute cracks and cracks are generated in the wafer edge 8. For this reason, there is a problem that the wafer 2 breaks due to progress of chipping or cracking of the wafer edge 8 due to the subsequent protective tape peeling step, dicing tape attaching step, impact during conveyance between processes, or the like.
[0008]
Accordingly, an object of the present invention is to provide a wafer polishing method capable of thinning a wafer without causing chipping or cracking of the wafer edge even when the finished thickness of the wafer is ultra-thin such as 100 μm or less.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the wafer polishing method of the present invention comprises:
Cutting or polishing the boundary between the inner region where the semiconductor element or circuit is formed on the wafer and the outer peripheral portion thereof perpendicular to the surface of the wafer to remove the outer peripheral portion of the wafer;
Bonding the surface of the wafer to a support member having a surface dimension greater than or equal to the surface dimension of the wafer;
Polishing the back surface of the wafer with the support member supporting the front surface of the wafer to reduce the thickness of the wafer to a predetermined finished thickness.
[0010]
Examples of means for “cutting or polishing vertically” include dicing or grinding.
[0011]
The phrase “the support member has a surface dimension greater than or equal to the surface dimension of the wafer” means that the support member has a surface dimension substantially equal to or greater than the surface dimension of the wafer.
[0012]
In the wafer polishing method according to the present invention, the boundary between the inner region of the wafer and the outer peripheral portion thereof is cut or polished perpendicularly to the surface of the wafer to remove the outer peripheral portion of the wafer. Therefore, even if the wafer edge is first chamfered, the wafer edge after the outer peripheral portion is removed is perpendicular to the surface. Thereafter, the front surface of the wafer is bonded to a support member having a surface dimension equal to or larger than the surface dimension of the wafer, and the back surface of the wafer is polished with the support member supporting the front surface of the wafer. Reduce the thickness to a predetermined finish thickness. In this way, the back surface of the wafer can be polished in a state where the entire surface of the wafer surface at this stage is supported, so that the accuracy of back surface polishing is increased. Further, after the back surface polishing step, the wafer edge does not have a sharp shape like a knife, and the wafer edge is perpendicular to the surface. Therefore, even if the finished thickness of the wafer is ultra-thin such as 100 μm or less, the wafer can be thinned without causing chipping or cracking of the wafer edge. Thereafter, for example, the back surface of the wafer (the back surface after polishing) is attached to a dicing tape stretched on a metal carrier frame, the support member is removed, and then dicing is performed. Thereby, it is possible to prevent the wafer from cracking and to improve the wafer manufacturing yield.
[0013]
In another aspect, the wafer polishing method of the present invention comprises:
At the boundary between the inner region where the semiconductor element or circuit is formed on the wafer and the outer periphery of the inner region, the depth is deeper than the finished thickness of the wafer from the surface of the wafer and stops halfway through the thickness of the wafer. Forming a notch; and
Bonding the surface of the wafer to a support member having a surface dimension greater than or equal to the surface dimension of the wafer;
Polishing the back surface of the wafer with the support member supporting the front surface of the wafer to reduce the thickness of the wafer to the finished thickness.
[0014]
Examples of means for “forming a cut” include dicing.
[0015]
In the wafer polishing method of the present invention, the depth of the wafer is deeper than the finished thickness of the wafer from the surface of the wafer and stopped at the middle of the thickness of the wafer at the boundary between the inner region and the outer peripheral portion on the wafer. After forming the notch, the wafer surface is bonded to a support member, the back surface of the wafer is polished with the support member supporting the wafer surface, and the wafer thickness is reduced to the finished thickness. ing. If it does in this way, after a back surface grinding | polishing process, an outer peripheral part will be in the state isolate | separated by the said notch | incision with respect to the internal area | region of the said wafer. Therefore, even if a chip or a crack occurs on the edge of the wafer that was initially chamfered, it does not travel to the inner region of the wafer. In addition, after the back surface polishing process, that is, after the outer periphery is separated, the new wafer edge is perpendicular to the wafer surface. Therefore, even if the finished thickness of the wafer is ultra-thin such as 100 μm or less, the wafer can be thinned without causing chipping or cracking of the wafer edge. Thereafter, for example, the back surface of the wafer (the back surface after polishing) is attached to a dicing tape stretched on a metal carrier frame, the support member is removed, and then dicing is performed. Thereby, it is possible to prevent the wafer from cracking and to improve the wafer manufacturing yield.
[0016]
In one embodiment of the wafer polishing method, the support member is a support substrate.
[0017]
In the wafer polishing method of this embodiment, since the support member is a support substrate, the wafer is strongly reinforced by the support substrate during the back surface polishing process dicing tape attaching process or during inter-process transfer. It is not affected by wafer warpage. Therefore, it is possible to further prevent the wafer from cracking and to further improve the wafer manufacturing yield.
[0018]
In one embodiment of the wafer polishing method, the support member is a protective tape provided with an adhesive material.
[0019]
In the wafer polishing method of this embodiment, since the support member is a protective tape, the wafer is reinforced by the protective tape during the backside polishing process, the dicing tape attaching process, and the inter-process conveyance. It is not affected by wafer warpage. Therefore, it is possible to further prevent the wafer from cracking and to further improve the wafer manufacturing yield. Moreover, since the said supporting member is a protective tape provided with the adhesive material, it can affix on the surface of the said wafer as it is, and does not require another adhesive member.
[0020]
In one embodiment of the wafer polishing method, the finished thickness is set to a value of 100 μm or less.
[0021]
In the wafer polishing method of this embodiment, a thin chip suitable for a stacked CSP (chip size package) can be obtained.
[0022]
In one embodiment of the wafer polishing method, the outer periphery of the wafer includes a region having a lower height than the uppermost surface of the wafer surface.
[0023]
Here, the “uppermost surface” of the wafer surface refers to the surface farthest from the semiconductor substrate forming the wafer.
[0024]
In the wafer polishing method according to this embodiment, the outer peripheral portion of the wafer includes a region having a lower height than the uppermost surface of the wafer surface. Therefore, the region having a height lower than the uppermost surface of the wafer surface is removed before the back surface polishing step or separated by the back surface polishing step. Therefore, the entire area of the wafer surface at this stage is reliably supported by the support member during the dicing tape attaching process and the inter-process transport. As a result, the wafer can be further prevented from cracking, and the wafer manufacturing yield can be further improved.
[0025]
The outer peripheral portion of the wafer preferably includes the entire region having a height lower than the uppermost surface of the wafer surface.
[0026]
The outer peripheral portion of the wafer corresponds to a portion that is not bonded to the support member when the surface of the wafer is bonded to the support member.
[0027]
The boundary between the inner region where the semiconductor element or circuit is formed on the wafer and the outer peripheral portion outside thereof corresponds to a step portion.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the wafer polishing method of the present invention will be described in detail with reference to the illustrated embodiments.
[0029]
(First embodiment)
1 (a) (i) to (vii) show a process flow of the wafer polishing method of the first embodiment, and FIGS. 1 (b) (i) to (vii) show FIGS. The process cross section corresponding to vii) is shown. 9 (a) to 9 (d) show process cross-sections in which the outer peripheral portion of the wafer is partially enlarged (FIGS. 1 (b), (i) to (vii) indicate that the orientation of the wafer 2 is up and down. The opposite is drawn.)
[0030]
As shown in detail in FIG. 9A, a semiconductor element or a circuit 9 is formed in the inner region 16 on the surface 3 of the wafer 2 to be polished, and a polyimide coat having a thickness of about 3 μm to 10 μm is formed so as to cover it. 14 is provided. As a result, there is a gap between the uppermost surface of the inner region 16 of the wafer 2 (the surface of the polyimide coat 14, which is depicted at the lowest position in FIG. 9A) and the outer peripheral portion 15. A step A of about 3 μm to 10 μm occurs. Further, the wafer edge 8 which is the outermost periphery of the wafer 2 is chamfered (rounded) 6.
[0031]
The target finish thickness of the wafer 2 is set to a value of 100 μm or less so that a thin chip suitable for a stacked CSP (chip size package) can be obtained.
[0032]
In this embodiment, first, as shown in FIGS. 1 (a) (i), 1 (b) (i), and 9 (b), the boundary between the inner region 16 and the outer peripheral portion 15 of the wafer 2 is the surface. 3 and the back surface 30 are cut perpendicularly. Thereby, the wafer outer peripheral portion 15 corresponding to the outside of the cut portion 17 is removed. Therefore, even if the wafer edge 8 is initially chamfered 6, the wafer edge after the outer peripheral portion 15 is removed is perpendicular to the front surface 3 and the back surface 30. The removed wafer outer peripheral portion 15 includes the entire region whose height is lower than the uppermost surface of the wafer surface 3. Practically, the width of the outer peripheral portion 15 may be about 5 mm. The cutting method may be, for example, dicing or grinding performed by applying a diamond wheel from the side of the wafer 2 while rotating it at a high speed.
[0033]
Next, as shown in FIGS. 1 (a) (ii) and 1 (b) (ii), a double-sided tape 11 is attached to the surface 3 of the wafer 2. This double-sided tape 11 serves as an adhesive means for bonding the surface 3 of the wafer 2 to a reinforcing support substrate 10 as a support member in the next step. As shown in FIG. 9C, the double-sided tape 11 includes, for example, an acrylic adhesive 24 having a thickness of 5 μm to 100 μm on one surface of a PET (polyethylene terephthalate) base material 23 having a thickness of 25 μm to 200 μm, and the other surface. And a heat-peelable adhesive material or UV (ultraviolet) peelable adhesive material 22 having a thickness of 5 to 100 μm. Then, the surface of the heat-peelable adhesive material or the UV-peelable adhesive material 22 is disposed on the wafer surface 3 side.
[0034]
Next, as shown in FIG. 1 (a) (iii), FIG. 1 (b) (iii) and FIG. 9 (c), the surface 3 of the wafer 2 is made of glass or a silicon wafer through a double-sided tape 11. Affixed to the reinforcing support substrate 10. The surface dimensions of the reinforcing support substrate 10 are equal to or larger than the surface dimensions of the wafer 2 at this stage, and are specified sizes such as 6 inch, 8 inch, and 12 inch diameters so that existing facilities can be used. And
[0035]
Next, as shown in FIGS. 1 (a), (iv), 1 (b), (iv) and FIG. 9 (d), the wafer back surface 30 is polished in a state where the wafer surface 3 is supported by the reinforcing support substrate 10. Then, the thickness of the wafer 2 is reduced to a predetermined finish thickness of 100 μm or less (the back surface after polishing is indicated by reference numeral 30 ′). In this way, the back surface 30 of the wafer can be polished while supporting the entire area of the wafer surface 3 at this stage, so that the accuracy of the back surface polishing is increased. Further, after the back surface polishing step, the wafer edge 19 does not have a sharp shape like a knife, and the wafer edge 19 is perpendicular to the front surface 3 and the back surface 30 '. Therefore, even if the finished thickness of the wafer 2 is ultra-thin such as 100 μm or less, the wafer 2 can be made thin without causing the chipping or cracking of the wafer edge 19.
[0036]
Thereafter, as shown in FIGS. 1 (a), 1 (v), 1 (b) and 1 (v), the dicing tape stretched on the metal carrier frame 4 while the reinforcing support substrate 10 is bonded to the wafer surface 3. 5, the back surface 30 ′ of the wafer 2 is attached. The dicing tape 5 is made of, for example, an acrylic adhesive material having a thickness of 5 μm to 50 μm, or an adhesive material that can be thermocompression bonded such as an epoxy or polyimide material, to a base material made of vinyl chloride, polyolefin, PET, or the like having a thickness of 80 μm to 200 μm. It has been crafted.
[0037]
Next, heating or UV irradiation is performed on the heat-peelable pressure-sensitive adhesive material 22 or the UV-peelable pressure-sensitive adhesive material 22 of the double-sided tape 11 shown in FIG. 9D to vaporize the gas generating material in the pressure-sensitive adhesive material. The adhesion to the wafer surface 3 is extremely reduced. As a result, the reinforcing support substrate 10 is peeled from the wafer surface 3 together with the double-sided tape 11 as shown in FIGS.
[0038]
Thereafter, dicing is performed as shown in FIGS. 1 (a) (vii) and 1 (b) (vii). As a result, a chip 20 having a thickness of 100 μm or less suitable for a stacked CSP (chip size package) is obtained.
[0039]
In this embodiment, the outer peripheral portion 15 removed at the beginning of the wafer includes the entire region whose height is lower than the uppermost surface of the wafer surface 3. Therefore, a region having a height lower than the uppermost surface of the wafer surface 3 is removed before the back surface polishing step or separated by the back surface polishing step. Therefore, the entire region of the wafer surface 3 at this stage is reliably supported by the reinforcing support substrate 10 during the dicing tape attaching process and the inter-process transport. As a result, the wafer 2 can be further prevented from cracking without being affected by the wafer warp, and the wafer manufacturing yield can be further improved.
[0040]
Further, since the surface dimension of the reinforcing support substrate 10 is equal to or larger than the surface dimension of the wafer 2, damage to the wafer edge 19 can be prevented during handling and transfer between processes. In addition, since the surface dimensions of the reinforcing support substrate 10 are set to specified sizes such as 6 inches, 8 inches, and 12 inches, existing equipment can be used as it is in the processes after bonding.
[0041]
In this embodiment, the surface of the heat-peelable adhesive material or the UV-peelable adhesive material 22 is disposed on the surface 3 side of the wafer 2, but the acrylic adhesive material is disposed on the surface 3 side of the wafer 2. 24 may be arranged. In that case, the reinforcing support substrate 10 shown in FIGS. 1 (a) (vi) and 1 (b) (vi) is peeled off, followed by double-sided tape peeling, and thereafter, FIG. 1 (a) ( vii), dicing is performed as shown in FIGS. 1 (b) and (vii). Although the double-sided tape 11 is used as an adhesive means for bonding the surface 3 of the wafer 2 to the reinforcing support substrate 10, it is naturally not limited to the double-sided tape. As the bonding means for bonding the surface 3 of the wafer 2 to the reinforcing support substrate 10, various modifications such as a method in which a liquid resin is spin-coated and bonded by UV irradiation or baking are possible.
[0042]
Also, in the process flow in which the back surface polishing shown in FIGS. 1 (a) (iv) and 1 (b) (iv) is performed, and thereafter, an adhesive film that can be thermocompression bonded to the wafer back surface 30 ′, coating, and the like are performed. good.
[0043]
(Second Embodiment)
FIGS. 2A to 2I show a process flow of the wafer polishing method of the second embodiment, and FIGS. 2B to 2I show FIGS. 2A to 2I. The process cross section corresponding to vii) is shown. 9 (e) to 9 (g) show process cross-sections in which the outer peripheral portion of the wafer is partially enlarged (FIGS. 2 (b), (i) to (vii) indicate that the orientation of the wafer 2 is up and down. The opposite is drawn.)
[0044]
The wafer 2 to be polished is the same as that shown in FIG. That is, on the surface 3 of the wafer 2, semiconductor elements and circuits 9 are formed in the internal region 16, and a polyimide coat 14 having a thickness of about 3 μm to 10 μm is provided so as to cover it. As a result, there is a gap between the uppermost surface of the inner region 16 of the wafer 2 (the surface of the polyimide coat 14, which is depicted at the lowest position in FIG. 9A) and the outer peripheral portion 15. A step A of about 3 μm to 10 μm occurs. Further, the wafer edge 8 which is the outermost periphery of the wafer 2 is chamfered (rounded) 6.
[0045]
The target finish thickness of the wafer 2 is set to a value of 100 μm or less so that a thin chip suitable for a stacked CSP (chip size package) can be obtained.
[0046]
In this embodiment, first, as shown in FIGS. 2 (a) (i), 2 (b) (i) and 9 (e), at the boundary between the inner region 16 and the outer peripheral portion 15 of the wafer 2, An incision 18 having a depth deeper than the finished thickness of the wafer 2 from the wafer surface 3 and stopping in the middle of the thickness of the wafer 2 is formed. Since the cut 18 stops in the middle of the thickness of the wafer 2, the inner region 16 and the outer peripheral portion 15 of the wafer 2 are still connected integrally at this stage. The wafer outer peripheral portion 15 to be separated includes the entire region whose height is lower than the uppermost surface of the wafer surface 3. Practically, the width of the outer peripheral portion 15 may be about 5 mm. As a method for forming the cut 18, for example, dicing may be used.
[0047]
Next, as shown in FIGS. 2 (a) (ii) and 2 (b) (ii), a double-sided tape 11 is attached to the surface 3 of the wafer 2. As in the first embodiment, the double-sided tape 11 serves as an adhesive means for bonding the surface 3 of the wafer 2 to a reinforcing support substrate 10 as a support member in the next step. As shown in FIG. 9 (f), the double-sided tape 11 includes, for example, an acrylic adhesive 24 having a thickness of 5 μm to 100 μm on one side of a PET (polyethylene terephthalate) base material 23 having a thickness of 25 μm to 200 μm, and the other side. And a heat-peelable adhesive material or UV (ultraviolet) peelable adhesive material 22 having a thickness of 5 to 100 μm. Then, the surface of the heat-peelable adhesive material or the UV-peelable adhesive material 22 is disposed on the wafer surface 3 side.
[0048]
Next, as shown in FIGS. 2 (a) (iii), 2 (b) (iii), and 9 (f), the surface 3 of the wafer 2 is made of glass or a silicon wafer with a double-sided tape 11 interposed therebetween. Affixed to the reinforcing support substrate 10. The surface dimensions of the reinforcing support substrate 10 are substantially the same as the surface dimensions of the wafer 2 and are specified sizes such as 6-inch, 8-inch, and 12-inch diameters so that existing equipment can be used. Shall.
[0049]
Next, as shown in FIGS. 2 (a) (iv), 2 (b) (iv) and FIG. 9 (g), the wafer back surface 30 is polished in a state where the wafer surface 3 is supported by the reinforcing support substrate 10. Then, the thickness of the wafer 2 is reduced to a predetermined finish thickness of 100 μm or less (the back surface after polishing is indicated by reference numeral 30 ′). In this way, after the back surface polishing step, the outer peripheral portion 15 is separated from the inner region of the wafer 2 by the cut 18. Therefore, even if a chip or a crack is generated in the wafer edge 8 that has been chamfered first, they do not travel to the inner region of the wafer 2. Further, after the back surface polishing step, that is, after separation of the outer peripheral portion 15, the new wafer edge 29 is perpendicular to the front surface 3 and the back surface 30 '. Therefore, even if the finished thickness of the wafer 2 is ultra-thin such as 100 μm or less, the wafer 2 can be made thin without causing the chipping or cracking of the wafer edge 29.
[0050]
Thereafter, as shown in FIGS. 2 (a), 2 (v), 2 (b) and 2 (v), the dicing tape stretched on the metal carrier frame 4 while the reinforcing support substrate 10 is bonded to the wafer surface 3. 5, the back surface 30 ′ of the wafer 2 is attached. The dicing tape 5 is made of, for example, an acrylic adhesive material having a thickness of 5 μm to 50 μm, or an adhesive material that can be thermocompression bonded such as an epoxy or polyimide material, to a substrate made of vinyl chloride, polyolefin, PET, or the like having a thickness of 80 μm to 200 μm. It has been crafted.
[0051]
Next, heating or UV irradiation is performed on the heat-peelable adhesive material 22 or the UV-peelable adhesive material 22 of the double-sided tape 11 shown in FIG. 9G to vaporize the gas generating material in the adhesive material. The adhesion to the wafer surface 3 is extremely reduced. As a result, the reinforcing support substrate 10 is peeled from the wafer surface 3 together with the double-sided tape 11 as shown in FIGS.
[0052]
Thereafter, dicing is performed as shown in FIGS. 2 (a) (vii) and 2 (b) (vii). Thereby, a chip 20 having a thickness of 100 μm or less suitable for a stacked CSP (chip size package) is obtained.
[0053]
In this embodiment, in particular, the process proceeds with the surface size of the wafer 2 being a predetermined size such as 6 inches, 8 inches, and 12 inches, so existing equipment and existing wafer cassettes can be used as they are. The disadvantage is that the separated wafer outer peripheral portion 15 (silicon region) flies due to the cutting resistance of the back surface polishing, and the silicon scraps may cause some trouble.
[0054]
Note that, as described in the previous embodiment, the surface of the heat release type adhesive material or the UV release type adhesive material 22 is disposed on the surface 3 side of the wafer 2. Acrylic adhesive material 24 may be disposed on the side. In that case, the reinforcing support substrate 10 shown in FIGS. 2 (a) (vi) and 2 (b) (vi) is peeled off, and then double-sided tape is peeled off. Thereafter, FIG. 2 (a) ( vii), dicing is performed as shown in FIGS. 2 (b) and (vii). As the bonding means for bonding the surface 3 of the wafer 2 to the reinforcing support substrate 10, various modifications such as a method in which a liquid resin is spin-coated and bonded by UV irradiation or baking are possible.
[0055]
In addition, the backside polishing shown in FIGS. 2 (a) (iv) and 2 (b) (iv) is performed, and thereafter, a process flow of applying an adhesive film that can be thermocompression bonded to the wafer backside 30 ′, coating, etc. good.
[0056]
(Third embodiment)
3 (a) (i) to (vi) show the process flow of the wafer polishing method of the third embodiment, and FIGS. 3 (b) (i) to (vi) are the same as FIGS. The process cross section corresponding to vi) is shown. 10 (a) to 10 (d) show process cross-sections in which the outer peripheral portion of the wafer is partially enlarged (FIGS. 3 (b), (i) to (vi) indicate that the orientation of the wafer 2 is up and down. The opposite is drawn.)
[0057]
As shown in detail in FIG. 10A, a semiconductor element or a circuit 9 is formed in the inner region 16 on the surface 3 of the wafer 2 to be polished, and a polyimide coat having a thickness of about 3 μm to 10 μm is formed so as to cover it. 14 is provided. As a result, there is a gap between the uppermost surface of the inner region 16 of the wafer 2 (the surface of the polyimide coat 14, depicted at the lowest position in FIG. 10A) and the outer peripheral portion 15. A step A of about 3 μm to 10 μm occurs. Further, the wafer edge 8 which is the outermost periphery of the wafer 2 is chamfered (rounded) 6.
[0058]
The target finish thickness of the wafer 2 is set to a value of 100 μm or less so that a thin chip suitable for a stacked CSP (chip size package) can be obtained.
[0059]
In this embodiment, first, as shown in FIGS. 3 (a) (i), 3 (b) (i), and 10 (b), the boundary between the inner region 16 and the outer peripheral portion 15 of the wafer 2 is the surface. 3 and the back surface 30 are cut perpendicularly. Thereby, the wafer outer peripheral portion 15 corresponding to the outside of the cut portion 17 is removed. Therefore, even if the wafer edge 8 is initially chamfered 6, the wafer edge after the outer peripheral portion 15 is removed is perpendicular to the front surface 3 and the back surface 30. The removed wafer outer peripheral portion 15 includes the entire region whose height is lower than the uppermost surface of the wafer surface 3. Practically, the width of the outer peripheral portion 15 may be about 5 mm. The cutting method may be, for example, dicing or grinding performed by applying a diamond wheel from the side of the wafer 2 while rotating it at a high speed.
[0060]
Next, as shown in FIGS. 3 (a) (ii), 3 (b) (ii), and FIG. 10 (c), a protective tape 1 as a support member is attached to the surface 3 of the wafer 2. As shown in FIG. 10C, the protective tape 1 is an acrylic or UV (ultraviolet) curable adhesive material having a thickness of 10 μm to 50 μm on one side of a PET (polyethylene terephthalate) substrate 13 having a thickness of 50 μm to 200 μm, for example. 12 is provided. Then, an acrylic or UV curable adhesive material 12 is disposed on the wafer surface 3 side. The surface dimensions of the protective tape 1 are substantially the same as the surface dimensions of the wafer 2 at this stage.
[0061]
In addition, in order to give the protective tape 1 a reinforcing effect and support the wafer 2 reliably, it is desirable to set the thickness of the PET base material 13 to about 10 μm to 150 μm. Further, in order to provide the protective tape 1 with a function of relaxing the stress of the wafer warp after the back surface polishing step, a stress relaxation layer made of an elastomer material is provided between the PET base material 13 and the acrylic adhesive material 12. Is desirable.
[0062]
Next, as shown in FIGS. 3 (a) (iii), 3 (b) (iii) and 10 (d), the wafer back surface 30 is polished while the wafer surface 3 is supported by the protective tape 1. The thickness of the wafer 2 is reduced to a predetermined finished thickness of 100 μm or less (the back surface after polishing is indicated by reference numeral 30 ′). In this way, the back surface 30 of the wafer can be polished while supporting the entire area of the wafer surface 3 at this stage, so that the accuracy of the back surface polishing is increased. Further, after the back surface polishing step, the wafer edge 19 does not have a sharp shape like a knife, and the wafer edge 19 is perpendicular to the front surface 3 and the back surface 30 '. Therefore, even if the finished thickness of the wafer 2 is ultra-thin such as 100 μm or less, the wafer 2 can be made thin without causing the chipping or cracking of the wafer edge 19.
[0063]
Thereafter, as shown in FIGS. 3 (a) (iv) and 3 (b) (iv), the protective tape 1 is adhered to the wafer surface 3 and the dicing tape 5 stretched on the metal carrier frame 4 is applied. A back surface 30 ′ of the wafer 2 is attached. The dicing tape 5 is made of, for example, an acrylic adhesive material having a thickness of 5 μm to 50 μm, or an adhesive material that can be thermocompression bonded such as an epoxy or polyimide material, to a substrate made of vinyl chloride, polyolefin, PET, or the like having a thickness of 80 μm to 200 μm. It has been crafted.
[0064]
Next, the protective tape 1 is peeled from the wafer surface 3 as shown in FIGS.
[0065]
Thereafter, dicing is performed as shown in FIGS. 3 (a) (vi) and 3 (b) (vi). Thereby, a chip 20 having a thickness of 100 μm or less suitable for a stacked CSP (chip size package) is obtained.
[0066]
Particularly in this embodiment, since the protective tape 1 is used as the support member, the wafer 2 is reinforced by the protective tape 1 during the back surface polishing process, the dicing tape application process, and the inter-process transport. It is not affected by wafer warpage. Therefore, it is possible to further prevent the wafer from cracking and to further improve the wafer manufacturing yield. Moreover, since the protective tape 1 is provided with the adhesive material 12, it can be affixed as it is to the wafer surface 3, and does not require another adhesive member. Therefore, the bonding process and the bonding material can be reduced, and the manufacturing cost can be reduced.
[0067]
Also, in the process flow in which the back surface polishing shown in FIGS. 3 (a) (iii) and 3 (b) (iii) is performed, and thereafter, an adhesive film that can be thermocompression bonded to the wafer back surface 30 ′ is applied and coated. good.
[0068]
(Fourth embodiment)
4 (a) (i) to (vi) show a process flow of the wafer polishing method according to the fourth embodiment, and FIGS. 4 (b) (i) to (vi) show FIGS. 4 (a) (i) to (vi). The process cross section corresponding to vi) is shown. 10 (e) to 10 (g) show process cross-sections in which the outer peripheral portion of the wafer is partially enlarged (FIGS. 10 (b), (i) to (vi) indicate that the orientation of the wafer 2 is up and down. The opposite is drawn.)
[0069]
The wafer 2 to be polished is the same as that shown in FIG. That is, on the surface 3 of the wafer 2, semiconductor elements and circuits 9 are formed in the internal region 16, and a polyimide coat 14 having a thickness of about 3 μm to 10 μm is provided so as to cover it. As a result, there is a gap between the uppermost surface of the inner region 16 of the wafer 2 (the surface of the polyimide coat 14, depicted at the lowest position in FIG. 10A) and the outer peripheral portion 15. A step A of about 3 μm to 10 μm occurs. Further, the wafer edge 8 which is the outermost periphery of the wafer 2 is chamfered (rounded) 6.
[0070]
The target finish thickness of the wafer 2 is set to a value of 100 μm or less so that a thin chip suitable for a stacked CSP (chip size package) can be obtained.
[0071]
In this embodiment, first, as shown in FIGS. 4 (a) (i), 4 (b) (i), and 10 (e), at the boundary between the inner region 16 and the outer peripheral portion 15 of the wafer 2, An incision 18 having a depth deeper than the finished thickness of the wafer 2 from the wafer surface 3 and stopping in the middle of the thickness of the wafer 2 is formed. Since the cut 18 stops in the middle of the thickness of the wafer 2, the inner region 16 and the outer peripheral portion 15 of the wafer 2 are still connected integrally at this stage. The wafer outer peripheral portion 15 to be separated includes the entire region whose height is lower than the uppermost surface of the wafer surface 3. Practically, the width of the outer peripheral portion 15 may be about 5 mm. As a method for forming the cut 18, for example, dicing may be used.
[0072]
Next, as shown in FIGS. 4 (a) (ii), 4 (b) (ii), and FIG. 10 (f), a protective tape 1 as a support member is attached to the surface 3 of the wafer 2. As shown in FIG. 10 (f), the protective tape 1 is an acrylic or UV (ultraviolet) curable adhesive material having a thickness of 10 μm to 50 μm on one side of a PET (polyethylene terephthalate) substrate 13 having a thickness of 50 μm to 200 μm, for example. 12 is provided. Then, an acrylic or UV curable adhesive material 12 is disposed on the wafer surface 3 side. The surface dimensions of the protective tape 1 are substantially the same as the surface dimensions of the wafer 2.
[0073]
In addition, in order to give the protective tape 1 a reinforcing effect and support the wafer 2 reliably, it is desirable to set the thickness of the PET base material 13 to about 10 μm to 150 μm. Further, in order to provide the protective tape 1 with a function of relaxing the stress of the wafer warp after the back surface polishing step, a stress relaxation layer made of an elastomer material is provided between the PET base material 13 and the acrylic adhesive material 12. Is desirable.
[0074]
Next, as shown in FIGS. 4 (a) (iii), 4 (b) (iii) and 10 (g), the wafer back surface 30 is polished in a state where the wafer surface 3 is supported by the protective tape 1. The thickness of the wafer 2 is reduced to a predetermined finished thickness of 100 μm or less (the back surface after polishing is indicated by reference numeral 30 ′). In this way, after the back surface polishing step, the outer peripheral portion 15 is separated from the inner region of the wafer 2 by the cut 18. Therefore, even if a chip or a crack is generated in the wafer edge 8 that has been chamfered first, they do not travel to the inner region of the wafer 2. Further, after the back surface polishing step, that is, after separation of the outer peripheral portion 15, the new wafer edge 29 is perpendicular to the front surface 3 and the back surface 30 '. Therefore, even if the finished thickness of the wafer 2 is ultra-thin such as 100 μm or less, the wafer 2 can be made thin without causing the chipping or cracking of the wafer edge 29.
[0075]
Thereafter, as shown in FIGS. 4 (a) (iv) and 4 (b) (iv), the protective tape 1 is adhered to the wafer surface 3 and the dicing tape 5 stretched on the metal carrier frame 4 is applied. A back surface 30 ′ of the wafer 2 is attached. The dicing tape 5 is made of, for example, an acrylic adhesive material having a thickness of 5 μm to 50 μm, or an adhesive material that can be thermocompression bonded such as an epoxy or polyimide material, to a substrate made of vinyl chloride, polyolefin, PET, or the like having a thickness of 80 μm to 200 μm. It has been crafted.
[0076]
Next, the protective tape 1 is peeled from the wafer surface 3 as shown in FIGS.
[0077]
Thereafter, dicing is performed as shown in FIGS. 4 (a) (vi) and 4 (b) (vi). Thereby, a chip 20 having a thickness of 100 μm or less suitable for a stacked CSP (chip size package) is obtained.
[0078]
In this embodiment, as in the second embodiment, the process is carried out with a specified size such as a 6-inch, 8-inch, or 12-inch diameter of the wafer 2, so existing facilities and existing wafer cassettes are utilized as they are. can do. The disadvantage is that the separated wafer outer peripheral portion 15 (silicon region) flies due to the cutting resistance of the back surface polishing, and the silicon scraps may cause some trouble.
[0079]
Further, in this embodiment, as in the third embodiment, the protective tape 1 is used as a support member. Therefore, the wafer 2 is reinforced by the protective tape 1 during the back surface polishing process, the dicing tape application process, and the inter-process transport. . It is not affected by wafer warpage. Therefore, it is possible to further prevent the wafer from cracking and to further improve the wafer manufacturing yield. Moreover, since the protective tape 1 is provided with the adhesive material 12, it can be affixed as it is to the wafer surface 3, and does not require another adhesive member. Therefore, the bonding process and the bonding material can be reduced, and the manufacturing cost can be reduced.
[0080]
Also, in the process flow in which the back surface polishing shown in FIGS. 4 (a) (iii) and 4 (b) (iii) is performed, and thereafter, an adhesive film that can be thermocompression bonded to the wafer back surface 30 ′ is applied and coated. good.
[0081]
【The invention's effect】
As apparent from the above, according to the wafer polishing method of the present invention, the wafer can be thinned without causing chipping or cracking of the wafer edge even if the final thickness of the wafer is 100 μm or less.
[Brief description of the drawings]
FIG. 1 (a) is a process flowchart of a wafer polishing method according to a first embodiment of the present invention, and FIG. 1 (b) is a process sectional view corresponding to FIG. 1 (a).
FIG. 2 (a) is a process flowchart of a wafer polishing method according to a second embodiment of the present invention, and FIG. 2 (b) is a process sectional view corresponding to FIG. 2 (a).
FIG. 3A is a process flowchart of a wafer polishing method according to a third embodiment of the present invention, and FIG. 3B is a process cross-sectional view corresponding to FIG.
4A is a process flowchart of a wafer polishing method according to a fourth embodiment of the present invention, and FIG. 4B is a process cross-sectional view corresponding to FIG.
5A is a process flowchart of a conventional general wafer polishing method, and FIG. 5B is a process sectional view corresponding to FIG. 5A.
6A is a process flowchart of another conventional wafer polishing method, and FIG. 6B is a process cross-sectional view corresponding to FIG. 6A.
FIG. 7A is a diagram showing a schematic configuration when a wafer to be polished is viewed from a direction perpendicular to the surface, and FIG. 7B is a diagram B in FIG. It is an expanded sectional view on the -B line.
FIG. 8 is a view showing a cross section of the outer periphery of a wafer after a back surface polishing step in a conventional wafer polishing method.
FIG. 9 is a process cross-sectional view focusing on the wafer outer periphery in the first and second embodiments of the present invention;
FIG. 10 is a process cross-sectional view focusing on the wafer outer periphery in the third and fourth embodiments of the present invention.
[Explanation of symbols]
1 protective tape
2 wafers
3 Surface
4 Carrier frame
5 Dicing tape
6 Chamfering
8, 19, 29 Wafer edge
10 Support substrate for reinforcement
11 Double-sided tape
15 Wafer outer periphery
20 chips

Claims (6)

Cutting or polishing the boundary between the inner region where the semiconductor element or circuit is formed on the wafer and the outer peripheral portion thereof perpendicular to the surface of the wafer to remove the outer peripheral portion of the wafer;
Bonding the surface of the wafer to a support member having a surface dimension greater than or equal to the surface dimension of the wafer;
Polishing the back surface of the wafer with the support member supporting the front surface of the wafer to reduce the thickness of the wafer to a predetermined finished thickness. At the boundary between the inner region where the semiconductor element or circuit is formed on the wafer and the outer periphery of the inner region, the depth is deeper than the finished thickness of the wafer from the surface of the wafer and stops halfway through the thickness of the wafer. Forming a notch; and
Bonding the surface of the wafer to a support member having a surface dimension greater than or equal to the surface dimension of the wafer;
Polishing the back surface of the wafer with the support member supporting the front surface of the wafer to reduce the thickness of the wafer to the finished thickness. The wafer polishing method according to claim 1 or 2,
In one embodiment of the wafer polishing method, the support member is a support substrate. The wafer polishing method according to claim 1 or 2,
In one embodiment of the wafer polishing method, the support member is a protective tape including an adhesive material. The wafer polishing method according to claim 1 or 2,
A wafer polishing method, wherein the finished thickness is set to a value of 100 μm or less. The wafer polishing method according to claim 1 or 2,
The wafer polishing method, wherein an outer peripheral portion of the wafer includes a region whose height is lower than an uppermost surface of the wafer surface.

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