JP2004289240A - Packet data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a packet data processor capable of realizing a decoder function with high processing performance for simultaneous processing of a plurality of digital stream data in receiving the data in a processor-based demultiplexing system for processing a plurality of streams. <P>SOLUTION: The packet data processor totally controls a start / end state of each processing unit when applying prescribed demultiplexing processing to a plurality of streams and dynamically switches the processing procedure in accordance with the operating state of each processing unit. Thus, operating a plurality of the processing units in parallel enhances the processing performance. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a transport stream decoder that receives a plurality of transport streams at bit rates as input, performs desired processing on the input plurality of transport streams, and generates a new transport stream. More specifically, the present invention identifies in real time whether or not packet data constituting a sequentially input transport stream of a different format is to be processed, and if the packet data is to be processed, a predetermined The present invention relates to a transport stream decoder that dynamically controls the processing according to the operation status of each processing.
[0002]
[Prior art]
Conventionally, requests for performing various processes and editing on digital contents and making secondary use of them are possible only for content production or distribution sources such as broadcasting stations. However, due to recent advances in digital technology, the quality and quantity of digital distribution systems as infrastructure have been enhanced every day. In other words, the enhancement of the transport stream that provides digital contents, the enhancement of the performance of hardware required for processing by the user, and the reduction of the cost for the transport stream have resulted in the transport stream being conventionally implemented only by facilities such as broadcasting stations. Environmental conditions for users to enjoy the editing of packet data and the editing of packet data constituting a transport stream are being prepared.
[0003]
However, in order for the user to perform desired processing for each digital content, real-time selection is performed for each of the packet data constituting the sequentially input transport stream, and further, for the selected packet data. Means are required to permit access of the processing means to perform corresponding processing or processing.
[0004]
A transport decoder that processes individual digital packet data with respect to selected packet data is known (for example, see Patent Literature 1 and Patent Literature 2).
[0005]
Hereinafter, a conventional transport decoder will be described with reference to FIG.
[0006]
In a conventional transport decoder (TSD), a transport stream (TSIN) demodulated by a tuner is input to an input device 10. If the input TSIN is a regular transport stream packet with synchronization, the corresponding TSIN is output to the packet selector 20.
[0007]
The packet selector 20 selects digital content packets necessary for the user to view the broadcast from the input packets. When sorting packets, the sorting is performed by comparing PIDs (Packet IDs), which are identifiers indicating the types of programs of the transport stream packets. In the digital broadcast receiver, information for discriminating a packet required for viewing on the user side is registered in advance in a recorder (not shown) in the packet selector by the TD controller 80.
[0008]
The transport stream packet (PIDO) extracted by the former-stage packet selection performs a decryption process on an encrypted stream that is performed for protecting digital contents. Next, the encrypted packet (PIDO) is input to the syntax processor A, and the syntax processor A performs a decryption process. The syntax processor A performs decryption processing on the encrypted transport stream packet (PIDO) based on the key information obtained according to the user, and outputs decrypted packet data (SPAO). . In the digital broadcast receiver, key information for decryption is also notified in advance by the TD controller 20 at the start of decryption processing.
[0009]
The transport stream packet (SPAO) decoded by the preceding decoding process is input to the syntax processing unit B40. The syntax processor B40 analyzes the SPAO and the data portion corresponding to the packet. More specifically, the processing analysis corresponds to processing for forming a transport stream packet format into a PES packet format.
[0010]
The data (SPBO) processed by the preceding syntax processor 40 is input to the main memory output unit 50. The main memory output unit 50 manages an address for outputting the input SPBO to the external main memory 70, buffers the SPBO in a transfer unit of the external main memory 70, and outputs the SPBO to a predetermined address. The digital data stored in the main memory 70 is read out again from the main memory 70 when there is a data request from a subsequent AV decoder (not shown), and outputs AV data (AVO).
[0011]
In parallel with the syntax processor 40, the SPAO is input to the stream output unit 60, and outputs the SPAO from an output port HSO of another system. This packet data HSO can be used as an input to a digital device for recording digital data.
[0012]
The above is the processing of the conventional transport decoder (TSD). FIG. 14 shows the data input / output timing of each processor in these processes. The pipeline processing is performed in the processing time (TD1, TD2, TD3, TD4, TD5) of each processor shown in FIG. As an example, in the case of a conventional transport decoder in which processing with a clock of 100 MHz has a processing performance of 60 Mbps, a transport packet in units of 188 bytes input at 60 Mbps takes a time from when a packet is input to when it is output. Pt is processed in about 30 us.
[0013]
[Patent Document 1]
JP-A-9-247237
[Patent Document 2]
JP-A-2000-151538
[0014]
[Problems to be solved by the invention]
When one transport stream is handled as in the above-described conventional technique, the above-described conventional example is suitable. However, when performing various processes on digital content, it is necessary to process a plurality of streams simultaneously. In such a case, when the above-described conventional apparatus is used, the circuit is required for a plurality of streams, and there is a problem that the circuit scale is drastically increased.
[0015]
In addition, some digital content processing involves a small amount of processing for stream analysis, such as extraction of AV data, and extraction of internal data during stream analysis, such as extraction of Program Service Information (PSI) packets. In some cases, the amount of processing that requires fine pattern selection is large, and the amount of calculation usually differs depending on the type of packet. In such a case, in the case of a pipeline in which the processing is constant as in the above-described conventional example, the processing time is different depending on the contents of the packet data, but the end of the processing in the preceding stage is sequentially waited. As a result, there is a problem that the processing performance is reduced.
[0016]
The present invention has been made in consideration of the above-described conventional problems, and a method of temporarily storing a plurality of streams in a stream buffer once and switching a processing procedure by software in accordance with processing contents of a received packet, thereby realizing a circuit. The purpose is to increase the processing performance without increasing the scale drastically.
[0017]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, an invention of a packet data processing apparatus according to claim 1 is a stream input device for use in an MPEG system which receives continuous transport stream data from a plurality of ports at the same time, and an input transport stream. , A packet selector for extracting desired transport packet data from the data, two or more syntax processors for processing and extracting the selected transport packet data into predetermined data, and a constant interval between input transport streams. A stream output device that outputs an input stream while keeping the data, a main memory output device that outputs digital data processed by the syntax processor to a memory, and the stream input device, syntax processor, stream output device, and main memory output. Arbitration of data transfer to the instrument Arbitrator, a stream buffer for storing an input transport stream, a data transfer controller for controlling data transfer to each processor, the packet selector, two or more syntax processors, and a stream output. A controller for controlling the device, a main memory output device, an arbitrator, and a data transfer controller; and a controller storage device for storing an instruction code sequence executed by the controller and contents processed by the controller.
[0018]
According to a second aspect of the present invention, after successive transport stream data used in an MPEG system is simultaneously input from a plurality of ports, desired transport packet data is extracted from the input transport stream. And simultaneously performing two or more syntax processes for processing and extracting the selected transport packet data into predetermined data, outputting an input stream while keeping a constant interval with the input transport stream, and performing syntax processing. A series of packet processing for outputting the performed digital data to the memory is controlled by a pipeline.
[0019]
According to a third aspect of the present invention, there is provided a packet data processing device, wherein the controller according to the first aspect sequentially processes a specific instruction sequence in accordance with an instruction addressed to a controller recorder. .
[0020]
According to a fourth aspect of the present invention, there is provided a packet data processing apparatus according to the first aspect, wherein the controller according to the first aspect includes two or more threads, and the threads are sequentially switched every specific cycle. .
[0021]
According to a fifth aspect of the present invention, the controller according to the first aspect shares information between two or more threads and operates each thread based on the shared information. Is what you do.
[0022]
According to a sixth aspect of the present invention, in the software control by the controller according to the second aspect, the processing common to the received transport stream packets is controlled by one task, and the received transport stream packets are controlled by one task. In this case, another task is used to control the processing whose processing content is determined in accordance with the task.
[0023]
According to a seventh aspect of the present invention, in the software control by the controller according to the second aspect, the packet data selection processing sequentially performed in the packet data processing, the syntax processing for decrypting the broadcast encryption, and the selected processing are performed. For a series of processing of syntax processing for analyzing data of packet data and main memory output processing for outputting to a main memory, packet data selection processing of a packet stored immediately before in a packet data processing device and broadcast encryption The decoding process is the first stage process, the syntax process for analyzing the data of the packet stored two steps before is the second stage process, and the main memory output of the packet stored three times before to the main memory. The processing performance is improved by performing a three-stage pipeline process as a third-stage process. That.
[0024]
According to an eighth aspect of the present invention, in the software control by the controller according to the second aspect, the number of packets being processed is counted, and the number of the corresponding packets is counted. The following processing contents are determined according to the processing status of the syntax processing unit and the main memory output unit.
[0025]
According to a ninth aspect of the present invention, in the packet data processing based on the packet count according to the eighth aspect, when a packet is not input, data being processed is being processed in the packet data processing apparatus. Is determined, the pipeline is partially changed, and packet processing in the middle of processing is performed.
[0026]
According to a tenth aspect of the present invention, in the software control by the controller according to the second aspect, the amount of processing operations of syntax processing and main memory output processing of a plurality of packets being processed is performed. In addition, by simultaneously performing processing with a small amount of processing during processing with a large amount of processing, the overall processing performance is improved.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described with reference to the drawings showing the embodiments.
[0028]
(Embodiment 1)
FIG. 1 shows the configuration of the packet data processing device according to the first embodiment of the present invention.
[0029]
In FIG. 1, a packet data processing device TSD includes a stream input device 100 that receives a plurality of transport stream packets or program stream packets TSI1 to TSIN, an arbiter 110 that arbitrates a data input / output request from each processor, A data transfer controller 120 for writing or reading data of the process arbitrated by the arbitrator 110 to the stream buffer 130 in units of several bytes, a stream buffer 130 for storing the received stream data, After storing the port stream packet in the stream packet 130, the packet selector 160 selects the packet to be processed by the stored packet, and the packet selected by the packet selector 160 is required according to the stream data. In this case, a syntax processing A180 for processing in such a case, a syntax processor B190 for filtering internal digital data from the stream data processed in the syntax processing A and extracting only necessary data, and a syntax processor B190 are used. A main memory 210 for outputting digital data to the main memory 220, a stream output device 200 for maintaining a reception interval of received stream data and outputting the digital data to a high-speed digital output port at regular intervals, the packet selector 160, 140 for controlling the activation of the device A 180, the syntax processor B 190, the stream output device 200, and the main memory output device 210, and collectively controlling the processing of the packet data processing device TSD; Binary data and controllers And a read-write pipeline processing storage unit 150 for storing the processed contents 40.
[0030]
The packet data processing device TSD is operated by a TD controller 230 that determines the processing content of each processor.
[0031]
The above-described processing of the packet data processing device TSD of the present invention will be described with reference to FIG. 1 in accordance with the flow of stream data.
[0032]
The input plurality of transport stream packets TS_1 to TS_N are input to the stream input unit 105. The stream input unit 105 detects a synchronization signal (packet start signal) of the input transport stream packet, and outputs requests TSI1 to TSIN for storing data in the stream buffer to the arbitrator 110. These requests TSI1 to TSIN are output to the arbitrator 110 independently for each input corresponding to the input ports.
[0033]
The arbitrator 110 arbitrates the plurality of requests generated as described above, transfers data corresponding to the acquired requests to the data transfer controller 120, and stores the data in the stream buffer 130. In the arbitration process in the arbitrator 110, a data transfer request from a syntax processor A180, a syntax processor B190, a stream output unit 200, and a main memory output unit 210, which will be described later, is managed and arbitrated.
[0034]
Next, it is determined whether the packet data stored in the stream buffer 130 is a packet to be processed by the packet data processing device TSD. The packet to be processed is identified by a packet identifier (hereinafter referred to as PID) in the transport stream packet. When the PID in the received transport stream packet and the PID for processing set by the TD controller 230 match, the packet is obtained, and thereafter, the process is similarly performed by the TD controller 230. Thereafter, the subsequent processing is started.
[0035]
If the packet determined as the packet to be processed is encrypted on the transmission side, subsequent data analysis cannot be performed. In that case, the decoding processing is performed by the syntax processor A180. In the packet data processing device TSD, whether or not the received packet has been encrypted is determined by TSC (Transport Scramble Control) in the received transport stream packet. When the received transport stream packet is encrypted, the syntax processor A 180 issues a request to read the encrypted packet data from the stream buffer to the arbiter 110. After arbitrating with a request from another processor, the arbitrator 110 obtains a read request from the syntax processor A180 and issues a data transfer instruction for the read request to the data transfer controller 120. The data transfer controller 120 reads the data from the address where the corresponding decoded data is stored, and inputs the data to the syntax processor A180 via the SBI path. The syntax processor A180 performs a decryption process using a decryption key set by the TD controller 230 for each transfer unit. The decrypted data issues a write request request signal to the arbiter 110 in the same way as when reading, to the arbiter 110 via the path to the SAO, and after the arbitrator 110 obtains the request, sends the stream buffer 130 To be stored again.
[0036]
Next, the data portion of the packet data decrypted in the above is extracted by the syntax processor B190. In a digital broadcasting system, PSI (Program Service Information) including video / audio data, information indicating a program configuration, personal information, and key information for decrypting data encrypted on the transmission side is multiplexed. Sending. The syntax processor B190 extracts only data necessary for decoding the transport stream from the multiplexed data.
[0037]
When the syntax processor B190 is activated, a request to read out the decoded data stored in the stream buffer 130 is issued to the arbitrator 110, as in the case of the activation of the syntax processing A180. After acquiring the request of the syntax processor B180 after arbitration with a request from another processor, the arbitrator 110 issues a data transfer instruction for the read request to the data transfer controller 120. The data transfer controller 120 reads data from the address where the corresponding decoded data is stored, and inputs the data to the syntax processor B via the SBI path. The syntax processor B190 performs a matching process on each transfer unit to determine whether the pattern matches the comparison data string pattern set by the TD controller 230. If they match, data of the data length up to the next comparison field is extracted. If they do not match, the data up to the next comparison field is discarded. Such processing is performed once or more in the transport, and for the extracted data, a write request request signal to the stream buffer is issued to the arbitrator 110. After the arbitrator 110 acquires the request, the data transfer controller 120 And re-stored in the stream buffer 130.
[0038]
Next, the stream data extracted and processed in a series of processes up to the syntax processor B190 is output from the main memory output unit 210. After the predetermined processing, data to be output from the main memory output device 210 is stored as a data format to be output to the stream buffer 130. When the stream data to be output to the main memory is stored in the stream buffer 130, the main memory output device 210 starts. The main memory output unit 210 issues a read request of the main memory output unit to the arbitrator 110. The arbitrator 110 arbitrates with a request from another processor, acquires this read request, and issues a data transfer instruction to the data transfer controller 120. The data transfer controller 120 decodes the memory address where the data read by the stream output unit 210 is stored, and reads the data from the stream buffer. The read data is input to the main memory output unit 210, and outputs a data transfer command for writing to a predetermined address of the main memory and a main memory address, and is stored in the main memory. The data stored in the main memory is used in processing by a TD controller or an AV decoder at a subsequent stage.
[0039]
The data stored in the stream buffer 130 is output via the stream output device 200 in parallel with a series of processing until the data is stored in the main memory. The process of outputting from the stream buffer 130 to the stream output device will be described with reference to FIG.
[0040]
2, the input device 105, the stream output device 200, the stream buffer 130, the controller 140, and the signals TSI1 to TSIN, RDI, RDO, and HO of the stream path are the same as those described in FIG. The stream output unit 200 includes a timer 2001 and a data output unit 2003. The data output unit has as inputs the value of the timer 2001 and an offset value 2002 that can be set by the data control unit 2003. The transport streams TS_A and TS_B in the figure are the first packet transport stream to which TS_A is input first and the transport stream TS_B is the second packet. FIG. 3 shows the timing of this transport stream TSD, input / output and time of this transport stream.
[0041]
When the transport stream TS_A is input to the input unit 105, the input unit 105 reads the timer value of the time when the input of TS_A has been completed, and adds the timer value as arrival time stamp information ATS when the stream buffer 130 is stored. Assuming that the arrival time of this TS_A is ATS_A, ATS_A is stored at the head of TS_A. An offset value set by the controller 140 is set in advance as an offset period from the time when the TS_A arrives at the packet data processing device of the present development to the time when it is output. As described above, when the data output unit is activated after performing a predetermined process on the corresponding transport stream packet TS_A, the data output unit issues a data read request for data output to the arbitrator 110. . The arbitrator 110 arbitrates with a request from another processor, acquires this read request, and issues a data transfer instruction to the data transfer controller 120. The data transfer controller 120 decodes the memory address where the data read by the stream output unit 210 is stored, and reads the data from the stream buffer. This data is input to the data output unit 2003 in the stream data output device 200. Upon receiving the arrival time stamp information of the data, the data output unit 2003 performs an addition process with the offset value 2002 input from the controller 140. When the added value is the current time during which the timer 2001 is constantly operating, a read request for the subsequent data portion is similarly issued, and the input data is sequentially output from the stream output unit. Similar processing is performed on the subsequent transport stream packets TS_B, and the stream is output while maintaining a constant interval from the input of the transport stream packets shown in FIG. Maintaining a constant interval is necessary for decoding without changing the bit rate of the input bit stream encoded by MPEG2-TS or the like, and this processing is performed simultaneously with the above-described packet data processing. The data output from the stream output device 200 can be used for connection to AV equipment conforming to the IEEE 1394 standard for transmitting processing in the TS protocol format.
[0042]
The above is the flow of a series of stream processing of each unit of the packet data processing device TSD of the present invention. Each processor is activated and performs a predetermined process by inputting a predetermined transport stream packet or processing data. It is the controller 140 which is the main object of the present invention that controls the activation of each unit as a whole. . For example, the processing is unique when the processing is sequentially performed in the above processing order without the intervention of the controller 140. However, when a plurality of inputs are performed, a part other than the processing such as which data in the stream buffer is to be referred to is used. It is necessary for each part to have this, leading to an increase in circuit scale. Also, most of the processing in the processor is not a single processing but a processing according to the type of the packet. If the switching is performed sequentially, the overhead until the start of the processing is large and the processing efficiency is deteriorated. Therefore, these processes are managed in series by the controller 140. In the control of the controller 140, a portion according to a control method of each processor will be described.
[0043]
First, the configuration of the controller 140 will be described with reference to FIG. In FIG. 1, a controller storage 150 for storing a predetermined operation instruction sequence of the controller 140 is provided in the packet data processing device TSD. When the processing instruction sequence is stored in the controller storage 150, the data is loaded into the controller 140 via the UDI when the controller 140 is started. The controller 140 has a mechanism for sequentially performing processing according to the loaded instruction sequence. The controller storage unit 150 is used as an operation storage unit that partially stores the operation results processed by the controller 140 and sequentially reads out stored data. In this case, at the time of processing of the storage command calculation by the controller 140, the data is stored at a predetermined address of the control recorder or read from the predetermined address via the UDL. Further, the controller 140 has a small register (not shown in FIG. 1) in addition to the controller recorder 150. This register is used for speeding up the processing inside the controller without accessing the controller recorder 150 sequentially. Further, the controller 140 has a plurality of data buses capable of extracting and storing data in the stream buffer 130, like the other processors. This data bus transfer will be described.
[0044]
When extracting predetermined data from the data stored in the stream buffer 130, the controller 140 issues a data read request CDWR to the arbitrator 110. The arbitrator 110 arbitrates with a request from another processor, acquires this read request, and issues a data transfer instruction to the data transfer controller 120. The data transfer controller 120 decodes the memory address where the data read by the controller 140 is stored, and reads the data from the stream buffer. This data is stored in a register of the controller 140 via the CDR. When the data processed by the controller is described in the stream buffer 130, a write request CDWR is issued to the arbitrator 110 in the same manner as the reading. The arbitrator 110 arbitrates with a request from another processor, acquires this write request, and issues a data transfer instruction to the data transfer controller 120. The data transfer controller 120 decodes a memory address where data written by the controller 140 is to be stored, and writes the decoded data to the stream buffer. This data is input from the register of the controller 140 to the data transfer controller 120 via the CDW and stored in the stream buffer.
[0045]
The controller 140 of the present invention is a multi-thread system that performs control by switching two or more processing tasks, and performs the parallel processing by allocating each processing described above to each thread. The mechanism of the multi-thlete will be described with reference to FIG.
[0046]
FIG. 4 shows the steady-state operation of the controller 140 according to the present invention. The controller 140 switches between two or more threads at regular intervals (four cycles in the drawing), and operates on a multi-thread processor in which the assigned thread performs processing of the thread. This multi-thread processor has the advantage that the processing of each thread can operate independently, and is suitable for simultaneous processing.
[0047]
The controller 140 includes an inter-thread communication register (not shown in the figure) in addition to the stream processing and extraction registers. The inter-thread communication register includes a plurality of communication bits that can be accessed from any of the threads 1 and 2 in the multi-thread processing. The present invention can be used to monitor the control of the entire packet data processing device TSD.
[0048]
The controller 140 having the above-described configuration controls the packet data processing of the present invention. The processing assignment of the packet data processing device TSD of the present invention will be described with reference to FIG. In FIG. 5, three or more threads can be allocated. However, the additional thread increases the circuit of the controller 140. Only the description will be given.
[0049]
In FIG. 5, the left column shows the assigned thread numbers. The middle column is represented by the name of each processor in FIG. 1, and the right column indicates the processing order of the corresponding packet. In the present invention, a transport stream packet is received from the input device 105, a processing packet is extracted by the packet selector 160, and a portion to be scrambled by the syntax processor A is assigned to the sod 1 for the scrambled stream. While descrambling data is output at high speed from the stream output unit 200, data extraction and knitting processing are performed by the syntax processing unit B190, and finally, the main memory output unit 210 outputs the data to the main memory in the thread 1. When the corresponding stream is processed sequentially, it is possible to perform the processing in accordance with the processing procedure shown in FIG. 5 and also to perform the processing from the order 1. In this case, after each processor finishes, the next processor To move, the processing time required for one stream packet is: packet selector time (A), syntax processor A processing time (B), stream output device control time (C) + syntax processor B processing time (D) + The sum of the main memory output time (E) and the efficiency is poor. Further, even during the packet processing, since the stream is sequentially input from a plurality of ports from the input unit 105, the capacity of the stream buffer 130 for reception from another system needs to be prepared on a large scale in the sequential processing. There is. The present invention is an invention of a control method for solving these problems, and specific contents of a control method for reducing processing efficiency will be described with reference to FIGS. 1, 6, 7, and 10. FIG.
[0050]
6 and 7 show an overall processing flow controlled by the control unit 140 of the packet data processing device of the present development. FIG. 6 shows a control method for the thread 1 of the multi-thread packet data processing, and FIG.
[0051]
In FIG. 6, first, at step 100, the controller 140 is activated. When the controller 140 is activated, the thread 1 is described in the controller storage 150 and performs one process per clock in accordance with the loaded instruction code. When the controller 140 is activated, the process proceeds to step 200.
[0052]
In step 200, a schedule for performing the packet data of the present invention in a multithread is set. The schedule determines the processing cycle of the packet data processing of the present invention in multiple threads by setting the number of threads used and the time allotment of one thread. Here, a setting is made such that the number of threads is 2, and the ratio of threads is such that threads 1 and 2 are equally allocated every four clocks. Further, when performing the present packet data processing, an area for temporarily storing the calculation result in the controller 140 is initialized. In this area, a part other than the part storing the processing instruction code of the controller memory is set as an operation storage area, and this part is initialized. After this initialization, the process proceeds to step 300.
[0053]
In step 300, the thread 2 is started to perform the multi-thread operation. In the controller according to the present invention, when the thread 1 serves as a main processor and only the main processor operates, processing can be performed by a single thread without switching between multi-threads. In the present invention, the process is performed by a plurality of controls by activating the thread 2 which is the slave processor. The above is the initial setting for processing the packet data processing device TSD of the present invention by the controller, and the processing from step 400 described below is a loop processing performed every time a packet arrives. Then, the process proceeds to step 400.
[0054]
In step 400, a process of storing packet data in the stream buffer 130 is performed. If the packet is in the receiving state up to step 300 and the packet data is being partially stored in the stream buffer, or if the packet data has not yet been input due to the bit rate of the packet data and the configuration of the input data, Until the storage is completed, a wait state is entered in step 400. If there is packet data for which packet data has been completely stored, the cell number storing the packet data of the packet data that has arrived first in the stored order is read from the data transfer controller 120, and the corresponding packet is read. Judge the position. Then, the process proceeds to step 500.
[0055]
In step 500, a packet selection process is performed to determine whether the packet data determined in step 400 is packet data to be processed thereafter. This determination is usually made based on a packet ID (hereinafter referred to as PID) indicating the type of packet data. To make this determination, the controller 140 requests a read request from the stream buffer to the arbiter 130 to obtain a data portion having a PID of the packet data, obtains the data, and stores the data in a predetermined register. This register value is loaded into a reference register (not shown) inside the packet selector, and the packet selector is activated. In the packet selector 160, the PID of the packet data to be processed and the processing information on how to process the data of each PID are previously set from the TD controller 230. The PID data string is compared with the PID value on the reference register. The result is displayed in a result register (not shown) of the packet selector 160. This result is two results, that is, a case where they are compared and processed (comparison match) and a case where they are not processed (comparison mismatch). Then, the process proceeds to step 600.
[0056]
In step 600, if the result of the packet selector in the packet selector 16 in step 500 is that the comparisons match, the subsequent processing content information is extracted from the packet data. The processing content information (hereinafter referred to as PET: Packet Entry Table) includes a descrambling process by syntax process A, a data extraction by syntax process B, a main memory output, and a stream output. Information for performing the subsequent processing in the processor, such as whether to perform the processing, is specified. The controller 140 loads this processing content from the content register of the packet selector 160, stores it in a register inside the controller storage 150, and proceeds to the next step 700.
[0057]
In step 700, it is determined whether to start the syntax processor A. The processing performed by the syntax processor A is mainly for decrypting an encrypted data portion of a broadcast packet data or stored packet data which is provided for the purpose of copyright protection, and converting the data into a data format which can be analyzed later. Say. In the PET extracted in the step 600, it is determined that the packet is a packet for activating the syntax processing A when the content is to perform the syntax processing A and the corresponding packet is encrypted. move on. If the packet processor does not activate the syntax processor A in the above-mentioned PET, or if the packet data is not encrypted, the syntax processor A is not activated unnecessarily and step 800 is skipped. Then, the process proceeds to step 900.
[0058]
Step 800 is a step only when the processing is performed by the syntax processor A. Here, the syntax processor A is controlled. The decryption key necessary for processing the syntax processor A is set in the controller storage 150 by the TD controller 230, and the controller 140 decodes the decryption key into the decryption key of the syntax processor A. Set in a key register (not shown). When the setting is completed, the address and size of the data including the encrypted data to be transferred to the syntax processor A are set. When the address and size settings are completed, the syntax processor A is started. When the activation is started, the syntax processor A receives the encrypted data of the set size through the stream path described above and sequentially performs the decryption processing. The controller 140 does not manage the end of the syntax processing A here, but performs another processing to perform parallel processing. Next, the process proceeds to step 900. The processing related to the packet data performed in the thread 1 is completed as described above, and the subsequent processing is related to the control processing for performing the parallel processing in the multi-thread.
[0059]
In step 900, the operation state of the thread 2 for continuing the packet data processing performed in the thread 1 by the thread 2 is determined. FIG. 8 shows the configuration of allocation of the controller storage for transferring information between threads in the transfer control between threads. 10, the result of the packet data processing performed in steps 400 to 800 and the processing content information extracted in step 600 are stored in the area of address A. Thereafter, it is determined whether the operation of the thread 2 has been started and the data in the intermediate data area at the address B can be updated. If it can be determined, the contents of address A are copied to the area of address B. If the update is not yet possible, the process waits until the intermediate data area can be updated. When the update is completed, the process proceeds to step 1000.
[0060]
In step 1000, it is notified that the packet data processing in thread 1 has been completed. When notifying, the notification is made by a communication register in the controller 140. FIG. 9 shows how to use the communication register of the packet data processing device TSD of the present development. The use of each bit will be described as appropriate when used in each step. In this step, an inter-thread notification bit of bit 1 is used. In the step 900, since this bit 1 is 0, that is, since the information of the packet that the thread 2 has processed in the previous stage has already been received, and the method of the thread 1 has been copied to the intermediate data area, The bit 1 is changed to 1, that is, the thread 2 can determine that the information notification of the thread 1 is completed. In this way, the thread 2 can continue the processing of the thread 1 only by using the bit 1 without monitoring the operation state of the thread 1. In this processing, the role of the thread 1 in the packet data processing ends, and the process returns to step 400, and the same processing is performed every time a packet is stored.
[0061]
Next, a control method for processing the packet data performed in the above processing by the thread 2 will be described with reference to FIGS. 1, 7, and 10. FIG. The main role of the thread 2 is to perform the packet processing that has been completed in the thread 1, but it is necessary to simultaneously perform the processing of the packet that has arrived up to two packets before the packet being processed in the thread 1. Thus, it is a feature of the present invention to increase the processing speed.
[0062]
FIG. 9 shows a control flow in the thread 2. Thread 2 is divided into four processes according to the processing state while thread 1 has a unique processing order. In step 2050, it is determined which of the four parts is to be activated. The determination method is shown in FIG. In FIG. 10, elliptical terms indicate processing branches case 1 to case 4 in the thread 2. The criterion is determined based on the number of packets being processed by the thread 2 (hereinafter referred to as a packet count) and whether or not bit0 of the communication register, that is, a state of waiting for the arrival of the packet. When the numeral portion described in the branch line indicates the packet count, and when not only the packet count but also the packet arrival waiting is used as the determination condition, it is described in parentheses. In FIG. 10, there is a case where the process proceeds from each case to another case. This branch processing is actually performed by the branch control in step 2050. However, it is described as it is for simplification of the drawing. Hereinafter, the case process in each branch will be described.
[0063]
In step 2050, if there is no packet to be processed by the thread 2 (packet count 0) or if there is one or two packets to be processed but there is no packet currently arrived (if the packet count is 1 or 2 and bit0 = 0) Proceed to case1. In case 1, first, in step 2100, a process of receiving process content information from the thread 1 is performed. In the processing of receiving the processing content information, the data in the intermediate data area in FIG. 8 is copied to the free area at the address C or the address D. Then, the process proceeds to step 2110.
[0064]
In step 2110, a process of notifying that the process information from the thread 1 has been received in step 2100 is performed. By setting bit1 of the communication register of the controller 140 in FIG. 1 to 0, the reception of the processing information of the thread 1 ends, and the thread 1 is notified that the intermediate data can be updated. Then, the process proceeds to step 2120.
[0065]
In step 2120, a process for determining the end of the process activation in the syntax processor A of the thread 1 is performed. This processing can be performed in the thread 1. However, while the syntax processor A in the thread 1 is running, the control of the controller 140 does not need to perform the processing until the processing of the syntax processing A is completed. Is performed in advance, and the efficiency of the packet data processing can be improved when the processing end determination is made after the end of the thread communication. Whether the syntax processing A has been activated in the thread 1 is stored in the processing content information from the thread 1 and can be determined. If the processing of the syntax processing A is not performed, the next step 2130 is skipped. If the processing of the syntax processing A is being performed, the process proceeds to step 2130.
[0066]
In step 2130, the end processing of the syntax processing A performed in the thread 1 is performed. When the syntax processor A has finished, the syntax processor A is reset, and the bit2 of the communication register of the controller 140 is set to 0, thereby performing the termination process. By doing so, it becomes possible to start again when the thread 1 decodes the packet data. Upon completion of the end processing, the flow advances to next step 2140.
[0067]
In step 2140, the packet counter for indicating that the thread 2 has received the packet from the thread 1 is incremented by one. This packet counter serves as an index when a plurality of packet processes are simultaneously performed in the thread 2, and the operation procedure cannot update the data in the stream buffer 130 or the controller storage 150 with the number of packet counters currently being processed. Is used as information on memory management for eliminating the adverse effects of the above. When the updating of the packet counter is completed, the process proceeds to the next step 2150.
[0068]
In step 2150, control for performing stream output by the stream output device is performed. At this stage of the stream output device, since the syntax processor A has performed the decoding process, the conversion to the data format that can be output as a stream has been completed. The controller 140 sets the packets for stream output in an output FIFO (not shown) so that the stream output device outputs the packets in the order set in the output FIFO after a certain delay time from the arrival of the packets.
[0069]
The above is a series of processes of one branch process case1. When this process ends, the process returns to step 2050 again to make a process determination.
[0070]
In step 2050, when the number of packets being processed after the processing of case 1 is one (packet count 1) and when the number of packets being processed is two after the processing of case 3 (packet count 2), the processing branch control of case 2 is performed. move on. The processing of case 2 performs processing up to the start of the processing of the syntax processor B. First, the process proceeds to step 2200.
[0071]
In step 2200, data analysis is performed according to the processing content of the corresponding packet data. In the data analysis, in the case of packet data for AV data, there are cases where a transport stream packet is output as it is, converted into a PES (Packetized Elementary Stream) stream format, and converted into an elementary stream and output. In this case, the data in the stream buffer 130 is analyzed, the head address of the data to be output to the main memory inside the data is described, and the process proceeds to step 2210. If the processing content is PSI data, a setting is made to transfer the packet data to the syntax processor B, and the process proceeds to step 2210.
[0072]
In step 2210, activation of the syntax processor B is controlled. Here, first, bit3 of the communication register of the controller 140 is set to 1, and it is notified that the syntax processor B is to be used. As a result, the use state of the syntax processor B can be monitored by another processing thread, and it is possible to prohibit the illegal execution of control of the syntax processor A by another. In step 2200, if the determined processing content format is an AV packet, a setting is made to store the transferred data in the output buffer area of the stream buffer 130 so that the transferred data can be transferred to the main memory as it is. If the processing format is PSI data, the processing mode is set to match the PSI pattern to be extracted, and the syntax processor B is started. After the startup, the syntax processor B sequentially receives the packet data and performs a process according to the format. During that time, the process returns to step 2050 again to determine the process.
[0073]
In step 2050, when there is only one packet currently being processed but there is no arriving packet (there is no arriving packet at packet count 1), and when the packet currently being processed is 1 after case 1 processing (packet count In the case of 1) and the case where the number of packets currently being processed after the case 5 processing is 2 (packet count 2), the process proceeds to the control of the processing branch of case 3. In the case 3 processing, a result determination processing is performed after the processing of the syntax processor B is completed. First, the process proceeds to step 2300.
[0074]
In step 2300, the processing after the end is performed by the syntax processor B. It waits for the end of the syntax processing B, and after that, resets the syntax processor B and sets bit3 of the communication register of the controller 140 to 0. As a result, when the case 2 is started, the syntax processor B is made usable. Thereafter, the process returns to step 2050 again to determine the processing.
[0075]
In step 2050, if the number of packets currently being processed after case 2 processing is 2 (packet count 2), or if the number of packets currently being processed after case 1 processing is 1 (packet count 1), case 4 The process proceeds to the branching process.
[0076]
In step 2400, processing up to activation of the main memory output device 210 is performed. When arriving at step 2400, the data formed into the main memory output data after the processing up to step 2300 has been completed is always stored in one area of the stream buffer 130. First, the controller 140 issues a start command to the main memory output unit 210 to transfer the start address of the molding data stored in the stream buffer 130 to the output to the main memory.
Upon receiving the start command, the main memory output unit 210 sequentially stores data from the head address of the stored data at the address of the main memory set by the TD2 controller 230. In the meantime, after the main memory is activated, the controller 140 returns to step 2050 again to determine the processing.
[0077]
In step 2050, if the number of packets currently being processed is 2, the current packet is also arriving (bit 0 = 1 in the packet count 2), or if the packet to be processed is 3 after case 1 processing. In this case (when the packet count is 3), or when the current packet to be processed is 1 after the case 4 processing (when the packet count is 1), the process proceeds to the case 5 branch processing.
[0078]
In step 2500, the processing after the main memory output device 210 is completed is performed. The main memory output unit 210 started in the step 2400 monitors the completion of the transfer of the molding data of a predetermined number of bytes to the main memory, and when the transfer is completed, clears the transfer instruction of the main memory output unit B and Set bit4 of the communication register to 0. As a result, the main memory output device A can be used at the time of the start of case4. Thereafter, the process returns to step 2050 again to determine the processing.
[0079]
As described above, the process in the thread 2 is a control method of switching the packet processing order according to the packet data input status from the thread 1 and the possession time of the syntax processor A and the main memory processor activated in the thread 2. Take. FIG. 11 shows the relationship between the flow of packet data and the time when the processing is performed as described above.
[0080]
In FIG. 11, TIN1 to TIN4 in the upper row show a case where four inputs to the input device 105 of FIG. 1 are simultaneously input. The next stage shows the operation timing of the processor controlled by the controller 140 in FIG. 1, and from the top, a packet selector, a syntax processor A, a syntax processor B, a main memory output device, Indicates activation of the stream output device. The next stage shows the timing of notification of the thread of the communication bit 1 in FIG. The next stage shows the input count of the packet count and the count number according to the processing state shown in the flow of FIG. As described in the embodiment described above, the packet storage management, the packet selector and the syntax processor A are controlled by the thread 1, and the syntax processor B, the main memory output device, and the stream output device are controlled by the thread 2. By performing the notification of the thread, the processing can be realized by a three-stage pipeline as shown in FIG. In FIG. 11, if four streams are input of a transport stream packet of 35 Mbps and the packet data processing device of the present invention operates at a clock of 200 MHz, the processing time of one packet indicated by PtA in FIG. The processing can be performed by the degree. For comparison, FIG. 12 shows a processing diagram when a packet data processing device having a similar configuration is used and the control of the present invention is not used. In this case, the processing of the next packet is started after a series of processing as shown in FIG. 11 is completed, so that the pipeline interval PtB is three times as large as PtA in FIG. Then, PTb requires a period of about 30 us. This means that the processing performance which can be processed by using buffers of the same scale is reduced to 1/3. According to another idea, if an attempt is made to configure a packet data processing apparatus having the same processing performance, a triple buffer must be prepared to absorb the deterioration of 1/3 of the processing, and the circuit scale increases. Leads to. That is, in the packet data processing method of the present invention configured as shown in FIG. 11, it is possible to process a plurality of packets at the same time, and to shorten the time to be stored in the stream buffer by performing the processing in the shortest time. Thus, packet data processing can be realized with a very small buffer.
[0081]
【The invention's effect】
In a packet data processing device used in a digital broadcast receiver, etc., when performing various processes on digital content and simultaneously processing a plurality of streams, storing packets in one packet data processing device Thus, the problem that a circuit as in the conventional example is required for a plurality of streams can be solved, and the problem that the circuit scale increases drastically can be solved.
[0082]
Further, in the case of a pipeline in which the processing is constant as in the conventional example, the processing of each processor is compared with the method of sequentially shifting to the next processing every time the processing of the preceding stage is completed, despite the different waiting time. A packet data processing apparatus having the highest performance can be realized by a control method of determining the next processing content according to time.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a packet data processing device according to a first embodiment of the present invention.
FIG. 2 is a detailed processing diagram of a stream processor in FIG. 1;
FIG. 3 is a correlation diagram between packet data input / output and time in the second embodiment;
FIG. 4 is a timing chart of switching a thread in a normal state of the controller 140 in FIG. 1;
FIG. 5 is an allocation diagram of control target processors in each thread in the controller 140 according to the first embodiment of the present invention.
FIG. 6 is a control flow diagram of thread 1 in controller 140 according to the first embodiment of the present invention.
FIG. 7 is a control flow chart of a thread 2 in the controller 140 according to the first embodiment of the present invention.
FIG. 8 is a diagram showing a communication method of information notified between threads in the controller 140 according to the first embodiment of the present invention.
FIG. 9 is a diagram showing information of a communication register in the controller 140 according to the first embodiment of the present invention.
FIG. 10 is a processing state transition diagram of the thread 2 in the controller 140 according to the first embodiment of the present invention.
FIG. 11 is a diagram showing a processing flow of the packet data processing device according to the first embodiment of the present invention.
FIG. 12 is a diagram showing a processing flow when dynamic control is not performed in the present invention.
FIG. 13 is a configuration diagram of a conventional packet processing device.
FIG. 14 is a correlation diagram between processing data and time in a conventional packet processing apparatus.
[Explanation of symbols]
105 Input unit
110 Arbitrator
120 Data transfer control unit
130 stream buffer
140 controller
150 Controller memory
160 packet selector
180 Syntax Processor A
190 Syntax Processor B
200 stream output device
210 Main memory output device
220 main memory
230 TD controller
2001 timer
2002 Addition offset value
2003 Data output unit
2010 data transfer bus
10 Input device
20 Packet selector
30 Syntax Processor A
40 Syntax Processor B
50 Main memory output device
60 stream output device
70 Main memory
80 TD2 controller

Claims (10)

A stream input unit for receiving continuous transport stream data from a plurality of ports simultaneously, a packet selector for extracting desired transport packet data from an input transport stream, and a selected transport packet used in an MPEG system Two or more syntax processors for processing and extracting data into predetermined data, a stream output unit for outputting an input stream while keeping a constant interval between input transport streams, and a syntax processor A main memory output device for outputting digital data to a memory,
To the stream input device, two or more syntax processors, a stream output device, an arbiter for arbitrating the transfer of data to the main memory output device, a stream buffer for storing the input transport stream, and A data transfer controller for controlling data transfer of the
A controller for controlling the packet selector, two or more syntax processors, a stream output device, a main memory output device, an arbitrator, and a data transfer controller; and the controller is the one or more syntax processors. A main memory output device, a stream processing device for storing an instruction code sequence for controlling the stream output device by a pipeline, and a pipeline processing storage device for partially storing contents for performing a pipeline process by the controller. Packet data processing device. Continuous transport stream data used in the MPEG system is simultaneously input from a plurality of ports, desired transport packet data is extracted from the input transport stream by software control, and the selected transport packet data is converted into a predetermined transport packet data. A series of processes in which two or more syntax processes for processing and extracting data are simultaneously performed, an input stream is output while maintaining a constant interval from an input transport stream, and the digital data subjected to the syntax process is output to a memory. A packet data processing apparatus characterized in that packet processing is controlled by a pipeline. 2. The packet data processing apparatus according to claim 1, wherein the controller sequentially processes a specific instruction sequence in accordance with an instruction addressed to the controller recorder. 2. The packet data processing device according to claim 1, wherein the controller comprises two or more threads, and the threads are sequentially switched every specific cycle to control a processor assigned to each thread. 2. The packet data processing device according to claim 1, wherein the controller shares information between two or more threads and operates each thread. The software control by the controller according to claim 2, wherein a process common to the received transport stream packet is controlled by one thread, and a process in which the processing content is determined by the received transport stream packet is another process. A packet data processing device controlled by a thread. 3. The software control by the controller according to claim 2, wherein a packet data selection process sequentially performed in the packet data process, a syntax process for decrypting the broadcast encryption, a syntax process for analyzing data of the selected packet data, and a main memory. The packet data selection processing of the packet stored immediately before in the packet data processing device and the decryption processing of the broadcast cipher are set as the first stage processing in the series of the main memory output processing to be output to the The second stage is a syntax process for analyzing data of a packet stored in the first stage, and the third stage is a process for outputting a main memory of a packet stored three times before to a main memory. A packet data processing apparatus characterized by improving processing performance by performing processing. The software control by the controller according to claim 2 counts the number of packets being processed, counts the number of packets, and processes the plurality of syntax processors and the main memory output device according to claim 1. A packet data processing device that determines the next processing content according to a situation. In the packet data processing based on the packet count according to claim 8, when a packet is not input, it is determined that data being processed is being processed in the packet data processing apparatus, and a partial pipeline is changed. A packet data processing apparatus for performing packet processing during processing. 3. The software control by the controller according to claim 2, wherein the amount of processing operation is large during the processing with a large amount of processing according to the amount of processing of syntax processing and main memory output processing of a plurality of packets being processed. A packet data processing apparatus characterized in that overall processing performance is improved by simultaneously performing processes having a small size.

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