JP2004241019A - Semiconductor memory device and its data input and output method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can relieve defects without inhibiting high speed, and also provide a method for controlling the device. <P>SOLUTION: A memory cell line 21 in which data are stored with a data storage area comprising successive memory cells of prescribed plurality of N-bits as a unit, a redundancy memory cell set having areas 22, 23 and 24 which store preliminary data of N-bits, reference information and a flag, respectively, and input/output control circuits 33 to 35 are provided. The input/output circuits 33 to 35 maintain the approval for the input/output of the data to the specific data storage area if a prescribed flag area 24 is not flagged when they get access to the memory cell line 21. If the prescribed area is flagged, they prohibit the input/output of the data to a specific data storage area based on the reference information in the area 23, and permit the input/output of the data to the preliminary data storage area 22 in place of the specific data storage area. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device capable of replacing data stored in a specific data storage area constituting a memory cell array with spare data and outputting the data, and a data input / output method therefor.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the development of semiconductor fine processing technology, a large capacity of a semiconductor memory has been remarkably advanced. However, on the other hand, a signal generated from a fine memory cell is extremely weak, and the probability that a cell defect occurs due to a variation in a manufacturing process, dust, or the like is increasing.
Various redundancy techniques have been proposed to remedy such defects afterwards, but most of them replace defective cells with spare redundancy cells in units of word lines or bit lines. It is difficult to replace a large number of randomly generated cell defects due to the area constraint occupied by the.
[0003]
On the other hand, by providing a set of a redundant cell and a defective address storage cell row for each row address and storing the location of the defective cell in the row in the defective address storage cell row, any cell in the row can be stored. A method of electrically replacing has been proposed (for example, see Patent Document 1).
[0004]
FIG. 4 shows a semiconductor memory device having a structure for electrically replacing an arbitrary cell in a row.
The semiconductor memory device illustrated in FIG. 4 includes a memory array 100 for storing normal data, a redundant memory cell array 102, an address cell array 103, and a 1-bit wide flag cell array 104. Here, if the "column" is defined as a memory cell group of one column, the redundant memory cell array 102 has a predetermined number of columns for storing data for each row of the memory cell array. In Patent Literature 1, the case where the number of columns is one and the case where the number of columns is four are exemplified. The address cell array 103 stores which address of the memory cell array the data stored in the redundant memory cell array 102 corresponds to. When the number of columns of the redundant memory cell array 102 is 1, the number of bits that can describe the same number of columns as the memory cell array 102 is required for the address cell array 103. For example, when the number of columns of the memory cell array is 512, the number of bits in each row of the address cell array 103 is at least 9 bits.
As means for controlling these various cell arrays, a row decoder 131, sense amplifier groups 111, 112, 113 and 114 in a single or array form, an input / output selector 133, and an address comparison circuit 134 are provided. Further, a column decoder (not shown), various driving circuits for driving word lines, sense amplifiers, and the like, a power supply circuit, and the like are also required.
[0005]
An example of a method for relieving random defective cells that can be implemented in the memory device having such a configuration is as follows.
When a defective cell 110 exists in the memory array 100, the column address is stored in advance in the defective address storage cell row 123 in the same row, and further, for example, “1” is stored in the flag storage cell 124 in the same row. Is done. On the other hand, when there is no defective cell in the row, “0” is stored in the flag.
Here, when a row is selected by the row decoder 131 and a corresponding word line is accessed, data from the memory cell row 121 connected to the word line is read out to the sense amplifier group 111. At this time, data, addresses, and the like are simultaneously read out from the redundancy cell 122, the defective address storage cell row 123, and the flag storage cell 124 by the sense amplifiers 112, 113, and 114, respectively.
Next, when an attempt is made to access data in the sense amplifier 111 in accordance with a column address input from the outside, the input column address is used by the address comparison circuit 134 to determine the defective cell read to the sense amplifier 113. Compared to the address. If they do not match or the flag in the flag storage cell 124 is “0”, the input / output data bus is connected to the normal sense amplifier by the input / output selector 133. An input / output data bus is connected to a sense amplifier connected to a column corresponding to an input address in the sense amplifier group 111 via a column switch (not shown). On the other hand, if the input column address matches the address of the defective cell and the flag is “1”, the input / output data bus is connected to the sense amplifier 112 corresponding to the redundant cell by the input / output selector 133. .
[0006]
By using the above method, random point defect data can be stored in the redundancy cell 122 for each row address in a cell unit, and the stored data can be used in response to an external access so that a large number of random point defects can be stored. Can be rescued.
Such a method for repairing a defective cell enables access at a much higher speed than that for repairing a defect by error correction. In particular, a ferroelectric memory in which the memory cell is non-volatile, a high-speed flash memory, a memory using a magnetic resistance, and the like. It is effective for
[0007]
[Patent Document 1]
JP-A-11-120788
[0008]
[Problems to be solved by the invention]
According to the technique described in Patent Document 1, random point defect data is stored in the redundant cell 122 in units of cells. Therefore, when a plurality of random defective cells exist in the same row, cells in different locations are used. Data will be mixed in the same redundant cell array. Therefore, in a semiconductor memory in which data to be output to the data bus is, for example, in units of 8 bits and the number of input / output data pins is 8, normal cell data is read from the original memory cell array 100 in one accessed data unit. The cell data read out from the redundant cell array corresponding to the defective cell data is mixed in the read cell data. In order to align such one data unit and discharge it to the data bus, the control of the input / output selector 133 and the column switch circuit (not shown) becomes complicated, and the circuit scale thereof becomes large. As a result, there is a disadvantage that the data input / output speed decreases and high-speed access becomes impossible.
[0009]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having a configuration capable of repairing a defect without impairing high-speed performance, and a control method thereof.
[0010]
[Means for Solving the Problems]
The first semiconductor memory device according to the present invention includes a memory cell row in which data is stored in units of a data storage area composed of a predetermined plurality of N-bit continuous memory cells, N-bit spare data, The reference information corresponding to the data storage area, and the redundant memory cell set having an area for storing the input / output permission flag for the spare data, and the input / output permission flag is set when the memory cell row is accessed. When not standing in the flag area of the redundant memory cell set, the data input / output permission to the specific data storage area is maintained. When the input / output permission flag is set, the data input / output permission is performed based on the reference information. Data input / output to / from a specific data storage area is prohibited, and the storage area of the spare data is replaced with the specific data storage area. Having a output control circuit that allows input and output of data to.
[0011]
Preferably, the flag area includes a plurality of memory cells.
Preferably, when the number of memory cells constituting the flag area is M (M: an integer of 2 or more), ^M The input / output permission is performed when any one of the different flag values stands in the flag area. In this case, more preferably, the flag area is initialized by a second flag value obtained by inverting all bits of the first flag value.
[0012]
Preferably, a plurality of data buses are connected to the input / output control circuit to simultaneously output a plurality of the N-bit data, and an identification value of the specific data bus is used as the reference information in the redundant memory cell set. When the flag value of the flag area indicates the input / output permission, the input / output control circuit stores data from the specific data storage area uniquely determined in correspondence with the identification value of the data bus. And the connection destination of the spare data input / output path is allocated in the plurality of data buses.
[0013]
A data input / output method of a semiconductor memory device according to the present invention includes a memory cell row in which data is stored in units of a data storage area composed of a predetermined plurality of N-bit continuous memory cells, an N-bit spare data, A data input / output method for a semiconductor memory device comprising: a reference information corresponding to the data storage area; and a redundant memory cell set including an area for storing an input / output permission flag for the spare data. When the input / output permission flag does not stand in the flag area of the redundant memory cell set when accessing the memory cell row, the input / output permission of data in units of the N bits with respect to the specific data storage area is maintained. However, when the input / output permission flag is on, the specific data storage area is Prohibits the input and output of data, to allow input and output of data in units of the N bits for storage areas of the preliminary data in place of the specific data storage area.
[0014]
In the semiconductor memory device of the present invention, data is stored in a memory cell row in units of a predetermined plurality of N bits. Each memory cell row portion storing the data of the bit number N is called a data storage area. If, for example, a defective cell exists in the memory cell row, the same N-bit data as that written in the data storage area (specific data storage area) including the defective cell is stored in a predetermined area in the redundant memory cell set as spare data. It is stored in advance. The correspondence between the spare data and the data in the memory cell row is stored in advance in a predetermined area of the redundant memory cell set as reference information. As the reference information, for example, the address of the data storage area of the memory cell row in which the same N-bit data as the spare data is written, or the data is read from the data storage area, or the data is written to the data storage area The identification value of the data bus. In addition, a flag for input / output permission of spare data is stored in advance in a flag area of the redundant memory cell set.
[0015]
In the data output of the semiconductor memory device of the present invention, when accessing the memory cell row, a flag for input / output permission of spare data is checked, and if the flag value indicates input / output permission, it is determined based on reference information. Data input / output from a specific data storage area is prohibited, and spare data is output in place of the specific data storage area. On the other hand, when the input / output permission flag is not set, data input / output permission for a specific data storage area is maintained.
Incidentally, in the semiconductor memory device of the present invention, these data outputs are controlled by an input / output control circuit. The input / output control circuit treats data for each of a plurality of N bits as one unit, and does not perform control for replacing a specific bit in the N-bit data.
[0016]
If the flag is composed of a plurality of bits in the above configuration, the numerical distance between the value of the permission of the preliminary data output and the value of the non-permission can be increased. For example, when the flag has two bits, the input / output permission flag value (first flag value) is set to, for example, “11”, and the initial setting value (second flag value) of the flag value indicating non-permission is set to “11”. 11 is set to "00", which is the farthest bit distance. In this case, since the existence probability of the data storage area including the defective cell and the data storage area not including the defective cell is normally occupied mostly by the latter normal one, most flag values are initially set. The second flag value “11” at the time of setting is taken. At this time, if any one bit of the second flag value “11” becomes defective and becomes “01” or “10” erroneously, the determination remains output disabled. Misjudgment occurs only when both bits are defective. In the point defect occurrence mode of the memory, such a defect of consecutive bits is extremely rare. Therefore, in the present invention, the probability of erroneous determination of permission / non-permission of preliminary data output is extremely small.
[0017]
On the other hand, when the reference information in the redundant memory cell set is the identification value of the data bus, the input / output control circuit responds to the identification value of the data bus when the flag value of the flag area indicates the input / output permission. An input / output path for data from a specific data storage area which is uniquely determined is separated, and a connection destination of the input / output path for spare data is allocated in a plurality of data buses. This control enables so-called burst transfer.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
[First Embodiment]
FIG. 1 is a block diagram showing a configuration of the semiconductor memory device according to the first embodiment of the present invention.
In the memory cell array 2 of the semiconductor memory device illustrated in FIG. 1, for example, data is stored in units of 8 bits in each row. In each row, for example, 64 storage areas (data storage areas) for the 8-bit data are arranged. The columns of the memory cell array 2 in the 8-bit data storage area are hereinafter simply referred to as “columns”. The address of the alum is referred to as a “column address”.
[0019]
The semiconductor memory device has a spare memory cell array for storing redundant spare data, a column address and a flag. Here, the column addresses stored in the spare memory cell array constitute an embodiment of the "reference information" of the present invention. The spare memory cell array has a spare data storage area 2 in which one row has 8 bits, a reference information storage area 3 in which one row has 6 bits, and a flag area 4 in which one row stores a flag of 4 bits. In the present embodiment, the number of bits of the flag may be plural, but the case of 4 bits is exemplified here. Each cell of the spare data storage area 2, the reference information storage area 3, and the flag area 4 has the same configuration as the memory cell.
[0020]
A row decoder 31 for simultaneously selecting each row of the memory cell array 1 and the spare memory cell array is connected to each word line (not shown) of the memory cell array 1.
Further, the memory cell array 1 is connected to a sense amplifier array 11 which is connected to each bit line (not shown) and includes sense amplifiers for detecting stored data. A sense amplifier array 12 connected to a bit line of the spare data storage area 2 and configured by a sense amplifier for detecting spare data stored in the spare data storage area 2 is connected to the spare data storage area 2. A sense amplifier array 13 that is connected to the bit line of the reference information storage area 3 and includes a sense amplifier that detects the reference information stored in the reference information storage area 3 is connected to the reference information storage area 3.
A sense amplifier array 14, which is connected to the bit lines of the flag area 4 and includes a sense amplifier for detecting a flag value, is connected to the flag area 4.
[0021]
The semiconductor memory device shown in FIG. 1 further includes a column switch circuit 32, an input / output selector 33, a comparator 34, and a latch circuit 35. The column switch circuit 32, the input / output selector 33, the comparator 34, and the latch circuit 35 constitute an embodiment of the "input / output control circuit" of the present invention.
The latch circuit 35 temporarily stores a column address input from the outside (hereinafter, referred to as an input address). The comparator 34 compares the input address held in the latch circuit 35 with reference information detected by the sense amplifier array 13 while referring to the flag value detected by the sense amplifier array 14.
On the other hand, the column switch circuit 32 selects a column for one data (8 bits) in the memory cell array according to the input address output from the latch circuit 35. The input / output selector 33 includes 8-bit data (hereinafter referred to as column data) selected and output by the column switch circuit 32 and one column data (hereinafter referred to as spare column data) of a spare data storage area output from the sense amplifier array 12. ) And outputs it to the 8-bit data bus 36. As described above, the input / output selector 33 selects the column data to be output based on the comparison result from the comparator 34.
[0022]
Next, the operation of the semiconductor memory device configured as described above will be described by taking a case of reading data as an example. Although there is a difference that the flow of data is opposite to that at the time of reading at the time of data writing, the replacement process of the column to be accessed is common to that at the time of reading, and therefore the description is omitted here.
When a defective cell 10 exists in the memory array 1, its column address is stored in advance as reference information in a reference information storage cell row in the reference information storage area 3 on the same row. Further, a first flag value indicating permission of input / output of spare data, for example, “1111” is stored in the flag cell 24 in the same row. On the other hand, when there is no defective cell in the same row, the flag cell 24 stores an initial setting value (second flag value) of a flag value indicating that input / output of spare data is not permitted, for example, “0000”.
These processes are executed, for example, at the time of shipment of an IC or at the time of a function test performed periodically.
[0023]
At the time of data reading, when a row is selected by the row decoder 31 and a corresponding word line is accessed, data from the memory cell row 21 connected to the word line is read to the sense amplifier array 11. At the same time, data, addresses and flags are also read from the 8-bit redundant cell 22, the 6-bit reference information storing cell row 23, and the 4-bit flag storing cell row 24, respectively, from the sense amplifier arrays 12 and 13. , 14. The 8-bit redundant cell 22, the 6-bit reference information storing cell row 23, and the 4-bit flag storing cell row 24 constitute one redundant memory cell set.
[0024]
Next, data in the sense amplifier array 11 is to be accessed according to an input address input from the outside. At this time, the input address temporarily stored in the latch circuit 35 is compared by the comparator 34 with a reference address (reference information) of a data storage area including a defective cell that has been read out to the sense amplifier array 13. . If the two do not match or the flag read by the sense amplifier array 14 is other than “1111”, the 8-bit input / output data bus 36 is connected to the normal sense amplifier by the input / output selector 33. That is, the input / output data bus 36 is connected to the 8-bit sense amplifier connected to the column corresponding to the input address in the sense amplifier array 11 via the column switch circuit 32. On the other hand, if they match and the flag is “1111”, the input / output data bus 36 is connected to the 8-bit sense amplifier array 12 corresponding to the redundant cell by the input / output selector 33.
[0025]
As described above, if the flag is composed of four bits and the redundant cell 22 is used only when the specific value is "1111", three bits out of the four bits of the flag are defective. Even if "0111" is output, the cell in the memory cell array is not erroneously selected in place of the redundant cell 22. Further, even if two bits out of the four bits of the flag are defective, for example, “1100”, “1010”, “1001”, “0110”, “0101”, and “0011” are output, instead of the redundant cell 22, A cell in the memory cell array 1 is not erroneously selected. The occurrence of these consecutive defective cells is usually very rare. Further, even if one of the four bits is defective and "1110", "1101", "1011", or "0111" is output, a cell in the memory cell array 1 is erroneously selected instead of the redundant cell 22. There is no.
[0026]
On the other hand, assuming that the flag is 1 bit in the same memory cell array configuration as in the present example in which the number of bits of data is 8 and the number of columns is 64, the redundant memory cell set in this case has 8 bits for the spare data, A total of 15 bits are required, 6 bits for the address and 1 bit for the flag. In this case, if a defective cell exists in the flag, access to the redundant cell 22 is prohibited, and a cell in the memory cell array 1 is erroneously selected.
Among such defective cells, particularly, a cell which becomes defective due to an increase in leak current or an electrical short with an adjacent cell is a bit having a different bit of “1” and “0” depending on the data read timing and data arrangement. Data is often output irregularly. When the flag has a 1-bit configuration, the access target is switched irregularly between the redundant cell and the normal memory cell. As a result, desired data cannot be written or read.
[0027]
On the other hand, in the present embodiment, the probability of occurrence of the malfunction can be reduced by orders of magnitude only by increasing the number M of bits of the flag. As described above, the non-permission of the spare data input / output (redundancy replacement) is maintained up to the random error of (M-1) bits. In the above example, the number of bits of the redundant memory cell set is increased to a total of 18 bits as the number of bits of the flag is changed from 1 bit to 4 bits, but the rate of increase in area in the entire array is small. In addition, the input / output control circuit controls a plurality of N bits (8 bits in the above example) as one set of data, and does not perform bit-by-bit replacement as in the conventional case, so that the operation speed is remarkably improved. There is a great advantage that the configuration can be simplified.
[0028]
Hereinafter, second and third embodiments in which the access speed is further improved will be described. In these embodiments, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
[0029]
[Second embodiment]
FIG. 2 is a block diagram showing a configuration of the semiconductor memory device according to the second embodiment.
In the above-described first embodiment, columns are defined so that eight adjacent cells corresponding to the 8-bit input / output data bus 36 are defined as one row, and memory cells are grouped for each column.
[0030]
In the second embodiment, when the number of input / output data buses is eight, the same number of data groups as the number of data buses in the memory cell array 1B (data of eight columns in the first embodiment). Are defined as one column in which memory cells can be input / output collectively. That is, in the present embodiment, one row of columns is composed of 64 (= 8 × 8) memory cells. Similarly to the data replacement unit of the memory cell array 1B, the number of bits in each row of the spare data storage area 2B is also 64 bits. The reference information storage area 3B includes eight data buses B (hereinafter, referred to as defective data buses) corresponding to one column including the defective cell 10B. ₁₁ ~ B ₁₈ Is stored. In the second and third embodiments, the identification information of the defective data bus constitutes the embodiment of the “reference information” of the present invention. In the example of FIG. 2, the data bus B corresponding to the fourth column including the defective cell 10B ₁₄ Becomes a defective data bus. When the number of input / output data buses is eight, each row of the reference information storage area 3B is composed of three bits. As in the first embodiment, each row of the flag area 4 is composed of a plurality of M bits, for example, 4 bits.
[0031]
The input / output selector 37B is connected to the sense amplifier array 11 via a regular data column switch circuit 32B. Further, an input / output selector 37B is connected to the sense amplifier array 12B via a column switch circuit 32R for spare data. The input / output selector 37B and the column switch circuits 32B and 32R of this example are composed of 64 sense amplifier groups and an input / output data bus B for each column. ₂₁ ~ B ₂₈ Controls connection and disconnection with. The input / output selector 37B and the column switch circuits 32B, 32R constitute an embodiment of the "input / output control circuit" of the present invention.
[0032]
More specifically, when input / output is permitted by the flag value read to the sense amplifier array 14, the input / output selector 37B of the present example outputs the defective data bus B read from the sense amplifier array 13B. ₁₄ Data bus B according to the identification value of ₁₄ To the input / output data bus B ₂₁ ~ B ₂₈ And a spare data bus B connected to the spare switching circuit 32R instead. _R To the input / output data bus B ₂₁ ~ B ₂₈ Connect with one of Data bus B ₁₁ ~ B ₁₈ And B _R Are usually referred to as internal buses, and correspond to specific examples of “data input / output path” in the present invention.
[0033]
When the defective cell 10B exists in the memory array 1B, a 3-bit value for identifying the defective data bus is stored in advance in the same row of the reference information storage cell row 23B, and further, the same row of the flag storage cell row 23B. For example, “1111” is stored in 24B. On the other hand, if there is no defective cell in the same row, “0000” is stored as an initial value in the flag storage cell row 24B.
[0034]
At the time of data input / output, when a row is selected by the row decoder 31 and a corresponding word line is accessed, data from the memory cell row 21B connected to the word line is read out to the sense amplifier array 11. At this time, the spare data and the like are simultaneously transferred to the sense amplifier arrays 12B, 13B, and 14B from the 64-bit redundant cell row 22B, the 3-bit reference information storage cell row 23B, and the 4-bit flag storage cell row 24B. Is read.
[0035]
If the flag called by the sense amplifier array 14B is “1111”, the input / output selector 37B shifts the connection state of the data bus, for example, according to the identification value of the defective data bus read by the sense amplifier array 13B. Then, the defective data bus is disconnected from the input / output data bus side. In this example, the data bus B ₁₄ Is an internal bus corresponding to the column including the defective cell 10B, and if this is identified as a defective data bus, the data bus B ₁₁ , B ₁₂ , B _Thirteen Are the input / output data bus B ₂₁ , B ₂₂ , B ₂₃ And data bus B _Fifteen ~ B ₁₈ And spare data bus B _R Are the input / output data bus B ₂₄ ~ B ₂₈ Connected to.
[0036]
On the other hand, if the flag value called by the sense amplifier array 14 is other than "1111", the data bus connection shift is not performed by the input / output selector 37B, and each data bus B is not shifted. ₁₁ ~ B ₁₈ Is the input / output data bus B ₂₁ ~ B ₂₈ Is connected to
[0037]
As a result of the above, when the input / output of spare data is permitted (the flag is “1111”), the input / output path of data to a specific column corresponding to the identification value of the data bus, that is, the defective data bus B ₁₄ On the other hand, input or output of data from the input / output data bus side is prohibited. At the same time, the spare data input / output path, ie, the spare data bus B _R , Input or output of data from the input / output data bus side is permitted.
Therefore, at the time of subsequent reading, the spare data is read from the redundant cell row 22B instead of the data storage area of the selected row of the column including the defective cell 10B.
At the time of writing, predetermined data is written to the redundant cell row 22B instead of the data storage area of the selected row of the column including the defective cell 10B.
[0038]
In the second embodiment, as in the first embodiment, writing or reading is performed by collecting a plurality of N-bit data as one unit, so that the operation speed is improved and the configuration of the input / output control circuit is simplified. Have been.
Also, as a unique advantage of the second embodiment, a high-speed data input / output method called burst transfer is adopted, but when a word line is accessed, the bus connection is set up only once, and thereafter, No extra signal manipulation is done in the column selection of. At this time, since the address is not referred to, it is not necessary to detect a match with the column address including the defective cell every time the column address is changed. After the bus connection is set up according to the data bus identification value, burst transfer can be performed at high speed without being aware of the data input destination and data output destination.
[0039]
Note that, in the above description, as shown in FIG. ₁₄ Internal bus B after (right side in the figure) _Fifteen ~ B ₁₈ Is shifted to the higher order one by one. However, the present invention is not limited to this example. ₁₄ In this example, the vacant input / output data bus B ₂₄ Spare internal bus B _R May be connected.
[0040]
[Third Embodiment]
In the above-described second embodiment, for simplicity of description, a case has been described in which an 8-bit internal data bus corresponding to an 8-bit input / output data bus is provided, but an internal data bus connected to a memory array is provided. (Bus width) does not always need to match the input / output data bus configuration of the chip. In recent years, there has been a tendency to increase the bus width in accordance with the demand for higher speed. For example, even if the number of input / output bits of the chip is 8 bits, the number of bits of the internal bus may be 64 bits.
[0041]
In such a case, the 6-bit column address is divided into upper 3 bits and lower 3 bits. The upper 3 bits are used for selection when connecting the sense amplifier to the 64-bit internal bus, and the lower 3 bits are 64 bits. Is used to select an 8-bit input / output data bus from the internal bus.
[0042]
Hereinafter, the third embodiment will be described using the above example.
FIG. 3 is a block diagram showing a configuration of the semiconductor memory device according to the third embodiment.
[0043]
In the third embodiment, a spare data storage area 5, a reference information storage area 6, and a flag area 7 are added as a configuration for adding another redundant memory cell set.
[0044]
In this example, as in the first embodiment, 8-bit cells are grouped and arranged for each data bus. Accordingly, the replacement unit also has 8 bits corresponding to the one group, and each row of the spare data storage areas 2 and 5 has 8 bits. Each of the reference information storage areas 3 and 6 has 6 bits in order to identify a defective data bus from the 64 data buses. Each of the flag areas 4 and 7 has 4 bits in each row as in the first and second embodiments.
[0045]
When the defective cells 10 and 20 exist in the memory array 1, the 6-bit value for identifying the data bus is previously stored in the reference information storage cell rows 23 and 26 of the same row, and the flag storage of the same row is performed. For example, “1111” is stored in the cell rows 24 and 27 for use. On the other hand, if there is no defective cell in the same row, “0000” is stored in the flag storage cell rows 24 and 27.
[0046]
When a row is selected by the row decoder 31 and a corresponding word line is accessed, data from the memory cell row 21 connected to the word line is read out to the sense amplifier array 11. At the same time, each of the senses to which data and the like correspond from the 8-bit redundant cell rows 22 and 25, the 6-bit reference information storing cell rows 23 and 26, and the 4-bit flag storing cell rows 24 and 27, respectively. Read to the amplifier array.
[0047]
If the flag value read to the sense amplifier array 14 or 17 is “1111”, the first selector circuit 37C of this example uses the bus identification value as reference information read to the sense amplifier array 13 or 16. , The connection state of the data bus is shifted in accordance with, and the defective data bus is disconnected from the input / output data bus. Further, the first selector circuit 37C includes a spare data bus B connected to the column switch circuits 32R and 32L. _R , B _L Is connected to an input / output data bus as appropriate.
For example, two data buses B ₁₀₃ , B ₁₆₂ Is identified as a defective data bus, the spare data bus B _L , Data bus B ₁₀₁ And B ₁₀₂ Is the input / output data bus B ₂₀₁ ~ B ₂₀₃ And data bus B ₁₀₄ ~ B ₁₆₁ Is the input / output data bus B ₂₀₄ ~ B ₂₆₁ And data bus B ₁₆₃ , B ₁₆₄ And spare data bus B _R Is the input / output data bus B ₂₆₂ ~ B ₂₆₄ Connected to each other.
[0048]
On the other hand, if the flag values read to the sense amplifier arrays 14 and 17 are both other than "1111", the connection shift by the first selector circuit 37C is not performed, and the spare data bus B _R , B _L Are disconnected from the first selector circuit 37C, and each data bus B ₁₀₁ ~ B ₁₆₄ Is the input / output data bus B ₂₀₁ ~ B ₂₆₄ And the connected state is maintained.
[0049]
Next, a sense amplifier is selected by the column switch circuit 32C one bit at a time from the sense amplifier array 11 for each column in the sense amplifier array 11 in accordance with the upper three bits of the column address input from the outside. ₁₀₁ ~ B ₁₆₄ Connected to.
Further, each one bit corresponding to the column address input from the sense amplifier arrays 12 and 15 corresponding to the redundant cell is used as the spare data bus B. _R , B _L Connected to.
[0050]
In this way, each of the appropriate data has 64 input / output data buses B ₂₀₁ ~ B ₂₆₄ Input and output. Of these, eight buses corresponding to the lower three bits of the column address are selected by the second column switch circuit 38 and connected to the 8-bit input / output data bus 36C.
[0051]
In this example, each redundant memory cell set is composed of a total of 18 bits of 8 bits for data, 6 bits for address, and 4 bits for flag, and two sets are provided. As a result, it is possible to remedy two defects independent of the 256-bit cell row for each word line.
[0052]
Note that the defect remedy methods of the first to third embodiments may be used in combination with a normal word line or bit line unit redundancy method. Can significantly improve the production yield.
Further, for example, a test can be performed at the time of starting the system, a defective cell can be detected on the spot, and a redundant cell can be set. In this case, the present invention can be applied to a volatile memory.
[0053]
The first to third embodiments have the following effects.
In a configuration in which input / output of data to / from a memory cell is controlled in units of a data storage area including a plurality of N bits, replacement processing of defect repair data is also performed in units of the plurality of N bits. This simplifies the configuration and control of the input / output control circuit, and enables high-speed access.
[0054]
In order to prevent erroneous selection due to a defect in the flag storage cell row, a plurality of bits are used in the flag storage cell row, and a redundant cell is used only when it has a specific value.
When the redundant memory cell set is not used, the bit inversion value of the specific value is previously written in the flag storage cell row.
Therefore, even if there is a defective cell in the flag storage cell row, a redundant cell is not erroneously selected if at least one bit in the multiple-bit flag value is normal. Therefore, the above-mentioned fatal defects can be dramatically reduced.
[0055]
Further, in the second and third embodiments, in order to improve the speed of the burst transfer, the connection state of the circuit is changed based on the defective address read by the sense amplifier, and the redundancy can be directly performed without address comparison. Provide a mechanism.
Specifically, the location of the data bus corresponding to the defective cell is recorded in the reference information storage cell row instead of the column address, and access to the defective cell is prohibited by shifting the bus connection based on the data. And access to the redundant cells.
Further, in the second and third embodiments, the address comparison in the column access can be made unnecessary. As a result, it is not necessary to change the circuit state every time the column address changes, and high-speed burst transfer becomes possible. The access performance of the memory can be greatly improved.
[0056]
【The invention's effect】
According to the semiconductor memory device and the control method thereof of the present invention, it is possible to perform defect repair suitable for data input / output in a unit of a plurality of bits, and therefore, the data input / output speed of the memory can be reduced. Does not inhibit. As a result, defect relief suitable for a high-speed memory can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a semiconductor memory device according to a first embodiment.
FIG. 2 is a block diagram showing a configuration of a semiconductor memory device according to a second embodiment.
FIG. 3 is a block diagram showing a configuration of a semiconductor memory device according to a third embodiment.
FIG. 4 is a block diagram of a conventional semiconductor memory device having a configuration for electrically replacing an arbitrary cell in a row.
[Explanation of symbols]
1, 1B ... memory cell array, 2, 2B, 5 ... spare data storage area, 3, 3B, 6 ... reference information storage area, 4, 7 ... flag area, 10, 20 ... defective cell, 31 ... row address decoder, 32 , 12 to 17: sense amplifier array, 33, 37, 37B, 37C, 38: input / output selector, 34: comparator, 35: latch circuit.

Claims (10)

A memory cell row in which data is stored in units of a data storage area composed of a predetermined plurality of N-bit continuous memory cells;
A redundant memory cell set having an area for storing N-bit spare data, reference information corresponding to the specific data storage area, and an input / output permission flag for the spare data;
When the input / output permission flag does not stand in the flag area of the redundant memory cell set when accessing the memory cell row, the data input / output permission for the specific data storage area is maintained, and the input / output permission is maintained. Is set, the input / output of data to / from the specific data storage area is prohibited based on the reference information, and the input / output of data to / from the spare data storage area is performed instead of the specific data storage area. A semiconductor memory device comprising: an input / output control circuit that permits output. 2. The semiconductor memory device according to claim 1, wherein said flag area is composed of a plurality of memory cells. Assuming that the number of memory cells constituting the flag area is M (M: an integer of 2 or more), any one of the 2 ^M different flag values will cause the first flag value to stand in the flag area. 3. The semiconductor memory device according to claim 2, wherein said input / output permission is performed when said device is in operation. 4. The semiconductor memory device according to claim 3, wherein said flag area is initialized by a second flag value obtained by inverting all bits of said first flag value. A plurality of data buses are connected to the input / output control circuit to simultaneously output the plurality of N-bit data,
The identification value of the specific data bus is stored in the redundant memory cell set as the reference information,
When the flag value of the flag area indicates the input / output permission, the input / output control circuit sets an input / output path for data from the specific data storage area that is uniquely determined according to the identification value of the data bus. 2. The semiconductor memory device according to claim 1, wherein the connection destination of the input / output path of the spare data is allocated in the plurality of data buses. A memory cell row in which data is stored in units of a data storage area composed of a predetermined plurality of N-bit continuous memory cells, N-bit spare data, reference information corresponding to the specific data storage area, and A redundant memory cell set including an area for storing an input / output permission flag for data, and a data input / output method for a semiconductor memory device, comprising:
When the input / output permission flag does not stand in the flag area of the redundant memory cell set when accessing the memory cell row, the input / output permission of the data in units of the N bits with respect to the specific data storage area is performed. When the input / output permission flag is set, input / output of data from / to the specific data storage area is prohibited based on the reference information, and the spare data is replaced in place of the specific data storage area. A data input / output method for a semiconductor memory device which permits input / output of data in units of N bits to / from the storage area of the memory device. 7. The data input / output method for a semiconductor memory device according to claim 6, wherein said flag area is composed of a plurality of memory cells. Assuming that the number of memory cells constituting the flag area is M (M: an integer of 2 or more), any one of the 2 ^M different flag values will cause the first flag value to stand in the flag area. 8. The data input / output method for a semiconductor memory device according to claim 7, wherein the input / output is permitted when the data is input. 9. The data input / output method for a semiconductor memory device according to claim 8, wherein said flag area is initialized in advance by a second flag value obtained by inverting all bits of said first flag value. An identification value of a specific data bus among the plurality of data buses for simultaneously outputting the plurality of N-bit data is stored in the redundant memory cell set as the reference information;
When the flag value in the flag area indicates the input / output permission at the time of accessing the memory cell row, an input / output path for data from the specific data storage area uniquely determined in correspondence with the identification value of the data bus. 7. The data input / output method for a semiconductor memory device according to claim 6, wherein a connection destination of the input / output path of the spare data is allocated in the plurality of data buses.

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