JP2004212384A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To independently test a functional block, without enlarging the scale of a testing circuit. <P>SOLUTION: The device is provided with: a scan path, which includes parallel routes between outputs of a logic part 80 and inputs of a functional block 90 and a serial shift route for serially transmitting data, and is equipped with selectors 10, 11, and 12 and flip-flops 30, 31, and 32; and selectors 60, 61, and 62, which are connected to the serial shift route of the scan path, and switch the outputs of the functional block 90 and the serial shift route to be connected to the inputs of a logic part 81. The test data are shifted-in the functional block 90 from an SI (scan in) terminal via the selectors 60, 61, and 62, and the selectors 60, 61, and 62 are switched so as to output the data outputted from the functional block 90. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device including a functional block such as a random access memory (RAM), a logic unit connected to the functional block, and a test circuit for testing them.

  FIG. 21 is a circuit diagram showing a conventional semiconductor integrated circuit device having a scan test function disclosed in Patent Document 1. As shown in FIG. 21, this semiconductor integrated circuit device includes selectors 10, 11, 12 controlled by a shift mode signal SM, flip-flops (FF) 30, 31, 32, and a selector 50 controlled by a test mode signal TEST. , 51, 52, logic units 80, 81, and a RAM 91.

  In FIG. 21, a scan path is constituted by the selectors 10, 11, 12 and the flip-flops 30, 31, 32. The scan path includes a parallel path between an output of the logic unit 80 and an input of the RAM 91 and a storage having a serial shift path for transmitting data from an SI (scan-in) terminal to an SO (scan-out) terminal in series. Circuit.

Next, the operation of the semiconductor integrated circuit device shown in FIG. 21 will be described.
During normal operation, the shift mode signal SM is set to 0 to switch the selectors 10, 11, and 12 to the "0" input terminals, and the test mode signal TEST is set to 0 to set the selectors 50, 51, and 52 to "0". Switch to input end. That is, data output from the logic unit 80 is selected by the selectors 10, 11, 12 and input to the input terminals DI0, DI1, DI2 of the RAM 91 via the flip-flops 30, 31, 32. Here, although not shown, it is assumed that a clock is input to the flip-flops 30, 31, and 32. Data from the output terminals DO0, DO1, DO2 of the RAM 91 are selected by the selectors 50, 51, 52 and transmitted to the logic unit 81. As described above, during the normal operation, the RAM 91 is inserted between the logic units 80 and 81, and data writing and reading are performed.

  When performing a scan test of the logic units 80 and 81, the test mode signal TEST = 1 is set and the selectors 50, 51 and 52 are switched to the “1” input terminals. In this state, the selectors 50, 51, and 52 select and output the data input to the "1" input terminal, so that the RAM 91 is bypassed and the scan path is inserted between the logic unit 80 and the logic unit 81. State. In this state, the scan test of the logic units 80 and 81 is performed by controlling the shift mode signal SM.

  When performing a scan test of the logic unit 81, the shift mode signal SM is set to 1 and the selectors 10, 11, and 12 are switched to the "1" input terminals. Since the selectors 10, 11, and 12 select the data input to the "1" input terminal, when a clock is applied to the flip-flops 30, 31, and 32 three times, the 3-bit test data from the SI terminal is subjected to a serial shift operation. Is stored in the flip-flops 30, 31, and 32. Since the test mode signal TEST = 1, the 3-bit test data stored in the flip-flops 30, 31, and 32 is given to the logic unit 81, and the data output from the logic unit 81 is checked to scan the logic unit 81. The test is performed.

  When performing a scan test of the logic unit 80, the shift mode signal SM is set to 0 and the selectors 10, 11, and 12 are switched to the "0" input terminals. The 3-bit data output from the logic unit 80 that has received test data and performed a predetermined operation is selected by the selectors 10, 11, and 12. When a clock is applied to the flip-flops 30, 31, and 32 once, 3-bit data from the logic unit 80 is stored in the flip-flops 30, 31, and 32, respectively. At this time, the 1-bit data stored in the flip-flop 32 is output to the SO terminal. Next, the shift mode signal SM is set to 1 to switch the selectors 10, 11, and 12 to the "1" input terminal. When a clock is applied twice to the flip-flops 30, 31, and 32, 1-bit data stored in the flip-flops 30 and 31 are serially output to the SO terminal by a serial shift operation, and a scan test of the logic unit 80 is performed. .

  In the semiconductor integrated circuit device shown in FIG. 21, it is possible to set the test data from the SI terminal to the input terminals DI0, DI1, and DI2 of the RAM 91 by the serial shift operation when the shift mode signal SM = 1. , The data output from the output terminals DO0, DO1, DO2 of the RAM 91 are not taken into the flip-flops 30, 31, 32 and read out from the SO terminal, so that the RAM 91 alone cannot be tested.

  FIG. 22 is a circuit diagram showing a conventional semiconductor integrated circuit device having a test function for the RAM 91 alone disclosed in Patent Document 1. In order to execute the test mode of the RAM 91, the selectors 60, 61, and 62 controlled by the output selection signal SELDO and the selectors 70 and 71 controlled by the RAM test signal RAMTEST in the semiconductor integrated circuit device shown in FIG. , 72 are added.

  Here, the data from the output terminals DO0, DO1, and DO2 of the RAM 91 are input to the "1" input terminals of the selectors 60, 61, and 62, respectively, and the test from the SI terminal is input to the "0" input terminal of the selector 60. Data is input, and data from flip-flops 30 and 31 are input to “0” input terminals of selectors 61 and 62, respectively. The data from the flip-flops 30, 31, and 32 are input to the “0” input terminals of the selectors 70, 71, and 72, and the “1” input terminals of the selectors 70, 71, and 72 are input from the SID terminal. RAM test data is input.

Next, the operation of the semiconductor integrated circuit device shown in FIG. 22 will be described.
During normal operation, the shift mode signal SM is set to 0 to switch the selectors 10, 11, and 12 to the "0" input terminals, and the test mode signal TEST is set to 0 to set the selectors 50, 51, and 52 to "0". Switch to the input terminal, set the RAM test signal RAMTEST = 0, and switch the selectors 70, 71, 72 to the "0" input terminal. In this state, data output from the logic unit 80 is input to the input terminals DI0, DI1, and DI2 of the RAM 91 via the flip-flops 30, 31, and 32. Here, it is assumed that a clock is input to the flip-flops 30, 31, and 32. Data from output terminals DO0, DO1, DO2 of RAM 91 is transmitted to logic 81. As described above, during normal operation, the RAM 91 is inserted between the logics 80 and 81, and data writing and reading are performed.

  When performing a scan test of the logic unit 80 and the logic unit 81, the test mode signal TEST = 1 is set, the selectors 50, 51, 52 are switched to the “1” input terminals, and the output selection signal SELDO = 0 is set. Switch the selectors 60, 61, 62 to the "0" input terminal. In this state, the RAM 91 is bypassed, and a scan path is inserted between the logic unit 80 and the logic unit 81. In this state, similarly to the semiconductor integrated circuit device shown in FIG. 21, a scan test is performed on the logic unit 80 and the logic unit 81 by controlling the shift mode signal SM.

  When testing the RAM 91, the RAM test signal RAMTEST = 1 is set, the selectors 70, 71, 72 are switched to the "1" input terminals, and the RAM test data from the SID terminal is supplied as write data to the RAM 91. Here, 1-bit RAM test data is commonly supplied to the RAM 91 as 3-bit write data. That is, "000" or "111" can be instantaneously given as write data to the RAM 91.

  The selectors 60, 61, and 62 controlled by the output selection signal SELDO are for taking in data of test results from the output terminals DO0 to DO2 of the RAM 91 into a scan path. Setting the output selection signal SELDO = 1 to switch the selectors 60, 61, 62 to the "1" input terminal, setting the shift mode signal SM = 1 to switch the selectors 10, 11, 12 to the "1" input terminal, When a clock is applied once to the flip-flops 30, 31, and 32, data of test results from the output terminals DO0 to DO2 of the RAM 91 are stored in the flip-flops 30, 31, and 32. At this time, the 1-bit data stored in the flip-flop 32 is output to the SO terminal. Next, when the output selection signal SELDO is set to 0 and the selectors 60, 61, 62 are switched to the "0" input terminals, and the clocks are applied to the flip-flops 30, 31, 32 twice, the clocks are stored in the flip-flops 30, 31. The 1-bit data is read from the SO terminal by a serial shift operation, and a failure determination is performed by a test device outside the chip or a self-test circuit inside the chip.

JP-A-10-73641 (paragraph numbers 0018 to 0039, FIGS. 1 and 4)

  Since the conventional semiconductor integrated circuit device is configured as described above, the circuit shown in FIG. 21 has a problem that it is not possible to test the functional blocks such as the RAM 91 alone. Further, the circuit shown in FIG. 22 has a problem that the scale of a test circuit of a functional block such as the RAM 91 becomes large.

  The present invention has been made to solve the above problems, and has as its object to provide a semiconductor integrated circuit device that can test a functional block alone such as the RAM 91 without increasing the scale of a test circuit.

  A semiconductor integrated circuit device according to the present invention includes a function block connected between a first logic unit and a second logic unit, a parallel path between an output of the first logic unit and an input of the function block, and data. And a plurality of first selectors for switching between the output of the first logic unit and the serial shift path to connect to the input of the functional block, and a plurality of data for storing data. A scan path constituted by flip-flops, connected on a serial shift path of the scan path, for switching between the output of the functional block and the serial shift path and connecting to the input of the second logic unit. , And shifts test data from the serial shift path of the scan path into the functional block via the second selector. The output data from the functional block Te Toggles and outputs via a second selector.

  The present invention includes a plurality of second selectors connected on the serial shift path of the scan path, for switching between the output of the functional block and the serial shift path and connecting to the input of the second logic unit. The test circuit shifts the test data from the serial shift path into the functional block via the second selector, switches the second selector, and outputs the data output from the functional block via the second selector. This has the effect that the function block can be tested alone without increasing the scale of the test.

Hereinafter, an embodiment of the present invention will be described.
Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 1 of the present invention. As shown in FIG. 1, the semiconductor integrated circuit device includes selectors 10, 11, and 12 (first selectors) controlled by a shift mode signal SM, flip-flops (FFs) 30, 31, and 32, and a test mode signal TEST2. , A logic unit 80 (first logic unit), a logic unit 81 (second logic unit), and a functional block 90. Here, the functional block 90 includes not only a RAM but also various logical functional blocks such as an arithmetic circuit, an interface circuit, and a memory block.

  In FIG. 1, a scan path is constituted by selectors 60, 61, 62, selectors 10, 11, 12, and flip-flops 30, 31, 32. The scan path includes a parallel path between an output of the logic unit 80 and an input of the function block 90, and a serial shift path for transmitting data from an SI (scan-in) terminal to an SO (scan-out) terminal in series. The selectors 60, 61, and 62 are connected to a serial shift path of a scan path.

  In FIG. 1, the insertion positions of the conventional selectors 50, 51, 52 in FIG. 21 are changed to selectors 60, 61, 62, and data output from the output terminals DO0, DO1, DO2 of the functional block 90 is used as a scan path. I am able to capture it. This makes it possible to test the functional block 90 alone without increasing the test circuit scale.

Next, the operation will be described.
During normal operation, the shift mode signal SM is set to 0 to switch the selectors 10, 11, and 12 to the "0" input terminal, and the test mode signal TEST2 is set to 0 to set the selectors 60, 61, and 62 to "0". Switch to input end. In this state, data output from the logic unit 80 is selected by the selectors 10, 11, 12 and input to the input terminals DI0, DI1, DI2 of the functional block 90 via the flip-flops 30, 31, 32. . Here, it is assumed that a clock is input to the flip-flops 30, 31, and 32.

  Further, data from the output terminals DO0, DO1, DO2 of the function block 90 are selected by the selectors 60, 61, 62 and transmitted to the logic unit 81. As described above, during the normal operation, the functional block 90 is inserted between the logic units 80 and 81, and predetermined calculations and data processing are performed.

  When performing a scan test of the logic units 80 and 81, the test mode signal TEST2 is set to 1 and the selectors 60, 61 and 62 are switched to "1" input terminals. In this state, the function block 90 is bypassed, and the scan path is inserted between the logic unit 80 and the logic unit 81. In this state, the scan test of the logic units 80 and 81 is performed by controlling the shift mode signal SM.

  When a scan test of the logic section 81 is performed, the shift mode signal SM is set to 1, the selectors 10, 11, and 12 are switched to the "1" input terminals, and clocks are applied to the flip-flops 30, 31, and 32 twice. And the 2-bit test data from the SI terminal are stored in the flip-flops 30 and 31 by a serial shift operation.

  Since the test mode signal TEST2 is set to 1, the next 1-bit test data of the SI terminal is selected by the selector 60 and input to the logic unit 81, and the 1-bit test data stored in the flip-flops 30 and 31 is output. The test data is selected by the selectors 61 and 62 and input to the logic unit 81, and a scan test of the logic unit 81 is performed using a total of 3 bits of test data.

  When performing a scan test of the logic unit 80, the shift mode signal SM is set to 0, the selectors 10, 11, and 12 are switched to the "0" input terminals, and a clock is applied to the flip-flops 30, 31, and 32 once. And the 3-bit data of the test result from the logic unit 80 to which the test data is input are stored in the flip-flops 30, 31, and 32, respectively. At this time, the 1-bit data stored in the flip-flop 32 is output to the SO terminal.

  Next, when the shift mode signal SM is set to 1 and the selectors 10, 11, and 12 are switched to the “1” input terminals, and the clocks are supplied to the flip-flops 30, 31, and 32 twice, they are stored in the flip-flops 30, 31. The 1-bit data is shifted out to the SO terminal, and the contents of the 3-bit data are confirmed. In this case, the next test data for the logic unit 81 can be stored in the flip-flops 30 and 31 from the SI terminal. The scan tests of the logic unit 80 and the logic unit 81 are repeated a plurality of times by changing the input test data.

  When the function block 90 is to be tested, the shift mode signal SM is set to 1 and the selectors 10, 11, and 12 are switched to the "1" input terminal. When the test mode signal TEST2 is set to 1, the selectors 60, 61, and 62 are switched to the "1" input terminals, and the clocks are supplied to the flip-flops 30, 31, and 32 three times. Data is stored in flip-flops 30, 31, and 32 by a serial shift operation, and is input to input terminals DI0, DI1, and DI2 of functional block 90. The function block 90 performs a desired operation, and data of a test result is output to the output terminals DO0, DO1, and DO2.

  Next, when the test mode signal TEST2 is set to 0, the selectors 60, 61, and 62 are switched to the "0" input terminals, and a clock is applied to the flip-flops 30, 31, and 32 once. , DO1 and DO2 are stored in flip-flops 30, 31, and 32, respectively. At this time, the 1-bit data stored in the flip-flop 32 is output to the SO terminal.

  Next, when the test mode signal TEST2 is set to 1 and the selectors 60, 61, 62 are switched to the "1" input terminals, and the clocks are applied to the flip-flops 30, 31, 32 twice, they are stored in the flip-flops 30, 31. The 1-bit data is shifted out to the SO terminal, and the contents of the 3-bit data are confirmed. Note that the test of the functional block 90 is repeated a plurality of times by changing the test data input from the SI terminal.

  As described above, according to the first embodiment, the effect is obtained that the test can be performed by the functional block 90 alone without increasing the scale of the test circuit.

Embodiment 2 FIG.
FIG. 2 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention. In the second embodiment, as shown in FIG. 2, the function block 90 in FIG. 1 of the first embodiment is changed to a RAM 91, and inverters 20, 21, and 22 are inserted in a serial shift path of a scan path. The test data to be written to the RAM 91 can be switched to all 0 (“000”) or all 1 (“111”) in one clock cycle by the inverters 20, 21, and 22. This makes it easy to write “000” and write “111” in the next cycle or “111” and write “000” in the next cycle when testing the RAM 91. Can be.

Next, the operation will be described.
During normal operation, the inverters 20, 21, and 22 are irrelevant, and the configuration is the same as that of the first embodiment except that the functional block 90 of the first embodiment is changed to a RAM 91. Also, the scan test of the logic units 80 and 81 is basically the same as that of the first embodiment, and the test data and the data of the test result are inverted or non-inverted by the inverters 20, 21 and 22. Should be considered.

A case of testing the RAM 91 will be described.
First, a case where a test for writing initial data to the RAM 91 is performed will be described. The shift mode signal SM is set to 1 to switch the selectors 10, 11, and 12 to "1" input terminals, and the test mode signal TEST2 is set to 1 to switch the selectors 60, 61, and 62 to "1" input terminals. When a clock is applied to flip-flops 30, 31, and 32 three times, 3-bit test data from the SI terminal is stored in flip-flops 30, 31, and 32 by a serial shift operation. However, since the flip-flops 30 and 32 store the test data inverted by the inverters 20, 21 and 22, when the test data "010" is shifted in from the SI terminal, the flip-flops 30, 31, and The test data of the output of 32 becomes “111”, and the test data “111” is inputted to the input terminals DI0, DI1, and DI2 of the RAM 91.

  When the subsequent test data “101010...” Is shifted in from the SI terminal, the test data input to the input terminals DI0, DI1, and DI2 of the RAM 91 repeat the state of “111” and the state of “000”. When desired test data “111” or “000” is set, writing is performed on the RAM 91. Thus, the test data to be written to the RAM 91 can be switched to all 0 (“000”) or all 1 (“111”) in one clock cycle. The writing of the test data into the RAM 91 is repeated a plurality of times while changing the address.

  Next, a case where a read test is performed on a specific address of the RAM 91 will be described. The shift mode signal SM is set to 1 to switch the selectors 10, 11, and 12 to "1" input terminals, and the test mode signal TEST2 is set to 0 to switch the selectors 60, 61, and 62 to "0" input terminals. When a read test is performed for a specific address of the RAM 91, data of the test result is output to the output terminals DO0, DO1, and DO2 of the RAM 91, and output from the selectors 10, 11, and 12 via the selectors 60, 61, and 62, respectively. Is done. When a clock is applied to the flip-flops 30, 31, and 32 once, the data of the test result is stored in the flip-flops 30, 31, and 32, respectively. At this time, the 1-bit data stored in the flip-flop 32 is output to the SO terminal.

  Next, the test mode signal TEST2 = 1 is set, and the selectors 60, 61, 62 are switched to the "1" input terminal. When a clock is applied to the flip-flops 30, 31, and 32 twice, the 1-bit data stored in the flip-flops 30 and 31 is shifted out to the SO terminal by the serial shift operation, and the contents of the data of a total of 3 bits are confirmed. Is done. However, the data stored in the flip-flop 30 passes through the inverters 21 and 22, and the data stored in the flip-flop 31 passes through the inverter 22 and is serially output to the SO terminal. There is a need to do. Note that the read test of the RAM 91 is repeated a plurality of times by changing the address.

  Further, the inverter 20 may be omitted. In this case, the test data shifted in from the SI terminal may be inverted from the above case.

  Compared to FIG. 22, the second embodiment eliminates the need for the selectors 50, 51, 52 and the selectors 70, 71, 72 of FIG.

  As described above, according to the second embodiment, the test can be performed by the RAM 91 alone without increasing the scale of the test circuit, and the test data to be written into the RAM 91 can be all 0 (“000”) or all 1 (“111”) can be switched in one clock cycle, and the effect of efficiently testing the RAM 91 can be obtained.

Embodiment 3 FIG.
FIG. 3 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 3 of the present invention. In the third embodiment, as shown in FIG. 3, inverters 40, 41, and 42 are inserted in the series shift path of the scan path instead of inverters 20, 21, and 22 in FIG. 2 of the second embodiment. . The test data to be written to the RAM 91 can be switched to all 0 (“000”) or all 1 (“111”) in one clock cycle by the inverters 40, 41, and 42.

Next, the operation will be described.
During normal operation, the inverters 40, 41, and 42 are irrelevant, and are similar to the first embodiment except that the functional block 90 of the first embodiment is changed to a RAM 91. Also, the scan test of the logic units 80 and 81 is basically the same as that of the first embodiment, and the test data and the data of the test result are inverted or non-inverted by the inverters 40, 41 and 42. Should be considered.

A case of testing the RAM 91 will be described.
First, a case where a test for writing initial data to the RAM 91 is performed will be described. The shift mode signal SM is set to 1 to switch the selectors 10, 11, and 12 to "1" input terminals, and the test mode signal TEST2 is set to 1 to switch the selectors 60, 61, and 62 to "1" input terminals. When a clock is applied to flip-flops 30, 31, and 32 three times, 3-bit test data from the SI terminal is stored in flip-flops 30, 31, and 32 by a serial shift operation. However, since the flip-flops 30, 32 store the test data inverted by the inverters 40, 41, 42, when the test data "010" is shifted in from the SI terminal, the flip-flops 30, 31,. The test data of the output of 32 becomes “111”, and the test data “111” is inputted to the input terminals DI0, DI1, and DI2 of the RAM 91.

  When the subsequent test data “101010...” Is shifted in from the SI terminal, the test data input to the input terminals DI0, DI1, and DI2 of the RAM 91 repeat the state of “111” and the state of “000”. When desired test data “111” or “000” is set, writing is performed on the RAM 91. Thus, the test data to be written to the RAM 11 can be switched to all 0 (“000”) or all 1 (“111”) in one clock cycle. The writing of the test data into the RAM 91 is repeated a plurality of times while changing the address.

  Next, a case where a read and write test is performed on a specific address of the RAM 91 will be described. The shift mode signal SM is set to 1 to switch the selectors 10, 11, and 12 to "1" input terminals, and the test mode signal TEST2 is set to 0 to switch the selectors 60, 61, and 62 to "0" input terminals. When a read test is performed on a specific address of the RAM 91, the data of the test result is output to the output terminals DO0, DO1, and DO2 of the RAM 91, and inverted by the inverters 40, 41, and 42 via the selectors 60, 61, and 62, respectively. Then, the data is output from the selectors 10, 11, and 12. When a clock is applied to flip-flops 30, 31, and 32 once, inverted data of the test result is stored in flip-flops 30, 31, and 32, respectively. At this time, the 1-bit data stored in the flip-flop 32 is output to the SO terminal.

  Next, the inverted data of the test result stored in the flip-flops 30, 31, and 32 is input to the input terminals DI0, DI1, and DI2 of the RAM 91, and the inverted data of the test result is written to the RAM 91. For example, when the test result data output to the output terminals DO0, DO1, DO2 of the RAM 91 is "000", the test data "111" is written to the RAM 91 in the next cycle.

  Next, the test mode signal TEST2 = 1 is set, and the selectors 60, 61, 62 are switched to the "1" input terminal. When a clock is applied to the flip-flops 30, 31, and 32 twice, the 1-bit data stored in the flip-flops 30, 31 is shifted out to the SO terminal, and the contents of the data of a total of 3 bits are confirmed. However, the data stored in the flip-flop 30 passes through the inverters 41 and 42, and the data stored in the flip-flop 31 passes through the inverter 42 and is shifted out to the SO terminal. There is a need to do. Note that the read and write tests of the RAM 91 are repeated a plurality of times while changing the address.

  As described above, according to the third embodiment, the test can be performed by the RAM 91 alone without increasing the scale of the test circuit, and the test data to be written in the RAM 91 can be all 0 (“000”) or all 1 (“111”) can be switched in one clock cycle, and the effect of efficiently testing the RAM 91 can be obtained.

Embodiment 4 FIG.
FIG. 4 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 4 of the present invention. In FIG. 1 of the first embodiment, the outputs of the flip-flops 30, 31, and 32 are input to the input terminals DI0, DI1, and DI2 of the function block 90. In the fourth embodiment, as shown in FIG. The outputs of the selectors 10, 11, and 12 are input to input terminals DI0, DI1, and DI2 of the functional block 90.

Next, the operation will be described.
During normal operation, the shift mode signal SM is set to 0 to switch the selectors 10, 11, and 12 to the "0" input terminal, and the test mode signal TEST2 is set to 0 to set the selectors 60, 61, and 62 to "0". Switch to input end. Data output from the logic unit 80 is selected by the selectors 10, 11, and 12, and is directly input to the input terminals DI0, DI1, and DI2 of the functional block 90.

  Further, data from the output terminals DO0, DO1, DO2 of the function block 90 are selected by the selectors 60, 61, 62 and transmitted to the logic unit 81. As described above, during the normal operation, the functional block 90 is inserted between the logic units 80 and 81, and predetermined calculations and data processing are performed. In the fourth embodiment, the flip-flops 30, 31, and 32 are irrelevant during the normal operation, and the flip-flops 30, 31, and 32 need not be supplied with a clock.

  The scan test of the logic units 80 and 81 is performed because the positions of the flip-flops 30, 31, and 32 in the serial shift path of the scan path in FIG. 1 of the first embodiment and FIG. 4 of the fourth embodiment are the same. This is the same as Embodiment 1.

  When the test of the functional block 90 is performed, the shift mode signal SM is set to 1 to switch the selectors 10, 11, and 12 to the "1" input terminal, and the test mode signal TEST2 is set to 1 to select the selectors 60 and 61. , 62 are switched to "1" input terminals. When a clock is applied to flip-flops 30, 31, and 32 twice, 2-bit test data from the SI terminal is stored in flip-flops 30, 31 by a serial shift operation.

  The next 1-bit test data from the SI terminal is selected by the selector 60 and the selector 10 and input to the input terminal DI0 of the functional block 90. The 1-bit test data stored in the flip-flops 30 and 31 is The signals are selected by the selectors 61 and 62 and the selectors 11 and 12, respectively, and input to the input terminals DI1 and DI2 of the functional block 90. The functional block 90 performs a desired operation and outputs test result data to the output terminals DO0, DO1, and DO2 of the functional block 90.

  Next, when the test mode signal TEST2 is set to 0, the selectors 60, 61, and 62 are switched to the "0" input terminals, and a clock is applied to the flip-flops 30, 31, and 32 once. Test result data from DO1 and DO2 are stored in flip-flops 30, 31, and 32. At this time, the 1-bit data stored in the flip-flop 32 is output to the SO terminal.

  Next, when the test mode signal TEST2 is set to 1 and the selectors 60, 61, 62 are switched to the "1" input terminals, and the clocks are applied to the flip-flops 30, 31, 32 twice, the clocks are stored in the flip-flops 30, 31. The 1-bit data is shifted out to the SO terminal, and the contents of the 3-bit data are confirmed. Note that the test of the functional block 90 is repeated a plurality of times by changing the test data input from the SI terminal.

  As described above, according to the fourth embodiment, the function block 90 can be tested alone without increasing the scale of the test circuit, and the clocks are supplied to the flip-flops 30, 31, and 32 during normal operation. The effect that it is not necessary to give the key is obtained.

Embodiment 5 FIG.
FIG. 5 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to a fifth embodiment of the present invention. In FIG. 2 of the second embodiment, the outputs of the flip-flops 30, 31, and 32 are input to the input terminals DI0, DI1, and DI2 of the RAM 91. However, in the fifth embodiment, as shown in FIG. The outputs of 10, 11, and 12 are input to input terminals DI0, DI1, and DI2 of the RAM 91.

Next, the operation will be described.
At the time of normal operation, the inverters 20, 21, 22 and the flip-flops 30, 31, 32 are irrelevant, and the functional block 90 of the fourth embodiment is the same as that of the fourth embodiment except that the function block 90 is changed to the RAM 91. The flip-flops 30, 31, and 32 need not be provided with a clock. The scan test of the logic units 80 and 81 is basically the same as that of the fourth embodiment, and the test data and the test result data are inverted or non-inverted by the inverters 20, 21 and 22. Should be considered.

  A case of testing the RAM 91 will be described. First, a case where a test for writing initial data to the RAM 91 is performed will be described. The shift mode signal SM is set to 1 to switch the selectors 10, 11, and 12 to "1" input terminals, and the test mode signal TEST2 is set to 1 to switch the selectors 60, 61, and 62 to "1" input terminals. When a clock is applied to flip-flops 30, 31, and 32 twice, 2-bit test data from the SI terminal is stored in flip-flops 30, 31 by a serial shift operation.

  However, since the flip-flop 30 stores the inverted test data, when “10” is shifted in from the SI terminal, the outputs of the flip-flops 30 and 31 become “11”. The output of the flip-flop 30 is input to the input terminal DI1 of the RAM 91 via the inverter 21, the output of the flip-flop 31 is input to the input terminal DI2 of the RAM 91 via the inverter 22, and is input to the input terminals DI1 and DI2 of the RAM 91. The test data becomes “00”. When the subsequent test data "1" is given from the SI terminal, the test data is input to the input terminal DI0 of the RAM 91 via the inverter 20, and the test data input to the input terminals DI0, DI1, and DI2 of the RAM 91 is changed to "000". Become.

  When the subsequent test data “101010...” (The leading “1” is the aforementioned test data “1”) is shifted in from the SI terminal, the test data input to the input terminals DI0, DI1, and DI2 of the RAM 91 becomes “ The state of “000” and the state of “111” are alternately repeated. When desired data “000” or “111” is input, writing is performed on the RAM 91. Thus, the test data to be written to the RAM 91 can be switched to all 0 (“000”) or all 1 (“111”) in one clock cycle. The writing of the test data into the RAM 91 is repeated a plurality of times while changing the address.

  The case where a read test is performed on a specific address of the RAM 91 is the same as in the second embodiment. Further, the inverter 20 may be omitted as in the second embodiment.

  As described above, according to the fifth embodiment, the test can be performed by the RAM 91 alone without increasing the scale of the test circuit, and the test data to be written to the RAM 91 can be all 0 (“000”) or all 1 ( "111") in one clock cycle, so that the test of the RAM 91 can be performed efficiently and the flip-flops 30, 31, and 32 need not be supplied with a clock during normal operation. Is obtained.

Embodiment 6 FIG.
FIG. 6 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 6 of the present invention. In FIG. 3 of the third embodiment, the outputs of the flip-flops 30, 31, and 32 are input to the input terminals DI0, DI1, and DI2 of the RAM 91. However, in the sixth embodiment, as shown in FIG. The outputs of 10, 11, and 12 are input to input terminals DI0, DI1, and DI2 of the RAM 91.

Next, the operation will be described.
At the time of normal operation, the inverters 40, 41, and 42 and the flip-flops 30, 31, and 32 are irrelevant, and the functional block 90 of the fourth embodiment is the same as that of the fourth embodiment except that the RAM 91 is changed. The flip-flops 30, 31, and 32 need not be provided with a clock. The scan test of the logic units 80 and 81 is basically the same as that of the fourth embodiment, and the test data and the data of the test result are inverted or non-inverted by the inverters 40, 41 and 42. Should be considered.

  A case of testing the RAM 91 will be described. The case of performing a test of writing initial data to the RAM 91 is the same as that of the fifth embodiment except that the inverters 20, 21, 22 are replaced by the inverters 40, 41, 42.

  Next, a case where a read and write test is performed on a specific address of the RAM 91 will be described. The shift mode signal SM is set to 1 to switch the selectors 10, 11, and 12 to "1" input terminals, and the test mode signal TEST2 is set to 0 to switch the selectors 60, 61, and 62 to "0" input terminals. When a read test is performed for a specific address of the RAM 91, data of the test result is output to the output terminals DO0, DO1, and DO2 of the RAM 91, and inverted by the inverters 40, 41, and 42 via the selectors 60, 61, and 62, respectively. Then, the data is output from the selectors 10, 11, and 12.

  Next, the inverted data of the test result output from the selectors 10, 11, and 12 is input to the input terminals DI0, DI1, and DI2 of the RAM 91, and the inverted data of the test result is written to the RAM 91. For example, when the test result data output to the output terminals DO0, DO1, DO2 of the RAM 91 is "000", the test data "111" is written to the RAM 91 in the next cycle.

  Next, when a clock is applied once to flip-flops 30, 31, and 32, inverted data of test results output from selectors 10, 11, and 12 are stored in flip-flops 30, 31, and 32, respectively. At this time, the 1-bit data stored in the flip-flop 32 is output to the SO terminal.

  Next, TEST2 = 1 is set and the selectors 60, 61, 62 are switched to the "1" input terminal. When a clock is applied to the flip-flops 30, 31, and 32 twice, the 1-bit data stored in the flip-flops 30, 31 is shifted out to the SO terminal, and the contents of the data of a total of 3 bits are confirmed. However, the data stored in the flip-flop 30 passes through the inverters 41 and 42, and the data stored in the flip-flop 31 passes through the inverter 42 and is shifted out to the SO terminal. There is a need to do. Note that the read and write tests of the RAM 91 are repeated a plurality of times while changing the address.

  As described above, according to the sixth embodiment, the test can be performed by the RAM 91 alone without increasing the scale of the test circuit, and the test data to be written into the RAM 91 can be all 0 (“000”) or all 1 ( "111") in one clock cycle, so that the test of the RAM 91 can be performed efficiently and the flip-flops 30, 31, and 32 need not be supplied with a clock during normal operation. Is obtained.

Embodiment 7 FIG.
FIG. 7 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 7 of the present invention. In the seventh embodiment, as shown in FIG. 7, a selector 100 (third selector) for feeding back data output to the SO terminal to the SI terminal side is added to FIG. 6 of the sixth embodiment. . The selector 100 is controlled by a loop enable signal LOOPEN. The selector 100 can be similarly added to FIG. 2 of the second embodiment, FIG. 3 of the third embodiment, and FIG. 5 of the fifth embodiment.

Next, the operation will be described.
During normal operation, the shift mode signal SM is set to 0 to switch the selectors 10, 11, and 12 to the "0" input terminal, and the test mode signal TEST2 is set to 0 to set the selectors 60, 61, and 62 to "0". Switch to input end. During normal operation, the inverters 40, 41, and 42 and the flip-flops 30, 31, and 32 are irrelevant, and are similar to the fourth embodiment except that the functional block 90 of the fourth embodiment is changed to a RAM 91. The flip-flops 30, 31, and 32 need not be provided with a clock.

  At the time of a scan test of the logic units 80 and 81, the loop enable signal LOOPEN = 0 is set, the selector 100 is switched to the “0” input terminal, and the test mode signal TEST2 = 1 is set to select the selectors 60, 61, 62. To the “1” input terminal. The scan test of the logic units 80 and 81 is basically the same as that of the fourth embodiment, and it is considered that the test data and the data of the test result are inverted or non-inverted by the inverters 40, 41 and 42. Just do it.

A case of testing the RAM 91 will be described.
First, a case where a test for writing initial data to the RAM 91 is performed will be described. The loop enable signal LOOPEN = 0 is set to switch the selector 100 to the “0” input terminal, the shift mode signal SM is set to 1, the selectors 10, 11, and 12 are switched to the “1” input terminal, and the test mode signal TEST2 is set. = 1, and switches the selectors 60, 61, 62 to the "1" input terminal.

  When a clock is applied to flip-flops 30, 31, and 32 three times, 3-bit test data from the SI terminal is stored in flip-flops 30, 31, and 32 by a serial shift operation. However, since flip-flops 30 and 32 store inverted test data, when "010" is shifted in from the SI terminal, the outputs of flip-flops 30, 31, and 32 become "111". In this state, the next test data of the SI terminal is inverted by the inverter 40 and transmitted to the input terminal DI0 of the RAM 91, and the data “1” of the output of the flip-flop 30 is inverted by the inverter 41 and transmitted to the input terminal DI1 of the RAM 91. The data "1" output from the flip-flop 31 is inverted by the inverter 42 and transmitted to the input terminal DI2 of the RAM 91.

  Next, when the loop enable signal LOOPEN = 1 is set and the selector 100 is switched to the “1” input terminal, the data “1” of the output of the flip-flop 32 is transmitted to the input terminal DI0 of the RAM 91 via the inverter 40 and the RAM 91 Data of the input terminals DI0, DI1, and DI2 become "000". With the loop enable signal LOOPEN = 1, every time a clock is applied to the flip-flops 30, 31, and 32, the data at the input terminals DI0, DI1, and DI2 of the RAM 91 is changed by the inverters 40, 41, and 42, and The state and the state of “111” are repeated. When desired test data “000” or “111” is set, writing is performed on the RAM 91. The writing of the test data in the RAM 91 is repeated a plurality of times while changing the address.

  The case where a read and write test is performed on a specific address of the RAM 91 is the same as in the sixth embodiment. In this case, the setting of the loop enable signal LOOPEN may be either.

  In the seventh embodiment, when a write test of initial data is performed on the RAM 91, test data is shifted in from the SI terminal so that the outputs of the flip-flops 30, 31, and 32 become "111". However, the test data may be shifted in from the SI terminal so that the outputs of the flip-flops 30, 31, and 32 become "000".

  As described above, according to the seventh embodiment, the test can be performed by the RAM 91 alone without increasing the scale of the test circuit, and the test data to be written in the RAM 91 can be all 0 (“000”) or all 1 ( "111") in one clock cycle, so that the test of the RAM 91 can be performed efficiently and the flip-flops 30, 31, and 32 need not be supplied with a clock during normal operation. Is obtained.

  Further, according to the seventh embodiment, the loop enable signal LOOPEN = 0 is set, and test data such as “111” or “000” is shifted in from the SI terminal into the flip-flops 30, 31, and 32, Thereafter, if the loop enable signal LOOPEN = 1 is switched, the data to the input terminals DI0 to DI2 of the RAM 91 alternates between "111" and "000" every time a clock is supplied to the flip-flops 30, 31, and 32. Therefore, there is no need to newly provide test data from the SI terminal, and the effect of facilitating the test of the RAM 91 can be obtained.

Embodiment 8 FIG.
FIG. 8 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to an eighth embodiment of the present invention. In the eighth embodiment, as shown in FIG. 8, a gate circuit 110 for monitoring test result data output from the RAM 91 in a short time is added to FIG. 7 of the seventh embodiment. The gate circuit 110 detects that the data output from the selectors 60, 61, and 62 have the same value. Although an AND gate is used as the gate circuit 110 in FIG. 8, any of a NAND gate, an OR gate, and a NOR gate may be used.

Next, the operation will be described.
The operation during the normal operation and the operation during the scan test of the logic units 80 and 81 are the same as in the seventh embodiment. Further, the operation in the case of performing a test of writing initial data to the RAM 91 in the test of the RAM 91 is the same as that of the seventh embodiment.

  Next, a case where a read and write test is performed on a specific address of the RAM 91 will be described. The loop enable signal LOOPEN = 1 is set to switch the selector 100 to the “1” input terminal, the shift mode signal SM is set to 1, the selectors 10, 11, and 12 are switched to the “1” input terminal, and the test mode signal TEST2 is set. = 0, and switches the selectors 60, 61, 62 to the "0" input terminal.

  When a read test is performed on a specific address of the RAM 91, data of the test result is output to the output terminals DO0, DO1, and DO2 of the RAM 91, and transmitted to the input of the gate circuit 110 via the selectors 60, 61, and 62, respectively. . At this time, if the test result data is “111”, the monitor signal MONI output from the gate circuit 110 becomes “1”. If the test result data is other than “111”, the monitor signal MONI becomes “1”. 0 ". Therefore, if the monitor signal MONI is checked, it can be determined whether or not the test result data from the output terminals DO0, DO1 and DO2 of the RAM 91 is "111" without shifting out from the SO terminal.

  The test result data from the output terminals DO0, DO1, and DO2 of the RAM 91 are inverted by inverters 40, 41, and 42 and applied to the input terminals DI0, DI1, and DI2 of the RAM 91. Next, when the inverted data of the test result is written into the RAM 91 and a clock is applied to the flip-flops 30, 31, and 32, the flip-flops 30, 31, and 32 store the inverted data of the test result.

  Next, when the test mode signal TEST2 is set to 1 and the selectors 60, 61, 62 are switched to the "1" input terminals, the inverted data of the test results stored in the flip-flops 30, 31, 32 are output from the selector 60, respectively. , 61, 62 to the input of the gate circuit 110. If the data of the test result is “000”, the input of the gate circuit 110 becomes “111”, the monitor signal MONI output from the gate circuit 110 becomes “1”, and the data of the test result is other than “000”. If there is, the monitor signal MONI becomes "0". Therefore, by checking the monitor signal MONI, it can be determined whether or not the test result data output from the output terminals DO0, DO1, DO2 of the RAM 91 is "000" without shifting out from the SO terminal. it can. Note that the read and write tests of the RAM 91 are repeated a plurality of times while changing the address.

  As described above, according to the eighth embodiment, the test can be performed by the RAM 91 alone without increasing the scale of the test circuit, and the test data to be written into the RAM 91 can be all 0 (“000”) or all 1 ( "111") in one clock cycle, so that the test of the RAM 91 can be performed efficiently and the flip-flops 30, 31, and 32 need not be supplied with a clock during normal operation. Is obtained.

  Further, according to the eighth embodiment, the loop enable signal LOOPEN = 0 is set, and test data such as “111” or “000” is shifted in from the SI terminal to the flip-flops 30, 31, and 32, After that, if the loop enable signal LOOPEN = 1 is switched, the input terminals DI0 to DI2 of the RAM 91 alternately repeat the state of "111" and "000" every time a clock is supplied to the flip-flops 30, 31, and 32. It is not necessary to newly provide test data from the SI terminal, and the effect that the test of the RAM 91 can be facilitated is obtained.

  Further, according to the eighth embodiment, a test as to whether the test result data from the output terminals DO0, DO1, DO2 of the RAM 91 is "111" and a test as to whether the data is "000" are made from the SO terminal. Since the monitoring can be performed only by checking the monitor signal MONI without shifting out, the effect of facilitating the test of the RAM 91 can be obtained.

Embodiment 9 FIG.
FIG. 9 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 9 of the present invention. In the ninth embodiment, as shown in FIG. 9, the gate circuit 110 in FIG. 8 of the eighth embodiment is replaced by a gate circuit 111 connected to the output side of the selectors 60, 61, 62 from the output side of the inverters 40, 41, 42. Have moved as. The gate circuit 111 detects that the data output from the inverters 40, 41, and 42 have the same value. Although an AND gate is used as the gate circuit 111 in FIG. 9, any one of a NAND gate, an OR gate, and a NOR gate may be used.

Next, the operation will be described.
The operation during the normal operation and the operation during the scan test of the logic units 80 and 81 are the same as in the seventh embodiment. Further, the operation in the case of performing a test of writing initial data to the RAM 91 in the test of the RAM 91 is the same as that of the seventh embodiment.

  Next, a case where a read and write test is performed on a specific address of the RAM 91 will be described. The loop enable signal LOOPEN = 1 is set to switch the selector 100 to the “1” input terminal, the shift mode signal SM is set to 1, the selectors 10, 11, and 12 are switched to the “1” input terminal, and the test mode signal TEST2 is set. = 0, and switches the selectors 60, 61, 62 to the "0" input terminal.

  When a read test is performed for a specific address of the RAM 91, data of the test result is output to the output terminals DO0, DO1, and DO2 of the RAM 91, and inverted by the inverters 40, 41, and 42 via the selectors 60, 61, and 62, respectively. And transmitted to the input of the gate circuit 111. At this time, if the test result data is “000”, the monitor signal MONI output from the gate circuit 111 becomes “1”. If the test result data is other than “000”, the monitor signal MONI becomes “1”. 0 ". Therefore, if the monitor signal MONI is checked, it can be determined whether or not the test result data from the output terminals DO0, DO1, DO2 of the RAM 91 is "000" without shifting out from the SO terminal.

  The test result data from the output terminals DO0, DO1, and DO2 of the RAM 91 are inverted by inverters 40, 41, and 42 and applied to the input terminals DI0, DI1, and DI2 of the RAM 91. Next, when the inverted data of the test result is written into the RAM 91 and a clock is applied once to the flip-flops 30, 31, and 32, the flip-flops 30, 31, and 32 store the inverted data of the test result.

  Next, when the test mode signal TEST2 is set to 1 and the selectors 60, 61, 62 are switched to the "1" input terminals, the inverted data of the test results stored in the flip-flops 30, 31, 32 are converted to the selectors 60, 61, 32, respectively. 61 and 62. The inverted data of the test results of the outputs of the selectors 60, 61, 62 are further inverted by the inverters 40, 41, 42 and transmitted to the input of the gate circuit 111. If the data of the test result is “111”, the input of the gate circuit 111 is “111”, the monitor signal MONI output from the gate circuit 111 is “1”, and the data of the test result is other than “111”. If there is, the monitor signal MONI becomes "0". Therefore, by checking the monitor signal MONI, it can be determined whether or not the test result data from the output terminals DO0, DO1, DO2 of the RAM 91 is "111" without shifting out from the SO terminal. Note that the read and write tests of the RAM 91 are repeated a plurality of times by changing the address.

  As described above, according to the ninth embodiment, the test can be performed by the RAM 91 alone without increasing the scale of the test circuit, and the test data to be written in the RAM 91 can be all 0 (“000”) or all 1 ( "111") in one clock cycle, so that the test of the RAM 91 can be performed efficiently and the flip-flops 30, 31, and 32 need not be supplied with a clock during normal operation. Is obtained.

  Further, according to the ninth embodiment, the loop enable signal LOOPEN = 0 is set, and test data such as "111" or "000" is shifted in from the SI terminal to the flip-flops 30, 31, and 32, After that, if the loop enable signal LOOPEN = 1 is switched, the input terminals DI0 to DI2 of the RAM 91 alternately repeat the state of "111" and "000" every time a clock is supplied to the flip-flops 30, 31, and 32. It is not necessary to newly provide test data from the SI terminal, and the effect that the test of the RAM 91 can be facilitated is obtained.

  Further, according to the ninth embodiment, a test as to whether the test result data from the output terminals DO0, DO1, DO2 of the RAM 91 is "000" and a test as to whether the data is "111" are made from the SO terminal. Since the monitoring can be performed only by checking the monitor signal MONI without shifting out, the effect of facilitating the test of the RAM 91 can be obtained.

Embodiment 10 FIG.
FIG. 10 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 10 of the present invention. In the tenth embodiment, as shown in FIG. 10, the gate circuit 110 in the eighth embodiment shown in FIG. 8 is replaced by a gate circuit 112 from the output side of the selectors 60, 61, 62 to the output side of the selectors 10, 11, 12. Have moved as. The gate circuit 112 detects that the data output from the selectors 10, 11, and 12 have the same value. Although an AND gate is used as the gate circuit 112 in FIG. 10, any one of a NAND gate, an OR gate, and a NOR gate may be used.

Next, the operation will be described.
The operation during the normal operation and the operation during the scan test of the logic units 80 and 81 are the same as in the seventh embodiment. Further, the operation in the case of performing a test of writing initial data to the RAM 91 in the test of the RAM 91 is the same as that of the seventh embodiment. Further, when a read and write test is performed for a specific address of the RAM 91, the gate circuit 112 performs a test from the output terminals DO0, DO1, and DO2 of the RAM 91 based on the data output from the selectors 10, 11, and 12. This is the same as Embodiment 9 except that it is determined whether the resulting data is “000” or “111”.

  As described above, according to the tenth embodiment, the same effects as in the ninth embodiment can be obtained.

Embodiment 11 FIG.
FIG. 11 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 11 of the present invention. In the eleventh embodiment, as shown in FIG. 11, the gate circuit 110 of the eighth embodiment shown in FIG. It has moved as 113. The gate circuit 113 detects that the data output from the flip-flops 30, 31, and 32 have the same value. Although an AND gate is used as the gate circuit 113 in FIG. 11, any one of a NAND gate, an OR gate, and a NOR gate may be used.

Next, the operation will be described.
The operation during the normal operation and the operation during the scan test of the logic units 80 and 81 are the same as in the seventh embodiment. Further, the operation in the case of performing a test of writing initial data to the RAM 91 in the test of the RAM 91 is the same as that of the seventh embodiment.

  Next, a case where a read and write test is performed on a specific address of the RAM 91 will be described. The loop enable signal LOOPEN = 1 is set to switch the selector 100 to the “1” input terminal, the shift mode signal SM is set to 1, the selectors 10, 11, and 12 are switched to the “1” input terminal, and the test mode signal TEST2 is set. = 0, and switches the selectors 60, 61, 62 to the "0" input terminal.

  When a read test is performed on a specific address of the RAM 91, data of the test result is output to the output terminals DO0, DO1, and DO2 of the RAM 91, and the data is output via the selectors 60, 61, and 62 and the selectors 10, 11, and 12, respectively. The inverted data of the test result is transmitted to the inputs of the flip-flops 30, 31, 32 and the input terminals DI0, DI1, DI2 of the RAM 91 after being inverted by the inverters 40, 41, 42.

  Next, when the inverted data of the test result is written into the RAM 91 and the flip-flops 30, 31, and 32 are given a clock once, the flip-flops 30, 31, and 32 store the inverted data of the test result and store the inverted data of the test result. The inverted data is transmitted to the input of the gate circuit 113.

  At this time, if the test result data is “000”, the output data of the flip-flops 30, 31, and 32 is “111”, and the monitor signal MONI output from the gate circuit 113 becomes “1”. If the resulting data is other than "000", the monitor signal MONI becomes "0". Therefore, if the monitor signal MONI is checked, it can be determined whether or not the test result data from the output terminals DO0, DO1, DO2 of the RAM 91 is "000" without shifting out from the SO terminal.

  Next, when the test mode signal TEST2 is set to 1 and the selectors 60, 61, 62 are switched to the "1" input terminals, the inverted data of the test results stored in the flip-flops 30, 31, 32 are output from the selector 60, respectively. , 61, 62. The inverted data of the test results output from the selectors 60, 61, and 62 are further inverted by inverters 40, 41, and 42 to become test result data, and are output to the flip-flops 30, 31, and 32 via the selectors 10, 11, and 12. Conveyed to the input. Next, when a clock is applied once to the flip-flops 30, 31, and 32, the flip-flops 30, 31, and 32 store the data of the test result and transmit the data to the input of the gate circuit 113.

  If the data of the test result is “111”, the input of the gate circuit 113 is “111”, the monitor signal MONI output from the gate circuit 111 is “1”, and the data of the test result is other than “111”. If there is, the monitor signal MONI becomes "0". As described above, by checking the monitor signal MONI, it is possible to determine whether or not the test result data from the output terminals DO0, DO1, and DO2 of the RAM 91 is "111" without shifting out from the SO terminal. it can. Note that the read and write tests of the RAM 91 are repeated a plurality of times by changing the address.

  As described above, according to the eleventh embodiment, the same effects as in the ninth embodiment can be obtained.

Embodiment 12 FIG.
FIG. 12 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 12 of the present invention. In FIG. 4 of the fourth embodiment, the inputs of the flip-flops 30, 31, and 32 are connected to the outputs of the selectors 10, 11, and 12. However, in the twelfth embodiment, as shown in FIG. The inputs of 30, 30, 32 are connected to the outputs of selectors 60, 61, 62, the outputs of flip-flops 30, 31, 32 are connected to logic section 81, and flip-flop 33 is connected between the output of selector 12 and the SO terminal. Has been added. Thus, the flip-flops 30, 31, and 32 can be used as output registers of the functional block 90 during normal operation without increasing the circuit scale during normal operation.

Next, the operation will be described.
During normal operation, the shift mode signal SM is set to 0 to switch the selectors 10, 11, and 12 to the "0" input terminal, and the test mode signal TEST2 is set to 0 to set the selectors 60, 61, and 62 to "0". Switch to input end. Data output from the logic unit 80 is selected by the selectors 10, 11, and 12, and is directly input to the input terminals DI0, DI1, and DI2 of the functional block 90.

  Data from the output terminals DO0, DO1, DO2 of the function block 90 are selected by selectors 60, 61, 62 and transmitted to the inputs of flip-flops 30, 31, 32, and the outputs of flip-flops 30, 31, 32 are logic. During normal operation, the function block 90 and the flip-flops 30, 31, and 32 are inserted between the logic units 80 and 81, and the clock is supplied to the flip-flops 30, 31, and 32 during normal operation. The given calculation and data processing are performed. At this time, the flip-flops 30, 31, and 32 operate as output registers of the functional block 90.

  When performing a scan test of the logic units 80 and 81, the test mode signal TEST2 is set to 1 and the selectors 60, 61 and 62 are switched to "1" input terminals. In this state, the function block 90 is bypassed, and the scan path is inserted between the logic unit 80 and the logic unit 81. In this state, the scan test of the logic units 80 and 81 is performed by controlling the shift mode signal SM.

  When performing a scan test of the logic unit 81, the shift mode signal SM is set to 1, the selectors 10, 11, and 12 are switched to the "1" input terminals, and clocks are supplied to the flip-flops 30, 31, and 32 three times. (May be supplied to the flip-flop 33), and the 3-bit test data from the SI terminal is stored in the flip-flops 30, 31, and 32 by a serial shift operation.

  The 3-bit test data output from the flip-flops 30, 31, and 32 is input to the logic unit 81, and the logic unit 81 performs a desired operation. The output of the logic unit 81 is connected to another scan path (not shown) or an output buffer of an LSI, and is tested by a conventional method.

  A case where a scan test of the logic unit 80 is performed will be described. The input of the logic unit 80 is connected to a flip-flop output of another scan path (not shown) or an input buffer of an LSI, and test test data is given by a conventional method. The logic unit 80 performs a desired operation based on the test data, and the output of the test result of the logic unit 80 is transmitted to the “0” input terminals of the selectors 10, 11, and 12. When the shift mode signal SM is set to 0, the selectors 10, 11, and 12 are switched to the "0" input terminals, and a clock is applied to the flip-flops 31, 32, and 33 once (or may be applied to the flip-flop 30). The 3-bit data of the test result from the logic unit 80 is stored in the flip-flops 31, 32, and 33, respectively. At this time, the 1-bit data stored in the flip-flop 33 is output to the SO terminal.

  Next, the shift mode signal SM is set to 1, the selectors 10, 11, and 12 are switched to the "1" input terminals, and the clock is supplied to the flip-flops 31, 32, and 33 twice (the clock may be supplied to the flip-flop 30). Then, the 1-bit data stored in the flip-flops 31 and 32 is shifted out to the SO terminal, and the contents of the data of a total of 3 bits are confirmed. In this case, the next test data for the logic unit 81 can be stored in the flip-flops 30 and 31 from the SI terminal. The scan tests of the logic unit 80 and the logic unit 81 are repeated a plurality of times by changing the input test data.

  When the test of the functional block 90 is performed, the shift mode signal SM is set to 1 to switch the selectors 10, 11, and 12 to the "1" input terminal, and the test mode signal TEST2 is set to 1 to select the selectors 60 and 61. , 62 are switched to "1" input terminals. When a clock is applied to flip-flops 30, 31, and 32 three times (or may be applied to flip-flop 33), 3-bit test data from the SI terminal is stored in flip-flops 30, 31, and 32 by a serial shift operation. You.

  The 3-bit test data stored in the flip-flops 30, 31, and 32 is selected by the selectors 10, 11, and 12, and is input to the input terminals DI0, DI1, and DI2 of the functional block 90. The functional block 90 performs a desired operation (provides a clock if necessary), and outputs test result data to the output terminals DO0, DO1, and DO2 of the functional block 90.

  Next, when the test mode signal TEST2 is set to 0, the selectors 60, 61, and 62 are switched to the "0" input terminals, and a clock is applied to the flip-flops 30, 31, and 32 once. Test result data from DO1 and DO2 are stored in flip-flops 30, 31, and 32.

  Next, the test mode signal TEST2 = 1 is set, the selectors 60, 61, and 62 are switched to the "1" input terminals, and the clock is supplied to the flip-flops 31, 32, and 33 three times (or may be supplied to the flip-flop 30). Then, the 1-bit data stored in the flip-flops 30, 31, and 32 is shifted out to the SO terminal, and the contents of the 3-bit data are confirmed. Note that the test of the functional block 90 is repeated a plurality of times by changing the test data input from the SI terminal.

  As described above, according to the twelfth embodiment, the function block 90 can be tested alone without increasing the scale of the test circuit, and the flip-flops 30 and The effect is obtained that the reference numerals 31 and 32 can be used as output registers of the RAM 91 during normal operation.

Embodiment 13 FIG.
FIG. 13 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 13 of the present invention. In FIG. 8 of the eighth embodiment, the inputs of the flip-flops 30, 31, and 32 are connected to the outputs of the selectors 10, 11, and 12. In the thirteenth embodiment, as shown in FIG. The inputs of 30, 30, 32 are connected to the outputs of selectors 60, 61, 62, the outputs of flip-flops 30, 31, 32 are connected to logic section 81, and flip-flop 33 is connected between the output of selector 12 and the SO terminal. Has been added. As a result, the flip-flops 30, 31, and 32 can be used as output registers of the RAM 91 during normal operation without increasing the circuit scale during normal operation. Although an AND gate is used as the gate circuit 110 in FIG. 13, any one of a NAND gate, an OR gate, and a NOR gate may be used.

Next, the operation will be described.
During normal operation, the shift mode signal SM is set to 0 to switch the selectors 10, 11, and 12 to the "0" input terminal, and the test mode signal TEST2 is set to 0 to set the selectors 60, 61, and 62 to "0". Switch to input end. Data output from the logic unit 80 is selected by the selectors 10, 11, and 12, and is directly input to the input terminals DI0, DI1, and DI2 of the RAM 91.

  Data from the output terminals DO0, DO1 and DO2 of the RAM 91 are selected by selectors 60, 61 and 62 and transmitted to the inputs of the flip-flops 30, 31, and 32, and the outputs of the flip-flops 30, 31, and 32 are output to the logic unit 81. During normal operation, the RAM 91 and the flip-flops 30, 31, and 32 are inserted between the logic units 80 and 81, and a predetermined clock is applied to the flip-flops 30, 31, and 32 to supply the clock to the flip-flops 30, 31, and 32. Calculation and data processing are performed. At this time, the flip-flops 30, 31, and 32 operate as output registers of the RAM 91.

  At the time of a scan test of the logic units 80 and 81, the loop enable signal LOOPEN = 0 is set, the selector 100 is switched to the “0” input terminal, and the test mode signal TEST2 = 1 is set to select the selectors 60, 61, 62. To the “1” input terminal. In this state, the RAM 91 is bypassed, and the scan path is inserted between the logic unit 80 and the logic unit 81. In this state, the scan test of the logic units 80 and 81 is performed by controlling the shift mode signal SM.

  When performing a scan test of the logic unit 81, the shift mode signal SM is set to 1, the selectors 10, 11, and 12 are switched to the "1" input terminals, and clocks are supplied to the flip-flops 30, 31, and 32 three times. (May be supplied to the flip-flop 33), and the 3-bit test data from the SI terminal is stored in the flip-flops 30, 31, and 32 by a serial shift operation. At this time, it is necessary to give appropriate test data in consideration of the inverters 40, 41, and 42 inserted in the serial shift path.

  The 3-bit test data output from the flip-flops 30, 31, and 32 is input to the logic unit 81, and the logic unit 81 performs a desired operation. The output of the logic unit 81 is connected to another scan path (not shown) or an output buffer of an LSI, and is tested by a conventional method.

  A case where a scan test of the logic unit 80 is performed will be described. The input of the logic unit 80 is connected to a flip-flop output of another scan path (not shown) or an input buffer of an LSI, and test test data is given by a conventional method. The logic unit 80 performs a desired operation based on the test data, and the output of the test result of the logic unit 80 is transmitted to the “0” input terminals of the selectors 10, 11, and 12. When the shift mode signal SM is set to 0, the selectors 10, 11, and 12 are switched to the "0" input terminals, and a clock is applied to the flip-flops 31, 32, and 33 once (or may be applied to the flip-flop 30). The 3-bit data of the test result from the logic unit 80 is stored in the flip-flops 31, 32, and 33, respectively. At this time, the 1-bit data stored in the flip-flop 33 is output to the SO terminal.

  Next, the shift mode signal SM is set to 1, the selectors 10, 11, and 12 are switched to the "1" input terminals, and the clock is supplied to the flip-flops 31, 32, and 33 twice (the clock may be supplied to the flip-flop 30). Then, the 1-bit data stored in the flip-flops 31 and 32 is shifted out to the SO terminal, and the contents of the data of a total of 3 bits are confirmed. In this case, the next test data for the logic unit 81 can be stored in the flip-flops 30 and 31 from the SI terminal. At this time, it is necessary to give appropriate test data in consideration of the inverters 40, 41, and 42 inserted in the serial shift path. The scan tests of the logic unit 80 and the logic unit 81 are repeated a plurality of times by changing the input test data.

A case of testing the RAM 91 will be described.
First, a case where a test for writing initial data to the RAM 91 is performed will be described. The loop enable signal LOOPEN = 0 is set to switch the selector 100 to the “0” input terminal, the shift mode signal SM is set to 1, the selectors 10, 11, and 12 are switched to the “1” input terminal, and the test mode signal TEST2 is set. = 1, and switches the selectors 60, 61, 62 to the "1" input terminal.

  When a clock is applied to flip-flops 30, 31, and 32 three times, 3-bit test data from the SI terminal is stored in flip-flops 30, 31, and 32 by a serial shift operation. However, since the flip-flop 31 stores the inverted test data, when "101" is shifted in from the SI terminal, the outputs of the flip-flops 30, 31, and 32 become "111". The outputs of flip-flops 30, 31, and 32 are inverted by inverters 40, 41, and 42, selected by selectors 10, 11, and 12, and data "000" is transmitted to input terminals DI0, DI1, and DI2 of RAM 91.

  Next, the loop enable signal LOOPEN = 1 is set, the selector 100 is switched to the “1” input terminal, and each time the clock is supplied to the flip-flops 30, 31, 32, the input terminal DI0 of the RAM 91 is controlled by the inverters 40, 41, 42. , DI1 and DI2 change, and the state of “000” and the state of “111” are repeated. When desired test data “000” or “111” is set, writing is performed on the RAM 91. The writing of the test data in the RAM 91 is repeated a plurality of times while changing the address.

  Next, a case where a read and write test is performed on a specific address of the RAM 91 will be described. The loop enable signal LOOPEN = 1 is set to switch the selector 100 to the “1” input terminal, the shift mode signal SM is set to 1, the selectors 10, 11, and 12 are switched to the “1” input terminal, and the test mode signal TEST2 is set. = 0, and switches the selectors 60, 61, 62 to the "0" input terminal.

  When a read test is performed on a specific address of the RAM 91, data of the test result is output to the output terminals DO0, DO1, and DO2 of the RAM 91, and transmitted to the input of the gate circuit 110 via the selectors 60, 61, and 62, respectively. . At this time, if the test result data is “111”, the monitor signal MONI output from the gate circuit 110 becomes “1”. If the test result data is other than “111”, the monitor signal MONI becomes “1”. 0 ". Therefore, if the monitor signal MONI is checked, it can be determined whether or not the test result data from the output terminals DO0, DO1 and DO2 of the RAM 91 is "111" without shifting out from the SO terminal.

  Next, when a clock is applied once to the flip-flops 30, 31, and 32, the flip-flops 30, 31, and 32 store the data of the test results. Next, when the test mode signal TEST2 = 1 is set and the selectors 60, 61, 62 are switched to the "1" input terminals, the data stored in the flip-flops 30, 31, 32 are converted by the inverters 42, 40, 41. The signal is inverted, selected by the selectors 12, 10, 11 and transmitted to the input terminals DI2, DI0, DI1 of the RAM 91, and transmitted to the "1" input terminals of the selectors 60, 61, 62. In this case, the data stored in the flip-flop 32 passes through the “1” input terminal of the selector 100.

  At this time, if the test result data of the RAM 91 is “000”, the monitor signal MONI output from the gate circuit 110 becomes “1”, and if the test result data of the RAM 91 is other than “000”, the monitor signal The signal MONI becomes "0". Therefore, if the monitor signal MONI is checked, it can be determined whether or not the test result data from the output terminals DO0, DO1, DO2 of the RAM 91 is "000" without shifting out from the SO terminal.

  Next, the inverted data of the test result (“000” or “111” when no failure occurs) is written to the RAM 91. Note that the read and write tests of the RAM 91 are repeated a plurality of times while changing the address.

  As described above, according to the thirteenth embodiment, the test can be performed by the RAM 91 alone without increasing the scale of the test circuit, and the test data to be written in the RAM 91 can be all 0 (“000”) or all 1 ( "111") in one clock cycle, so that the test of the RAM 91 can be performed efficiently.

  Further, according to the thirteenth embodiment, the loop enable signal LOOPEN = 0 is set, and test data such as “111” or “000” is shifted in from the SI terminal to the flip-flops 30, 31, and 32, After that, if the loop enable signal LOOPEN = 1 is switched, the input terminals DI0 to DI2 of the RAM 91 alternately repeat the state of "111" and "000" every time a clock is supplied to the flip-flops 30, 31, and 32. It is not necessary to newly provide test data from the SI terminal, and the effect that the test of the RAM 91 can be facilitated is obtained.

  Further, according to the thirteenth embodiment, the test whether the data of the test result from the output terminals DO0, DO1, DO2 of the RAM 91 is "111" and the test whether the data is "000" are performed from the SO terminal. Since the monitoring can be performed only by checking the monitor signal MONI without shifting out, the effect of facilitating the test of the RAM 91 can be obtained.

  Further, according to the thirteenth embodiment, an effect is obtained that the flip-flops 30, 31, and 32 can be used as output registers of the RAM 91 during normal operation without increasing the circuit scale during normal operation.

Embodiment 14 FIG.
FIG. 14 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 14 of the present invention. In the fourteenth embodiment, as shown in FIG. 14, the gate circuit 110 of the thirteenth embodiment shown in FIG. Have moved as. The gate circuit 114 detects that the output data of the inverters 40, 41, and 42 have the same value, and the RAM 91 may be tested in consideration of this. Although an AND gate is used as the gate circuit 114 in FIG. 14, any one of a NAND gate, an OR gate, and a NOR gate may be used. In FIG. 14, the flip-flops 30, 31, and 32 can be used as output registers of the RAM 91 during normal operation, as in FIG.

Next, the operation will be described.
The operations during the normal operation and during the scan test of the logic units 80 and 81 are the same as those in the thirteenth embodiment. Further, the operation in the case of performing a test of writing initial data to the RAM 91 in the test of the RAM 91 is the same as that of the thirteenth embodiment.

  Next, a case where a read and write test is performed on a specific address of the RAM 91 will be described. The loop enable signal LOOPEN = 1 is set to switch the selector 100 to the “1” input terminal, the shift mode signal SM is set to 1, the selectors 10, 11, and 12 are switched to the “1” input terminal, and the test mode signal TEST2 is set. = 0, and switches the selectors 60, 61, 62 to the "0" input terminal.

  When a read test is performed for a specific address of the RAM 91, data of the test result is output to the output terminals DO0, DO1, and DO2 of the RAM 91, and the data of the flip-flops 30, 31, and 32 are output via the selectors 60, 61, and 62, respectively. Conveyed to the input. When a clock is applied to flip-flops 30, 31, and 32 once, flip-flops 30, 31, and 32 store the data of the test results. The test result data stored in the flip-flops 30, 31, 32 is inverted by the inverters 40, 41, 42 and transmitted to the input of the gate circuit 114.

  At this time, if the test result data is “000”, the monitor signal MONI output from the gate circuit 114 becomes “1”. If the test result data is other than “000”, the monitor signal MONI becomes “1”. 0 ". Therefore, if the monitor signal MONI is checked, it can be determined whether or not the test result data from the output terminals DO0, DO1, DO2 of the RAM 91 is "000" without shifting out from the SO terminal.

  Next, the test mode signal TEST2 = 1 is set, the selectors 60, 61, and 62 are switched to the "1" input terminals. Once applied, the data stored in flip-flops 30, 31, and 32 are inverted by inverters 42, 40, and 41, selected by selectors 12, 10, and 11, and "1" of selectors 60, 61, and 62. Via the input terminal, the data is taken into the flip-flops 30, 31, 32 and output. In this case, the data stored in the flip-flop 32 passes through the “1” input terminal of the selector 100.

  Since the output data of the flip-flops 30, 31, and 32 are inverted by the inverters 40, 41, and 42 and transmitted to the input of the gate circuit 114, the output of the flip-flops 30, 31, and 32 is "000" (data of the test result). Is "111"), the monitor signal MONI output from the gate circuit 114 becomes "1". If the test result data in the RAM 91 is other than "111", the monitor signal MONI becomes "0". Become. Therefore, if the monitor signal MONI is checked, it can be determined whether or not the test result data from the output terminals DO0, DO1 and DO2 of the RAM 91 is "111" without shifting out from the SO terminal. Note that the read and write tests of the RAM 91 are repeated a plurality of times while changing the address.

  As described above, according to the fourteenth embodiment, the test can be performed by the RAM 91 alone without increasing the scale of the test circuit, and the test data to be written into the RAM 91 can be all 0 (“000”) or all 1 ( "111") in one clock cycle, so that the test of the RAM 91 can be performed efficiently.

  Further, according to the fourteenth embodiment, the loop enable signal LOOPEN = 0 is set, and test data such as "111" or "000" is shifted in from the SI terminal to the flip-flops 30, 31, and 32, After that, if the loop enable signal LOOPEN = 1 is switched, the input terminals DI0 to DI2 of the RAM 91 alternately repeat the state of "111" and "000" every time a clock is supplied to the flip-flops 30, 31, and 32. It is not necessary to newly provide test data from the SI terminal, and the effect that the test of the RAM 91 can be facilitated is obtained.

  Further, according to the fourteenth embodiment, a test as to whether the test result data from the output terminals DO0, DO1, DO2 of the RAM 91 is "111" and a test as to whether the data is "000" are performed from the SO terminal. Since the monitoring can be performed only by checking the monitor signal MONI without shifting out, the effect of facilitating the test of the RAM 91 can be obtained.

  Further, according to the fourteenth embodiment, the effect is obtained that the flip-flops 30, 31, 32 can be used as output registers of the RAM 91 during normal operation without increasing the circuit scale during normal operation.

Embodiment 15 FIG.
FIG. 15 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 15 of the present invention. In the fifteenth embodiment, as shown in FIG. 15, the gate circuit 110 shown in FIG. 13 of the thirteenth embodiment is changed from the output side of the selectors 60, 61, 62 to the output side of the selectors 10, 11, 12. Have moved as. The gate circuit 115 detects that the output data of the selectors 10, 11, and 12 have the same value, and the test of the RAM 91 may be performed in consideration of this. Although an AND gate is used as the gate circuit 115 in FIG. 15, any one of a NAND gate, an OR gate, and a NOR gate may be used. In FIG. 15, as in FIG. 13, the flip-flops 30, 31, and 32 can be used as output registers of the RAM 91 during normal operation.

Next, the operation will be described.
The operations during the normal operation and during the scan test of the logic units 80 and 81 are the same as those in the thirteenth embodiment. Further, the operation in the case of performing a test of writing initial data to the RAM 91 in the test of the RAM 91 is the same as that of the thirteenth embodiment.

  Next, a case where a read and write test is performed on a specific address of the RAM 91 will be described. The loop enable signal LOOPEN = 1 is set to switch the selector 100 to the “1” input terminal, the shift mode signal SM is set to 1, the selectors 10, 11, and 12 are switched to the “1” input terminal, and the test mode signal TEST2 is set. = 0, and switches the selectors 60, 61, 62 to the "0" input terminal.

  When a read test is performed for a specific address of the RAM 91, data of the test result is output to the output terminals DO0, DO1, and DO2 of the RAM 91, and the data of the flip-flops 30, 31, and 32 are output via the selectors 60, 61, and 62, respectively. Conveyed to the input. When a clock is applied to flip-flops 30, 31, and 32 once, flip-flops 30, 31, and 32 store the data of the test results. The test result data stored in the flip-flops 30, 31, and 32 are inverted by the inverters 40, 41, and 42, and transmitted to the inputs of the gate circuit 115 via the selectors 10, 11, and 12.

  At this time, if the test result data is “000”, the monitor signal MONI output from the gate circuit 115 becomes “1”, and if the test result data is other than “000”, the monitor signal MONI becomes “1”. 0 ". Therefore, if the monitor signal MONI is checked, it can be determined whether or not the test result data from the output terminals DO0, DO1, DO2 of the RAM 91 is "000" without shifting out from the SO terminal.

  Next, the test mode signal TEST2 = 1 is set, the selectors 60, 61, and 62 are switched to the "1" input terminals. Once applied, the data stored in flip-flops 30, 31, and 32 are inverted by inverters 42, 40, and 41, selected by selectors 12, 10, and 11, and "1" of selectors 60, 61, and 62. Via the input terminal, the data is taken into the flip-flops 30, 31, 32 and output. In this case, the data stored in the flip-flop 32 passes through the “1” input terminal of the selector 100.

  The output data of the flip-flops 30, 31, and 32 are inverted by the inverters 40, 41, and 42 and transmitted to the input of the gate circuit 115 via the selectors 10, 11, and 12, so that the outputs of the flip-flops 30, 31, and 32 are output. Is "000" (the test result data is "111"), the monitor signal MONI output from the gate circuit 115 is "1", and if the test result data in the RAM 91 is other than "111". , The monitor signal MONI becomes “0”. Therefore, if the monitor signal MONI is checked, it can be determined whether or not the test result data from the output terminals DO0, DO1 and DO2 of the RAM 91 is "111" without shifting out from the SO terminal. Note that the read and write tests of the RAM 91 are repeated a plurality of times while changing the address.

  As described above, according to the fifteenth embodiment, the test can be performed by the RAM 91 alone without increasing the scale of the test circuit, and the test data to be written into the RAM 91 can be all 0 (“000”) or all 1 ( "111") in one clock cycle, so that the test of the RAM 91 can be performed efficiently.

  Further, according to the fifteenth embodiment, the loop enable signal LOOPEN = 0 is set, and test data such as "111" or "000" is shifted in from the SI terminal to the flip-flops 30, 31, and 32, After that, if the loop enable signal LOOPEN = 1 is switched, the input terminals DI0 to DI2 of the RAM 91 alternately repeat the state of "111" and "000" every time a clock is supplied to the flip-flops 30, 31, and 32. , There is no need to newly provide test data from the SI terminal, and the effect of facilitating the test of the RAM 91 is obtained.

  Further, according to the fifteenth embodiment, a test as to whether the test result data from the output terminals DO0, DO1, DO2 of the RAM 91 is "111" and a test as to whether the test result data is "000" are made from the SO terminal. Since the monitoring can be performed only by checking the monitor signal MONI without shifting out, the effect of facilitating the test of the RAM 91 can be obtained.

  Further, according to the fifteenth embodiment, an effect is obtained that the flip-flops 30, 31, and 32 can be used as output registers of the RAM 91 during normal operation without increasing the circuit scale during normal operation.

Embodiment 16 FIG.
FIG. 16 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 16 of the present invention. In the sixteenth embodiment, as shown in FIG. 16, the gate circuit 110 in the thirteenth embodiment shown in FIG. It has moved as 116. The gate circuit 116 detects that the output data of the flip-flops 30, 31, and 32 have the same value, and the test of the RAM 91 may be performed in consideration of this. Although an AND gate is used as the gate circuit 116 in FIG. 16, any one of a NAND gate, an OR gate, and a NOR gate may be used. In FIG. 16, as in FIG. 13, the flip-flops 30, 31, and 32 can be used as output registers of the RAM 91 during normal operation.

Next, the operation will be described.
The operations during the normal operation and during the scan test of the logic units 80 and 81 are the same as those in the thirteenth embodiment. Further, the operation in the case of performing a test of writing initial data to the RAM 91 in the test of the RAM 91 is the same as that of the thirteenth embodiment.

  Next, a case where a read and write test is performed on a specific address of the RAM 91 will be described. The loop enable signal LOOPEN = 1 is set to switch the selector 100 to the “1” input terminal, the shift mode signal SM is set to 1, the selectors 10, 11, and 12 are switched to the “1” input terminal, and the test mode signal TEST2 is set. = 0, and switches the selectors 60, 61, 62 to the "0" input terminal.

  When a read test is performed for a specific address of the RAM 91, data of the test result is output to the output terminals DO0, DO1, and DO2 of the RAM 91, and the data of the flip-flops 30, 31, and 32 are output via the selectors 60, 61, and 62, respectively. Conveyed to the input. When a clock is applied to flip-flops 30, 31, and 32 once, flip-flops 30, 31, and 32 store the data of the test results. The data of the test result stored in the flip-flops 30, 31, and 32 is transmitted to the input of the gate circuit.

  At this time, if the test result data is "111", the monitor signal MONI output from the gate circuit 116 becomes "1". If the test result data is other than "111", the monitor signal MONI becomes "1". 0 ". Therefore, if the monitor signal MONI is checked, it can be determined whether or not the test result data from the output terminals DO0, DO1 and DO2 of the RAM 91 is "111" without shifting out from the SO terminal.

  Next, the test mode signal TEST2 = 1 is set, the selectors 60, 61, and 62 are switched to the "1" input terminals. Once applied, the data stored in flip-flops 30, 31, and 32 are inverted by inverters 42, 40, and 41, selected by selectors 12, 10, and 11, and "1" of selectors 60, 61, and 62. Via the input terminal, the data is taken into the flip-flops 30, 31, 32 and output. In this case, the data stored in the flip-flop 32 passes through the “1” input terminal of the selector 100.

  Since the output data of the flip-flops 30, 31, and 32 are transmitted to the input of the gate circuit 116, when the output of the flip-flops 30, 31, and 32 is "111" (the data of the test result is "000"), The monitor signal MONI output from the gate circuit 116 becomes "1", and if the test result data in the RAM 91 is other than "000", the monitor signal MONI becomes "0". Therefore, if the monitor signal MONI is checked, it can be determined whether or not the test result data from the output terminals DO0, DO1, DO2 of the RAM 91 is "000" without shifting out from the SO terminal. Note that the read and write tests of the RAM 91 are repeated a plurality of times while changing the address.

  As described above, according to the sixteenth embodiment, the test can be performed by the RAM 91 alone without increasing the scale of the test circuit, and the test data written to the RAM 91 can be all 0 (“000”) or all 1 ( "111") in one clock cycle, so that the test of the RAM 91 can be performed efficiently.

  Further, according to the sixteenth embodiment, the loop enable signal LOOPEN = 0 is set, and test data such as "111" or "000" is shifted in from the SI terminal into the flip-flops 30, 31, and 32, After that, if the loop enable signal LOOPEN = 1 is switched, the input terminals DI0 to DI2 of the RAM 91 alternately repeat the state of "111" and "000" every time a clock is supplied to the flip-flops 30, 31, and 32. , There is no need to newly provide test data from the SI terminal, and the effect of facilitating the test of the RAM 91 is obtained.

  Further, according to the sixteenth embodiment, a test as to whether the test result data from the output terminals DO0, DO1, DO2 of the RAM 91 is "111" and a test as to whether the data is "000" are performed from the SO terminal. Since the monitoring can be performed only by checking the monitor signal MONI without shifting out, the effect of facilitating the test of the RAM 91 can be obtained.

  Further, according to the sixteenth embodiment, an effect is obtained that the flip-flops 30, 31, and 32 can be used as output registers of the RAM 91 during normal operation without increasing the circuit scale during normal operation.

Embodiment 17 FIG.
FIG. 17 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 17 of the present invention. In the seventeenth embodiment, as shown in FIG. 17, the selectors 10, 11, 12 and the selectors 60, 61, 62 in FIG. 8 of the eighth embodiment are replaced with AND-OR composite gate type selectors 10a, 11a, 12a and Change to AND-OR composite gate type selectors 60a, 61a, 62a, AND-OR composite gate type selectors 10a, 11a, 12a are controlled by shift mode signals SMA, SMB, and composite gate type selectors 60a, 61a, 62a are tested. Controlled by the mode signals TEST2A and 2B.

Next, the operation will be described.
The operation at the time of the normal operation is basically the same as that of the eighth embodiment. However, in FIG. 17, the shift mode signal SMA = 0 and the shift mode signal SMB = 1 are set, and the AND-OR composite gate type selectors 10a, 11a and 12a select the output of the logic 80, and the test mode signal TEST2A = 0, the test mode signal TEST2B = 1 is set, and the composite gate selectors 60a, 61a, 62a select the output of the RAM 91, so that the RAM 91 is inserted between the logic section 80 and the logic section 81. It becomes. Also, during normal operation, it is not necessary to apply a clock to the flip-flops 30, 31, 32.

  The operation of the logic units 80 and 81 at the time of the scan test is basically the same as in the eighth embodiment. However, in FIG. 17, the loop enable signal LOOPEN = 0 is set, the selector 100 is switched to the “0” input terminal, the test mode signal TEST2A = 1, the test mode signal TEST2B = 0, and the composite gate type selector 60a is set. , 61a, and 62a select a scan path, whereby the RAM 91 is bypassed, and the scan path is inserted between the logic unit 80 and the logic unit 81. In this state, the scan tests of the logic units 80 and 81 are performed by controlling the shift mode signals SMA and SMB.

  When a scan test of the logic unit 81 is performed, the shift mode signal SMA = 1 and the shift mode signal SMB = 0 are set, and a clock is applied to the flip-flops 30, 31, and 32 twice. Bit test data is stored in flip-flops 30 and 31 by a serial shift operation.

  Since the test mode signal TEST2A is set to 1, the next 1-bit test data of the SI terminal is selected by the composite gate type selector 60a, input to the logic unit 81, and stored in the flip-flops 30 and 31. The 1-bit test data is selected by the composite gate type selectors 61a and 62a and input to the logic unit 81, and a scan test of the logic unit 81 is performed by a total of 3-bit test data.

  When performing a scan test of the logic unit 80, the shift mode signal SMA = 0 and the shift mode signal SMB = 1 are set, and a clock is applied to the flip-flops 30, 31, and 32 once, and test data is input. The 3-bit data of the test result from the logic unit 80 is stored in the flip-flops 30, 31, and 32, respectively. At this time, the 1-bit data stored in the flip-flop 32 is output to the SO terminal.

  Next, when the shift mode signal SMA = 1 and the shift mode signal SMB = 0 are set and the clock is applied to the flip-flops 30, 31, and 32 twice, the 1-bit data stored in the flip-flops 30, 31 becomes The data is shifted out to the SO terminal, and the contents of the data of a total of 3 bits are confirmed. In this case, the next test data for the logic unit 81 can be stored in the flip-flops 30 and 31 from the SI terminal. The scan tests of the logic unit 80 and the logic unit 81 are repeated a plurality of times by changing the input test data.

  At the time of testing the RAM 91, the data written in the RAM 91 can be easily controlled by utilizing the states of the shift mode signals SMA = 0 and SMB = 0 and the states of the test mode signals TEST2A = 0 and TEST2B = 0. Specifically, by setting the shift mode signals SMA = 0 and SMB = 0, the input data to the input terminals DI0, DI1, and DI2 of the RAM 91 can be set to the state of “000”. Also, by setting the shift mode signal SMA = 1, the test mode signals TEST2A = 0, and TEST2B = 0, the input data to the input terminals DI0, DI1, and DI2 of the RAM 91 can be set to the state of “111”. That is, in the seventeenth embodiment, it is unnecessary to set the write data by the scan path serial shift operation.

  An operation in the case of performing a test of writing initial data to the RAM 91 in the test of the RAM 91 will be described. By setting the shift mode signals SMA = 0 and SMB = 0, the initial data to the input terminals DI0, DI1, and DI2 of the RAM 91 is set to “000”, and the initial data “000” is written. Further, by setting the shift mode signal SMA = 1, the test mode signal TEST2A = 0, and the test mode signal TEST2B = 0, the initial data to the input terminals DI0, DI1, and DI2 of the RAM 91 is set to the state of “111”. "111" is written. The operation of writing the initial data is performed a plurality of times while changing the address.

  Next, a case where a read and write test is performed on a specific address of the RAM 91 will be described. The loop enable signal LOOPEN = 1, the shift mode signals SMA = 1, SMB = 0, the test mode signal TEST2A = 0, and the test mode signal TEST2B = 1 are set.

  When a read test is performed for a specific address of the RAM 91, the data of the test result is output to the output terminals DO0, DO1, and DO2 of the RAM 91, and is input to the gate circuit 110 via the composite gate type selectors 60a, 61a, and 62a, respectively. Conveyed to. At this time, if the test result data is “111”, the monitor signal MONI output from the gate circuit 110 becomes “1”. If the test result data is other than “111”, the monitor signal MONI becomes “1”. 0 ". Therefore, if the monitor signal MONI is checked, it can be determined whether or not the test result data from the output terminals DO0, DO1 and DO2 of the RAM 91 is "111" without shifting out from the SO terminal.

  The test result data from the output terminals DO0, DO1 and DO2 of the RAM 91 are inverted by the inverters 40, 41 and 42, and input to the input terminals DI0 and DI0 of the RAM 91 via the AND-OR composite gate type selectors 10a, 11a and 12a. DI1 and DI2. Next, when the inverted data of the test result is written into the RAM 91 and one clock is applied to the flip-flops 30, 31, and 32, the flip-flops 30, 31, and 32 store the inverted data of the test result. Next, the test mode signal TEST2A = 1 and the test mode signal TEST2B = 0 are set, and the inverted data of the test results stored in the flip-flops 30, 31, and 32 are respectively passed through the composite gate type selectors 60a, 61a and 62a. To the input of the gate circuit 110. In this case, the data stored in the flip-flop 32 passes through the “1” input terminal of the selector 100.

  If the data of the test result is “000”, the input of the gate circuit 110 becomes “111”, the monitor signal MONI output from the gate circuit 110 becomes “1”, and the data of the test result is other than “000”. If there is, the monitor signal MONI becomes "0". Therefore, by checking the monitor signal MONI, it can be determined whether or not the test result data output from the output terminals DO0, DO1, DO2 of the RAM 91 is "000" without shifting out from the SO terminal. it can. Note that the read and write tests of the RAM 91 are repeated a plurality of times while changing the address.

  As described above, according to the seventeenth embodiment, the RAM 91 can be tested alone without increasing the scale of the test circuit. When the RAM 91 is tested, the state of the shift mode signals SMA = 0, SMB = 0 and By utilizing the states of the test mode signals TEST2A = 0 and TEST2B = 0, the setting of the write data by the serial shift operation of the scan path becomes unnecessary, and the write data of the RAM 91 can be easily controlled. The effect is obtained that a clock need not be applied to the flip-flops 30, 31, and 32.

  According to the seventeenth embodiment, a test as to whether the test result data from the output terminals DO0, DO1, and DO2 of the RAM 91 is “111” and a test as to whether the data is “000” are performed from the SO terminal. Since the monitoring can be performed only by checking the monitor signal MONI without shifting out, the effect of facilitating the test of the RAM 91 can be obtained.

Embodiment 18 FIG.
FIG. 18 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 18 of the present invention. In the eighteenth embodiment, as shown in FIG. 18, the AND-OR composite gate type selectors 60a, 61a, 62a in FIG. 17 of the seventeenth embodiment are changed to AND-NOR composite gate type selectors 60b, 61b, 62b. Then, the inverters 40, 41, and 42 inserted in the scan path in FIG. 17 are deleted, and the inverters 40a, 41a, and 42a are provided on the path from the outputs of the AND-NOR composite gate selectors 60b, 61b, and 62c to the logic unit 81. Has been added.

Next, the operation will be described.
Since the AND-NOR composite gate type selectors 60b, 61b, and 62b include the function of an inverter, the inverters 40, 41, and 42 inserted in the scan path in FIG. 17 become unnecessary. The outputs of the AND-NOR composite gate type selectors 60b, 61b, 62b are connected to the inverters 40a, 41a so that the test result data from the output terminals DO0, DO1, DO2 of the RAM 91 are not inverted and transmitted to the logic unit 81. , 42a to the logic unit 81. If the test result data from the output terminals DO0, DO1 and DO2 of the RAM 91 can be inverted and transmitted to the logic unit 81, the inverters 40a, 41a and 42a are deleted. Other operations are the same as in the seventeenth embodiment.

  As described above, according to the eighteenth embodiment, the same effects as in the seventeenth embodiment can be obtained.

Embodiment 19 FIG.
FIG. 19 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 19 of the present invention. Although FIG. 8 of the eighth embodiment is directed to a 3-bit RAM 91, the nineteenth embodiment is directed to a 4-bit RAM 91a as shown in FIG. That is, the input terminals of the RAM 91a are DI0, DI1, DI2, and DI3, the output terminals are DO0, DO1, DO2, and DO3. The selector 13, the selector 63, the flip-flop 33, and the inverter 43 are added. The input terminal of the logic unit 80 has 4 bits, and the gate circuit 110 in FIG. 8 of the eighth embodiment is composed of three gate circuits 110a, 110b, and 110c. The input of the gate circuit 110a is connected to the outputs of the selectors 60 and 62, the input of the gate circuit 110b is connected to the outputs of the selectors 61 and 63, and the input of the gate circuit 110c is connected to the outputs of the gate circuits 110a and 110b. The output of the circuit 110c corresponds to the output of the gate circuit 110 in FIG.

Next, the operation will be described.
For example, by monitoring the output MONIA of the gate circuit 110a with the test mode signal TEST2 = 0 at the time of testing the RAM 91a, it is possible to test whether there is a failure with respect to the even-numbered bit outputs DO0 and DO2 of the RAM 91a. Similarly, by monitoring the output MONIB of the gate circuit 110b, it is possible to test whether or not there is a failure with respect to the odd-numbered bit outputs DO1 and DO3 of the RAM 91a. That is, in the nineteenth embodiment, compared to the eighth embodiment, a function capable of determining whether the failure position of the RAM 91a is an even-numbered bit or an odd-numbered bit is added, so that a more detailed failure diagnosis of the RAM 91a can be performed. . Other operations are the same as in the eighth embodiment.

  As described above, according to the nineteenth embodiment, in addition to the effect of the eighth embodiment, an effect is obtained that a more detailed failure diagnosis of the RAM 91a can be performed.

Embodiment 20 FIG.
FIG. 20 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 20 of the present invention. In the twentieth embodiment, as shown in FIG. 20, a fail flag generation circuit (FAIL FLAG GENEATOR) 120 and an OR circuit 130 are added to FIG. 8 of the eighth embodiment to facilitate failure diagnosis of the RAM 91. To do. The fail flag generation circuit 120 includes an inverter 121, an AND circuit 122, an OR circuit 123, an AND circuit 124, and a flip-flop 125.

  In the fail flag generation circuit 120 shown in FIG. 20, the compare enable signal CMPEN is basically set to the compare enable signal CMPEN = 1 when it is expected that the monitor signal MONI = 1 at the time of the RAM test. When the monitor signal MONI is uncertain or when the monitor signal MONI = 0 is expected, the compare enable signal CMPEN = 0 is set, and the comparison operation of the monitor signal MONI becomes a mask state. The fail monitor signal FAILMONI is output to, for example, a self-test control circuit mounted inside the LSI in order to determine the presence or absence of a failure in real time. That is, in the state where the conveyor enable signal CMPEN = 1 is set, if a failure occurs unexpectedly, the monitor signal MONI = 0, and the fail monitor signal FAILMONI = 1 is output.

  When the reset signal RESETL = 0 is set and a clock is applied to the flip-flop 125, the flip-flop 125 is reset to “0”. The fail flag signal FAILFLAG is output to, for example, a self-test control circuit mounted inside the LSI in order to determine the test result of the RAM. If there is no failure, a fail monitor signal FAILMONI = 0, and if there is a failure, the fail monitor signal FAILMONI = 0 FAILMONI = 1. Once the fail flag signal FAILFLAG = 1, an OR circuit 123 is provided in the fail flag generation circuit 120 so that the state is maintained.

  The OR circuit 130 outputs a test mode signal TEST2 to the selectors 60, 61, 62 in response to an external test mode signal TEST2A or a fail flag signal FAILFLAG.

Next, the operation will be described.
At the time of failure diagnosis of the RAM 91, a clock is applied to the flip-flop 125 in the fail flag generation circuit 120 with the reset signal RSETL = 0, and the fail flag signal FAILFLAG = 0 is set. Next, the reset signal RSETL is set to 1 and a test of the RAM 91 as described with reference to FIG.

  When the monitor signal MONI = 0 from the gate circuit 110 due to a failure, the output of the AND circuit 124 becomes “1”. When a clock is applied to the flip-flop 125, the output becomes the fail flag signal FAILFLAG = 1. At the same time, the test mode signal TEST2 = 1 is set, and the selectors 60, 61, and 62 are switched to "1" input terminals. At this time, a clock is also applied to the flip-flops 30, 31, and 32 to store the fault data. Here, the subsequent RAM test is canceled, and a failure analysis operation for investigating the cause of the failure flag signal FAILFLAG = 1 is performed by, for example, a self-test control circuit mounted inside the LSI.

  At the time of the test of the RAM 91, the shift mode signal SM is set to 1, so that the flip-flop 30 is set in a state where the loop enable signal LOOPEN = 1, the test mode signal TEST2 = 1, and the shift mode signal SM = 1. , 31, and 32, the fault data is held in a loop-connected circular shift register of the three flip-flops 30, 31, and 32 in the serial shift path of the scan path. If the exact number of clocks is known, it is possible to shift out data including the failure data from the SO terminal and analyze which data bit has failed.

  For example, a case where the test is performed in the order of address 0, address 1, address 2, address 3,... Of the RAM 91 will be described. After the first failure is detected at address 1, the fail flag signal FAILFLAG = 1, and the operation proceeds to the failure analysis operation. The data including the fault data held in the loop-connected circular shift register of the three flip-flops 30, 31, and 32 is shifted out from the SO terminal.

  When the test for detecting the second failure is performed, the operation is started from the operation of resetting the fail flag signal FAILFLAG. However, when the addresses 0 and 1 are tested, the compare enable signal CMPEN is set to 0 and the comparison operation is in a masked state. The control for setting the compare enable signal CMPEN = 0 is performed, for example, based on the address of the first failure stored in the self-test control circuit. Since the compare enable signal CMPEN is set to 0 at the time of testing the addresses 0 and 1, the fail monitor signal FAILMONI is forcibly set to "0" and becomes a mask state regardless of the value of the monitor signal MONI.

  In the test after the address 2, the comparison operation is performed by appropriately controlling the compare enable signal CMPEN. For example, when the second fault exists at the address 3, the fail flag signal FAILFLAG = 1 at the time of the test of the address 3, and at this time, the operation proceeds to the fault analysis operation, and the loop of the three flip-flops 30, 31, and 32 is performed. Data including the failure data held in the connected circular shift register is shifted out from the SO terminal.

  When the RAM 91 is a RAM with a redundancy function, these failure data can be used as switching control data for the redundancy circuit.

  As described above, according to the twentieth embodiment, in addition to the effects of the eighth embodiment, the fail flag signal FAILFLAG is generated by the fail flag generation circuit 120, and the failure data in the RAM 91 is stored in the flip-flops 30, 31, and 32. After the test is completed or after the test is interrupted, the failure data is shifted out from the SO terminal, whereby an effect is obtained that a detailed diagnosis regarding the detected failure can be performed.

  The embodiment of the present invention does not need to be applied to all of the input / output terminals of the functional block 90 or the RAM 91, and is effective even by partial application. For example, when the number of input terminals and the number of output terminals of the functional block 90 are different, a pair may be formed in accordance with the smaller number to implement the present invention.

FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 9 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 13 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 3 of the present invention. FIG. 14 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 4 of the present invention. FIG. 15 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 5 of the present invention. FIG. 15 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 6 of the present invention. FIG. 15 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 7 of the present invention. FIG. 15 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to an eighth embodiment of the present invention. FIG. 15 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 9 of the present invention. FIG. 15 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 10 of the present invention. FIG. 21 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 11 of the present invention. FIG. 21 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 12 of the present invention. FIG. 21 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 13 of the present invention. FIG. 24 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 14 of the present invention. FIG. 15 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 15 of the present invention. FIG. 26 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 16 of the present invention. FIG. 21 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 17 of the present invention. FIG. 28 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 18 of the present invention. FIG. 35 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 19 of the present invention. FIG. 21 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 20 of the present invention. FIG. 9 is a circuit diagram illustrating a configuration of a conventional semiconductor integrated circuit device. FIG. 9 is a circuit diagram illustrating a configuration of a conventional semiconductor integrated circuit device.

Explanation of reference numerals

  10, 11, 12, 13 selector, 10a, 11a, 12a AND-OR composite gate type selector, 20, 21, 22, inverter, 30, 31, 32, 33 flip-flop, 40, 41, 42, 43 inverter, 40a, 41a, 42a inverter, 60, 61, 62, 63 selector, 60a, 61a, 62a AND-OR composite gate type selector, 60b, 61b, 62b AND-NOR composite gate type selector, 80, 81 logic unit, 90 functional block, 91 RAM, 91a RAM, 100 selector, 110, 111, 112, 113, 114, 115, 116 gate circuit, 110a, 110b, 110c gate circuit, 120 fail flag generation circuit, 121 inverter, 122 AND circuit, 123 OR circuit, 24 the AND circuit, 125 a flip-flop 125, 130 OR circuit.

Claims (18)

First and second logic units;
A functional block connected between the first logic unit and the second logic unit;
There is a parallel path between the output of the first logic unit and the input of the functional block and a serial shift path for transmitting data in series, and switching between the output of the first logic unit and the serial shift path. A semiconductor integrated circuit device comprising: a plurality of first selectors for connecting to the input of the functional block; and a scan path including a plurality of flip-flops storing the data.
A plurality of second selectors connected on the serial shift path of the scan path, for switching between the output of the functional block and the serial shift path and connecting to the input of the second logic unit;
Test data is supplied from the serial shift path of the scan path to the function block via the second selector, and the data output from the function block is switched by switching the second selector via the second selector. A semiconductor integrated circuit device for outputting.   2. The semiconductor integrated circuit device according to claim 1, wherein the flip-flop on the serial shift path is connected outside the parallel path between the output of the first logic unit and the input of the functional block.   When the functional block is a RAM (Random Access Memory), a plurality of inverters are inserted on the serial shift path of the scan path in order to change data given to the RAM to all 0s or all 1s in one shift operation. 2. The semiconductor integrated circuit device according to claim 1, wherein:   4. The semiconductor integrated circuit device according to claim 3, wherein the inverter is connected to an output of the second selector.   4. The semiconductor integrated circuit device according to claim 3, wherein the scan path includes a third selector circuit for feeding back the output of the serial shift path to the input of the serial shift path.   6. The semiconductor integrated circuit device according to claim 5, further comprising a gate circuit for detecting that the data from the functional block output via the second selector has a predetermined value.   6. The semiconductor integrated circuit device according to claim 5, further comprising a gate circuit for detecting that the data output from the functional block via the inverter has a predetermined value.   6. The semiconductor integrated circuit device according to claim 5, further comprising a gate circuit for detecting that the data output from the functional block via the first selector has a predetermined value.   6. The semiconductor integrated circuit device according to claim 5, further comprising a gate circuit for detecting that data from the function block stored in the flip-flop is a predetermined value.   2. The semiconductor integrated circuit according to claim 1, wherein an input of a flip-flop on a serial shift path of the scan path is connected to an output of the second selector, and an output of the flip-flop is connected to an input of a second logic unit. Circuit device. When the function block is RAM,
A plurality of inverters inserted on a serial shift path of a scan path to change data given to the RAM to all 0s or all 1s in one shift operation;
A third selector circuit for feeding back the output of the serial shift path of the scan path to the input of the serial shift path;
11. The semiconductor integrated circuit device according to claim 10, further comprising: a gate circuit for detecting that the data output from the RAM via the second selector has a predetermined value. When the function block is RAM,
A plurality of inverters inserted on a serial shift path of a scan path to change data given to the RAM to all 0s or all 1s in one shift operation;
A third selector circuit for feeding back the output of the serial shift path of the scan path to the input of the serial shift path;
11. The semiconductor integrated circuit device according to claim 10, further comprising a gate circuit for detecting that the data output from said RAM via said inverter is a predetermined value. When the function block is RAM,
A plurality of inverters inserted on a serial shift path of a scan path to change data given to the RAM to all 0s or all 1s in one shift operation;
A third selector circuit for feeding back the output of the serial shift path of the scan path to the input of the serial shift path;
11. The semiconductor integrated circuit device according to claim 10, further comprising a gate circuit for detecting that the data output from the RAM via the first selector has a predetermined value. When the function block is RAM,
A plurality of inverters inserted on a serial shift path of a scan path to change data given to the RAM to all 0s or all 1s in one shift operation;
A third selector circuit for feeding back the output of the serial shift path of the scan path to the input of the serial shift path;
11. The semiconductor integrated circuit device according to claim 10, further comprising a gate circuit for detecting that the data from the RAM stored in the flip-flop is a predetermined value. When the function block is RAM,
2. The semiconductor integrated circuit device according to claim 1, wherein an AND-OR composite gate type selector is used as the first selector and the second selector. When the function block is RAM,
2. The semiconductor integrated circuit device according to claim 1, wherein an AND-OR composite gate type selector and an AND-NOR composite gate type selector are used as the first selector and the second selector. When the function block is RAM,
A plurality of inverters inserted on a serial shift path of a scan path to change data given to the RAM to all 0s or all 1s in one shift operation;
A third selector circuit for feeding back the output of the serial shift path of the scan path to the input of the serial shift path;
2. A gate circuit according to claim 1, further comprising: a gate circuit for detecting that the data of the odd-numbered bits and the data of the even-numbered bits output from the RAM via the scan path have a predetermined value. Semiconductor integrated circuit device. When the function block is RAM,
A plurality of inverters inserted on a serial shift path of a scan path to change data given to the RAM to all 0s or all 1s in one shift operation;
A third selector circuit for feeding back the output of the serial shift path of the scan path to the input of the serial shift path;
A gate circuit for detecting that the data output from the RAM via the scan path is a predetermined value,
When the gate circuit detects that the data from the RAM is not a predetermined value, the gate circuit outputs a fail flag signal for canceling the next test of the RAM and performing a failure analysis, and sets the second selector to 2. The semiconductor integrated circuit device according to claim 1, further comprising a fail flag generation circuit for switching to the serial shift path.

Images