JP2004192043A - Memory control device, information processing system equipped with it, and memory control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control device capable of reducing power consumption even when receiving intermittently transferred data or when intermittently transferring data, an information processing system equipped with it, and a memory control method. <P>SOLUTION: This memory control device 21 has an SRAM 5/6 and an SDRAM control part 9, and writes the data intermittently transferred from external devices 1-3 in a plurality of batches in an SDRAM 18 at a writing speed higher than the data transfer rate from the external devices 1-3. The SRAM 5/6 once accumulates the data intermittently transferred in a predetermined number of batches before writing in the SDRAM 18. The SDRAM control part 9 continuously writes the data accumulated in the SRAM 5/6 in the SRAM, and sets the SDRAM 18 to a self-refresh mode while the writing of data to the SDRAM 18 is not carried out. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a memory control device that controls the operation of a memory such as an SDRAM (Synchronous Dynamic Random Access Memory), an information processing system including the same, and a memory control method.
[0002]
[Prior art]
Generally, an information processing system includes a system memory (hereinafter, referred to as a memory) for storing data, a CPU (Central Processing Unit) for controlling various operations of the system and various operations, and an input / output (I / O) for input / output. It has an interface section and the like.
[0003]
For example, considering a controller of a printer that prints an image on paper as an information processing system, the printer controller stores an image data and an interface unit used to receive image data from an external device (for example, a personal computer). It has a memory and an interface unit used for sending image data to the printer engine. In such an information processing system, high-speed processing is required, and high-speed access to a memory is also required.
[0004]
For example, an SDRAM (Synchronous Dynamic Random Access Memory) is often used as a memory in such an information processing system.
[0005]
By the way, the CPU and the memory (SDRAM) cannot be directly connected because the control signal function and the processing method are different from each other. Therefore, using an SDRAM as a memory in an information processing system requires a memory control device that controls access to the memory from a CPU or the like. The CPU or the like accesses the memory via the memory control device.
[0006]
For example, there is a virtual SDRAM that achieves a high-speed system by increasing the speed of data transfer of an external device using a buffer (for example, see Patent Document 1).
[0007]
However, the configuration described in Patent Document 1 is a configuration in a case where the data transfer speed of the SDRAM is lower than the data transfer speed of the external device. Therefore, an SDRAM that can be accessed at high speed by burst access is used, and data transfer from an external device is intermittent, so that the data transfer speed of the external device is higher than that of the SDRAM. If it is slower, it cannot respond.
[0008]
Further, for example, when data is intermittently transferred from an external device, the memory must be activated every time data is transferred, resulting in increased power consumption. However, the configuration described in Patent Document 1 is not a configuration for reducing power consumption.
[0009]
Therefore, for example, there is a memory controller that operates the power-down mode function of the SDRAM by a cache hit / miss to reduce power consumption (for example, see Patent Document 2).
[0010]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2000-21199 (released on January 21, 2000)
[0011]
[Patent Document 2]
Japanese Patent Application Laid-Open No. 2000-148858 (published May 30, 2000)
[0012]
[Problems to be solved by the invention]
However, since the configuration described in Patent Document 2 uses the power-down mode, unlike the self-refresh mode, the memory itself (DRAM: Dynamic Random Access Memory) does not refresh.
[0013]
Therefore, the power down mode cannot be continued for a long time. In the power-down mode, the time required to exit the mode is shorter than in the self-refresh mode, but the effect of reducing power consumption is small.
[0014]
The present invention has been made in view of the above problems, and has as its object to reduce power consumption even when data is transferred intermittently or when data is transferred intermittently. An object of the present invention is to provide a memory control device that can be achieved, an information processing system including the same, and a memory control method.
[0015]
[Means for Solving the Problems]
In order to solve the above-described problem, the memory control device of the present invention transfers data intermittently divided into a plurality of times from an external device to a memory at a writing speed higher than a transfer rate from the external device. A memory control device for writing, comprising: an intermediary buffer for temporarily storing data transferred intermittently from the external device in a predetermined number of times before writing to a memory; And a memory control unit that sets the memory to a self-refresh mode while data is not being written to the memory.
[0016]
Normally, when data transferred from the outside is transferred a plurality of times, if data is written to the memory each time it is transferred, power consumption in the memory increases if the memory is always in operation. In addition, if the memory is set to the self-refresh mode while data is not written to the memory, it takes a long time to return the memory to its original state (operating state) because the mode is switched many times. Also, if the memory is turned on / off each time data is transferred, power is required to start from OFF to ON, for example, and power consumption increases accordingly.
[0017]
However, according to the above configuration, data from the external device is temporarily stored in the mediation buffer, and then writing to the memory is performed continuously (in a short time). Thereby, the time for writing data to the memory can be reduced.
[0018]
Thus, by limiting the access time to the memory, the continuous time during which the memory is not accessed (not written) can be extended.
[0019]
That is, since the setting and release of the self-refresh mode (the self-refresh mode and the normal mode) are not repeated frequently, the time required for changing the mode can be reduced. Therefore, the time during which the self-refresh mode is entered becomes longer, and the ratio of the time zone in the self-refresh mode becomes longer.
[0020]
As a result, the power consumption of the memory can be reduced.
[0021]
In order to solve the above-mentioned problem, a memory control device of the present invention reads data stored in a memory, and transmits the data to an external device at a transfer rate lower than a reading speed from the memory, or A memory control device for transferring data in a plurality of times in response to a transfer request from a device, wherein the mediation buffer temporarily stores data read from the memory before transferring the data to an external device, and Memory control for reading data transferred to the external device in a predetermined number of times continuously from the memory to the intermediary buffer and setting the memory to a self-refresh mode while the data is not read from the memory And a unit.
[0022]
According to the above configuration, the data continuously read from the memory is temporarily stored in the intermediary buffer and then transferred to the outside. As a result, the time for reading data into the memory can be reduced.
[0023]
Thus, by limiting the access time to the memory, the continuous time during which the memory is not accessed (not read) can be extended.
[0024]
Therefore, the time during which the self-refresh mode is entered becomes longer, and the ratio of the time zone in the self-refresh mode becomes longer. As a result, the power consumption of the memory can be reduced.
[0025]
In the above memory control device, the memory is preferably an SDRAM.
[0026]
According to the above configuration, for example, the access time can be shortened by using an SDRAM that can perform burst access and can access at a higher speed than other types of DRAM. Thus, the time of the self-refresh mode can be lengthened, and the power consumption of the memory can be reduced.
[0027]
It is preferable that the memory control device includes a plurality of intermediary buffers and a buffer switching unit that switches the intermediary buffers so that each of the intermediary buffers is sequentially accessed.
[0028]
According to the above configuration, the amount of data that can be stored in the mediation buffer can be increased, and high-speed processing can be performed.
[0029]
In the above memory control device, it is preferable that the memory control unit writes data to the memory while data is not transferred between the external device and the intermediary buffer.
[0030]
According to the above configuration, when the data transfer rate with the external device is low, it is possible to write data to the mediation buffer without switching and using a plurality of mediation buffers.
[0031]
Therefore, since a configuration for switching the mediation buffer is not required, the power consumption of the memory control device can be reduced with a simple configuration.
[0032]
Preferably, the memory control device includes a write timing control unit that manages a write timing for writing data to the memory, and the memory control unit preferably writes data to the memory based on the write timing.
[0033]
According to the above configuration, it is possible to easily set / cancel the self-refresh mode of the memory.
[0034]
In the above memory control device, it is preferable that the memory control unit reads data from the memory while data is not transferred between the external device and the intermediary buffer.
[0035]
According to the above configuration, when the data transfer rate with the external device is low, it is possible to write data to the mediation buffer without switching and using a plurality of mediation buffers.
[0036]
Therefore, since a configuration for switching the mediation buffer is not required, the power consumption of the memory control device can be reduced with a simple configuration.
[0037]
Preferably, the memory control device includes a read timing control unit that manages a read timing for reading data from the memory, and the memory control unit preferably reads data from the memory based on the read timing.
[0038]
According to the above configuration, it is possible to easily set / cancel the self-refresh mode of the memory.
[0039]
In the above memory control device, it is preferable that the access to the memory is a burst access.
[0040]
According to the above configuration, continuous input / output of data to / from the memory becomes possible, so that the access time to the memory can be shortened. Thus, the time of the self-refresh mode can be lengthened, and the power consumption of the memory can be reduced.
[0041]
In the memory control device described above, it is preferable that the amount of data stored in the mediation buffer is a natural number times the burst length in burst access.
[0042]
According to the above configuration, the need for extra data processing (for data less than the burst length for burst access) is eliminated, and control is simplified.
[0043]
An information processing system according to the present invention includes the memory control device described above and a memory whose operation is controlled by the memory control device and stores data to be transferred.
[0044]
According to the above configuration, it is possible to provide a system that is in the self-refresh mode for a long time and has low power consumption.
[0045]
In order to solve the above-mentioned problem, a memory control method of the present invention is a memory for writing data transferred intermittently from an external device in a plurality of times to a memory at a writing speed higher than a transfer rate from the external device. A control method, comprising: temporarily storing data transferred intermittently from an external device in a predetermined number of times in an intermediary buffer before writing to a memory, and then continuously storing the data stored in the intermediary buffer in the memory. On the other hand, while data is not being written to the memory, the memory is set to a self-refresh mode.
[0046]
According to the above-described method, the time for writing data to the memory can be reduced by temporarily storing data from the external device in the intermediary buffer and then performing writing to the memory continuously.
[0047]
Thus, by limiting the access time to the memory, the continuous time during which the memory is not accessed (not written) can be extended. Therefore, the power consumption of the memory can be reduced.
[0048]
In order to solve the above-mentioned problems, the memory control method of the present invention reads out data stored in a memory and sends the data to an external device at a transfer rate lower than the reading speed from the memory, or A memory control method in which data is transferred in a plurality of times in response to a transfer request from a device, wherein the data read from the memory is temporarily stored in a mediation buffer before being transferred to an external device, and is then transferred from the mediation buffer. While the data to be transferred to the external device in a predetermined number of times is continuously read from the memory to the intermediary buffer, the memory is set to a self-refresh mode while the data is not read from the memory. It is characterized by:
[0049]
According to the above method, the data continuously read from the memory is temporarily stored in the intermediary buffer and then intermittently transmitted to the external device (at a predetermined transfer rate set in advance, or when a transfer request is received from the external device). Transferring rows can reduce the time to write data to memory.
[0050]
Thus, by limiting the access time to the memory, the continuous time during which the memory is not accessed (not read) can be extended. Therefore, the power consumption of the memory can be reduced.
[0051]
In the above memory control method, it is preferable to use a plurality of mediation buffers and switch the mediation buffers so that each mediation buffer sequentially accesses the memory.
[0052]
According to the above method, the amount of data that can be stored in the mediation buffer can be increased, and high-speed processing can be performed.
[0053]
In the above memory control method, it is preferable that data be written to the memory while data is not being transferred between the external device and the intermediary buffer.
[0054]
According to the above method, when the transfer rate of data with the external device is low, it is possible to write data in the mediation buffer without switching and using a plurality of mediation buffers.
[0055]
In the above memory control method, it is preferable that data is read from the memory while data is not being transferred between the external device and the intermediary buffer.
[0056]
According to the above method, when the transfer rate of data with the external device is low, it is possible to write data in the mediation buffer without switching and using a plurality of mediation buffers.
[0057]
In the above memory control method, it is preferable to perform burst access to the memory.
[0058]
According to the above method, continuous input / output of data to / from the memory becomes possible, so that the access time to the memory can be shortened. Thus, the time of the self-refresh mode can be lengthened, and the power consumption of the memory can be reduced.
[0059]
In the above memory control method, it is preferable that data of a natural number times the burst length in burst access is temporarily stored in the mediation buffer.
[0060]
According to the above-mentioned method, there is no need to perform extra data processing (for data less than the burst length for burst access), and control is simplified.
[0061]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described below with reference to FIGS.
[0062]
As shown in FIG. 1, the information processing system 20 according to the present embodiment includes an SDRAM (Synchronous Dynamic Random Access Memory) 18, a CPU (Central Processing Unit) 19, and a memory control device 21 on a Main Board. An interface unit (not shown) for performing data transfer with a device (external device) is provided.
[0063]
The memory control device 21 is formed of an ASIC (Application Specific Integrated circuit). The CPU 19 controls the Main Board, that is, the entire information processing system, and performs various settings for each unit on the Main Board. Access to the SDRAM (memory) 18 from the CPU 19 and external devices is performed via the memory control device 21.
[0064]
The memory control device 21 temporarily stores data transferred from the external device, stores the data in the SDRAM 18, and transfers the data from the SDRAM 18 to the connected external device.
[0065]
Data is transferred to the memory controller 21 from external devices such as a charge coupled device (CCD) 1, a HOST PC (hereinafter, referred to as a PC (personal computer)) 2, and an external board 3.
[0066]
The CCD 1 is an image reading unit provided in a scanner or the like, and uses an 8-bit data bus (interface unit) for transferring data (for example, scanner data). The PC 2 outputs print data, and an interface used for transferring data is USB or IEEE 1284 (interface unit). The external board 3 is a board provided for a facsimile (facsimile), and an interface used for data transfer is a handshake local bus (interface section).
[0067]
The memory control device 21 transmits the data stored in the SDRAM 18 to external devices such as an LSU (laser scanner unit) 15, a HOST PC (hereinafter, referred to as a PC (personal computer)) 16, and an external board 17. Forward.
[0068]
The LSU 15 receives serial data and controls printing. The PC 16 receives the scanner data, and the interface used for transferring the data is USB (Universal Serial Bus) or IEEE1284. The external board 17 is a board provided for a facsimile, and an interface used for data transfer is a handshake local bus.
[0069]
The memory control device 21 temporarily buffers data that is transferred intermittently or that needs to be transferred intermittently in SRAMs 5, 6, 11, and 12, which will be described later. Thereby, the memory control device 21 can shorten the access (write / read) time to the SDRAM 18 described later. The memory control device 21 operates the self-refresh mode function of the SDRAM 18 when not accessing the SDRAM 18. Access control to the SDRAM 18 in the memory control device 21 will be described later in detail.
[0070]
The memory control device 21 includes an input data control unit 4, an SRAM (Static Random Access Memory) 5.6, an SRAM control unit 7, a write timing control unit 8, an SDRAM control unit 9, a read timing control unit 10, SRAMs 11 and 12, and an SRAM. A control unit 13 and an output data control unit 14 are provided.
[0071]
The input data control unit 4 controls data input from outside (external devices such as the CCD 1, the PC 2, and the external board 3). That is, the input data control unit 4 inputs the input data to the SRAM 5 or the SRAM 6 via the SRAM control unit 7 described later.
[0072]
The SRAMs 5 and 6 (mediation buffers) buffer input data. That is, the SRAMs 5 and 6 temporarily accumulate data transferred from the external device intermittently at a predetermined number of times before writing to the SDRAM 18.
[0073]
The SRAM control unit 7 is a circuit that controls writing and reading of data to and from the SRAMs 5 and 6 by controlling the SRAMs 5 and 6. That is, the SRAM control unit 7 switches between the SRAMs 5 and 6 that perform writing or reading of input data.
[0074]
The SDRAM control unit 9 controls access to the SDRAM 18. That is, the SDRAM control unit 9 mainly performs writing of data to the SDRAM 18, reading of data from the SDRAM 18, a request for setting / releasing (Entry / Exit) to a self refresh mode (Self Refresh Mode), and the like, and operation of the SDRAM 18. Perform control.
[0075]
The write timing control unit 8 notifies the SDRAM control unit 9 of the start and end of writing data to the SDRAM 18. That is, the write timing control unit 8 is a circuit that manages writing of data to the SDRAM 18, and manages a request to set / cancel the self-refresh mode to the SDRAM 18 to the SDRAM control unit 9.
[0076]
The read timing control unit 10 notifies the SDRAM control unit 9 of the start and end of reading data from the SDRAM 18. That is, the read timing control unit 10 is a circuit that manages reading of data from the SDRAM 18, and manages a request for setting / cancelling the self-refresh mode to the SDRAM 18 to the SDRAM control unit 9.
[0077]
The SRAMs (mediation buffers) 11 and 12 buffer data read from the SDRAM 18. The SRAM control unit 13 is a circuit that controls writing and reading of data to and from the SRAMs 11 and 12 by controlling the SRAMs 11 and 12. That is, the SRAM control unit 13 switches between the SRAMs 11 and 12 for writing or reading data.
[0078]
The output data control unit 14 controls data output to the outside (external devices such as the LSU 15, PC 16, and external board 17).
[0079]
The SDRAM 18 is a memory (storage device) for storing (storing) input data such as image data. As described above, the SDRAM 18 enters the self-refresh mode, which is a low power consumption mode, by the SDRAM control unit 9.
[0080]
Here, the SDRAM 18 needs to perform a refresh operation by periodically reading and rewriting the accumulated data (stored data). An operation mode in which all the control for the refresh operation is performed inside the SDRAM 18 is called a self-refresh mode. As described above, unlike the power-down mode, the self-refresh mode performs a refresh operation inside the SDRAM 18, so that data stored in the SDRAM 18 can be saved.
[0081]
The data transfer rate (transfer rate) between the external devices (CCD1, PC2, external board 3, LSU15, PC16, external board 17) and the memory controller 21 is determined by the writing / reading speed (access speed) for the SDRAM 18. In comparison, it is slow. That is, data transferred from the external device to the memory control device 21 or data transferred from the memory control device 21 to the external device is divided into a plurality of times, that is, intermittently transferred. Alternatively, data transferred from the memory control device 21 to the external device is intermittently (divided into a plurality of times) in response to a transfer request from the external device.
[0082]
Hereinafter, access control to the SDRAM 18 in the memory control device 21 will be described.
[0083]
First, writing control of data transferred from an external device such as the CCD 1, the PC 2, or the external substrate 3 in the SRAM 5 or the SRAM 6 will be described with reference to FIG. The writing control from the external device to the SRAM (Receive-SRAM) 5.6 is performed by the writing timing control unit 8 through the SRAM control unit 7.
[0084]
Here, the SRAM 5 and the SRAM 6 are switched and used. For example, the SRAM control unit 7 reads the data written in the SRAM 5 and writes (transfers) the data to the SDRAM 18, and writes the next data transferred from the external device to the SRAM 6.
[0085]
When the SRAM 5 becomes empty and the writing to the SRAM 6 is completed, the SRAM 5 and the SRAM 6 are switched, the data written to the SRAM 6 is read and written to the SDRAM 18, and the input data transferred from the external device is next transferred. Is written to the SRAM 5.
[0086]
That is, when the write timing control unit 8 first confirms that one of the SRAMs (Receive-SRAM) is empty (Empty) (S1), it writes the data input from the external device into the SRAM (S2). When it is confirmed that a predetermined number of data (here, the number of unit data (eg, data for one line)) has been written (S3), the SRAM is switched, that is, the state of the write selection signal is switched (S4). As a result, the next data transferred from the external device is written into the other SRAM.
[0087]
In this case, since the writing speed to the SDRAM 18 (processing speed of the SDRAM 18) is faster than the data transfer rate of the external device, the other SRAM is always empty at the end of S3, and the next transfer is performed. The incoming data can be written immediately.
[0088]
Then, data is read (transferred) from one of the SRAMs into which the data has been written to the SDRAM 18 (S5). The data transferred from the external device to the SRAM is written into the SRAM while switching the SRAM until the number of data (the number of transferred data) input to both SRAMs reaches the total number of data output from the external device (S6). Repeated.
[0089]
Next, control of reading data from the SRAMs 5 and 6 when writing data read from the SRAM 5 or 6 to the SDRAM 18 will be described with reference to FIG. The read control from the SRAMs 5 and 6 is performed by the write timing control unit 8.
[0090]
When the writing of the data transferred from the external device to the SRAM in one SRAM is completed, the write timing control unit 8 issues a data read request (see S5 in FIG. 2) to the SRAM (S11), and the write timing control is performed. The start of writing to the SDRAM 18 is notified from the unit 8 to the SRAM control unit 9. Upon receiving this notification, the SRAM control unit 9 releases the self-refresh mode of the SDRAM 18 (transition to the normal mode, S12).
[0091]
Then, data is read from the SRAM in which the data has been written (S13), and a request to write data to the SDRAM 18 is made (S14). When the number of unit data written in the SRAM is read and it is confirmed that the data has been written in the SDRAM 18 (S15), the write timing control unit 8 switches the SRAM via the SRAM control unit 7, that is, switches the state of the read selection signal (S16). ).
[0092]
Then, when the writing of data to the SDRAM 18 is completed, the SRAM control unit 9 waits until the next read request is made to the SRAM (the write timing control unit 8 notifies the start of writing to the SDRAM 18). Into the self-refresh mode (S17).
[0093]
At this time, if the data transfer to the SDRAM 18 has not been completed yet (the data read from the SRAM and written (transferred) to the SDRAM 18 is not the total number of data transferred from the external device to the memory control device). After waiting for predetermined data to be written to the other switched SRAM, data is read from the other SRAM (S18).
[0094]
Next, control of reading data from the SDRAM 18 to the SRAM 11 or the SRAM 12 will be described with reference to FIG. The read control is performed based on a read request from the read timing control unit 10 to the SDRAM control unit 9. Here, the SRAMs 11 and 12 are used by being switched by the SRAM control unit 13 similarly to the SRAMs 5 and 6 described above.
[0095]
First, when the read timing control unit 10 inputs a transfer start signal to the SDRAM control unit 9 (S21), the SDRAM control unit 9 releases the self-refresh mode of the SDRAM 18 (S22) and reads data from the SDRAM 18 (S23).
[0096]
Then, the storage (writing) of the data read from the SDRAM 18 is started in one SRAM (Transfer-SRAM) (S24). Thereafter, when it is confirmed that a predetermined number of data (here, the number of unit data (for example, data for one line)) has been read (S25), the SRAM is switched, that is, the state of the write selection signal is switched (S26).
[0097]
Subsequently, the data is read (transferred) from the one SRAM in which the data is stored to an external device (S27). When the number of data (the number of transferred data) read from the SDRAM 18 and accumulated in the SRAM (transferred to the outside) reaches the total number of data in the SDRAM 18, the read timing control unit 10 sends the SDRAM control unit 9 the SDRAM 18. Notify the end of reading from. Then, the SDRAM control unit 9 issues a request for setting the self-refresh mode to the SDRAM 18 (S29).
[0098]
On the other hand, if the number of transfer data has not reached the total number of data in the SDRAM 18, it is checked whether or not the other SRAM switched in S26 is empty (S30). If it is empty, data is read from the SDRAM 18 again (S30). S23). If not empty, the read timing control unit 10 sets the SDRAM 18 to the self-refresh mode via the SDRAM control unit 9 (S31).
[0099]
Then, when it is confirmed that the other SRAM switched in S26 is empty (S32), a request to cancel the self-refresh mode is issued (S22), and data is read from the SDRAM 18 again.
[0100]
Next, control of reading (transferring) of data from the SRAM 11 or the SRAM 12S to the external device (LSU 15, PC 16, external board 17) will be described with reference to FIG. This read control is performed by the read timing control unit 10.
[0101]
First, when there is a read request from the SRAM to the external device (see S27 in FIG. 4) (S41), the read timing control unit 10 reads data from one of the SRAMs in the unit number of data (S42, 43), Forward. When it is confirmed that the data of the unit data number has been transferred to the external device, the SRAM is switched, that is, the read selection signal state is switched (S44).
[0102]
Then, the process is repeated until the number of data transferred from the SRAM to the external device reaches the total number of data stored in the SDRAM 18 (S45).
[0103]
Hereinafter, signals for writing data input from the CCD 1 to the SDRAM 18 will be described with reference to a timing chart shown in FIG.
[0104]
As shown in the drawing, data (DATA) from the CCD 1 to the memory control device 21 is intermittently input in units of one line in synchronization with a SYNC signal. For example, here, image data of A4 size, color printing, and 600 dpi is input as data, so the number of data per line is 14881 bytes.
[0105]
When 1 byte of data is input, the sram_wr signal for writing data to one SRAM (here, SRAM5) rises in the write timing control unit 8. Thereby, data is written (transferred) to one SRAM (SRAM5). The number of written data is counted by wr_counter in the SRAM control unit 7.
[0106]
When the value of wr_counter reaches the value of one line (the number of unit data) (here, “14880” because the counting is started from 0), the state of the wr_ram_sel signal in the write timing control unit 8 changes from low to high. Change. That is, the state of the write selection signal is switched (see S4 in FIG. 2).
[0107]
Thus, the SRAM to which the data input from the CCD 1 is transferred is switched by the SRAM control unit 7 from one SRAM (SRAM5) to the other SRAM (SRAM6).
[0108]
Further, when the state of the wr_ram_sel signal in the write timing control unit 8 changes from Low to High, the write timing control unit 8 notifies the SDRAM control unit 9 of the start of writing to the SDRAM 18. Accordingly, a signal (SelfRefExit signal) for releasing the self-refresh mode of the SDRAM 18 in the SDRAM control unit 9 rises, and the SDRAM 18 returns from the self-refresh mode to the normal mode.
[0109]
When the SDRAM 18 enters the normal mode, a sram_read signal for reading data accumulated from one of the SRAMs (SRAM 5) rises in the write timing control unit 8, and the read data is continuously written to the SDRAM 18. Further, the read data is counted by rd_counter of the write timing control unit 8.
[0110]
When rd_counter reaches a value for one line (here, “14880”), data reading from one SRAM (SRAM5) ends.
[0111]
Then, the state of the rd_ram_sel signal in the write timing control unit 8 changes from Low to High. That is, the state of the read selection signal is switched (see S16 in FIG. 3). As a result, the SRAM from which the stored data is read is switched from one SRAM (SRAM5) to the other SRAM (SRAM6) by the SRAM control unit 7.
[0112]
Further, when the state of the wr_ram_sel signal in the write timing control unit 8 changes from Low to High, the write timing control unit 8 notifies the SDRAM control unit 9 of the end of writing to the SDRAM 18. As a result, a signal (SelfRefExit signal) for releasing the self-refresh mode of the SDRAM 18 in the SDRAM control unit 9 rises, and the SDRAM 18 is changed from the normal mode to the self-refresh mode.
[0113]
That is, the SDRAM 18 is in the self-refresh mode when there is no need to access (connect) (write data).
[0114]
As shown in FIG. 7, write access to the SDRAM 18 includes single access (Single access) and burst access (Burst Access). Either one may be used. It is preferable to use them.
[0115]
Note that the burst access is continuous input / output of data in a read (read) cycle or a write (write) cycle, and the burst length is the number of words of data in the burst access.
[0116]
In the burst access shown in FIG. 7, for example, data of 8 words (16 bytes) can be continuously written to the SDRAM 18, so that the access time to the SDRAM 18 can be further reduced.
[0117]
The amount of data temporarily stored in the SRAMs 5 and 6 is preferably n times (n is a natural number) the burst length at the time of burst access to the SDRAM 18.
[0118]
This eliminates the need for extra data processing (for data less than the burst length for burst access (here, 16 bytes)), and simplifies control.
[0119]
Hereinafter, a signal for transferring data read from the SDRAM 18 to the LSU 15 will be described with reference to a timing chart shown in FIG.
[0120]
Here, the print_start signal is a trigger signal for starting printing. When the print_start signal becomes High, the SelfRefExit signal rises in the SDRAM control unit 9 based on the management by the read timing control unit 10. Thereby, SDRAM 18 returns from the self-refresh mode to the normal mode.
[0121]
The data read from the SDRAM 18 is written (stored) in one of the SRAMs (here, the SRAM 11) in units of a predetermined number of unit data. “Total_counter” in the read timing control unit 10 is a counter for managing the total number of data transferred to the LSU 15, and counts down every time data is read from the SDRAM 18. For example, in image data of A4 size, color printing, and 600 dpi, the number of data per line is 14881 bytes, and the number of sub-scanning lines is 7015 lines.
[0122]
When data of a preset unit number is written in the one SRAM (SRAM 11), the state of the wr_ram_sel signal in the read timing control unit 10 changes from low to high. That is, the state of the write selection signal is switched (see S26 in FIG. 4). Thus, the SRAM to which the data read from the SDRAM 18 is written is switched by the SRAM control unit 13 from one SRAM (SRAM 11) to the other SRAM (SRAM 12).
[0123]
When a predetermined number of units of data is written in the one SRAM (SRAM 11), the sram_read signal rises in the read timing control unit 10, and transfer (read) of data from the SRAM to the LSU 15 starts. Is done.
[0124]
Rd_counter in the read timing control unit 10 is a counter for managing the number of data read from the SRAM (SRAM 11), and counts down every time data is read.
[0125]
Also, when data of a predetermined number of units (one line) is written to the other SRAM (SRAM 12) (wr_counter becomes “14880”), the state of the wr_ram_sel signal changes from High to Low.
[0126]
At this time, since there is data which has not been read yet in one SRAM (SRAM 11), writing of the next data to one SRAM (SRAM 11) is not performed. Therefore, the data reading from the next SDRAM 18 is not started until the data transfer from one SRAM (SRAM 11) is completed. For this reason, the SDRAM control unit 9 sets the SDRAM 18 to the self-refresh mode again.
[0127]
Thereafter, if the value of total_counter is not 0, there is still data to be transferred to the LSU 15 in the SDRAM 18. Therefore, when the data transfer from one SRAM (SRAM 11) to the LSU 15 is completed (rd_counter becomes "14880"), the next data is read from the SDRAM 18, so that the SelfRefExit signal rises in the SDRAM control unit 9, and the SDRAM 18 self-starts. Return from the refresh mode to the normal mode.
[0128]
Then, data is read from the SDRAM 18 and written to one SRAM (SRAM 11).
[0129]
When the transfer of all the data stored in the SDRAM 18 is completed (the value of total_counter becomes 0), the next data read from the SDRAM 18 is not performed. That is, in the reading timing control unit 10, the sram_write signal does not rise. Therefore, the SDRAM control unit 9 does not need to access the SDRAM 18, and sets the SDRAM 18 to the self-refresh mode again.
[0130]
That is, the SDRAM 18 is in the self-refresh mode when it is not necessary to access (connect) (read).
[0131]
Here, as shown in FIG. 9, the read access to the SDRAM 18 (reading from the SDRAM 18) includes a single access (Single access) and a burst access (Burst Access), and either of them may be used. It is preferable to use access. In the burst access, for example, 8 words (16 bytes) of data can be continuously written to the SDRAM 18, so that the access time to the SDRAM 18 can be further reduced.
[0132]
Note that the read access shown in FIG. 9 differs from the write access shown in FIG. 7 in that there is a delay (latency) from when a read command is input to when data is read. Generally, the delay is 2CLK or 3CLK, but FIG. 9 shows a case where the delay is 2CLK, that is, data is output from the SDRAM 18 after 2CLK from the input of the Read command.
[0133]
In the above description, two SRAMs are used for transferring data to the SDRAM 18 and two SRAMs are used for transferring data from the SDRAM 18, respectively. Is not particularly limited. For example, more SRAMs may be used, and they may be switched and used sequentially, or one SRAM may be used to transfer data via the SDRAM 18.
[0134]
When one SRAM is used when transferring data to the SDRAM 18 or when transferring data from the SDRAM 18, a predetermined amount of data (the number of unit data (for example, one line)) is accumulated as described above. There is no need to switch the SRAM, and data may be read from the SRAM while data is not stored (written) in the SRAM.
[0135]
An example in which reading and writing are performed alternately in one SRAM will be described with reference to FIG. Here, signals having the same functions as the signals shown in the timing chart of FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted. Further, the SDRAM 18 is set to burst access, and the number of unit data once stored in the SRAM is 16 bytes.
[0136]
First, when 1 byte of data (DATA) is input, a sram_wr signal for writing data to the SRAM rises, and the data is accumulated (written) in the SRAM. The number of stored data is counted by wr_counter.
[0137]
Then, when 16 bytes of data corresponding to one write to the SDRAM 18 in burst access are accumulated in the SRAM, the SDRAM 18 is returned from the self-refresh mode to the normal mode.
[0138]
Thereafter, data is read from the SRAM by the sram_read signal, and the data is written to the SDRAM 18. Here, since the data bus of the SDRAM 18 is considered as a 16-bit bus, 16-byte data is written in 8 bursts.
[0139]
After 16 bytes of data are written to the SDRAM 18, the SDRAM 18 is set to the self-refresh mode, and the next data is written to the SRAM.
[0140]
Thus, there is no need to switch and use a plurality of SRAMs, and power consumption can be reduced with a simple configuration. In this case, a certain interval is required between data to be written to the SRAM. For example, if a burst access is used, a long interval can be obtained, which is effective.
[0141]
As described above, the memory control device 21 writes the data intermittently divided into a plurality of times from the external device into the SDRAM 18 (memory) at a writing speed higher than the transfer rate from the external device. Further, the memory control device 21 stores the data temporarily transferred to the SDRAM 18 before and after the data transferred intermittently at a predetermined number of times from the external device into the SRAM 5 (SRAM 6) and the data stored in the SRAM 5 (SRAM 6). An SDRAM control unit 9 for continuously writing data to the SDRAM 18 and setting the SDRAM 18 to the self-refresh mode while data is not being written to the SDRAM 18 is provided.
[0142]
Normally, when data transferred from the outside is transferred in a plurality of times, if data is written to the SDRAM each time it is transferred, power consumption in the SDRAM increases if the SDRAM is always operating. Further, if the SDRAM is set to the self-refresh mode while data is not written in the SDRAM, it takes a long time to return the SDRAM to the original state (operating state) as a whole since the mode is switched many times. Also, if the memory is turned on / off each time data is transferred, power is required to start from OFF to ON, for example, and power consumption increases accordingly.
[0143]
However, according to the above configuration, data from the external device is temporarily stored in the SRAM 5 (SRAM 6), and then writing to the SDRAM 18 is performed continuously (in a short time). Thus, the time for writing data to the SDRAM 18 can be reduced.
[0144]
In this way, by limiting the access time to the SDRAM 18, a continuous time during which the SDRAM 18 is not accessed (not written) can be extended.
[0145]
That is, since the setting and release of the self-refresh mode (the self-refresh mode and the normal mode) are not repeated frequently, the time required for changing the mode can be reduced. Therefore, the time during which the self-refresh mode is entered becomes longer, and the ratio of the time zone in the self-refresh mode becomes longer.
[0146]
As a result, the power consumption of the SDRAM 18 can be reduced.
[0147]
The memory control device 21 reads the stored data from the SDRAM 18 and divides the data into an external device at a transfer rate lower than the reading speed from the SDRAM 18 or in response to a transfer request from the external device, and divides the data into a plurality of times. To transfer. Further, the memory control device 21 stores the data read from the SDRAM 18 once in the SRAM 11 (SRAM 12) before being transferred to the external device, and the data transferred from the SRAM 11 (SRAM 12) to the external device in a predetermined number of times. , An SDRAM control unit 9 for continuously reading data from the SDRAM 18 to the SRAM 11 (SRAM 12) and setting the SDRAM 18 to the self-refresh mode while the data is not read from the SDRAM 18.
[0148]
According to the above configuration, data read continuously from the SDRAM 18 is temporarily stored in the SRAM 11 (SRAM 12) and then transferred to the outside. As a result, the time for reading data to the SDRAM 18 can be reduced.
[0149]
Thus, by limiting the access time to the SDRAM 18, a continuous time during which the SDRAM 18 is not accessed (not read) can be extended.
[0150]
Therefore, the time during which the self-refresh mode is entered becomes longer, and the ratio of the time zone in the self-refresh mode becomes longer. As a result, the power consumption of the SDRAM 18 can be reduced.
[0151]
Note that the SDRAM 18 is not particularly limited to the use of the SDRAM, but burst access is possible by using the SDRAM as the memory. In addition, by using an SDRAM that can be accessed at a higher speed than other types of DRAMs, the access time can be shortened. Thus, the time of the self-refresh mode can be lengthened, and the power consumption of the memory can be reduced.
[0152]
Further, the memory control device 21 includes a plurality of SRAMs (SRAM 5.6 or SRAMs 11 and 12) as intermediary buffers. The SRAMs are controlled via the SRAM control units 7 and 13 so that each SRAM is sequentially accessed by the SDRAM 18. A write timing control unit 8 and a read timing control unit 10 for switching between the two.
[0153]
According to the above configuration, the amount of data that can be stored in the SRAM can be increased, and high-speed processing can be performed.
[0154]
Alternatively, the memory control device 21 may include one SRAM corresponding to writing / reading to / from the SDRAM 18. In this case, the SDRAM control unit 9 writes / reads data to / from the SDRAM 18 while data is not being transferred between the external device and the SRAM.
[0155]
According to the above configuration, when the data transfer rate with the external device is low, it is possible to write data into the SRAM without switching and using a plurality of SRAMs.
[0156]
Therefore, since a configuration for switching the SRAM is not required, the power consumption of the memory control device 21 can be reduced with a simple configuration.
[0157]
【The invention's effect】
As described above, a memory control device according to the present invention is a memory control device that writes data transferred from an external device intermittently in a plurality of times into a memory at a write speed higher than the transfer rate from the external device. An intermediary buffer for temporarily storing data transferred intermittently from the external device in a predetermined number of times before writing the data to a memory, and data stored in the intermediary buffer being continuously stored in the memory. And a memory control unit that sets the memory to a self-refresh mode while data is not being written to the memory.
[0158]
Thus, since the data from the external device is temporarily stored in the intermediary buffer and then written to the memory continuously (in a short time), the time for writing the data to the memory can be reduced.
[0159]
Therefore, the setting and release of the self-refresh mode (the self-refresh mode and the normal mode) are not frequently repeated, so that the time required for changing the mode can be reduced. As a result, the time during which the self-refresh mode is entered is prolonged, and the power consumption of the memory can be reduced.
[0160]
As described above, the memory control device of the present invention reads out data stored in a memory and transfers the data to an external device at a transfer rate lower than the reading speed from the memory or transfer from the external device. A memory control device that transfers data in a plurality of times in response to a request, the mediation buffer temporarily accumulating data read from the memory before transferring the data to an external device, and a predetermined buffer from the mediation buffer to the external device. A memory control unit that reads data transferred in the number of times continuously from the memory to the intermediary buffer and sets the memory to a self-refresh mode while the data is not read from the memory. Configuration.
[0161]
Thus, since the data continuously read from the memory is temporarily stored in the intermediary buffer and then transferred to the outside, the time required for reading the data into the memory can be reduced.
[0162]
Therefore, by limiting the access time to the memory, the continuous time during which the memory is not accessed (not read) can be extended. As a result, the time during which the self-refresh mode is entered is prolonged, and the power consumption of the memory can be reduced.
[0163]
The memory control device of the present invention has a configuration in which the memory is an SDRAM.
[0164]
As a result, it is possible to lengthen the time of the self-refresh mode and to reduce the power consumption of the memory.
[0165]
The memory control device of the present invention is configured to include a plurality of intermediary buffers and a buffer switching unit that switches the intermediary buffers so that each intermediary buffer is sequentially connected to the memory.
[0166]
As a result, the amount of data that can be stored in the intermediary buffer can be increased, and high-speed processing can be performed.
[0167]
The memory control device according to the present invention has a configuration in which the memory control unit writes data to the memory while data is not transferred between the external device and the intermediary buffer.
[0168]
Accordingly, when the data transfer rate with the external device is low, data can be written to the mediation buffer without switching and using a plurality of mediation buffers.
[0169]
Therefore, since there is no need for a configuration for switching the mediation buffer, there is an effect that the power consumption of the memory control device can be reduced with a simple configuration.
[0170]
A memory control device of the present invention includes a write timing control unit that manages a write timing for writing data to a memory, and the memory control unit writes data to the memory based on the write timing.
[0171]
As a result, there is an effect that the self-refresh mode of the memory can be easily set and released.
[0172]
The memory control device of the present invention has a configuration in which the memory control unit reads data from the memory while data is not transferred between the external device and the mediation buffer.
[0173]
Accordingly, when the data transfer rate with the external device is low, data can be written to the mediation buffer without switching and using a plurality of mediation buffers.
[0174]
Therefore, since there is no need for a configuration for switching the mediation buffer, there is an effect that the power consumption of the memory control device can be reduced with a simple configuration.
[0175]
The memory control device of the present invention includes a read timing control unit that manages a read timing for reading data from a memory, and the memory control unit is configured to read data from the memory based on the read timing.
[0176]
As a result, there is an effect that the self-refresh mode of the memory can be easily set and released.
[0177]
The memory control device of the present invention has a configuration in which the access to the memory is a burst access.
[0178]
As a result, continuous input / output of data to / from the memory becomes possible, so that the access time to the memory can be shortened. Therefore, the self-refresh mode can be extended, and the power consumption of the memory can be reduced.
[0179]
The memory control device of the present invention is configured such that the amount of data stored in the mediation buffer is a natural number times the burst length in burst access.
[0180]
This eliminates the need for data processing for data less than the burst length for burst access, and has the effect of simplifying control.
[0181]
An information processing system according to the present invention is configured to include the memory control device described above and a memory whose operation is controlled by the memory control device and stores data to be transferred.
[0182]
As a result, there is an effect that a system in which the self-refresh mode is performed for a long time and power consumption of the memory is small can be provided.
[0183]
As described above, the memory control method of the present invention is a memory control method for writing data intermittently transferred from an external device in a plurality of times into a memory at a writing speed higher than a transfer rate from the external device. The data transferred from the external device intermittently at a predetermined number of times is temporarily stored in the intermediary buffer before being written to the memory, and then the data stored in the intermediary buffer is continuously written to the memory. While the data is not being written to the memory, the memory is set to the self-refresh mode.
[0184]
As a result, the time for writing data to the memory can be reduced by temporarily storing data from the external device in the intermediary buffer and then continuously writing the data to the memory. Therefore, there is an effect that the power consumption of the memory can be reduced.
[0185]
As described above, the memory control method of the present invention reads out data stored in a memory and transfers the data to an external device at a transfer rate lower than the reading speed from the memory or transfer from the external device. A memory control method for transferring data in a plurality of times in response to a request, wherein the data read from the memory is temporarily stored in an intermediary buffer before being transferred to an external device, and is then transferred from the intermediary buffer to the external device. Data transferred in a predetermined number of times is continuously read from the memory to the intermediary buffer, and the memory is set to a self-refresh mode while the data is not read from the memory.
[0186]
As a result, the data continuously read from the memory is temporarily stored in the intermediary buffer, and then intermittently transferred to the external device (at a predetermined transfer rate set in advance or when a transfer request is issued from the external device). By doing so, the time for writing data to the memory can be reduced. Therefore, there is an effect that the power consumption of the memory can be reduced.
[0187]
The memory control method of the present invention has a configuration in which a plurality of mediation buffers are used, and the mediation buffers are switched so that each of the mediation buffers is sequentially accessed to the memory.
[0188]
As a result, the amount of data that can be stored in the intermediary buffer can be increased, and high-speed processing can be performed.
[0189]
The memory control method of the present invention has a configuration in which data is written to the memory while data is not being transferred between the external device and the intermediary buffer.
[0190]
As a result, when the data transfer rate with the external device is low, there is an effect that data can be written to the mediation buffer without switching and using a plurality of mediation buffers.
[0191]
The memory control method of the present invention has a configuration in which data is read from a memory while data is not transferred between an external device and an intermediary buffer.
[0192]
As a result, when the data transfer rate with the external device is low, there is an effect that data can be written to the mediation buffer without switching and using a plurality of mediation buffers.
[0193]
The memory control method of the present invention is configured to perform burst access to a memory.
[0194]
As a result, continuous input / output of data to / from the memory becomes possible, so that the access time to the memory can be shortened. Therefore, the self-refresh mode can be extended, and the power consumption of the memory can be reduced.
[0195]
The memory control method of the present invention has a configuration in which data of a natural number times the burst length in burst access is temporarily stored in the mediation buffer.
[0196]
This eliminates the need for data processing for data less than the burst length for burst access, and has the effect of simplifying control.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of a main part of an information processing system according to an embodiment of the present invention.
FIG. 2 is a flowchart illustrating write control of data transferred from an external device in an SRAM.
FIG. 3 is a flowchart showing control of reading from the SRAM when writing data read from the SRAM to the SDRAM;
FIG. 4 is a flowchart showing control of reading from the SDRAM when data is read from the SDRAM and written to the SRAM;
FIG. 5 is a flowchart showing control of reading from the SRAM when data is transferred from the SRAM to an external device.
FIG. 6 is a timing chart showing SRAM and signals to the SDRAM when data input from the CCD is written to the SDRAM.
FIG. 7 is a diagram showing a difference in data between a single access and a burst access at the time of writing to an SDRAM.
FIG. 8 is a timing chart showing signals for the SRAM and the SDRAM when data read from the SDRAM is transferred to the LSU.
FIG. 9 is a diagram illustrating a difference in data between single access and burst access when reading from an SDRAM.
FIG. 10 is a timing chart showing signals to the SRAM and the SDRAM when reading and writing are alternately performed by one SRAM when writing data input from an external device to the SDRAM.
[Explanation of symbols]
1 CCD (external equipment, external equipment)
2,16 HOST PC (PC, external device, external device)
3,17 External board (external equipment, external device)
5,6 SRAM (mediation buffer)
7 SRAM control unit
8. Write timing control unit (buffer switching means)
9 SDRAM control unit (memory control unit)
10. Read timing control unit (buffer switching means)
11,12 SRAM (mediation buffer)
13 SRAM control unit
14 Output data control unit
15 LSU (external device)
18 SDRAM (memory)
20 Information processing system
21 Memory controller

Claims (18)

A memory control device that writes data transferred from an external device intermittently in a plurality of times to a memory at a write speed higher than a transfer rate from the external device,
An intermediary buffer that temporarily accumulates data transferred intermittently from the external device a predetermined number of times before writing to a memory;
A memory controller configured to continuously write the data stored in the mediation buffer to the memory and to set the memory to a self-refresh mode while data is not being written to the memory. Memory control device. A memory that reads stored data from a memory and transfers the data to an external device at a transfer rate lower than the reading speed from the memory, or in a plurality of times according to a transfer request from the external device. A control device,
An intermediate buffer for temporarily storing data read from the memory before transferring the data to an external device;
Data transferred from the intermediary buffer to the external device in a predetermined number of times is continuously read from the memory to the intermediary buffer, and while the data is not being read from the memory, the memory is in a self-refresh mode. And a memory control unit for setting the memory control unit to a value. The memory control device according to claim 1, wherein the memory is an SDRAM. A plurality of the above mediation buffers are provided,
3. The memory control device according to claim 1, further comprising a buffer switching unit that switches the mediation buffer so that each mediation buffer accesses the memory sequentially. 2. The memory control device according to claim 1, wherein the memory control unit writes the data into the memory while data is not being transferred between the external device and the mediation buffer. 3. A write timing control unit that manages a write timing for writing the data in the memory;
2. The memory control device according to claim 1, wherein the memory control unit writes the data to the memory based on the write timing. The memory control device according to claim 2, wherein the memory control unit reads the data from the memory while data is not being transferred between the external device and the mediation buffer. A read timing control unit that manages read timing for reading the data from the memory;
The memory control device according to claim 2, wherein the memory control unit reads the data from the memory based on the read timing. 3. The memory control device according to claim 1, wherein the memory is accessed by performing a burst access. 10. The memory control device according to claim 9, wherein an amount of data stored in the mediation buffer is a natural number times a burst length in the burst access. A memory control device according to any one of claims 1 to 10,
An information processing system, the operation of which is controlled by the memory control device, and comprising a memory for storing data to be transferred. A memory control method for writing data transferred from an external device intermittently in a plurality of times to a memory at a write speed higher than a transfer rate from the external device,
The data transferred intermittently from the external device at a predetermined number of times is temporarily stored in the mediation buffer before being written to the memory,
A memory control method, wherein data stored in the mediation buffer is continuously written to the memory, and the memory is set to a self-refresh mode while data is not written to the memory. . A memory that reads stored data from a memory and transfers the data to an external device at a transfer rate lower than the reading speed from the memory, or in a plurality of times according to a transfer request from the external device. A control method,
After temporarily storing the data read from the memory in the intermediary buffer before transferring the data to the external device,
While the data transferred from the intermediary buffer to the external device in a predetermined number of times is continuously read from the memory to the intermediary buffer, the memory is self-refreshed while the data is not read from the memory. A memory control method characterized by setting a mode. Using a plurality of the above mediation buffers,
14. The memory control method according to claim 12, wherein the intermediary buffers are switched so that the intermediary buffers sequentially access the memory. 13. The memory control method according to claim 12, wherein the data is written to the memory while data is not transferred between the external device and the mediation buffer. 14. The memory control method according to claim 13, wherein the data is read from the memory while data is not transferred between the external device and the mediation buffer. 14. The memory control method according to claim 12, wherein the access to the memory is performed by burst access. 18. The memory control method according to claim 17, wherein data of a natural number times a burst length in the burst access is temporarily stored in the mediation buffer.

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