JP2004185451A - Memory access arbitration method and memory access arbitration unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory access arbitration method capable of maximally using an access speed of a memory for which an FIFO area is set. <P>SOLUTION: This arbitration unit 20 is provided with a counter 19a determining an accumulated data quantity N in the FIFO area 22, a first setting part 31 setting a condition D1, in which FIFO read access has higher priority to FIFO write access, when the accumulated data quantity N is larger than a first set value S1, and a second setting part 32 setting a condition D2, in which the FIFP write access has a higher priority to the FIFO read access, when the accumulated data quantity N is lower than a second set value S2. When change to the condition D1 or D2, in which the relationship based on the FIFO read access or the FIFO write access alone is carried out, is carried out, occurrence of buffer full or buffer underrun can be prevented surely, and reduction in performance of another memory access is also prevented. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method and an apparatus for arbitrating access to a memory in which an area for a FIFO is set.
[0002]
[Prior art]
There is known a system in which an area for FIFO is set in a memory such as a RAM or a memory device, and is used for a FIFO buffer and other purposes. Japanese Patent Application Laid-Open No. 2001-175591 discloses a data buffer device and method using a memory as a FIFO.
[0003]
[Patent Document 1]
JP-A-2001-175591
[0004]
[Problems to be solved by the invention]
When one memory is used for several purposes, arbitration processing for memory access is indispensable. A round robin method and a priority (priority) method are known as arbitration processing algorithms used as task scheduling of an operating system (OS) or the like. By using these arbitration methods, it is possible to construct a system in which the memory is shared for the FIFO area and other purposes.
[0005]
In the arbitration method, the priority or the frequency of the write channel or the read channel is set based on the expected access frequency to the FIFO in the system. However, if a low-priority design is employed for writing to the FIFO (write access or write channel), the probability of buffer underrun increases when the amount of data stored in the FIFO area is small, and the overall system There is a concern that the capacity may be reduced.
[0006]
On the other hand, if a design with a low priority order for reading (read access or read channel) for the FIFO is adopted, when the amount of data stored in the FIFO area is large, the time ratio of the buffer full state increases, and the FIFO write access However, there is a concern that the performance of the entire system will be degraded due to waiting.
[0007]
Considering only that the memory is effectively used as a FIFO, a design in which the priority of write access and read access of the FIFO is increased in advance may prevent buffer underrun or buffer full and improve the performance of the FIFO. unknown. However, if the memory is shared for a purpose other than the FIFO, the performance of accessing the memory for purposes other than the FIFO access will be reduced. There is.
[0008]
FIG. 7 shows an arbitration method based on a simple weighted round robin method. Arbitration targets are FIFO write access M1, FIFO read access M2, memory access M3 of other job A, memory access M4 of other job B, and memory access M5 of other job C. . An access (channel) is assigned to the arbitration unit 90 such that seven cycles constitute one cycle in total. In FIG. 7, both the FIFO write access M1 and the FIFO read access M2 are set so that 2/7 of the entire band rate of the memory can be used. However, when the analysis of the normal operation of the system shows that the frequency of the FIFO write access is small, the frequency of the FIFO write access M1 is smaller than the frequency of the FIFO read access M2, that is, the frequency of the FIFO write access M1. The band rate is set to 1/7. At this time, if the data capacity of the FIFO area becomes smaller, the setting of the band rate is higher in the FIFO read access than in the FIFO write access. Therefore, the data in the FIFO area is hardly increased, and is consumed by the FIFO read. Underrun. For this reason, the performance of the FIFO read access is reduced in a system that mainly performs the FIFO read access rather than the FIFO write access, so that the system performance may be reduced.
[0009]
Conversely, when it is determined that the frequency of the FIFO write access is higher than that of the FIFO read access, the band rate of the FIFO read access is set to be smaller than the band rate of the FIFO write access. At this time, if there is much data in the FIFO area, the data in the FIFO area further increases, a buffer full state occurs, and the FIFO write access is interrupted. Then, in a system in which the FIFO write access is larger than the FIFO read access, the FIFO write access is hindered, and the performance of the system is reduced.
[0010]
By increasing the frequency of the FIFO write access and the FIFO read access or increasing the maximum transfer rate, the above-mentioned state hardly occurs. However, since access to the memory is dominated by the FIFO, access to other jobs is kept waiting, and the performance of the system may be degraded. Therefore, if arbitration is performed so that the read access is prioritized even if the condition of access to the memory also used as the FIFO is a system with a high read access frequency, a buffer underrun may occur and the performance of the system may be degraded. Conversely, arbitration so that write access is prioritized even for a system with a high frequency of write access will result in a buffer full, which may degrade the performance of the system.
[0011]
Therefore, in the present invention, in a method and a unit for arbitrating access to a memory shared as a FIFO area, the frequency of read access can be increased in a system having a high frequency of read access, and the frequency of write access can be increased. It is an object of the present invention to provide a memory access arbitration method and unit that can increase the frequency of write access in a high system. On the other hand, it is an object of the present invention to provide a memory access arbitration method and unit capable of preventing occurrence of buffer underrun and buffer full, and preventing a decrease in system performance due to an increase in read or write access frequency.
[0012]
[Means for Solving the Problems]
For this reason, in the memory access arbitration method of the present invention, conditions for giving priority to FIFO read access and conditions for giving priority to FIFO write access are provided, and these conditions are stored in the stored data stored in the FIFO area. It can be changed according to the amount. That is, in the memory access arbitration method of the present invention for permitting access to a memory in which a FIFO area is set, a step of determining the amount of stored data stored in the FIFO area; If it is determined that the value is larger than the set value, a first step of setting conditions for permitting access to the memory so that priority is given to FIFO read access for reading data from the FIFO area, and accumulation of the FIFO area If it is determined that the data amount is smaller than the second set value, a second step of setting conditions for permitting access to the memory so that FIFO write access for writing data to the FIFO area is prioritized. Have.
[0013]
The memory access arbitration unit of the present invention for permitting access to a memory in which a FIFO area is set includes means for determining the amount of stored data stored in the FIFO area, First setting means for setting conditions for permitting access to the memory so that the FIFO read access is prioritized if it is determined to be larger than the set value, and it is determined that the accumulated data amount is smaller than the second set value. Then, there is provided a second setting means for setting a condition for permitting access to the memory so that the FIFO write access is prioritized. Further, the memory access arbitration method of the present invention can be provided as a program that operates on an information processing device. That is, the present invention allows a processor such as a CPU or a computer, which is an information processing apparatus, to execute the determining step, the first step, and the second step of the above-described memory access arbitration method. Includes programs with possible instructions. Such a program can be provided by being recorded on a suitable recording medium such as a CD-ROM or a ROM in the system, or can be provided via a computer network.
[0014]
In the memory access arbitration method and arbitration unit of the present invention, when it is determined that the amount of data stored in the FIFO area is larger than the first set value, the FIFO read access is prioritized, and the frequency of the FIFO read access increases. Therefore, the frequency of reading the stored data in the FIFO area increases, so that the occurrence of buffer full can be prevented beforehand. On the other hand, when it is determined that the amount of data stored in the FIFO area is smaller than the second set value, the condition for giving priority to the FIFO write access is set, so that the frequency of the FIFO write access increases. Therefore, the frequency of writing data in the FIFO area increases, so that the amount of accumulated data increases, and the occurrence of buffer underrun can be prevented. For this reason, in a steady state, even if the frequency of FIFO read access and FIFO write access is arbitrated so as to be suitable for the system, it is possible to prevent a state in which the system performance is degraded such as buffer underrun or buffer full. And maintain high system performance.
[0015]
Therefore, a memory unit having the memory access arbitration unit of the present invention and a memory in which an area for a FIFO is set, and which is permitted to be accessed by the memory access arbitration unit, can be written and read in accordance with a system request. Can be set, and on the other hand, a situation in which the system performance is degraded, such as buffer underrun or buffer full, is prevented. Therefore, a data processing device having the memory unit, a data supply device for supplying data to a FIFO area set in the memory, and a data consuming device for reading and consuming data stored in the FIFO region Can perform processing with high performance.
[0016]
In order to reliably prevent the occurrence of buffer full and buffer underrun, in the first step and the first setting means, the condition that the frequency of the FIFO read access is higher than the frequency of the FIFO write access, that is, the priority is set. In the case of the system, the priority is set, and in the case of the round robin system, the band rate is set. In the second step and the second setting means, conditions are set such that the frequency of the FIFO read access is lower than the frequency of the FIFO write access. It is desirable to set. By setting the conditions in this manner, the increase and decrease of the data amount in the FIFO area can be reliably controlled, so that the occurrence of buffer full and buffer underrun can be reliably controlled.
[0017]
If only the relationship between the FIFO read access and the FIFO write access is set in the first and second steps and the first and second setting means, the buffer full and the buffer can be set without affecting other accesses to the memory. The occurrence of underrun can be suppressed. On the other hand, in the first step and the first setting means, the setting is made so that the FIFO read access is given priority over all accesses to the memory, and in the second step and the second setting means, the FIFO write access is performed. It is also possible to set so that priority is given to all accesses to the memory. In this case, although other accesses to the memory are affected, the amount of data in the FIFO area can be adjusted most efficiently, and the occurrence of buffer full and buffer underrun can be suppressed efficiently.
[0018]
The first and second set values may be determined in consideration of the data amount of the data supply source and the processing speed of the data consumption destination. It is possible to set the second set value to about 70% of the data amount or to set the second set value to about 30% of the allowable data amount of the FIFO area. Also, the first and second set values can be set to half or 50% of the allowable data amount that can be stored in the FIFO area.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in more detail with reference to the drawings. FIG. 1 shows a schematic configuration of the printer. The printer 1 has a memory unit provided with a memory access arbitration unit according to the present invention. The printer 1 performs image processing of print data φ transferred from the host device 8 or the like, and prints it on the paper 5 by the printing mechanism 4. The data processing apparatus 2 that performs image processing and controls the printing mechanism 4 is used. Have. The data processing device 2 includes a CPU 11, a ROM 12 in which firmware and the like are recorded, an interface 13 for acquiring print data φ, an image processing ASIC 14 for performing image processing on the print data φ, and a memory unit 3. These are connected via a bus 17. The memory unit 3 includes a memory or a memory device 21 such as a RAM, an arbitration unit 20 capable of arbitrating memory access to the memory 21, and a memory controller 15. Further, the data processing device 2 includes a mechanical control unit 16 that controls the printing mechanism 4.
[0020]
An area 22 for FIFO is set in the memory 21 of the memory unit 3, and data processed by the image processing ASIC 14 is stored or stored in the FIFO area 22, and the stored data (accumulated data) is controlled by mechanical control. The data is output to the printing mechanism 4 via the unit 16. For this reason, the difference between the amount of data or the processing speed supplied from the image processing ASIC 14 to the FIFO area 22 and the amount of data or the processing speed in the FIFO area consumed by the printing mechanism 4 via the mechanical control unit 16 is stored in the memory 21. Is absorbed by the FIFO area 22 set to the. Therefore, in this example, the image processing ASIC 14 is a data supply device that supplies data to the FIFO area 22, and the mechanical control unit 16 or the printing function 4 is a data consumption device that consumes accumulated data in the FIFO area 22.
[0021]
The memory 21 of the memory unit 3 is also used as an area developed when executing a program recorded in the ROM 12 and a temporary storage area for data for executing the program. One memory 21 or a memory block accessed as one memory 21 is shared with the FIFO for other purposes.
[0022]
The memory unit 3 includes a memory 21 in which a FIFO area 22 is set, an arbitration unit 20 for arbitrating an access request to the memory 21, and a control signal to the memory 21 to output an access request granted by the arbitration unit 20. And a memory controller 15 capable of writing or reading data to or from a predetermined address.
[0023]
The arbitration unit 20 includes a FIFO read request (or read access) for reading data from the FIFO area 22, a FIFO write request (or write access) for writing data to the FIFO area 22, and a memory write request (or memory write access) for other jobs. An arbitration circuit 24 that receives a memory read request (or memory read access) and permits an access request to the memory 21 in accordance with a predetermined condition or setting; and an amount of data stored in the FIFO area 22 (amount of stored data) A FIFO controller 19 having a function 19a for counting N. Therefore, data for writing and reading data to and from the FIFO area 22 is controlled by the arbitration circuit 24 via the FIFO controller 19. For example, data to be written into the FIFO area 22 is supplied to the arbitration circuit 24 via the FIFO controller 19, and data read from the FIFO area 22 is supplied to the FIFO controller 19 via the arbitration circuit 24 and transmitted to the mechanical control unit 16. Is output. Accordingly, the FIFO controller 19 can grasp the accumulated data amount N in the FIFO area 22 by operating the counter 19a based on the input / output of data. The counter 19a corresponds to a means for determining the accumulated data amount N.
[0024]
FIG. 2 shows details of the memory unit 3 using a block diagram. The arbitration circuit 24 of the memory unit 3 includes a FIFO read channel 41 that receives a FIFO read request, a FIFO write channel 42 that receives a FIFO write request, a memory write channel 43 that receives another memory write request, and a memory that receives another memory read request. It has a read channel 44 and can accept a plurality of types of access requests. For an access request related to the FIFO, a read address and a write address of data are generated by a read pointer and a write pointer provided in the FIFO controller 19 and supplied to the arbitration circuit 24. The operation of reading data in the written order is realized.
[0025]
The arbitration circuit 24 includes a setting unit 30 capable of changing the priority order or band rate of access to the memory, and permits a predetermined memory access according to the priority order or band rate set by the setting unit 30. And an arbitration unit 35 for waiting for access. If the output of the counter 19a, that is, if the accumulated data amount N of the FIFO area 22 is determined to be larger than the first set value S1, the FIFO read access M2 for reading data from the FIFO area 22 A first setting unit 31 that sets a condition D1 for permitting access to the memory 21 in the arbitration unit 35 so as to be prioritized over the FIFO write access M1 that writes data to the arbitration unit 35; A second setting unit 32 that sets a condition D2 for permitting access to the memory 21 in the arbitration unit 35 so that the FIFO write access M1 has a higher priority than the FIFO read access M2 if it is determined to be smaller. ing. In this example, the first and second set values S1 and S2 are both set to 50% or half (C / 2) of the allowable data amount or capacity C that can be stored in the FIFO area 22.
[0026]
FIG. 3 shows how the access to the memory 21 changes when the setting of the arbitration unit 35 is changed by the first setting unit 31, and FIG. 4 shows how the setting of the arbitration unit 35 is changed by the second setting unit 32. The processing when it is changed is shown. Note that, in these figures as well, as described with reference to FIG. 7, the FIFO write access M1, the FIFO read access M2, the memory access M3 of the other job A, the memory access M4 of the other job B, and the other There are five memory accesses of the memory access M5 of the job C, and channel assignment is performed with seven cycles as one cycle in total. Then, it is assumed that both the FIFO write access M1 and the FIFO read access M2 are set to the condition D in which 2/7 of the entire band rate of the memory 21 can be used.
[0027]
Basically, the first setting unit 31 and the second setting unit 32 are adapted to arbitrate the memory access by employing the round robin algorithm described with reference to FIG. The frequency of the FIFO write access M1 and the frequency of the FIFO read access M2 are flexibly changed in accordance with the accumulated data amount N of 22. First, as shown in FIG. 3A, when the first setting unit 31 determines that the accumulated data amount N is larger than C / 2 from the output of the counter 19a of the FIFO controller 19, the arbitrating unit 35 A setting is made so that the frequency of the FIFO write access M1 is reduced, and the reduced amount is assigned to the FIFO read access M2 (condition D1). As a result, the frequency of the FIFO read access M2 increases. That is, in the FIFO write access M1, the overall band rate of the memory 21 is reduced from 2/7 to 1/7, and the band rate of the FIFO read access M2 is increased from 2/7 to 3/7. Priority is given to the write access M1, and the frequency of read access is increased. Therefore, even if the accumulated data amount N becomes large, there is no possibility that the buffer becomes full, and the occurrence of the buffer full can be prevented beforehand.
[0028]
On the other hand, as shown in FIG. 4A, when the second setting unit 32 determines that the accumulated data amount N is smaller than C / 2 from the output of the counter 19a of the FIFO controller 19, the arbitrating unit 35 The frequency of the FIFO read access M2 is reduced, and the reduced amount is set to be assigned to the FIFO write access M1 (condition D2). As a result, the frequency of the FIFO write access M1 increases. That is, in the FIFO read access M2, the overall band rate of the memory 21 is reduced from 2/7 to 1/7, and the band rate of the FIFO write access M1 is increased from 2/7 to 3/7. This is prioritized over the read access M2, and the frequency of write access is increased. For this reason, when the accumulated data amount N is small, the FIFO write is permitted prior to the FIFO read, so that the data amount in the FIFO area increases and the occurrence of buffer underrun can be prevented beforehand.
[0029]
In the above control, the first setting unit 31 and the second setting unit 32 set the conditions D1 and D2 in which only the relationship between the FIFO write access M1 and the FIFO read access M2 has been changed, and set the memory access M3 for other jobs. The conditions of .about.M5 are not changed. That is, the band rates of the other memory accesses M3 to M5 are maintained at 1/7, and the priorities of the other memory accesses M3 to M5 do not change. Therefore, occurrence of buffer full and buffer underrun is reliably prevented without affecting other memory accesses.
[0030]
FIG. 5 shows the arbitration process performed by the arbitration unit 20 using a flowchart. First, in step 51, when the arbitration circuit 24 of the arbitration unit 20 receives any of the memory access requests M1 to M5, in step 52, it arbitrates memory access according to the set conditions. Next, in step 53, the setting unit 30 refers to the counter 19a of the FIFO controller 19 to determine the accumulated data amount N. If the accumulated data amount N is larger than the first set value S1 in step 54, the first setting unit 31 changes the condition of the arbitration unit 35 in step 56. In this example, the conditions are changed so that the number of valid cycles of the FIFO write access M1 is reduced and the number of valid cycles of the FIFO read access M2 is increased, so that the frequency of the FIFO read access M2 is increased. That is, the arbitration condition is set to the condition D1. On the other hand, in step 55, if the accumulated data amount N is smaller than the second set value S2 (in this example, both the first set value S1 and the second set value S2 are C / 2), the second set value is set. The unit 32 changes the condition of the arbitration unit 35 in Step 57. The arbitration unit 35 is set to reduce the number of valid cycles of the FIFO write access M2 and increase the number of valid cycles of the FIFO write access M1, thereby increasing the frequency of the FIFO write access M1. That is, the arbitration condition is set to the condition D2.
[0031]
Such processing can be incorporated in the arbitration unit 20 as hardware logic, or can be incorporated as software logic (firmware). Alternatively, the control as the arbitration unit 20 can be controlled by a dedicated microprocessor. In the case of performing software control, the above-described steps are executed by an information processing device that operates as a microprocessor or another computer. A program (program product) provided with instructions is recorded on a recording medium such as a ROM and provided. The program may be provided via a computer network.
[0032]
The arbitration unit 20 of this example can flexibly change the frequency of the FIFO read cycle and the FIFO write cycle in accordance with the amount N of data stored in the FIFO area 22. Therefore, the frequency of access to the FIFO is set in advance so as to be suitable for a system such as the printer 1, and in a normal state, even if arbitration is performed under such conditions, a buffer full or a buffer underrun occurs. When there is a possibility, the access priority is automatically changed so as to prevent such occurrence, so that occurrence of buffer full or buffer underrun can be prevented beforehand. For this reason, the priority criterion for access to the FIFO is set to the most suitable priority criterion expected in the system (printer), and the performance of the system can be maintained high in the normal state. When a situation in which the system performance is reduced is likely to occur, the state in which the system performance is reduced can be prevented, so that the system performance can always be maintained at a high level. Therefore, even in various printing processes having different amounts of print data, different types of image processing, and the like, high-speed processing can be realized while always maintaining high memory access efficiency. In particular, in the arbitration method shown in FIGS. 3A and 4A, the arbitration unit 20 keeps the frequency of the other memory accesses M3 to M5 unchanged, and improves the performance of the memory access related to other jobs. Since it is maintained, the processing performance of the FIFO operation can be efficiently improved without lowering the processing speed of jobs other than the FIFO. For this reason, it is optimal for making full use of the processing capacity of the system. On the other hand, a high-performance system that used to be built using excessively high-speed memory may be able to build a system with equivalent performance using low-cost, not so fast (slow) memory. According to the present invention, a high-performance system can be provided at low cost.
[0033]
Further, by using the arbitration unit 20 of this example, the speed at which the data processed by the data supply device (image processing ASIC) 14 is accumulated in the FIFO area 22 without causing the CPU 11 to perform a special job or processing. The difference from the speed at which data is consumed by the data consuming device (mechanical control unit) 16 can be absorbed or matched by the FIFO area 22 set in the memory 21. Therefore, by using the memory unit 3 including the arbitration unit 20, it is possible to match the speed difference between the data supply device and the data consuming device in the closed range of the memory unit 3, and to set the arbitration unit 20 to the printer. A high-speed, low-cost system in which a memory device such as a RAM is commonly used as a FIFO can be easily constructed simply by incorporating it into a system such as a host and a host device.
[0034]
Furthermore, since the accumulated data amount N in the FIFO area 22 can be easily grasped by using the counter 19a, it is not necessary to perform a dedicated process by a CPU or the like. Therefore, it is possible to efficiently extract system performance without increasing excessive processing. Further, since the change of the arbitration condition depends on the first and second set values, when the processing load accompanying the change of the condition is large, only changing the first and second set values reduces the processing load. It is also possible to ease it easily. Therefore, by changing the first and second set values according to the system in which the arbitration unit 20 or the memory unit 3 is incorporated, arbitration conditions that match the system, that is, are directly linked to an increase in the performance of the system. It is also possible to realize a change process.
[0035]
In the above description, only the relationship between the FIFO write access M1 and the FIFO read access M2 is changed so as not to affect the other memory accesses M3 to M5. It is also possible to arbitrate the relationship between accesses M1 and M2. In this case, the other memory accesses M3 to M5 are affected, but the data amount of the FIFO area 22 can be adjusted most efficiently. In such a case, the first setting unit 31 sets the FIFO read access M2 to be given priority over other accesses to the memory 21, and the second setting unit 32 sets the FIFO write access M1 to What is necessary is just to set so that priority may be given to other accesses.
[0036]
One such method is that, as shown in FIG. 3B, the first setting unit 31 increases the cycle by one to make eight cycles one cycle, and performs FIFO read access M2 for the increased cycle. Is to assign Thus, the condition D3 can be set in which the band rate of the FIFO read access M2 is increased to ／ and the band rates of the other memory accesses M1, M3 to M5 are relatively reduced. On the other hand, as shown in FIG. 4B, the second setting unit 32 adds one cycle to eight cycles as one cycle, and assigns the FIFO write access M1 to the increased cycle. Thus, the condition D4 can be set in which the band rate of the FIFO write access M1 is increased to 3/8 and the band rates of the other memory accesses M2 and M3 to M5 are relatively reduced.
[0037]
Further, it is possible to use both the method of increasing the number of cycles and the method of changing the assignment between the FIFO read access and the FIFO write access as described above. This makes it possible to control the condition in which the FIFO read access or the FIFO write access is prioritized in another stage, and to change the arbitration condition in real time according to the amount of stored data.
[0038]
In the above, the data processing device 2 in which the image processing ASIC 14 is mounted and the data processed by the ASIC 14 is supplied to the FIFO area 22 has been described as an example. Further, the present invention can be applied to a printer that sends the data supplied from the host 8 to the printing mechanism as it is, without using the ASIC 14, and prints the data. FIG. 6 schematically shows such a printer 1 and a data processing device 2a mounted thereon. The data processing device 2a of the printer 1 does not include the image processing ASIC 14, and the data φ from the host 8 acquired by the interface 13 is directly supplied from the interface 13 to the FIFO controller 19. Therefore, in the data processing device 2a, the interface 13 is a data supply device that supplies data to the FIFO area 22.
[0039]
In such a data processing device 2a, the data transferred from the host 8 is acquired by the interface 13 and sent to the FIFO area 22, so that the FIFO write access depends on the communication speed between the host 8 and the interface 13. Therefore, when the buffer becomes full, a long waiting time (Busy time) for communication with the host 8 occurs. If the arbitration unit 20 according to the present invention is mounted on such a data processing device 2a, the occurrence of buffer full can be prevented by changing the allocation of memory access, so that the waiting time for communication with the host 8 ( Busy time) can be reduced or eliminated, and the band rate between the host and the interface can be maximized.
[0040]
Note that the accumulated data amount N in the FIFO area 22 may be obtained by calculating a difference between a read address and a write address for the FIFO area 22 instead of a counter (up / down counter) for incrementing and decrementing data input / output. It is possible. For this reason, the data processing device 2a is provided with a function 19b for calculating the difference between these addresses as means for determining the accumulated data amount N.
[0041]
In the above description, as the first and second setting values, the accumulated data amount N of the FIFO area 22 is assigned a value that is half of the capacity of the area 22, but the data amount supplied to the FIFO area by the data supply device, The first and second set values can be set to values suitable for other systems according to the amount of data processed by the data consuming device.
[0042]
In addition, the method of checking (sampling) the access request of each channel includes a method of checking in order from the channel with the highest priority and a method of checking at the same time at a certain time. The present invention depends on the sampling method. is not.
[0043]
In the above description, the printer has been described as an example. However, the device or system to which the arbitration unit or the memory unit of the present invention can be applied is not limited to the printer. The arbitration unit or the memory unit of the present invention can be applied.
[0044]
【The invention's effect】
As described above, in the present invention, the priority of FIFO read access and FIFO write access is flexibly changed according to the amount of data stored in the FIFO area. Therefore, even if the FIFO read access and the FIFO write access are arbitrated so as to be in a state suitable for the system, it is possible to reliably prevent the occurrence of a buffer underrun or a buffer full, which leads to a decrease in system performance. It is possible to always bring out the maximum performance. That is, even when the memory in the system is shared as a FIFO, the access speed of the memory can be maximized, and a high-performance system can be constructed at low cost without mounting an excessively high-speed memory. .
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing a printer equipped with a data processing device according to the present invention.
FIG. 2 is a block diagram showing details of a memory unit mounted on the data processing device shown in FIG. 1;
FIG. 3 is a diagram showing how the setting of an arbitration unit is changed by a first setting unit, and FIG. 3 (a) is a diagram showing a method of changing only the relationship between FIFO read access and FIFO write access; FIG. 3B is a diagram showing a method for increasing the number of cycles by one.
FIG. 4 is a diagram showing how the setting of an arbitration unit is changed by a second setting unit, and FIG. 4 (a) is a diagram showing a method of changing only the relationship between FIFO read access and FIFO write access; FIG. 4B is a diagram showing a method for increasing the number of cycles by one.
FIG. 5 is a flowchart showing a process of changing the priority of FIFO read access and FIFO write access in the arbitration unit.
FIG. 6 is a diagram schematically illustrating a printer on which a different data processing device is mounted.
FIG. 7 is a diagram for explaining a method of arbitrating a memory in which a FIFO area is set using a round robin method.
[Explanation of symbols]
1 Printer
2, 2a Data processing device
3 Memory unit
14. Image processing ASIC (data supply device)
15 Memory controller
16 Mechanical control unit (data consuming device)
19 FIFO controller
19a counter (means for judging the amount of accumulated data)
20 Mediation unit
21 memory
22 Area for FIFO
24 Arbitration circuit
30 Setting section
31 First setting unit
32 Second setting unit
35 Arbitration Department

Claims (15)

A memory access arbitration method for permitting access to a memory in which a FIFO area is set,
Determining the amount of stored data stored in the FIFO area;
If it is determined that the accumulated data amount is larger than the first set value, a first condition for permitting access to the memory is set so that a FIFO read access for reading data from the FIFO area is prioritized. Process and
If it is determined that the accumulated data amount is smaller than the second set value, a second condition for permitting access to the memory is set so that FIFO write access for writing data to the FIFO area is prioritized. And a memory access arbitration method. 2. The method according to claim 1, wherein in the first step, the condition is set such that a frequency of the FIFO read access increases.
In the second step, a memory access arbitration method for setting the condition so that the frequency of the FIFO write access increases. 3. The condition according to claim 2, wherein in the first step, the condition is set such that a frequency of the FIFO read access is higher than a frequency of the FIFO write access.
In the second step, a memory access arbitration method for setting the condition such that a frequency of the FIFO read access is smaller than a frequency of the FIFO write access. 2. The memory access arbitration method according to claim 1, wherein the first and second set values are half of an allowable data amount that can be stored in the FIFO area. 2. The method according to claim 1, wherein in the first step, the FIFO read access is set to have priority over all accesses to the memory.
In the second step, a memory access arbitration method in which the FIFO write access is set to have priority over all accesses to the memory. 2. The memory access arbitration method according to claim 1, wherein in the first and second steps, only a relationship between the FIFO read access and the FIFO write access is set. A memory access arbitration unit for permitting access to a memory in which a FIFO area is set,
Means for determining the amount of stored data stored in the FIFO area;
If it is determined that the accumulated data amount is larger than the first set value, a first condition for permitting access to the memory is set so that a FIFO read access for reading data from the FIFO area is prioritized. Setting means,
If it is determined that the accumulated data amount is smaller than the second set value, a second condition for permitting access to the memory is set so that FIFO write access for writing data to the FIFO area is prioritized. A memory access arbitration unit comprising: 8. The method according to claim 7, wherein the first setting unit sets the condition so that a frequency of the FIFO read access increases.
The second setting unit is a memory access arbitration unit that sets the condition so that the frequency of the FIFO write access increases. 9. The method according to claim 8, wherein the first setting unit sets the condition such that a frequency of the FIFO read access is higher than a frequency of the FIFO write access.
The second setting means is a memory access arbitration unit that sets the condition such that the frequency of the FIFO read access is lower than the frequency of the FIFO write access. 8. The memory access arbitration unit according to claim 7, wherein the first and second set values are half of an allowable data amount that can be stored in the FIFO area. 8. The method according to claim 7, wherein the first setting unit sets the FIFO read access such that the FIFO read access is prioritized over all accesses to the memory.
The second setting means is a memory access arbitration unit for setting the FIFO write access such that the FIFO write access is prioritized for all accesses to the memory. 8. The memory access arbitration unit according to claim 7, wherein the first and second setting units set only a relationship between the FIFO read access and the FIFO write access. A memory unit comprising: the memory access arbitration unit according to claim 7; and a memory in which an area for FIFO is set, wherein the memory is permitted to be accessed by the memory access arbitration unit. 14. The memory unit according to claim 13, a data supply device that supplies data to an area for FIFO set in the memory, and a data consumption device that reads and consumes data stored in the area for FIFO. Data processing device. A program for arbitrating memory access for permitting access to a memory in which an area for FIFO is set,
Determining the amount of stored data stored in the FIFO area;
If it is determined that the accumulated data amount is larger than the first set value, a first condition for permitting access to the memory is set so that a FIFO read access for reading data from the FIFO area is prioritized. Process and
If it is determined that the accumulated data amount is smaller than the second set value, a second condition for permitting access to the memory is set so that FIFO write access for writing data to the FIFO area is prioritized. Having instructions capable of executing the steps of

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