JP2004038586A - Data processor, and system and method for processing data - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the memory capacity of a ROM, etc., for storing program data by varying the length of an instruction in response to a register usage frequency, and also setting the instruction being short in length in the register which frequently perform access. <P>SOLUTION: A data processing system includes: a program generating device 200 for compressing the number of instruction bits to specify the register ri based on the usage frequency of the register ri, describing register kinds in the instruction structure of the program, and also generating compressed programs AP being different in instruction length; and a data processor 100 for obtaining the compressed programs AP generated by the program generating device 200 so as to decode the register kinds, restoring the number of the instruction bits to specify the register ri based on the register kinds, designating the plurality of registers ri based on the program which is restored to have the instruction structure with the prescribed instruction length, and performing arbitrary calculation. <P>COPYRIGHT: (C)2004,JPO

Description

が表示される。このような代入・加算等の処理を示す「ｄｏ」が記述されている場合は、ステップＣ８に移行して現在のプログラムアドレスを記憶する。その後、ステップＣ１４に移行する。
【００９４】
ステップＣ７で「ｄｏ」が記述されていない場合はステップＣ９に移行してＣ言語のプログラムでその間の処理を示す「ｗｈｉｌｅ」が記述されているかをチェックする。このとき、表示装置２４のプログラム記述画面Ｐ１には、例えば、「ｗｈｉｌｅ」を示す
ｗｈｉｌｅ（ｃｏｕｎｔｅｒ　！＝ｅｎｄ　ｖａｌ）；
が表示される。このような比較・分岐等の処理を示す「ｗｈｉｌｅ」が記述されている場合は、ステップＣ１０に移行して代入・演算処理を実行する。
【００９５】
例えば、図９に示すサブルーチンをコールして、そのフローチャートのステップＥ１でＣ言語のプログラムにおいて、当該行が「ｗｈｉｌｅ」を記述している行かがチェックされる。「ｗｈｉｌｅ」が記述されている行の場合は、ステップＥ２に移行して後続の処理で生成する命令をｃｍｐ命令とする。その後、ステップＥ６に移行する。
【００９６】
ステップＥ１で「ｗｈｉｌｅ」が記述されていない行の場合は、ステップＥ３に移行して演算処理は加算かをチェックする。演算処理が加算の場合はステップＥ４に移行して後続の処理で生成する命令をａｄｄ命令とする。演算処理が加算ではない場合はステップＥ５に移行して後続の処理で生成する命令をｌｏａｄ命令とする。その後、ステップＥ６に移行する。
【００９７】
ステップＥ６ではレジスタｒｉに書き込まれる変数に対応するレジスタ番号と、レジスタアレイ１１から読み出される変数に対応するレジスタｒｉのレジスタ番号を調べられる。書込みアドレスＡｗ及び読み出しアドレスＡｒを決めるためである。その後、ステップＥ７に移行する。
【００９８】
ステップＥ７では両方のレジスタ番号が「３２」以上かをチェックする。両方のレジスタ番号が「３２」以上の場合はステップＥ８に移行して図５Ａに示した命令形態＃Ｆ１で命令を生成する。この命令形態＃Ｆ１で「レジスタ種類１」及び「レジスタ種類２」には「１」が記述される。このとき、「レジスタ種類１」及び「レジスタ種類２」は圧縮プログラムの命令構造の中に記述される。例えば、第３２番から第８１９１番のグループのレジスタｒ３２〜ｒ８１９１に関して「レジスタ種類１」及び「レジスタ種類２」に「１」が記述される。その後、図８に示したメインルーチンのステップＣ１０にリターンする。
【００９９】
また、ステップＥ７で両方のレジスタ番号が「３２」以上ではない場合はステップＥ９に移行して両方のレジスタ番号が「３１」以下かをチェックする。ここで両方のレジスタ番号が「３１」以下の場合はステップＥ１０に移行して図５Ｄに示した命令形態＃Ｆ４で命令を生成する。この命令形態＃Ｆ４で「レジスタ種類１」及び「レジスタ種類２」には「０」が記述される。このとき、「レジスタ種類１」及び「レジスタ種類２」は圧縮プログラムの命令構造の中に記述される。例えば、第０番から第３１番のグループのレジスタｒ０〜ｒ３１に関して「レジスタ種類１」及び「レジスタ種類２」に「０」が記述される。その後、図８に示したメインルーチンのステップＣ１０にリターンする。
【０１００】
更に、両方のレジスタ番号が「３１」以下ではない場合はステップＥ１１に移行してレジスタアレイ１１から読み出される変数のレジスタｒｉの番号が「３２」以上かをチェックする。読み出される変数のレジスタｒｉの番号が「３２」以上の場合は、ステップＥ１２に移行して図５Ｂに示した命令形態＃Ｆ２で命令を生成する。この命令形態＃Ｆ２で「レジスタ種類１」に「０」が記述され、「レジスタ種類２」には「１」が記述される。その後、図８に示したメインルーチンのステップＣ１０にリターンする。
【０１０１】
更にまた、レジスタアレイ１１から読み出される変数のレジスタｒｉの番号が「３２」以上ではない場合は、ステップＥ１３に移行して図５Ｃに示した命令形態＃Ｆ３で命令を生成する。この命令形態＃Ｆ３では「レジスタ種類１」に「１」が記述され、「レジスタ種類２」に「０」が記述される。その後、図８に示したメインルーチンのステップＣ１０にリターンする。その後、ステップＣ１１に移行してｊｕｍｐ命令を生成する。ｊｕｍｐ命令の飛び先は先に記憶したプログラムアドレスを用いる。その後、ステップＣ１４に移行する。
【０１０２】
上述のステップＣ９で「ｗｈｉｌｅ」が記述されていない場合はステップＣ１２に移行してＣ言語のプログラムにおいて、データの代入又は加算かをチェックする。データの代入又は加算の場合はステップＣ１３に移行してデータの代入又は演算処理を実行する。このステップＣ１３では、図９に示したサブルーチンをコールして、そのフローチャートのステップＥ１〜Ｅ１３を経て図８に示したメインルーチンのステップＣ１３にリターンする。その後、ステップＣ１４に移行する。
【０１０３】
また、ステップＣ１２でＣ言語のプログラムにおいて、データの代入又は加算ではない場合はステップＣ１４に移行する。ステップＣ１４ではＣ言語のプログラムに関して最後の行かをチェックされる。最後の行ではない場合は、ステップＣ１５に移行してプログラムアドレスを進める。その後、ステップＣ２に戻って上述したコンパイル処理を繰り返すようになされる。最後の行に至ってこのコンパイル処理を終了する。
【０１０４】
これにより、図５Ａ〜図５Ｅに示したような命令形態＃Ｆ１〜＃Ｆ５であって、命令長の異なる圧縮プログラムＡＰを作成することができる。この圧縮プログラムＡＰにおいて、第０番から第３１番のグループのレジスタｒ０〜ｒ３１を指定する命令ビット数に関してはｍ＝５ビットであり、第３２番から第８１９１番のグループのレジスタｒ３２〜ｒ８１９１を指定する命令ビット数に関してはｎ＝１３ビットである。
【０１０５】
続いて、プログラム実行系ＩＩにおける処理例について説明をする。図１０は復元された演算プログラムによる演算命令の例を示す表図である。図１１はレジスタｒ０，ｒ１・・・・ｒ３２，ｒ３３，ｒ３４，ｒ３５等の状態例、図１２は外部メモリ２におけるデータ格納例を各々示すイメージ図である。
【０１０６】
この例では、データ処理装置１００に接続された外部メモリ２の中に図１２に示すような１０個のメモリセルの配列を二組用意する。一方はメモリ配列＃Ｍ１で、他方はメモリ配列＃Ｍ２である。そして、図１０に示す８つの演算命令（Ｉｎｓｔｒｕｃｔｉｏｎ）＃Ｉ１〜＃Ｉ８に基づいて、その一組のメモリ配列＃Ｍ１に格納された値に「１」を加算し、もう一組のメモリ配列＃Ｍ２にその結果を格納する演算処理の例を挙げる。
【０１０７】
図１０に示す演算命令（Ｉｎｓｔｒｕｃｔｉｏｎ）＃Ｉ１〜＃Ｉ８はＲＯＭ１４の圧縮プログラムＡＰを復元した後の演算プログラムによるものである。この演算プログラムでは図１１に示すように、アクセス頻度が高いレジスタｒｉが二つあるため、これらをそれぞれｒ０とｒ１に割り当てた。これにより、プログラム全体の長さを圧縮する前の演算プログラムに比べて効率よく短縮することができた。
【０１０８】
また、図１１において、レジスタ番号ｒ０で示されるレジスタは一時的に使用され、レジスタ番号ｒ１で示されるレジスタには加算値「１」が格納される。また、レジスタ番号ｒ３２で示されるレジスタには読み出しアドレス「０」が格納され、レジスタ番号ｒ３３で示されるレジスタには書込みアドレス「１０」が格納され、レジスタ番号ｒ３４で示されるレジスタにはカウンタの初期値「０」が格納され、レジスタ番号ｒ３５で示されるレジスタには演算回数値（終了値）「１０」が格納される。
【０１０９】
図１０に示す各々の演算命令＃Ｉ１〜＃Ｉ８には、ニーモニックによる表現、機械語による表現及び処理の内容が示されている。演算命令＃Ｉ１は図５に示した命令構造において、機械語で１４００２０ｈによって表されるｌｏａｄ，ｒ０，（ｒ３２）であり、レジスタアレイ１１のレジスタｒ３２の値をアドレスとし、外部メモリ２から読み出した値をレジスタｒ０に格納する内容である。動作としては例えば、レジスタｒ３２の値を「０」としたとき、図１２に示した外部メモリ２の読み出しアドレスが「０」の内容である、メモリ配列＃Ｍ１のデータ「０」が読み出され、このデータ「０」がレジスタｒ０に書き込まれる。
【０１１０】
演算命令＃Ｉ２は機械語で４００１ｈによって表されるａｄｄ，ｒ０，ｒ１であり、レジスタアレイ１１のレジスタｒ０にレジスタｒ１の値を加算し、その結果をレジスタｒ０に格納する内容である。動作としてはレジスタｒ０の内容である「０」にレジスタｒ１の値である「１」が加算され、その結果「１」がレジスタｒ０に書き込まれる。
【０１１１】
演算命令＃Ｉ３は機械語で２８０４２０ｈによって表されるｌｏａｄ，（ｒ３３），ｒ０であり、レジスタアレイ１１のレジスタｒ３３の値をアドレスとして、レジスタｒ０の値を外部メモリ２に書き込む内容である。動作としてはレジスタｒ３３が示す外部メモリ２のメモリ配列＃Ｍ２のアドレスにデータ「１」が書き込まれる。
【０１１２】
演算命令＃Ｉ４は機械語で４８０４０１ｈによって表されるａｄｄ，ｒ３２，ｒ１であり、レジスタアレイ１１のレジスタｒ３２にレジスタｒ１の値を加算して、その結果をレジスタｒ３２に格納する内容である。動作としてはレジスタｒ３２の内容である「０」にレジスタｒ１の値である「１」が加算され、その結果「１」がレジスタｒ３２に書き込まれる。
【０１１３】
演算命令＃Ｉ５は機械語で４８０４２１ｈによって表されるａｄｄ，ｒ３３，ｒ１であり、レジスタアレイ１１のレジスタｒ３３にレジスタｒ１の値を加算して、その結果をレジスタｒ３３に格納する内容である。動作としてはレジスタｒ３３の内容である「０」にレジスタｒ１の値である「１」が加算され、その結果「１」がレジスタｒ３３に書き込まれる。
【０１１４】
演算命令＃Ｉ６は機械語で４８０４４１ｈによって表されるａｄｄ，ｒ３４，ｒ１であり、レジスタアレイ１１のレジスタｒ３４にレジスタｒ１の値を加算して、その結果をレジスタｒ３４に格納する内容である。動作としてはレジスタｒ３４の内容である「０」にレジスタｒ１の値である「１」が加算され、その結果「１」がレジスタｒ３４に書き込まれる。この演算命令＃Ｉ４〜＃Ｉ６によって実行ステートマシーン５１内のカウンタでは読み出しアドレスＡｒ及び書き込みアドレスＡｗに関して「１」が加算される。
【０１１５】
演算命令＃Ｉ７は機械語で８Ｃ０４４０２３ｈによって表されるｃｍｐ，ｒ３４，ｒ３５であり、レジスタアレイ１１のレジスタｒ３４の内容とレジスタｒ３５の内容とを比較し、その値が同じ場合は、ｚｅｒｏ　ｆｌａｇに「１」をセットし、異なっている場合は「０」にセットする内容である。動作としてはレジスタｒ３４とレジスタｒ３５の値である「１」と「１０」は異なるので、ｚｅｒｏｆｌａｇには「０」がセットされる。ｚｅｒｏ　ｆｌａｇの値はラッチ回路５１０によって保持され、以降の命令によって参照される。
【０１１６】
演算命令＃Ｉ８は機械語でＥ０００００ｈによって表されるｊｕｍｐ　ｎｚ，ＬＯＯＰであり、ｚｅｒｏ　ｆｌａｇが「０」の場合は、ＬＯＯＰで示されるラベルへ制御を移す内容である。動作としては、ｚｅｒｏ　ｆｌａｇが「０」の場合は制御を演算命令＃Ｉ１に移す。上記の動作が１０回、繰り返されるとレジスタｒ３４の値が「１０」になり、演算命令＃Ｉ７によりｚｅｒｏ　ｆｌａｇが「１」にセットされ、演算命令＃Ｉ８で制御が移らなくなり、演算処理を終了するようになされる。このように、全てのレジスタｒｉの命令ビット数を単一の方法で表現した場合と比べて、効率良くＲＯＭ１４を使用することが可能になる。
【０１１７】
続いて、マイクロプロセッサ１０１における動作例について説明をする。図１３はマイクロプロセッサ１０１における動作例を示すフローチャートである。図１４及び図１５は命令ビット復元デコーダ１３における処理例（その１，２）を示すフローチャートである。
【０１１８】
この実施例ではマイクロプロセッサ１０１がプログラム実行系ＩＩを構成し、ＲＯＭ１４から読み出された圧縮プログラムＡＰから図１０に示した演算命令＃Ｉ１〜＃Ｉ８を含む演算プログラムを復元する。このとき、命令形態＃Ｆ１〜＃Ｆ４に関して「レジスタ種類１」及び、「レジスタ種類２」にコード「０」が記述されている場合は、命令ビット復元デコーダ１３によってレジスタ番号の拡張が行われる。この際の命令ビットの拡張では、例えば、「レジスタ番号１」の命令ビット数ｍ＝５ビットの上位に８ビットの「０」を追加するようになされる。この演算プログラムに基づいて、図１２に示した外部メモリ２の中のメモリ配列＃Ｍ１の値に「１」を加算し、メモリ配列＃Ｍ２に格納するようになされる。
【０１１９】
レジスタアレイ１１のレジスタ状態については、図１１に示したように例えば、６個のレジスタｒ０，ｒ１，ｒ３２，ｒ３３，ｒ３４，ｒ３５に関して、ｒ０が不定、ｒ１が初期値「１」、ｒ３２及びｒ３４が共に初期値「０」、ｒ３３及びｒ３５が初期値「１０」が設定される。これらの値を書き込む場合は、実行ステートマシーン５１ではレジスタアレイ１１に書き込みアドレスＡｗが出力され、その初期値「０」、「１」、「１０」が設定される。
【０１２０】
これを動作条件にして、図１３に示すフローチャートのステップＦ１で、まず、命令ビット復元デコーダ１３はＲＯＭ１４から圧縮プログラム（機械語命令）ＡＰを順次受け取り、このプログラムＡＰを解読して所定の命令長の演算命令＃Ｉ１〜＃Ｉ８を検出する。
【０１２１】
この命令ビット復元デコーダ１３は例えば、図１４に示すサブルーチンをコールしてそのフローチャートのステップＧ１で命令部分を取り出し、命令信号Ｓ９を実行ステートマシーン５１に出力する。これと共に、命令ビット復元デコーダ１３ではステップＧ２に移行して当該命令形態がｊｕｍｐ命令であるかをチェックする。当該命令形態が＃Ｆ５で示されるｊｕｍｐ命令の場合はステップＧ１２に移行してｆｌａｇ　ｃｏｎｄｉｔｉｏｎ、ｊｕｍｐ　ａｄｄｒｅｓｓを出力する。その後、メインルーチンのステップＦ１にリターンする。
【０１２２】
また、ステップＧ２で当該命令形態がｊｕｍｐ命令でない場合は、ステップＧ４に移行して当該命令形態に関して「レジスタ種類１」に記述されているコードは「０」又は「１」かをチェックする。「レジスタ種類１」にコード「０」が記述されている場合はステップＧ４に移行して「レジスタ番号１」の命令ビット数ｍを５ｂｉｔ長として圧縮プログラムＡＰから取り出す。その後、ステップＧ５に移行して「レジスタ番号１」の命令ビット数ｍ＝５ｂｉｔの上位８ビットに「０」を付加して１３ｂｉｔ長とする。その後、ステップＧ７に移行する。
【０１２３】
上述のステップＧ３で「レジスタ種類１」にコード「１」が記述されている場合はステップＧ６に移行して「レジスタ番号１」の命令ビット数ｎを１３ｂｉｔ長として圧縮プログラムＡＰから取り出す。その後、ステップＧ７に移行して、当該命令形態に関して「レジスタ種類２」に記述されているコードは「０」又は「１」かをチェックする。「レジスタ種類２」にコード「０」が記述されている場合はステップＧ８に移行して「レジスタ番号２」の命令ビット数ｍを５ｂｉｔ長として圧縮プログラムＡＰから取り出す。その後、ステップＧ９に移行して「レジスタ番号２」の命令ビット数ｍ＝５ｂｉｔの上位８ビットに「０」を付加して１３ｂｉｔ長とする。その後、ステップＧ１１に移行する。
【０１２４】
上述のステップＧ７で「レジスタ種類２」にコード「１」が記述されている場合はステップＧ１０に移行して「レジスタ番号２」の命令ビット数ｎを１３ｂｉｔ長として圧縮プログラムＡＰから取り出す。その後、ステップＧ１１に移行して、「レジスタ番号１」、「レジスタ番号２」、「アクセス方法＃１」及び「アクセス方法＃２」を検出する。
【０１２５】
その後、図１３に示したメインルーチンのステップＦ１にリターンする。従って、実行ステートマシン５１には「レジスタ種類１」及び「レジスタ種類２」は出力されず、所定の命令長の演算命令＃Ｉ１〜＃Ｉ８に基づく命令制御信号Ｓ４、命令信号Ｓ９及び各引数信号Ｓ１０が出力される。
【０１２６】
この命令信号Ｓ９にはｌｏａｄ命令、ａｄｄ命令、ｃｍｐ命令、ｊｕｍｐ命令が含まれる。各引数信号Ｓ１０にはアクセス方法＃１，アクセス方法＃２，レジスタ番号ｒ０，ｒ１・・・等、フラグ状態（ｆｌａｇ　ｃｏｎｄｉｔｉｏｎ）及びジャンプアドレス等が含まれる。命令制御信号Ｓ４はデコーダ１３から命令読出しステートマシーン５２に出力される。
【０１２７】
なお、ＲＯＭ１４で圧縮プログラムＡＰを読み出す場所（アドレス）はプログラムカウンタ５４（ＰＣ）によって指定される。これらの読み出しの動作は命令読み出しステートマシーン５２によって制御される。
【０１２８】
命令読出しステートマシーン５２では命令ビット復元デコーダ１３から出力される命令制御信号Ｓ４に基づいてプログラムカウンタ５４及び実行ステートマシーン５１を制御する。例えば、当該マシーン５２は命令ビット復元デコーダ１３から命令信号Ｓ９及び各引数信号Ｓ１０が実行ステートマシーン５１へ出力されると共に命令実行開始信号Ｓ２９を出力する。
【０１２９】
実行ステートマシーン５１では命令実行開始信号Ｓ２９に基づいて命令の実行を開始する。例えば、データの書込み時には、書込み制御信号Ｓｗがレジスタアレイ１１に出力され、セレクタ５９には選択制御信号Ｓ２４が出力される。データの読出し時には、レジスタアレイ１１に読出しアドレスＡｒが出力される。
【０１３０】
演算時には、ラッチ制御信号Ｓ３４がラッチ回路５８に出力され、ラッチ回路５１０にはラッチ制御信号Ｓ３８が出力される。当該プロセッサ外部には外部制御信号Ｓ１６が出力される。命令の実行が終了すると、実行ステートマシーン５１は命令読み出しステートマシーン５２へ実行終了信号Ｓ２６を出力し、プログラムカウンタ５４の値を進めるようになされる。
【０１３１】
プログラムカウンタ５４ではカウント制御信号Ｓ３０に基づいてＲＯＭ１４から圧縮プログラムＡＰを読み出す場所が指定される。＋１インクリメンタ５５はプログラムカウンタ５４のカウント出力信号Ｓ５を「＋１」してインクリメンとするようになされる。
【０１３２】
そして、ステップＦ２で実行ステートマシーン５１は命令読出しステートマシーン５２の命令読出し制御を受けて演算命令＃Ｉ１を受け取ると、機械語で１４００２０ｈによって表されるｌｏａｄ，ｒ０，（ｒ３２）に基づいて書込み信号Ｓ１６を外部メモリ２に出力する。この値はレジスタアレイ１１の読み出しアドレスＡｒとして用いられる。レジスタアレイ１１は３２番目の値をデータ信号線Ｌ２０に出力する。
【０１３３】
この値はラッチ回路５１１によって保持され、アドレスバス１９Ｂを経由し、外部メモリ２へ出力される。そして、レジスタアレイ１１のレジスタｒ３２の値をアドレスとし、外部メモリ２から読み出した値をレジスタｒ０に格納する。このとき、レジスタｒ３２の値が「０」であるので、図１２に示した外部メモリ２のアドレスが「０」の内容であるメモリ配列＃Ｍ１のデータ「０」が読み出され、このデータ「０」がレジスタｒ０に書き込まれる。
【０１３４】
つまり、外部メモリ２からアドレスバス１９Ｂによって転送されたアドレス（場所）のデータがセレクタ５９に出力される。実行ステートマシーン５１ではこのデータが選択されるように、選択信号Ｓ２４を出力する。これにより、データがレジスタアレイ１１に入力される。そして、実行ステートマシーン５１では書き込みアドレスＡｗ＝「０」をレジスタアレイ１１に出力する。その後、実行ステートマシン５１は書き込み信号Ｓｗを用いて実際に、演算結果値の書き込みを指示するようになされる。
【０１３５】
その後、ステップＦ３で実行ステートマシン５１は命令読出しステートマシーン５２の命令読出し制御を受けて演算命令＃Ｉ２を受け取ると、機械語で４００１ｈによって表されるａｄｄ，ｒ０，ｒ１に基づいてレジスタアレイ１１のレジスタｒ０にレジスタｒ１の値を加算し、その結果をレジスタｒ０に格納する。このとき、レジスタｒ０の内容である「０」にレジスタｒ１の値である「１」が加算され、その結果「１」がレジスタｒ０に書き込まれる。
【０１３６】
そして、ステップＦ４で実行ステートマシン５１は命令読出しステートマシーン５２の命令読出し制御を受けて演算命令＃Ｉ３を受け取ると、機械語で２８０４２０ｈによって表されるｌｏａｄ，（ｒ３３），ｒ０に基づいてレジスタアレイ１１のレジスタｒ３３の値をアドレスとして、レジスタｒ０の値を外部メモリ２に書き込む。このとき、レジスタｒ３３が示す外部メモリ２のメモリ配列＃Ｍ２のアドレスにデータ「１」が書き込まれる。
【０１３７】
その後、ステップＦ５で実行ステートマシン５１は命令読出しステートマシーン５２の命令読出し制御を受けて演算命令＃Ｉ４を受け取ると、機械語で４８０４０１ｈによって表されるａｄｄ，ｒ３２，ｒ１に基づいてレジスタアレイ１１のレジスタｒ３２にレジスタｒ１の値を加算して、その結果をレジスタｒ３２に格納する。このとき、レジスタｒ３２の内容である「０」にレジスタｒ１の値である「１」が加算され、その結果「１」がレジスタｒ３２に書き込まれる。この演算命令＃Ｉ４によって実行ステートマシーン５１内のカウンタでは読み出しアドレスＡｒ及び書き込みアドレスＡｗに関して「１」が加算される。
【０１３８】
そして、ステップＦ６で実行ステートマシン５１は命令読出しステートマシーン５２の命令読出し制御を受けて演算命令＃Ｉ５を受け取ると、機械語で４８０４２１ｈによって表されるａｄｄ，ｒ３３，ｒ１に基づいてレジスタアレイ１１のレジスタｒ３３にレジスタｒ１の値を加算して、その結果をレジスタｒ３３に格納する。このとき、レジスタｒ３３の内容である「０」にレジスタｒ１の値である「１」が加算され、その結果「１」がレジスタｒ３３に書き込まれる。この演算命令＃Ｉ５によって実行ステートマシーン５１内のカウンタでは読み出しアドレスＡｒ及び書き込みアドレスＡｗに関して「１」が加算される。
【０１３９】
その後、ステップＦ７で実行ステートマシン５１は命令読出しステートマシーン５２の命令読出し制御を受けて演算命令＃Ｉ６を受け取ると、機械語で４８０４４１ｈによって表されるａｄｄ，ｒ３４，ｒ１に基づいてレジスタアレイ１１のレジスタｒ３４にレジスタｒ１の値を加算して、その結果をレジスタｒ３４に格納する。このとき、レジスタｒ３４の内容である「０」にレジスタｒ１の値である「１」が加算され、その結果「１」がレジスタｒ３４に書き込まれる。この演算命令＃Ｉ６によって実行ステートマシーン５１内のカウンタでは読み出しアドレスＡｒ及び書き込みアドレスＡｗに関して「１」が加算される。
【０１４０】
この例では、ステップＦ８でレジスタｒ３５が示す値＝１０回に至ったかが判別される。例えば、実行ステートマシン５１は命令読出しステートマシーン５２の命令読出し制御を受けて演算命令＃Ｉ７を受け取ると、機械語で８Ｃ０４４０２３ｈによって表されるｃｍｐ，ｒ３４，ｒ３５に基づいてレジスタアレイ１１のレジスタｒ３４の内容とレジスタｒ３５の内容とを比較し、その値が同じ場合は、ｚｅｒｏ　ｆｌａｇに「１」をセットし、異なっている場合は「０」にセットする。このとき、レジスタｒ３４とレジスタｒ３５の値である「１」と「１０」は異なるので、ｚｅｒｏ　ｆｌａｇには「０」がセットされる。ｚｅｒｏ　ｆｌａｇの値はラッチ回路５１０によって保持され、以降の命令によって参照される。
【０１４１】
そして、実行ステートマシン５１は命令読出しステートマシーン５２の命令読出し制御を受けて演算命令＃Ｉ８を受け取ると、機械語でＥ０００００ｈによって表されるｊｕｍｐ　ｎｚ，ＬＯＯＰに基づいてｚｅｒｏ　ｆｌａｇが「０」の場合は、ＬＯＯＰで示されるラベルへ制御を移行する。ｚｅｒｏ　ｆｌａｇが「０」の場合は制御をステップＦ２の演算命令＃Ｉ１に移す。上記の動作がステップＦ８で１０回繰り返されるとレジスタｒ３４の値が「１０」になり、演算命令＃Ｉ７によりｚｅｒｏ　ｆｌａｇが「１」にセットされ、演算命令＃Ｉ８で制御が移らなくなり、演算処理を終了するようになされる。
【０１４２】
このように、本発明に係る実施例としてのマイクロプロセッサ１０１によれば、８１９２個のレジスタｒ０〜ｒ８１９１の中でその使用頻度に基づいて当該レジスタｒｉを指定する命令ビット数が予め圧縮されると共に、当該プログラムの命令構造の中に「レジスタ種類１」及び「レジスタ種類２」が記述された命令長の異なる圧縮プログラムＡＰに基づいてデータを処理するようになされる。
【０１４３】
ＲＯＭ１４には８１９２個のレジスタｒ０〜ｒ８１９１の中から当該レジスタｒｉを指定するための圧縮プログラムＡＰが記憶される。命令ビット復元デコーダ１３では、このＲＯＭ１４から圧縮プログラムＡＰを読み出して「レジスタ種類１」及び「レジスタ種類２」が解読され、この「レジスタ種類１」及び「レジスタ種類２」に基づいて当該レジスタｒｉを指定するための命令ビット数が復元される。
【０１４４】
従って、レジスタｒｉの使用頻度に応じて可変された命令の長さの圧縮プログラムＡＰであって、頻繁にアクセスするレジスタｒ０〜ｒ３１には短い長さの命令がセットされた、圧縮プログラムデータをＲＯＭ１４に格納することができるので、そのメモリ容量を低減することができる。この例ではプログラムを圧縮する前に比べて１６ビット×３２個×命令数分だけメモリ容量を低減できる。
【０１４５】
これにより、メモリセルや論理演算素子から成るＰＬＤによりマイクロプロセッサ１０１を構築する場合に、ＲＯＭとして機能させるメモリセルの占有率を低減することができ、その分のメモリセルをレジスタに多く割り当てることができるようになる。
【０１４６】
【発明の効果】
以上説明したように、本発明に係るデータ処理システムによれば、一方で、所定のプログラム言語に基づいて目的の演算処理を実行するための命令を編集してプログラムを作成し、他方で、当該プログラムと複数のレジスタとを使用してデータを処理する場合に、プログラム作成系で作成された圧縮プログラムを取得してレジスタ種類を解読し、このレジスタ種類に基づいて当該レジスタを指定する命令ビット数を復元し、所定長さの命令に基づいて複数のレジスタを指定して任意の演算を実行するデータ処理装置を備えるものである。
【０１４７】
この構成によって、プログラム作成系ではレジスタの使用頻度に応じて命令の長さを可変できるので、頻繁にアクセスするレジスタに短い長さの命令をセットすることができる。従って、プログラム実行系ではプログラムデータを格納するＲＯＭ等のメモリ容量を低減することができる。また、メモリセルや論理演算素子から成るＰＬＤによりプロセッサを構築する場合に、ＲＯＭとして機能させるメモリセルの占有率を低減することができ、その分のメモリセルをレジスタに多く割り当てることができる。
【０１４８】
本発明に係るデータ処理装置によれば、レジスタを使用する頻度に基づいて当該レジスタを指定する命令ビット数が予め圧縮されると共に、当該プログラムの命令構造の中にレジスタ種類が記述された命令長の異なる圧縮プログラムに基づいてデータを処理する場合に、この圧縮プログラムから解読したレジスタ種類に基づいて当該レジスタを指定するための命令ビット数を復元する命令解読復元手段を備え、この命令解読復元手段によって復元された所定長の命令に基づいてレジスタを指定して任意の演算を実行するものである。
【０１４９】
この構成によって、レジスタの使用頻度に応じて可変された命令の長さの圧縮プログラムであって、頻繁にアクセスするレジスタには短い長さの命令がセットされた、圧縮プログラムデータを記憶手段に格納することができるので、そのメモリ容量を低減することができる。従って、メモリセルや論理演算素子から成るＰＬＤによりプロセッサを構築する場合に、ＲＯＭとして機能させるメモリセルの占有率を低減することができ、その分のメモリセルをレジスタに多く割り当てることができる。
【０１５０】
本発明に係るデータ処理方法によれば、プログラム作成系で所定のプログラム言語に基づいて目的の演算処理を実行するための命令を編集してプログラムを作成し、プログラム実行系で当該プログラムと複数のレジスタとを使用してデータを処理する場合に、プログラム作成系では、レジスタを使用する頻度に基づいて当該レジスタを指定する命令ビット数を圧縮すると共に、当該プログラムの命令構造の中にレジスタ種類を記述して命令長の異なる圧縮プログラムを作成し、プログラム実行系では、プログラム作成系で作成された圧縮プログラムを取得してレジスタ種類を解読し、ここで解読されたレジスタ種類に基づいて当該レジスタを指定する命令ビット数を復元し、ここで復元された所定長さの命令に基づいて複数のレジスタを指定して任意の演算を実行するようになされる。
【０１５１】
この構成によって、プログラム作成系ではレジスタの使用頻度に応じて命令の長さを可変できるので、頻繁にアクセスするレジスタに短い長さの命令をセットすることができる。従って、プログラム実行系ではプログラムデータを格納するＲＯＭ等のメモリ容量を低減することができる。また、メモリセルや論理演算素子から成るＰＬＤによりプロセッサを構築する場合に、ＲＯＭとして機能させるメモリセルの占有率を低減することができ、その分のメモリセルをレジスタに多く割り当てることができる。
【０１５２】
この発明は命令実行プログラム等に基づいて各種データ処理をするＣＰＵや、ＭＰＵ、ＰＬＤ等、これらの組み込み電子機器に適用して極めて好適である。
【図面の簡単な説明】
【図１】本発明に係る実施形態としてのデータ処理システム１０の構成例を示すブロック図である。
【図２】データ処理システム１０における処理例を示すフローチャートである。
【図３】本発明に係る実施例としてのマイクロプロセッサ１０１の構成例を示すブロック図である。
【図４】レジスタアレイ１１の内部構成例を示すブロック図である。
【図５】Ａ〜ＥはＲＯＭ１４にセットされる命令の構造例を示すフォーマットである。
【図６】Ａ〜Ｄは命令構造における記述内容例を示す表図である。
【図７】プログラム作成系Ｉにおけるプログラム作成例を示す表図である。
【図８】プログラム作成装置２００におけるコンパイル例を示すフローチャート（メインルーチン）である。
【図９】コンパイラにおける代入及び演算処理例を示すフローチャート（サブルーチン）である。
【図１０】復元された演算プログラムによる演算命令の例を示す表図である。
【図１１】ｒ０，ｒ１・・・・ｒ３２，ｒ３３，ｒ３４，ｒ３５等のレジスタの状態例を示すイメージ図である。
【図１２】外部メモリ２におけるデータ格納例を示すイメージ図である。
【図１３】マイクロプロセッサ１０１における動作例を示すフローチャートである。
【図１４】命令ビット復元デコーダ１３における処理例（その１）を示すフローチャートである。
【図１５】命令ビット復元デコーダ１３における処理例（その２）を示すフローチャートである。
【符号の説明】
２・・・外部メモリ、３・・・命令解読復元手段、４・・・記憶手段、１０・・・データ処理システム、１１・・・レジスタアレイ、１２・・・ＡＬＵ、１３・・・命令ビット復元デコーダ（命令解読復元手段）、１４・・・ＲＯＭ（記憶手段）、５０・・・命令実行演算手段、１００・・・データ処理装置、１０１・・・マイクロプロセッサ、２００・・・プログラム作成装置[0001]
TECHNICAL FIELD OF THE INVENTION
INDUSTRIAL APPLICABILITY The present invention is applied to a central processing unit (CPU), a microprocessor unit (MPU), and the like that perform various data processing based on a system program, a programmable logical operation element (PLD), and an electronic device embedded therein. A data processing system, a data processing device, and a data processing method.
[0002]
In detail, a data processing device is provided that executes an arbitrary operation by designating a plurality of registers, obtains a compression program created by a program creation system, decodes a register type, and registers the register based on the register type. By restoring a designated instruction bit number and restoring a program having an instruction structure of a prescribed instruction length, it is possible to reduce the memory capacity of a ROM or the like for storing program data, In the case where a processor is constructed by using a PLD composed of PLDs, the occupancy of memory cells functioning as ROM can be reduced.
[0003]
[Prior art]
2. Description of the Related Art In recent years, microprocessors including a central processing unit (CPU) have been often used in various electronic devices such as mobile terminal devices, electronic cards, and information processing devices. In this type of processor, a read-only memory (hereinafter, referred to as a ROM) for storing an instruction execution program, many registers used for the instruction execution operation processing, and the like are mounted in addition to the instruction execution operation unit.
[0004]
According to a conventional microprocessor, when a processor is incorporated in an arbitrary electronic device and used, an instruction for performing a certain operation corresponds one-to-one with an instruction for performing the operation. In other words, a register created by a uniform-length instruction with the same number of instruction bits for designating the register is often used for both the frequently used register and the infrequently used register. Thus, the fixed-length instructions are stored in the ROM and used.
[0005]
On the other hand, with the development of semiconductor integrated circuit technology, it has become possible to mount a large number of registers in a processor (hereinafter also referred to as a data processing device). In this case, the number of instruction bits for specifying the register is required more and more. For example, when 1024 registers are implemented, 10 bits are required as instruction bits to specify one of the 1024 registers. However, in an actual program, the access frequency to all the registers is not uniform, and the access frequency varies. The number of frequently accessed registers is generally determined by the compiler.
[0006]
[Problems to be solved by the invention]
By the way, according to the conventional data processing device, there are the following problems in mounting a ROM for storing an instruction execution program.
[0007]
{Circle around (1)} When looking at the entire code of the instruction execution program, among the 10 instruction bits for designating a register, for example, the entire 10 bits are rarely used uniformly. Therefore, there are many useless bits in a memory (for example, a ROM or a flash memory) for storing an instruction execution program. Thus, a method of expressing all registers with a single instruction bit number hinders efficient use of the ROM.
[0008]
{Circle around (2)} When an attempt is made to construct a microprocessor or the like using a programmable logic device (PLD) including a memory cell and a logic operation element, an instruction execution operation unit is arranged on the same semiconductor chip. A method of arranging a register array, a ROM, and the like in a peripheral portion thereof can be considered. In this case, if the number of instruction execution programs increases due to a demand for multifunctional processors, a large memory capacity of a ROM for storing the programs is required. Therefore, the memory cells are occupied by the construction of the ROM, and it becomes difficult to allocate many memory cells to the registers.
[0009]
In view of the above, the present invention has been made to solve such a conventional problem. In addition to making it possible to change the length of an instruction according to the frequency of use of a register, a frequently accessed register has a short instruction length. It is an object of the present invention to provide a data processing system, a data processing device, and a data processing method that can set a data processing method and reduce a memory capacity of a ROM or the like for storing program data.
[0010]
[Means for Solving the Problems]
The problem described above is, on the one hand, to create a program by editing instructions for executing a target arithmetic processing based on a predetermined programming language, and, on the other hand, to use the program and a plurality of registers to transfer data. A processing system that compresses the number of instruction bits specifying a register based on the frequency of use of the register, and describes a register type in the instruction structure of the program to create a compressed program having a different instruction length. A program creating device that obtains the compressed program created by the program creating device, decodes the register type, restores the number of instruction bits specifying the register based on the register type, and And a data processing device for executing an arbitrary operation by designating a plurality of registers. It is resolved by the arm.
[0011]
According to the data processing system of the present invention, on the one hand, an instruction for executing a target arithmetic processing is edited based on a predetermined program language to create a program, and on the other hand, the program and a plurality of registers are created. When processing data using, the program creation device compresses the number of instruction bits that specify the register based on the frequency of using the register, and describes the register type in the instruction structure of the program. Compression programs with different instruction lengths are created.
[0012]
The data processing device obtains the compressed program created by the program creating device, decodes the register type, restores the number of instruction bits designating the register based on the register type, and, based on the instruction of a predetermined length, An arbitrary operation is executed by designating a plurality of registers.
[0013]
Therefore, in the program creation system, the length of an instruction can be changed according to the frequency of use of the register, so that an instruction having a short length can be set in a frequently accessed register. As a result, in the program execution system, compressed instructions can be set in the ROM or the like, and the memory capacity of the ROM or the like for storing program data can be reduced. Further, when a processor is constructed by a PLD including memory cells and logical operation elements, the occupancy of the memory cells functioning as ROM can be reduced, and more memory cells can be allocated to registers.
[0014]
In the data processing device according to the present invention, the number of instruction bits designating the register is compressed in advance based on the frequency of using the register, and the instruction length of the instruction type in which the register type is described in the instruction structure of the program is different. An apparatus for processing data based on a compression program, comprising: a plurality of registers; storage means for storing a compression program for designating the registers; and reading a compression program from the storage means to decode a register type. Instruction decoding and restoring means for restoring the number of instruction bits for designating a register based on a register type, and executing an arbitrary operation by designating a register based on an instruction of a predetermined length restored by the instruction decoding and restoring means And an instruction execution calculating means.
[0015]
According to the data processing device of the present invention, the number of instruction bits for designating a register is pre-compressed based on the frequency of using the register, and the instruction length in which the register type is described in the instruction structure of the program When processing data based on different compression programs, a storage program stores a compression program for designating the register from among a plurality of registers. In the instruction decoding and restoring means, the compression program is read from the storage means to decode the register type, and the number of instruction bits for designating the register is restored based on the register type. On the premise of this, the instruction execution operation means executes an arbitrary operation by designating a register based on a program of a predetermined instruction length restored by the instruction decoding / reconstruction means.
[0016]
Therefore, it is possible to store compressed program data in a storage means, which is a compression program having an instruction length that is variable according to the frequency of use of a register, wherein an instruction of a short length is set in a frequently accessed register. Therefore, the memory capacity can be reduced. This makes it possible to reduce the occupancy of the memory cells functioning as the ROM when constructing a processor using the PLD including the memory cells and the logic operation elements, and allocate more memory cells to the registers.
[0017]
The data processing method according to the present invention edits an instruction for executing a target arithmetic process based on a predetermined program language in a program creation system to create a program, and the program execution system associates the program with a plurality of registers. This is a method of processing data using a program. In a program creation system, the number of instruction bits specifying the register is compressed based on the frequency of use of the register, and the register type is described in the instruction structure of the program. To create compressed programs with different instruction lengths, and the program execution system obtains the compressed program created by the program creation system, decodes the register type, and specifies the register based on the decoded register type. The number of instruction bits to be restored is specified, and a plurality of registers are specified based on the restored instructions of a predetermined length. It is characterized in that to perform any operation.
[0018]
According to the data processing method according to the present invention, a program creation system edits an instruction for executing a target arithmetic process based on a predetermined program language to create a program, and the program execution system combines the program with a plurality of programs. When processing data using registers, the length of instructions can be varied according to the frequency of use of registers in the program creation system, so that short-length instructions can be set in frequently accessed registers. .
[0019]
Therefore, in the program execution system, the compressed instruction can be set in the ROM or the like, and the memory capacity of the ROM or the like for storing the program data can be reduced. Further, when a processor is constructed by a PLD including memory cells and logical operation elements, the occupancy of the memory cells functioning as ROM can be reduced, and more memory cells can be allocated to registers.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an embodiment of a data processing system, a data processing apparatus, and a data processing method according to the present invention will be described with reference to the drawings.
[0021]
(1) Embodiment
FIG. 1 is a block diagram showing a configuration example of a data processing system 100 as an embodiment according to the present invention.
In this embodiment, a data processing apparatus is provided which executes a given operation by designating a plurality of registers, obtains a compression program created by a program creation system, decodes a register type, and, based on the register type, To restore a program having an instruction structure of a predetermined instruction length to reduce the memory capacity of a ROM or the like for storing program data, and to reduce memory cells and logical operations. When a processor is constructed using PLDs composed of elements, the occupancy of memory cells functioning as a ROM can be reduced.
[0022]
In the program creation system, the length of an instruction can be changed according to the frequency of use of a register, and an instruction having a short length can be set in a frequently accessed register.
[0023]
On the one hand, the data processing system 10 shown in FIG. 1 creates a program by editing an instruction for executing a target arithmetic processing based on a predetermined program language, and, on the other hand, associates the program with a plurality of registers. It is a system that uses and processes data. In the data processing system 10, a program creation device 200 that forms the program creation system I is prepared. This is to create a program for operating the newly designed and manufactured data processing apparatus 100. The data processing device 100 constitutes a program execution system II, in which an instruction execution operation unit, a storage unit, a plurality of registers, and the like are mounted.
[0024]
The program creation device 200 compresses the number of instruction bits for designating the register based on the frequency of use of the register in the data processing device 100, and describes the register type in the instruction structure of the program to specify the instruction length. Of different compression programs AP. This is for reducing the memory capacity of the storage means for storing the program mounted on the data processing apparatus 100.
[0025]
The program creation device 200 includes, for example, a database 21, a keyboard 22, a mouse 23, a display device 24, and a control device 25. The database 21 stores data necessary for creating a program for the data processing device 100. For example, “Global variable declaration”, “function declaration”, “Local variable declaration”, “assignment”, “addition”, “comparison”, and “branch” necessary for describing a program in the C language are stored. A control device 25 is connected to the database 21, and a keyboard 22, a mouse 23 and a display device 24 are connected to the control device 25.
[0026]
The program creation device 200 displays a program description screen in C language on the display device 24, and creates a program using the keyboard 22 and the mouse 23. For example, in the case where the data processing apparatus 100 according to the new design and manufacturing uses N registers, and when the first to N-th serial numbers are assigned to the N registers, the first to N-th serial numbers are assigned. A “Local variable declaration” is made for the K-th group of registers that are frequently used, and a “Global variable declaration” is made for the K + 1-th to N-th groups of registers that are infrequently used.
[0027]
These declarations are specified by using the keyboard 22 and the mouse 23. The register types are classified into two types, and registers that are used frequently are set with a small number of instruction bits, and registers that are used less frequently are set longer. This is for setting an instruction by the number of instruction bits. When the number of registers in the data processing device 100 is, for example, about 4,000 to 8,000, the number of instruction bits for designating the registers becomes 12 to 13 bits.
[0028]
The control device 25 changes the length of the instruction according to the frequency of use of the register. Frequently accessed registers set short-length instructions. Registers that are frequently used are assigned a shorter number of instruction bits, and registers that are less frequently used are assigned a longer number of instruction bits.
[0029]
The data processing device 100 acquires the compressed program AP created by the program creating device 200, decodes the register type, restores the number of instruction bits designating the register based on the register type, and obtains an instruction of a predetermined length. , An arbitrary operation is executed by designating a plurality of registers.
[0030]
The data processing device 100 includes, for example, an instruction decoding / reconstructing unit 3, a storage unit 4, a register array 11, and an instruction execution operation unit 50. The register array 11 is a collection of a plurality of registers.
[0031]
The storage means 4 stores a compression program AP for designating a corresponding register from the register array 11. The compression program AP created by the program creation device 200 is used. For example, the compression program AP is written in the storage means 4 for storing the program constructed by the data processing device 100 using a ROM writer or the like.
[0032]
This is because, in the data processing apparatus 100, a processor may be constructed from a programmable logic device (Programmable Logic Device; PLD) including a plurality of memory cells and arithmetic logic elements. The occupancy of the memory cells functioning as the ROM can be reduced. Of course, the storage means 4 for storing the program may be manufactured separately from the arithmetic processing device, and the compression program AP may be stored in the individual storage means 4 and then mounted on the same substrate. This is because a read-only memory (ROM) or an EEPROM (flash memory) is used as the storage unit 4.
[0033]
An instruction decoding / restoring means 3 is connected to the storage means 4, reads out the compressed program AP from the storage means 4, decodes the register type, and determines the number of instruction bits for designating the register based on the register type. It is made to restore. This is for aligning the instruction lengths and designating a plurality of registers based on the instructions.
[0034]
The instruction decoding / reconstruction means 3 is connected to an instruction execution operation means 50, and the instruction execution operation means 50 is connected to the register array 11. The instruction execution operation means 50 executes an arbitrary operation by designating a corresponding register in the register array 11 based on a program of a predetermined instruction length restored by the instruction decoding and restoration means 3.
[0035]
Subsequently, an example of processing in the data processing system 10 regarding the data processing method according to the present invention will be described. FIG. 2 is a flowchart illustrating a processing example in the data processing system 10.
[0036]
In this system 10, a program creation system I edits an instruction for executing a target arithmetic process based on a predetermined program language to create a program, and a program execution system II uses the program and a plurality of registers. It is assumed that data is processed by using The case where the data processing apparatus 100 uses N registers and the first to Nth serial numbers are assigned to the N registers as an example.
[0037]
With this as a processing condition, the program creation system edits an instruction for executing a target arithmetic process based on a predetermined program language in step A1 of the flowchart in FIG. 2A. Then, in step A2, the number of instruction bits designating the register is compressed based on the frequency of using the register, and the instruction length is shortened. For example, when the number of instruction bits for specifying the registers of the (K + 1) th to Nth groups is n bits and the number of instruction bits for specifying the registers of the first to Kth groups is m bits, for example, The number of instruction bits designating the first to Kth group registers is compressed so that nm = 8 bits.
[0038]
Then, in step A3, the register type is described in the instruction structure of the program. For example, a set of registers holding the augend and the addend, which are referred to as "register type 1" for the register type of "register number 1" and "register type 2" for the register type of "register number 2" At this time, if the use frequency of the registers of the first to Kth groups is high, the code “0” is described in “register type 1” and “register type 2”. When the usage frequency of the registers in the (K + 1) th to the Nth groups is low, the code “1” is described in “register type 1” and “register type 2”.
[0039]
Then, in step A4, compressed programs AP having different instruction lengths are created. In the compressed program AP, the number of instruction bits for specifying the registers of the first to Kth groups is m bits, and the number of instruction bits for specifying the registers of the (K + 1) th to Nth groups is n. Is a bit. In the above example, the instruction form including the first to Kth group register designations has an instruction length shorter by 16 bits than the instruction form including the K + 1th to Nth group register designations.
[0040]
On the other hand, in the program execution system, the compressed program AP created in the program creation system is acquired in step B1 of the flowchart shown in FIG. 2B. For example, the compression program AP is written in the storage means 4 for storing the program constructed by the data processing device 100 using a ROM writer or the like. In this compression program AP, registers that are frequently used are set with a short instruction bit number = m bits, and registers that are used less frequently are set with a long instruction bit number = n bits.
[0041]
Then, it is determined in step B2 whether to execute the instruction. The determination at this time is made by a known technique. When executing the instruction, the register type is decoded in step B3. For example, regarding the “register type 1” and the “register type 2”, the register numbers of the first to K-th groups are decoded from the code “0” as the frequently used registers, and the “register type 1” and the “register type” are decoded. With respect to “2”, the register numbers of the (K + 1) th to Nth groups are decoded as the registers whose use frequency is low from the code “1”.
[0042]
Then, based on the decoded register type, the number of instruction bits for designating the register is restored in step B4. For example, “0” is added to the upper 8 bits of the instruction bit number = m bits of the registers of the 1st to Kth groups, in this example. The instruction bit numbers of the registers of the first to Kth groups are aligned to n bits in the same manner as the instruction bit numbers of the registers of the (K + 1) th to Nth groups.
[0043]
At step B5, an arbitrary operation is executed by designating a plurality of registers based on the restored instruction having the predetermined length. After that, it is determined whether or not to end the arithmetic processing in step B6. If the arithmetic processing is not completed, the process returns to step B2 to determine whether to execute the instruction, and continues the arithmetic processing. When ending the arithmetic processing, power-off information or the like is detected, and the arithmetic processing ends.
[0044]
As described above, according to the data processing system 10 as the embodiment according to the present invention, on the one hand, a program is created by editing an instruction for executing a target arithmetic process based on a predetermined program language, and When processing data using the program and a plurality of registers, the program creating apparatus 200 compresses the number of instruction bits for designating the register based on the frequency of using the register, and executes the instruction of the program. Compressed programs AP having different instruction lengths are created by describing the register types in the structure.
[0045]
The data processing device 100 obtains the compressed program AP created by the program creating device 200, decodes the register type, restores the number of instruction bits designating the register based on the register type, and obtains an instruction of a predetermined length. , An arbitrary operation is executed by designating a plurality of registers.
[0046]
Accordingly, in the program creation system I, the length of the instruction can be changed according to the frequency of use of the register, so that an instruction having a short length can be set in a frequently accessed register. Thus, in the program execution system II, the compressed instruction can be set in the storage means 4 such as a ROM, and the memory capacity of the storage means 4 for storing the program data can be reduced. Further, when a processor is constructed by a PLD composed of memory cells and logical operation elements, the occupancy of memory cells functioning as ROM can be reduced, and more memory cells can be allocated to registers. Become.
[0047]
(2) Example
FIG. 3 is a block diagram illustrating a configuration example of a microprocessor 101 as an embodiment according to the present invention.
In this embodiment, the external memory 2 is connected to the data processing device 100 to constitute the microprocessor 101, and an arbitrary operation is executed by designating a plurality of registers. For this purpose, a compressed program AP of machine language instructions created by the program creation system I is obtained, the register type is decoded, and the number of instruction bits designating the register is restored based on the register type. A program having a long instruction structure is restored. By doing so, the memory capacity of a ROM or the like for storing program data can be reduced.
[0048]
In the microprocessor 101 shown in FIG. 3, the number of instruction bits designating the register is compressed in advance based on the frequency of use of the register, and the instruction length of the instruction type in which the register type is described in the instruction structure of the program is different. This is a device that processes data based on a compression program AP. The processor 101 acquires the compressed program AP created by the program creating device 200, decodes the register type, restores the number of instruction bits designating the register based on the register type, and restores the instruction bit number based on the instruction of a predetermined length. Thus, an arbitrary operation is executed by designating a plurality of registers.
[0049]
The microprocessor 101 has, for example, a register array 11, an instruction bit restoration decoder 13, a ROM 14, and an instruction execution operation unit 50. The register array 11 is a collection of a plurality of registers. The register array 11 is provided with, for example, 8192 × 32-bit registers ri (i = 0 to 8191). Each register ri holds an arbitrary value based on the write address Aw and the write control signal Sw, and outputs values such as the augend X and the addend Y based on the read address Ar.
[0050]
In the microprocessor 101, a ROM 14 for storing a program, which is an example of a storage unit, is mounted, and a compression program AP for designating a corresponding register ri from the register array 11 is stored. The compressed program AP has a machine language instruction (Instruction) structure, and a program created by the program creating device 200 is used. For example, the compression program AP is written in the ROM 14 using a ROM writer or the like. When the instruction is executed, the ROM 14 outputs the compression program AP based on, for example, the count output signal S5 from the program counter 54.
[0051]
An instruction bit restoration decoder 13 is connected to the ROM 14, and reads out a compressed program AP of machine language instructions from the ROM 14 to generate an instruction control signal S4, an instruction signal S9, and respective argument signals S10. The command signal S9 includes a load command, an add command, a cmp command, and a jump command. Each of the argument signals S10 includes access method # 1, access method # 2, "register type 1", "register type 2", register numbers r0, r1,..., A flag state (flag condition), a jump address, and the like. It is.
[0052]
The compression program AP includes an operation instruction for executing a register relative memory addressing process. In this processing, one register is selected based on the operation instruction, and the external memory 2 is selected based on the value held by the selected register. This process is executed by, for example, the access method # 1.
[0053]
In this example, the instruction bit restoration decoder 13 decodes “register type 1” and “register type 2”, and specifies an instruction bit for designating the register ri based on the “register type 1” and “register type 2”. It is arranged to recover the number = n bits. This is because the instruction length is made equal to the number of bits before compression, and a plurality of registers ri and the like are specified based on this instruction. The above-described instruction control signal S4 is output to the instruction reading state machine 52.
[0054]
Instruction execution operation means 50 is connected to the register array 11 and the instruction bit restoration decoder 13 described above. The instruction execution operation means 50 executes an arbitrary operation by designating the corresponding register ri in the register array 11 based on a program of a predetermined instruction length restored by the instruction bit restoration decoder 13.
[0055]
The instruction execution operation unit 50 includes an arithmetic and logic unit (ALU) and an execution state machine 51, an instruction reading state machine 52, a selector 53, a program counter (PC) 54, a +1 incrementer 55, and an input. Selector 59 and latch circuits 58, 510, and 511, and execute register-relative memory addressing processing.
[0056]
A data signal line L20 is connected to the register array 11, and the ALU 12 is connected through the signal line L20. The ALU 12 calculates values such as X and Y read from a register designated in the register array 11. The value of the operation result is Z. The operation types are addition, multiplication, subtraction, division, and the like. The calculation type is set based on the ALU control signal S35 output from the execution state machine 51. The data signal line L20 is connected to latch circuits 58, 511, 59 and the like in addition to the ALU12. DATA, an augend X value, an addend Y value, and the like are transmitted to the data signal line L20.
[0057]
The instruction bit restoration decoder 13 is connected to an execution state machine 51 and an instruction reading state machine 52, and controls the register array 11 and the ALU 12 to execute the operation instruction decoded by the instruction bit restoration decoder 13. You.
[0058]
The instruction reading state machine 52 controls the program counter 54 and the execution state machine 51 based on the instruction control signal S4 output from the instruction bit restoration decoder 13. For example, the machine 52 outputs the instruction signal S9 and the respective argument signals S10 from the instruction bit restoration decoder 13 to the execution state machine 51 and outputs an instruction execution start signal S29.
[0059]
The register array 11, the ALU 12, the latch circuits 58, 510, 511, and the selector 59 are connected to the execution state machine 51. The machine 51 starts executing the instruction based on the instruction execution start signal S29. For example, at the time of writing data, a write control signal Sw is output to the register array 11, and a selection control signal S24 is output to the selector 59. When reading data, a read address Ar is output to the register array 11.
[0060]
At the time of calculation, the latch control signal S34 is output to the latch circuit 58, and the latch control signal S38 is output to the latch circuit 510. An external control signal S16 is output outside the processor. When the execution of the instruction is completed, the execution state machine 51 outputs an execution completion signal S26 to the instruction reading state machine 52, and the value of the program counter 54 is advanced.
[0061]
A selector 53 is connected to the execution state machine 51 and the instruction reading state machine 52, and selects one of the increment output signal S7 and the branch control signal S27 based on the selection control signal S28, and uses this as a selector output. An output is made to the program counter 54. The selection control signal S28 is supplied from the execution state machine 51. The increment output signal S7 is output from the incrementer 55 to the selector 53.
[0062]
In the program counter 54, a location where the compressed program AP is read from the ROM 14 is designated based on the count control signal S30. The +1 incrementer 55 increments the count output signal S5 of the program counter 54 by "+1". The count control signal S30 is supplied from the instruction decoding state machine 52. The count output signal S5 is output to the ROM 14 in addition to the +1 incrementer 55.
[0063]
The selector 59 is connected to the data bus 19A, the register array 11 and the ALU 12, and outputs data (DATA) taken from the data bus 19A, an augend X value (addend Y value) output from the register array 11, or an output from the ALU 12. Any one of the calculated operation result values Z is input controlled based on the selection control signal S24.
[0064]
The latch circuit 58 is connected between the read port of the register array 11 and the ALU 12, and latches the output value X of the register ri based on the latch control signal S34. The latch circuit 510 is connected to the comparison output unit of the ALU 12, latches the coincidence detection signal S22 based on the latch control signal S38, and outputs a flag condition (flag condition) signal S23. The latch circuit 511 is connected between the read port of the register array 11 and the address bus 19B, and latches an external address (address) based on a latch control signal S17.
[0065]
If a jump (instruction branch) occurs due to the executed instruction, a branch control signal S27 indicating the jump destination address is output from the execution state machine 51 to the selector 53. The selector 53 selects the branch control signal S27 based on the selection control signal S28, and writes the branch control signal S27 to the program counter 54.
[0066]
The external memory 2 is connected to the execution state machine 51, the selector 59, the data signal line L20, and the latch circuit 511 through the I / O interface 60. This is for operating the ALU 12 based on the register relative memory addressing processing. The I / O interface 60 and the external memory 2 are connected by a data bus 19A, an address bus 19B and a control bus 19C, data is transferred by the data bus 19A, an address is transferred by the address bus 19B, and a control bus 19C. The external control signal S16 is transferred to the external memory 2. This is for controlling the external memory 2. As the external memory 2, for example, a RAM of 512 Mbytes × 32 bits (memory that can be written and read at any time) is used.
[0067]
FIG. 4 is a block diagram showing an example of the internal configuration of the register array 11. According to the register array 11 shown in FIG. 4, for example, 8192 32-bit registers ri (i = 0 to 8191) are provided, and the write port 15 is connected to the input of each register ri. The 1-bit register includes a D-type flip-flop circuit and the like.
[0068]
The write port 15 is connected to the selector 59 shown in FIG. 3, and based on the write control signal Sw and the write address Aw, the data (DATA) fetched from the data bus 19A, and the operand X output from the register array 11. Either the value (addend Y value) or the operation result value Z output from the ALU 12 is written into the registers r0 to ri. The write port 15 is connected to the execution state machine 51 and supplies a write address Aw.
[0069]
A read port 16 is connected to the output of each register ri. The read port 16 is connected to the ALU 12, the latch circuits 58, 511, the selector 59, and the like shown in FIG. 3 through the data signal line L20, and reads data (DATA) from the register ri specified based on the read address Ar. Is made. The read port 16 is connected to the execution state machine 51 and supplies a read address Ar.
[0070]
Next, an example of the structure of an instruction set in the ROM 14 will be described. FIGS. 5A to 5E are formats showing an example of the structure of an instruction handled by the microprocessor 101. 6A to 6D are table diagrams showing examples of description contents in the instruction structure.
[0071]
As shown in FIGS. 5A to 5E, there are five types of instructions set in the ROM 14 such as # F1 to # F5. In the microprocessor 101, the instructions of the instruction forms # F2 to # F4 are restored to the instruction form of the instruction form # F1 and handled. In each of these instruction forms # F1 to # F5, each instruction is roughly divided into load, add, and cmp instructions and a jump instruction. In the instruction forms # F1 to # F4, in the case of a load instruction, a code "0" is described in the instruction as shown in FIG. 6A, in the case of the add instruction, the code "1" is described in the instruction, and in the case of the cmp instruction, The code "2" is described in each instruction.
[0072]
The instruction form # F5 is a jump instruction, and in this case, code "3" is described in the instruction. For the cmp instruction, if the comparison results are the same, zero flag is set to “1” based on the flag state signal S23 of the latch circuit 510 shown in FIG. 3, and if not, “0” is set. Set.
[0073]
In this example, the load, add, and cmp instructions are represented by 5 bits when the number of the register ri to be accessed can be represented by, for example, 5 bits, and are represented by 13 bits otherwise. That is, the 0th register r0 to the 31st register r31, which are frequently used, are represented by m = 5 bits. The 32nd register r32 to the 8191st register r8191 which are used less frequently are represented by m = 13 bits.
[0074]
In the instruction form # F1, the instruction length is 32 bits, the number of instruction bits of the register ri indicated by “register number 1” is n = 13 bits, and the number of instruction bits of the register ri indicated by “register number 2” is also n = 13 bits. In the instruction form # F2, the instruction length is 24 bits, the number of instruction bits of the register ri indicated by “register number 1” is m = 5 bits, and the number of instruction bits of the register ri indicated by “register number 2” is n = 13 bits.
[0075]
Also in the instruction form # F3, the instruction length is 24 bits, the number of instruction bits of the register ri indicated by “register number 1” is n = 13 bits, and the instruction bit of the register ri indicated by “register number 2” is The number is m = 5 bits. The instruction form # F4 has an instruction length of 16 bits, the number of instruction bits of the register ri indicated by “register number 1” is m = 5 bits, and the number of instruction bits of the register ri indicated by “register number 2” is also m = 5 bits.
[0076]
In each of the instruction forms # F1 to # F4, the first two bits indicate the instruction type. Regarding the instruction type, load indicates transfer, add indicates addition, cmp indicates comparison, and jump indicates control transfer (branch). In the case of the load, add, and cmp instructions, 2-bit access methods # 1 and # 2 follow the instruction. The left of Operand is represented by access method # 1, "register number 1" on the left, and the right is represented by access method # 2, "register number 2" on the right.
[0077]
That is, access method # 1 indicates an access method of register ri indicated by “register number 1”, and access method # 2 indicates an access method of register ri indicated by “register number 2”. Access method # 1 and access method # 2 correspond to register number No. 1, register number No. 2, and processing is performed between them. In both cases, as shown in FIG. 6B, two types of access methods # 1 and # 2 are prepared.
[0078]
When the code “0” is described for the access methods # 1 and # 2, this is a method of directly accessing the register ri indicated by the register number 2. This indicates that the value of the register ri indicated by the register number is directly used. When the code “1” is described for the access methods # 1 and # 2, the microprocessor 101 accesses the external memory 2 using the value of the register ri indicated by “register number 1” as an address. (See FIG. 6B).
[0079]
In FIGS. 5A to 5D, 2-bit “register type 1” and “register type 2” are described successively after access methods # 1 and # 2. “Register type 1” indicates the type of register ri indicated by “register number 1”, and “register type 2” indicates the type of register ri indicated by “register number 2”. As shown in FIG. 6C, two types of registers are prepared. When a code “0” is described for “register type 1” and “register type 2”, the register ri has a register number of “31” or less and is frequently used. The register ri (i = 0 to 31) can represent the register number with m = 5 bits.
[0080]
When “1” is described for “register type 1” and “register type 2”, it indicates a register ri whose register number is “32” or more and whose use frequency is low. The register ri (i = 32 to 8191) represents the register number with n = 13 bits. Thus, the program can be compressed by distinguishing the register numbers.
[0081]
"Register type 1" and "Register number 2" are followed by "Register number 1" and "Register number 2". “Register number 1” indicates, for example, a register ri holding an augend, and “register number 2” indicates a register ri holding an addend.
[0082]
According to the format of the jump instruction shown in FIG. 5E, the instruction is described in the first two bits, and the flag state is described in the subsequent two bits. The next 20 bits describe a jump address. The flag state is a condition for determining whether to shift the instruction execution control as shown in FIG. 6D. The code “0” always transfers control “unconditionally”. The code “1” is “zero flag”, and the control is transferred when the zero flag is “1”. The code "2" is "non-zero flag", and the control is transferred when the zero flag is "0". Code "3" is unused.
[0083]
Subsequently, a processing example in the program creation system I will be described. FIG. 7 is a table showing an example of program creation in the program creation system I. In FIG. 7, P1 is an image of a program description screen, P2 shows the description contents, and P3 describes conditions applicable in the embodiment. This is for creating a compressed program by editing instructions for executing a target arithmetic process based on a predetermined program language by the program creating apparatus 200 shown in FIG.
[0084]
The program creation device 200 displays the program description screen P1 in C language shown in FIG. 7 on the display device 24 shown in FIG. 1, and creates a compressed program using the keyboard 22 and the mouse 23. At this time, data necessary for creating a program for the microprocessor 101 is read from the database 21. For example, “Global variable declaration”, “function declaration”, “Local variable declaration”, “assignment”, “addition”, “comparison”, and “branch” necessary for describing a program in the C language are read.
[0085]
In this example, the microprocessor 101 according to the new design / manufacture uses N = 8192 32-bit registers ri. Serial numbers 0 to 8191 are assigned to the 8192 registers ri. At this time, a “Local variable declaration” is made with the registers r0 to r31 in the 0th to 31st groups as a frequently used category. That is, in this example, “Local variable declaration” is assigned to the 31st and lower registers ri. In addition, a “Global variable declaration” is made for the registers r32 to r8191 of the 32nd to 8191st groups as a low-use category. That is, “Global variable declaration” is assigned to the 32nd or higher register ri.
[0086]
In the program creation device 200, when the number of instruction bits of the registers r32 to r8191 of the 32nd to 8191st groups where the “Global variable declaration” is made is n = 13 bits, the registers r0 to r31 where the Local variable declaration is made Are compressed to m = 5 bits, which is 8 bits less than this. At the same time, "register type 1" and "register type 2" are described in the instruction structure of the program, and compressed programs AP having different instruction lengths are created.
[0087]
In the control device 25 shown in FIG. 1, the length of the instruction is changed according to the frequency of use of the register ri. In this example, the frequently used registers r0 to r31 are set with a short instruction bit number m = 5 bits, and the infrequently used registers r32 to r8191 are set with a long instruction bit number n = 13 bits. You. In this manner, frequently accessed registers r0 to r31 can be set with short-length instructions, and the memory capacity of the program storage ROM 14 mounted on the microprocessor 101 can be reduced.
[0088]
Next, a compile example in the program creation device 200 will be described. FIG. 8 is a flowchart (main routine) showing a compilation example in the program creation device 200. FIG. 9 is a flowchart (subroutine) showing an example of assignment and calculation processing in the compiler.
[0089]
In this embodiment, it is assumed that the program creating system I edits an instruction for executing a target arithmetic process based on a program in C language and creates a compressed program. In addition, the microprocessor 101 uses 8192 registers r0 to r8191 and a case where serial numbers 0 to 8191 are assigned to the 8192 registers ri is taken as an example.
[0090]
Under this processing condition, the program creation system I sets the program address to “0” in step C1 of the flowchart in FIG. 8 in order to edit the instruction based on the program in C language. Thereafter, the process proceeds to step C2 to read one line of the C language program. At this time, for example, "global variable declaration" is shown on the program description screen P1 of the display device 24.
int * read add * write add, counter, end val;
Is displayed and also indicates the function declaration
void main ()
｛
Is displayed.
[0091]
Then, in step C3, it is checked whether the description of the program is "global variable declaration". If the description is "global variable declaration", the process proceeds to step C4, where the 32nd or more registers r32 to r8191 are allocated. When the number of instruction bits designating registers r32 to r8191 of this group is m, m = 13 bits. The instruction is created in the instruction form # F1. Thereafter, the process proceeds to step C14.
[0092]
If the description is not "global variable declaration" in step C3, the process shifts to step C5 to check whether it is "local variable declaration". At this time, for example, "local variable declaration" is shown on the program description screen P1 of the display device 24.
int temp, added val;
Is displayed. If the description is "local variable declaration", the process proceeds to step C6, where the 31st and lower registers r0 to r31 are allocated. Since the frequency of using the register ri is high, the number of instruction bits n for specifying the register ri is compressed to 5 bits, which is 8 bits smaller than the registers r32 to r8191 declared as “global variables”. Instructions are created in instruction forms # F2 to # F4. Thereafter, the process proceeds to step C14.
[0093]
If the description is not "local variable declaration" in step C5, the process proceeds to step C7 to check whether "do" indicating the execution of the assignment / addition processing or the like is described in the C language program. At this time, for example, “do” is displayed on the program description screen P1 of the display device 24.

Is displayed. If "do" indicating such a substitution / addition process is described, the process proceeds to step C8 to store the current program address. Thereafter, the process proceeds to step C14.
[0094]
If "do" is not described in step C7, the process proceeds to step C9, and it is checked whether "while" indicating the process during the process is described in the C language program. At this time, for example, “while” is displayed on the program description screen P1 of the display device 24.
while (counter! = end val);
Is displayed. If "while" indicating such a process of comparison / branch, etc., is described, the process proceeds to step C10 to execute an assignment / operation process.
[0095]
For example, a subroutine shown in FIG. 9 is called, and in step E1 of the flowchart, it is checked whether or not the relevant line describes "while" in the C language program. In the case of the line in which “while” is described, the process proceeds to step E2, and the command generated in the subsequent processing is the cmp command. Thereafter, the process shifts to step E6.
[0096]
If it is determined in step E1 that the row does not include "while", the process proceeds to step E3 to check whether the arithmetic processing is addition. If the arithmetic processing is addition, the process proceeds to step E4, and the instruction generated in the subsequent processing is set as an add instruction. If the arithmetic processing is not addition, the process proceeds to step E5, and the instruction generated in the subsequent processing is set as a load instruction. Thereafter, the process shifts to step E6.
[0097]
In step E6, the register number corresponding to the variable written to the register ri and the register number of the register ri corresponding to the variable read from the register array 11 can be checked. This is for determining the write address Aw and the read address Ar. Thereafter, the process shifts to step E7.
[0098]
In step E7, it is checked whether both register numbers are "32" or more. If both register numbers are equal to or larger than "32", the process proceeds to step E8 to generate an instruction in the instruction form # F1 shown in FIG. 5A. In this instruction form # F1, "1" is described in "register type 1" and "register type 2". At this time, “register type 1” and “register type 2” are described in the instruction structure of the compression program. For example, “1” is described in “register type 1” and “register type 2” for the registers r32 to r8191 in the 32nd to 8191st groups. Thereafter, the process returns to step C10 of the main routine shown in FIG.
[0099]
If both register numbers are not equal to or larger than "32" in step E7, the process shifts to step E9 to check whether both register numbers are equal to or smaller than "31". If both register numbers are equal to or smaller than "31", the process proceeds to step E10 to generate an instruction in the instruction mode # F4 shown in FIG. 5D. In this instruction form # F4, “0” is described in “register type 1” and “register type 2”. At this time, “register type 1” and “register type 2” are described in the instruction structure of the compression program. For example, “0” is described in “register type 1” and “register type 2” for the registers r0 to r31 of the 0th to 31st groups. Thereafter, the process returns to step C10 of the main routine shown in FIG.
[0100]
Further, when both register numbers are not equal to or smaller than "31", the process proceeds to step E11 to check whether the number of the register ri of the variable read from the register array 11 is equal to or larger than "32". If the number of the register ri of the variable to be read is “32” or more, the process proceeds to step E12 to generate an instruction in the instruction format # F2 shown in FIG. 5B. In this instruction form # F2, “0” is described in “register type 1”, and “1” is described in “register type 2”. Thereafter, the process returns to step C10 of the main routine shown in FIG.
[0101]
Furthermore, when the number of the register ri of the variable read from the register array 11 is not equal to or more than “32”, the process proceeds to step E13, and an instruction is generated in the instruction form # F3 shown in FIG. 5C. In this instruction form # F3, “1” is described in “register type 1”, and “0” is described in “register type 2”. Thereafter, the process returns to step C10 of the main routine shown in FIG. Thereafter, the process proceeds to step C11 to generate a jump instruction. The jump address of the jump instruction uses the previously stored program address. Thereafter, the process proceeds to step C14.
[0102]
If "while" is not described in step C9 described above, the process proceeds to step C12 to check whether data is to be substituted or added in the C language program. In the case of data substitution or addition, the process proceeds to step C13 to execute data substitution or arithmetic processing. In this step C13, the subroutine shown in FIG. 9 is called, and the process returns to step C13 of the main routine shown in FIG. 8 through steps E1 to E13 of the flowchart. Thereafter, the process proceeds to step C14.
[0103]
If it is not the substitution or addition of data in the C language program in step C12, the process proceeds to step C14. In step C14, it is checked whether the program is the last line in the C language program. If it is not the last line, the process goes to step C15 to advance the program address. Thereafter, the process returns to step C2 to repeat the above-described compile processing. This compile process ends at the last line.
[0104]
As a result, it is possible to create compressed programs AP having instruction formats # F1 to # F5 as shown in FIGS. 5A to 5E and different instruction lengths. In this compressed program AP, the number of instruction bits for specifying the registers r0 to r31 in the 0th to 31st groups is m = 5 bits, and the registers r32 to r8191 in the 32nd to 8191st groups are The number of instruction bits to be specified is n = 13 bits.
[0105]
Next, a processing example in the program execution system II will be described. FIG. 10 is a table showing an example of operation instructions according to the restored operation program. 11 is a state example of registers r0, r1,... R32, r33, r34, r35 and the like, and FIG. 12 is an image diagram showing an example of data storage in the external memory 2.
[0106]
In this example, two sets of ten memory cell arrays as shown in FIG. 12 are prepared in the external memory 2 connected to the data processing device 100. One is a memory array # M1 and the other is a memory array # M2. Then, based on eight operation instructions (Instruction) # I1 to # I8 shown in FIG. 10, "1" is added to the value stored in the set of memory arrays # M1, and the other set of memory arrays # An example of a calculation process for storing the result in M2 will be described.
[0107]
The operation instructions (Instruction) # I1 to # I8 shown in FIG. 10 are based on the operation program after the compression program AP in the ROM 14 is decompressed. In this operation program, as shown in FIG. 11, there are two registers ri having a high access frequency, and these are assigned to r0 and r1, respectively. As a result, the length of the entire program can be efficiently reduced as compared with the operation program before compression.
[0108]
In FIG. 11, the register indicated by the register number r0 is temporarily used, and the register indicated by the register number r1 stores the added value “1”. The register indicated by register number r32 stores the read address “0”, the register indicated by register number r33 stores the write address “10”, and the register indicated by register number r34 stores the initial value of the counter. The value “0” is stored, and the number of operations (end value) “10” is stored in the register indicated by the register number r35.
[0109]
In each of the operation instructions # I1 to # I8 shown in FIG. 10, the expression by mnemonic, the expression by machine language, and the contents of the processing are shown. The operation instruction # I1 is load, r0, (r32) represented by 140020h in machine language in the instruction structure shown in FIG. 5, and is read from the external memory 2 using the value of the register r32 of the register array 11 as an address. This is the content of storing the value in the register r0. As an operation, for example, when the value of the register r32 is set to “0”, the data “0” of the memory array # M1 in which the read address of the external memory 2 shown in FIG. 12 is “0” is read. The data "0" is written to the register r0.
[0110]
The operation instruction # I2 is add, r0, r1 represented by 4001h in machine language, and is a content for adding the value of the register r1 to the register r0 of the register array 11 and storing the result in the register r0. As an operation, “1” which is the value of the register r1 is added to “0” which is the content of the register r0, and as a result, “1” is written to the register r0.
[0111]
The operation instruction # I3 is load, (r33), r0 represented by 280420h in machine language, and is a content for writing the value of the register r0 into the external memory 2 using the value of the register r33 of the register array 11 as an address. As an operation, data “1” is written to the address of the memory array # M2 of the external memory 2 indicated by the register r33.
[0112]
The operation instruction # I4 is add, r32, r1 represented by 480401h in machine language, and is a content for adding the value of the register r1 to the register r32 of the register array 11 and storing the result in the register r32. As an operation, “1” which is the value of the register r1 is added to “0” which is the content of the register r32, and as a result “1” is written to the register r32.
[0113]
The operation instruction # I5 is add, r33, r1 represented by 480421h in machine language, and is a content for adding the value of the register r1 to the register r33 of the register array 11 and storing the result in the register r33. As an operation, “1” that is the value of the register r1 is added to “0” that is the content of the register r33, and as a result, “1” is written to the register r33.
[0114]
The operation instruction # I6 is add, r34, r1 represented by 480441h in machine language, and is a content for adding the value of the register r1 to the register r34 of the register array 11 and storing the result in the register r34. As an operation, “1” which is the value of the register r1 is added to “0” which is the content of the register r34, and as a result “1” is written to the register r34. By the operation instructions # I4 to # I6, "1" is added to the read address Ar and the write address Aw in the counter in the execution state machine 51.
[0115]
The operation instruction # I7 is cmp, r34, and r35 represented by 8C044023h in machine language. The contents of the register r34 of the register array 11 are compared with the contents of the register r35. "1" is set, and if different, "0" is set. As the operation, since the values “1” and “10” of the registers r34 and r35 are different, “0” is set to zeroflag. The value of the zero flag is held by the latch circuit 510, and is referred to by a subsequent instruction.
[0116]
The operation instruction # I8 is jump nz, LOOP represented by E00000h in a machine language. When the zero flag is “0”, the content of the control is transferred to the label indicated by LOOP. As an operation, when the zero flag is “0”, the control is transferred to the operation instruction # I1. When the above operation is repeated 10 times, the value of the register r34 becomes "10", the zero flag is set to "1" by the operation instruction # I7, the control is not transferred by the operation instruction # I8, and the operation processing is ended. It is made to do. In this manner, the ROM 14 can be used more efficiently than when the number of instruction bits of all the registers ri is expressed by a single method.
[0117]
Subsequently, an operation example in the microprocessor 101 will be described. FIG. 13 is a flowchart illustrating an operation example of the microprocessor 101. 14 and 15 are flowcharts showing processing examples (parts 1 and 2) in the instruction bit restoration decoder 13.
[0118]
In this embodiment, the microprocessor 101 constitutes the program execution system II and restores the operation program including the operation instructions # I1 to # I8 shown in FIG. 10 from the compressed program AP read from the ROM 14. At this time, if the code “0” is described in “register type 1” and “register type 2” for the instruction forms # F1 to # F4, the register number is expanded by the instruction bit restoration decoder 13. In the expansion of the instruction bits at this time, for example, 8-bit “0” is added to the upper part of the instruction bit number m = 5 bits of “register number 1”. Based on this calculation program, “1” is added to the value of the memory array # M1 in the external memory 2 shown in FIG. 12 and stored in the memory array # M2.
[0119]
Regarding the register state of the register array 11, as shown in FIG. 11, for example, for six registers r0, r1, r32, r33, r34, and r35, r0 is undefined, r1 is an initial value “1”, r32 and r34. Are both set to the initial value “0”, and r33 and r35 are set to the initial value “10”. When writing these values, the write address Aw is output to the register array 11 in the execution state machine 51, and its initial values “0”, “1”, and “10” are set.
[0120]
Under these operating conditions, in step F1 of the flowchart shown in FIG. 13, first, the instruction bit decompression decoder 13 sequentially receives a compressed program (machine instruction) AP from the ROM 14, decodes the program AP, and decodes the program AP into a predetermined instruction length. Are detected.
[0121]
The instruction bit restoration decoder 13 calls, for example, a subroutine shown in FIG. 14 to fetch an instruction portion in step G1 of the flowchart, and outputs an instruction signal S9 to the execution state machine 51. At the same time, the instruction bit restoration decoder 13 proceeds to step G2 and checks whether the instruction type is a jump instruction. If the instruction form is a jump instruction indicated by # F5, the process shifts to step G12 to output a flag condition and a jump address. Thereafter, the process returns to step F1 of the main routine.
[0122]
If the instruction type is not a jump instruction in step G2, the process proceeds to step G4 to check whether the code described in “register type 1” is “0” or “1” for the instruction type. If the code “0” is described in the “register type 1”, the process proceeds to step G4, and the instruction bit number m of the “register number 1” is extracted from the compressed program AP as a 5-bit length. Thereafter, the process proceeds to step G5, where “0” is added to the upper 8 bits of the instruction bit number m = 5 bits of “register number 1” to make the length 13 bits. Thereafter, the process proceeds to step G7.
[0123]
If the code "1" is described in the "register type 1" in step G3 described above, the process shifts to step G6 to take out the instruction bit number n of "register number 1" as 13 bits long from the compression program AP. After that, the process shifts to step G7 to check whether the code described in the “register type 2” is “0” or “1” for the instruction mode. If the code "0" is described in the "register type 2", the process proceeds to step G8, and the instruction bit number m of the "register number 2" is extracted from the compressed program AP as a 5-bit length. After that, the process shifts to step G9 to add “0” to the upper 8 bits of the instruction bit number m = 5 bits of “register number 2” to make it 13 bits long. Thereafter, the process proceeds to step G11.
[0124]
If the code "1" is described in the "register type 2" in step G7 described above, the process proceeds to step G10, where the instruction bit number n of "register number 2" is taken out from the compression program AP with a 13-bit length. After that, the process shifts to step G11 to detect "register number 1", "register number 2", "access method # 1" and "access method # 2".
[0125]
Thereafter, the process returns to step F1 of the main routine shown in FIG. Therefore, the “register type 1” and the “register type 2” are not output to the execution state machine 51, and the instruction control signal S4, the instruction signal S9, and the respective argument signals based on the operation instructions # I1 to # I8 having a predetermined instruction length. S10 is output.
[0126]
The command signal S9 includes a load command, an add command, a cmp command, and a jump command. Each argument signal S10 includes a flag state (flag condition), a jump address, and the like, such as access method # 1, access method # 2, register numbers r0, r1,. The instruction control signal S4 is output from the decoder 13 to the instruction reading state machine 52.
[0127]
The location (address) where the compressed program AP is read from the ROM 14 is specified by the program counter 54 (PC). These read operations are controlled by the instruction read state machine 52.
[0128]
The instruction reading state machine 52 controls the program counter 54 and the execution state machine 51 based on the instruction control signal S4 output from the instruction bit restoration decoder 13. For example, the machine 52 outputs the instruction signal S9 and the respective argument signals S10 from the instruction bit restoration decoder 13 to the execution state machine 51 and outputs an instruction execution start signal S29.
[0129]
The execution state machine 51 starts executing the instruction based on the instruction execution start signal S29. For example, at the time of writing data, a write control signal Sw is output to the register array 11, and a selection control signal S24 is output to the selector 59. When reading data, a read address Ar is output to the register array 11.
[0130]
At the time of calculation, the latch control signal S34 is output to the latch circuit 58, and the latch control signal S38 is output to the latch circuit 510. An external control signal S16 is output outside the processor. When the execution of the instruction is completed, the execution state machine 51 outputs an execution completion signal S26 to the instruction reading state machine 52, and the value of the program counter 54 is advanced.
[0131]
In the program counter 54, a location where the compressed program AP is read from the ROM 14 is designated based on the count control signal S30. The +1 incrementer 55 increments the count output signal S5 of the program counter 54 by "+1".
[0132]
Then, in step F2, when the execution state machine 51 receives the operation instruction # I1 under the instruction reading control of the instruction reading state machine 52, the execution state machine 51 writes the write signal based on load, r0, (r32) represented by 140020h in machine language. S16 is output to the external memory 2. This value is used as the read address Ar of the register array 11. Register array 11 outputs the 32nd value to data signal line L20.
[0133]
This value is held by the latch circuit 511 and output to the external memory 2 via the address bus 19B. Then, using the value of the register r32 of the register array 11 as an address, the value read from the external memory 2 is stored in the register r0. At this time, since the value of the register r32 is “0”, the data “0” of the memory array # M1 having the content of the address “0” of the external memory 2 shown in FIG. "0" is written to the register r0.
[0134]
That is, the data of the address (location) transferred from the external memory 2 by the address bus 19B is output to the selector 59. The execution state machine 51 outputs a selection signal S24 so that this data is selected. As a result, data is input to the register array 11. Then, the execution state machine 51 outputs the write address Aw = "0" to the register array 11. Thereafter, the execution state machine 51 is instructed to actually write the operation result value by using the write signal Sw.
[0135]
Thereafter, in step F3, when the execution state machine 51 receives the operation instruction # I2 under the instruction read control of the instruction read state machine 52, the execution state machine 51 reads the register array 11 based on the add, r0, r1 represented by the machine language 4001h. The value of the register r1 is added to the register r0, and the result is stored in the register r0. At this time, "1" which is the value of the register r1 is added to "0" which is the content of the register r0, and as a result "1" is written to the register r0.
[0136]
In step F4, when the execution state machine 51 receives the operation instruction # I3 under the instruction reading control of the instruction reading state machine 52, the execution state machine 51 registers the register array based on load, (r33), and r0 represented by 280420h in machine language. The value of the register r0 is written to the external memory 2 using the value of the register r33 of No. 11 as an address. At this time, data “1” is written to the address of the memory array # M2 of the external memory 2 indicated by the register r33.
[0137]
After that, in step F5, when the execution state machine 51 receives the operation instruction # I4 under the instruction reading control of the instruction reading state machine 52, the execution state machine 51 reads the register array 11 based on add, r32, r1 represented by the machine language 480401h. The value of the register r1 is added to the register r32, and the result is stored in the register r32. At this time, "1" which is the value of the register r1 is added to "0" which is the content of the register r32, and as a result "1" is written to the register r32. By the operation instruction # I4, "1" is added to the read address Ar and the write address Aw in the counter in the execution state machine 51.
[0138]
Then, in step F6, when the execution state machine 51 receives the operation instruction # I5 under the instruction reading control of the instruction reading state machine 52, the execution state machine 51 reads the register array 11 based on add, r33, and r1 represented by the machine language 480421h. The value of the register r1 is added to the register r33, and the result is stored in the register r33. At this time, “1” that is the value of the register r1 is added to “0” that is the content of the register r33, and as a result, “1” is written to the register r33. By the operation instruction # I5, the counter in the execution state machine 51 adds "1" to the read address Ar and the write address Aw.
[0139]
After that, in step F7, when the execution state machine 51 receives the operation instruction # I6 under the instruction reading control of the instruction reading state machine 52, the execution state machine 51 reads the register array 11 based on add, r34, r1 represented by the machine language 480441h. The value of the register r1 is added to the register r34, and the result is stored in the register r34. At this time, "1" which is the value of the register r1 is added to "0" which is the content of the register r34, and the result "1" is written to the register r34. By the operation instruction # I6, "1" is added to the read address Ar and the write address Aw in the counter in the execution state machine 51.
[0140]
In this example, it is determined in step F8 whether the value indicated by the register r35 has reached 10 times. For example, when the execution state machine 51 receives the operation instruction # I7 under the instruction reading control of the instruction reading state machine 52, the execution state machine 51 reads the register r34 of the register array 11 based on cmp, r34, and r35 represented by 8C044023h in machine language. The content is compared with the content of the register r35. If the values are the same, zero flag is set to "1", and if they are different, the value is set to "0". At this time, since the values “1” and “10” of the registers r34 and r35 are different, “0” is set in the zero flag. The value of the zero flag is held by the latch circuit 510, and is referred to by a subsequent instruction.
[0141]
Then, when the execution state machine 51 receives the operation instruction # I8 under the instruction reading control of the instruction reading state machine 52, if the zero flag is “0” based on jump nz, LOOP represented by E00000h in machine language, Transfers control to the label indicated by LOOP. If the zero flag is "0", the control is transferred to the operation instruction # I1 in step F2. When the above operation is repeated 10 times in step F8, the value of the register r34 becomes "10", the zero flag is set to "1" by the operation instruction # I7, and the control is not transferred by the operation instruction # I8. Is made to end.
[0142]
As described above, according to the microprocessor 101 as the embodiment according to the present invention, the number of instruction bits for designating the register ri based on the frequency of use among the 8192 registers r0 to r8191 is compressed in advance. The data is processed based on compressed programs AP having different instruction lengths in which "register type 1" and "register type 2" are described in the instruction structure of the program.
[0143]
The ROM 14 stores a compression program AP for designating the register ri from among the 8192 registers r0 to r8191. The instruction bit decompression decoder 13 reads out the compressed program AP from the ROM 14 and decodes “register type 1” and “register type 2”. Based on the “register type 1” and “register type 2”, the register ri is read. The number of instruction bits to specify is restored.
[0144]
Therefore, a compressed program AP having an instruction length variable according to the frequency of use of the register ri, in which frequently-accessed registers r0 to r31 are set with a short-length instruction, , So that the memory capacity can be reduced. In this example, the memory capacity can be reduced by 16 bits × 32 pieces × the number of instructions as compared with before the program is compressed.
[0145]
This makes it possible to reduce the occupancy of the memory cells functioning as the ROM when the microprocessor 101 is constructed by the PLD including the memory cells and the logic operation elements, and it is possible to allocate more memory cells to the registers. become able to.
[0146]
【The invention's effect】
As described above, according to the data processing system of the present invention, on the one hand, an instruction for executing a target arithmetic process is edited based on a predetermined program language to create a program, and on the other hand, When processing data using a program and multiple registers, obtain the compressed program created by the program creation system, decode the register type, and specify the number of instruction bits that specify the register based on this register type. And a data processing device for executing an arbitrary operation by designating a plurality of registers based on an instruction of a predetermined length.
[0147]
With this configuration, the length of an instruction can be changed in the program creation system according to the frequency of use of the register. Therefore, an instruction with a short length can be set in a frequently accessed register. Therefore, in the program execution system, the capacity of a memory such as a ROM for storing program data can be reduced. Further, when a processor is constructed by a PLD including memory cells and logical operation elements, the occupancy of the memory cells functioning as ROM can be reduced, and more memory cells can be allocated to registers.
[0148]
According to the data processing device of the present invention, the number of instruction bits for designating a register is pre-compressed based on the frequency of using the register, and the instruction length in which the register type is described in the instruction structure of the program When processing data based on a compression program different from the compression program, there is provided an instruction decoding and restoring means for restoring the number of instruction bits for designating the register based on the type of register decoded from the compression program. And performs an arbitrary operation by designating a register based on the instruction of a predetermined length restored by the above.
[0149]
With this configuration, a compressed program having an instruction length that is variable according to the frequency of use of a register, wherein a short-length instruction is set in a frequently accessed register, and compressed program data is stored in a storage unit. Therefore, the memory capacity can be reduced. Therefore, when a processor is constructed by a PLD including memory cells and logical operation elements, the occupancy of the memory cells functioning as ROM can be reduced, and more memory cells can be allocated to registers.
[0150]
According to the data processing method according to the present invention, a program creation system edits an instruction for executing a target arithmetic process based on a predetermined program language to create a program, and the program execution system combines the program with a plurality of programs. When processing data using a register, the program creation system compresses the number of instruction bits for designating the register based on the frequency of use of the register, and specifies the register type in the instruction structure of the program. Write a compressed program with a different instruction length by writing, and the program execution system obtains the compressed program created by the program creation system, decodes the register type, and registers the register based on the decoded register type. Restore the specified number of instruction bits, and specify multiple registers based on the restored instruction of the specified length. It is adapted to perform any of the operations Te.
[0151]
With this configuration, the length of an instruction can be changed in the program creation system according to the frequency of use of the register. Therefore, an instruction with a short length can be set in a frequently accessed register. Therefore, in the program execution system, the capacity of a memory such as a ROM for storing program data can be reduced. Further, when a processor is constructed by a PLD including memory cells and logical operation elements, the occupancy of the memory cells functioning as ROM can be reduced, and more memory cells can be allocated to registers.
[0152]
The present invention is very suitable when applied to these embedded electronic devices such as a CPU that performs various data processing based on an instruction execution program and the like, an MPU, a PLD, and the like.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a data processing system 10 as an embodiment according to the present invention.
FIG. 2 is a flowchart illustrating a processing example in the data processing system 10.
FIG. 3 is a block diagram illustrating a configuration example of a microprocessor 101 as an embodiment according to the present invention.
FIG. 4 is a block diagram showing an example of the internal configuration of a register array 11;
5A to 5E are formats showing examples of the structure of an instruction set in a ROM 14. FIG.
FIGS. 6A to 6D are table diagrams showing examples of description contents in an instruction structure.
FIG. 7 is a table showing an example of program creation in the program creation system I.
FIG. 8 is a flowchart (main routine) illustrating a compilation example in the program creation device 200.
FIG. 9 is a flowchart (subroutine) showing an example of assignment and calculation processing in a compiler.
FIG. 10 is a table showing an example of an operation instruction according to a restored operation program.
FIG. 11 is an image diagram showing a state example of registers such as r0, r1,..., R32, r33, r34, and r35.
FIG. 12 is an image diagram showing an example of data storage in an external memory 2;
FIG. 13 is a flowchart illustrating an operation example of the microprocessor 101.
FIG. 14 is a flowchart illustrating a processing example (part 1) in the instruction bit restoration decoder 13;
FIG. 15 is a flowchart showing a processing example (part 2) in the instruction bit restoration decoder 13;
[Explanation of symbols]
2 ... external memory, 3 ... instruction decoding and restoring means, 4 ... storage means, 10 ... data processing system, 11 ... register array, 12 ... ALU, 13 ... instruction bits Restoration decoder (instruction decoding / restoration means), 14 ROM (storage means), 50 instruction execution calculation means, 100 data processing apparatus, 101 microprocessor, 200 program creation apparatus

Claims (7)

On the one hand, a system for editing a command for executing a target arithmetic processing based on a predetermined programming language to create a program, and, on the other hand, a system for processing data using the program and a plurality of registers. hand,
A program creating device that compresses the number of instruction bits specifying the register based on the frequency of using the register, and describes a register type in an instruction structure of the program to create a compressed program having a different instruction length;
Obtain the compressed program created by the program creation device, decode the register type, restore the number of instruction bits specifying the register based on the register type, and restore a plurality of registers based on an instruction of a predetermined length. A data processing system comprising: a data processing device that executes an arbitrary operation by designating the data processing device. The data processing device includes:
Multiple registers,
Storage means for storing a compression program for specifying the register;
Instruction decoding and restoring means for reading the compressed program from the storage means to decode the register type, and for restoring the number of instruction bits for designating the register based on the register type;
2. The data processing apparatus according to claim 1, further comprising: an instruction execution operation unit configured to execute an arbitrary operation by designating the register based on the instruction of a predetermined length restored by the instruction decoding and restoration unit. system. The register type is
When using N registers,
When the first to Nth serial numbers are assigned to the N registers,
The registers of the 1st to Kth groups are classified into a class that is frequently used,
The data processing system according to claim 1, wherein the registers of the (K + 1) th to (N) th groups are classified into low-use categories. The number of instruction bits designating the register is pre-compressed based on the frequency of use of the register, and the data is processed based on a compression program having a different instruction length in which the register type is described in the instruction structure of the program. A device,
Multiple registers,
Storage means for storing a compression program for specifying the register;
Instruction decoding and restoring means for reading the compressed program from the storage means to decode the register type, and for restoring the number of instruction bits for designating the register based on the register type;
A data processing apparatus comprising: an instruction execution operation unit configured to execute an arbitrary operation by designating the register based on an instruction having a predetermined length restored by the instruction decryption restoration unit. The register type is
When using N registers,
When the first to Nth serial numbers are assigned to the N registers,
5. The register according to claim 4, wherein the registers of the first to Kth groups are classified into a category of high use frequency, and the registers of the K + 1th to Nth groups are classified into a category of low frequency use. The data processing device as described in the above. A method in which a program creating system edits an instruction for executing a target arithmetic process based on a predetermined program language to create a program, and the program executing system processes data using the program and a plurality of registers. And
In the program creation system,
While compressing the number of instruction bits specifying the register based on the frequency of using the register, writing a register type in the instruction structure of the program to create a compressed program with a different instruction length,
In the program execution system,
Obtain the compression program created by the program creation system and decode the register type,
Restoring the number of instruction bits specifying the register based on the decoded register type,
A data processing method, wherein a plurality of registers are designated and an arbitrary operation is executed based on the restored predetermined length instruction. The register type is
When using N registers,
When the first to Nth serial numbers of the N registers are assigned,
The registers of the 1st to Kth groups are classified into a class that is frequently used,
7. The data processing method according to claim 6, wherein the registers in the (K + 1) th to the Nth groups are classified into low-use categories.

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