JP2003348374A - Phase-locked loop circuit, time base correcting circuit and method, and image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase-locked loop circuit, a time base correcting circuit and method, and an image display device in which smooth and stable frequency pull-in characteristics at ordinary time are compatible with frequency pull-in characteristics of excellent responsiveness in the case of a sudden change in an input signal. <P>SOLUTION: In an R-PLL circuit 65 for generating a read clock CKR, a first low-pass filter 652 of a large time constant is provided between a phase detector 651 and a VCO 653, and a second low-pass filter 654 having a time constant sufficiently smaller than the time constant of the first low-pass filter 652 is arranged parallel with the first low-pass filter 652 between the phase detector 651 and the VCO 653. In accordance with an output voltage of the phase detector 651, it is switched by a diode circuit 655 whether or not the second low-pass filter 654 is to be validated. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit used for accurately adjusting the phase of an input or reference frequency and an output, and a correction for removing an error (phase error) on the time axis of an input signal. The present invention relates to a time axis correction circuit and a method for generating an output signal without time axis fluctuation by performing, and an image display device provided with such a time axis correction circuit.

[0002]

2. Description of the Related Art A phase-locked loop circuit called a PLL (phase-locked loop) has been known as a means for accurately adjusting the phase of an input or reference frequency and an output. This PLL circuit includes a phase detector that compares the frequency of a voltage controlled oscillator with the frequency of an input carrier signal or a reference frequency generator, a low-pass filter, and a voltage controlled oscillator as basic elements. After the output of the phase detector passes through the low-pass filter,
It is fed back to the voltage controlled oscillator. By repeating this loop, the phase of the input or reference frequency and the output are accurately matched.

In this PLL circuit, in order to obtain a clock signal having a more stable phase in a steady state, it is necessary to increase the time constant of the low-pass filter to some extent so as to increase the pull-in time. If the time constant of the low-pass filter is too small, the pull-in time becomes too short, and the PLL can be used even for phase fluctuations or frequency fluctuations (time fluctuations, that is, jitter) within the allowable range (standard range) of the input signal. As a result of the circuit responding one by one,
This is because the phase of the output clock signal is not stable.

[0004]

SUMMARY OF THE INVENTION However, PLL
If the time constant of the low-pass filter in the circuit is made sufficiently large and the pull-in time is lengthened, the PLL may be used when the input signal has a sudden (large) phase variation or frequency variation exceeding its standard range. As a result of the response of the circuit being too slow, it takes a very long time (sometimes several seconds) to reach a steady state.

That is, in the conventional PLL circuit, a gradual (stable) frequency pull-in characteristic in a steady state and
It has been difficult in principle to achieve both a rapid (high response) frequency pull-in characteristic.

[0006] This problem also appears remarkably when the PLL circuit is applied to, for example, a time base correction circuit called a time base collector. Hereinafter, a technical problem in applying a PLL circuit to the time base collector will be described together with a technical background of the time base collector.

In general, a time base collector generates an output signal with no time-axis fluctuation by performing correction for removing a phase fluctuation from an input signal such as a video signal (video signal) or an audio signal (audio signal). It has a function. For example, VCR (Video Cassete Record
er) often includes jitter due to tape warping or vibration, so that the display device can display clear images without rolling. Needs to remove jitter from the reproduced signal. As a means for removing such jitter, a time base collector is generally used.

According to this time base collector, PL
A write clock is extracted from an input signal such as a video signal using an L circuit, and is temporarily stored in a memory based on the write clock. By reading the stored signal from the memory, it is possible to obtain an output video signal without phase fluctuation. In this case, the read clock can be generated based on the horizontal synchronizing signal of the input video or the write clock, or can be free-run irrelevant to the write clock.

[0009] A reproduced signal output from a VCR often includes phase fluctuations due to switching of a reproducing head. This phase fluctuation occurs when the two reproducing heads disposed on the rotating drum alternately scan on the tape and switch between them. When a phase change occurs in the input video signal, as shown in FIG. 8, the phase of the write clock CKW of the time base collector extracted from the input video signal greatly changes. Therefore, usually, the head switching timing is set within the range of the vertical blanking period TB in the vertical synchronizing signal VS of the input video P1, so that, for example, the input video P1
Even if the influence of the phase fluctuation of the write clock CKW affects the read clock CKR, the output video P2 itself is not affected by the change.

However, in a television receiver having a signal processing circuit such as a texture enhancer, which has a signal delay of less than one field of a video signal (or a signal delay which is not a field unit), switching of a reproducing head is required. The accompanying phase fluctuation of the input image P1 poses a problem. Note that the texture enhancer separates the video signal into a structure component representing the outline of the video and a texture component representing the details of the video, amplifies the texture component, and then synthesizes this with the structure component.
Image processing for enhancing details corresponding to texture components is performed.

As shown in FIG. 9, during image processing by the texture enhancer, a delay of the number of lines less than one field (about 40 lines), that is, a halfway delay occurs in the input image. Therefore, when the read clock CKR of the time base collector undergoes a phase change due to the phase fluctuation of the input video P1 and the write clock CKW, the output video P2 is affected. That is, a state occurs in which the delayed output video P2 straddles the switching timing of the reproducing head, and a phase shift (hereinafter, also referred to as horizontal skew) of the horizontal synchronization signal occurs in the middle of the output video P2. As a result, as shown in FIG. 9, the output image P2 on the screen of the image display device appears to be largely shifted laterally at the horizontal skew position, and the image quality is significantly deteriorated.

In order to avoid this problem, the read clock is affected by the phase fluctuation of the write clock by generating the read clock based on the write clock using a PLL circuit having a sufficiently long pull-in time. There are ways to avoid it. Specifically, the pull-in time of the reading PLL circuit may be set to, for example, about 20 to 30 times the pull-in time of the deflection system used in a normal television receiver.

[0013] By the way, due to the demand for cost reduction, the time base collector is restricted by using a small capacity (several lines) line memory capable of storing only several lines of video signals. is there. In this case,
The pull-in time of the read PLL circuit cannot be increased without limit, and there are certain restrictions. If the pull-in time of the read PLL circuit is too long, the center frequency of the read clock does not follow the center frequency of the write clock (the locked state is not maintained), and the center frequency of the read clock and the center frequency of the write clock are reduced. As a result, a so-called memory overtaking occurs in which the address of the write clock overtakes the address of the read clock, and the video is shifted by an amount corresponding to the delay amount of the line memory. This is because inconvenience occurs.

That is, when an attempt is made to form a time base collector using a line memory of a small size, the pull-in time of the PLL circuit for generating the read clock is such that the center frequency of the read clock is equal to the center frequency of the write clock. There is a restriction that it must be as long as possible within a range that can be followed.

However, under such a restriction, when the input video signal itself is switched, for example, when the program channel of the television receiver is switched, there is a problem that the transient response becomes too slow. Occurs.
That is, when the input video signal is switched, the frequency of the horizontal synchronizing signal changes abruptly before and after the switching, so that if the pull-in time of the PLL circuit for reading is made very long as described above, The time from the switching of the video signal to the locking of the frequency of the read clock to the frequency of the horizontal synchronization signal becomes extremely long (in some cases, about several seconds), and during this time, the displayed image is greatly disturbed.

To avoid this, for example, a frame synchronizer using a field memory capable of storing input video signals for several fields is used, and the read clock is set to a free run irrelevant to the write clock. A method is also conceivable. However, this type of frame synchronizer is generally very expensive due to its large-scale device configuration, and it is not practical to mount it on a popular television receiver.

Also, about one field (for example, 200 fields)
A method is also conceivable in which a line memory capable of storing video signals of up to 300 horizontal lines is used to convert the delay amount of the video signal into a unit of one field, and the horizontal skew position is moved again to the vertical blanking period. However, in this case, since there is a delay of only several tens of horizontal lines, a line memory having a large capacity of almost one field must be prepared, which is inefficient.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a first object of the present invention is to provide a gradual and stable frequency pull-in characteristic in a steady state and a responsiveness when a sudden change occurs in an input signal. Another object of the present invention is to provide a phase-locked loop circuit capable of achieving both good frequency pull-in characteristics and good frequency lock characteristics.

A second object of the present invention is to perform a gradual and stable time-base correction in a steady state, and to perform a time-base correction with good responsiveness when a sudden change occurs in an input signal. A time axis correction circuit and a time axis correction method are provided.

A third object of the present invention is to provide an image display device capable of displaying a stable output image irrespective of phase fluctuations occurring in an input video signal due to various factors.

[0021]

According to the present invention, there is provided a phase locked loop circuit comprising: a voltage controlled oscillator for outputting a signal having a frequency corresponding to an input voltage; a phase of a signal obtained by dividing an output from the voltage controlled oscillator; A phase detector that detects a phase difference with the phase of the phase detector and outputs a voltage corresponding to the phase difference; a first low-pass filter provided between the phase detector and the voltage-controlled oscillator; A second low-pass filter which is provided in parallel with the first low-pass filter between the first low-pass filter and the second low-pass filter and has a time constant smaller than that of the first low-pass filter; Switching means for switching whether or not the low-pass filter is made effective.

A time axis correction circuit according to the present invention includes a line memory, a first phase locked loop circuit for generating a write clock, and a second phase locked loop circuit for generating a read clock. Two phase locked loop circuits
A voltage-controlled oscillator that outputs a signal having a frequency corresponding to the input voltage, and a phase difference between a phase of a signal obtained by dividing the output from the voltage-controlled oscillator and a phase of a horizontal synchronization signal or a write clock of the input video, A phase detector that outputs a voltage corresponding to the phase difference; and a phase detector that is provided between the phase detector and the voltage controlled oscillator and has a time constant corresponding to a second pull-in time longer than the first pull-in time. A first low-pass filter, a second low-pass filter provided between the phase detector and the voltage-controlled oscillator in parallel with the first low-pass filter, and having a time constant smaller than that of the first low-pass filter; Switching means for switching whether or not to enable the second low-pass filter based on the output of the phase detector.

According to the time axis correction method of the present invention, a write clock is generated based on a horizontal synchronizing signal of an input video signal using a first phase locked loop circuit, and the write clock is generated as a horizontal synchronizing signal or a write clock of the input video. The input video signal is written to the line memory based on the input video signal. If the horizontal fluctuation signal of the input video or the phase fluctuation of the write clock is smaller than a predetermined level, the second
The read clock is generated at the first pull-in time based on the horizontal sync signal of the input video or the write clock by using the phase locked loop circuit of FIG. When the level is larger than the level, the second phase locked loop circuit is used to generate a read clock with a second pull-in time shorter than the first pull-in time based on the horizontal sync signal of the input video or the write clock, By reading the input video signal from the line memory based on the generated read clock, the time axis fluctuation of the input video signal is corrected.

An image display device according to the present invention includes a time axis correction circuit including a line memory, a first phase locked loop circuit for generating a write clock, and a second phase locked loop circuit for generating a read clock. A voltage-controlled oscillator that outputs a signal having a frequency corresponding to the input voltage, a phase-locked signal of a signal obtained by dividing the output from the voltage-controlled oscillator, and a horizontal synchronization signal of the input image. A phase detector that detects a phase difference from the phase of the write clock and outputs a voltage corresponding to the phase difference, and is provided between the phase detector and the voltage controlled oscillator, and corresponds to a second pull-in time. A first low-pass filter having a time constant, and a time constant smaller than the time constant of the first low-pass filter, provided between the phase detector and the voltage-controlled oscillator in parallel with the first low-pass filter. A second low-pass filter, based on the output of the phase detector, which is constituted to include a switching means for switching whether to enable the second low-pass filter.

In the phase locked loop circuit of the present invention, a voltage corresponding to the phase difference between the phase of the signal obtained by dividing the output signal from the voltage controlled oscillator and the phase of the input signal to the phase locked loop circuit is detected by the phase detector. Output from A second low-pass filter having a time constant smaller than the time constant of the first low-pass filter is provided between the phase detector and the voltage-controlled oscillator in parallel with the first low-pass filter. Is activated or deactivated based on the output of the phase detector.

In the time axis correction circuit, the time axis correction method, or the image display device according to the present invention, the phase of the signal obtained by dividing the output signal from the voltage controlled oscillator, the phase of the horizontal synchronizing signal of the input video or the phase of the write clock are determined. Is output from the phase detector. A second low-pass filter having a time constant smaller than that of the first low-pass filter is provided between the phase detector and the voltage-controlled oscillator in parallel with the first low-pass filter. The two low-pass filters are activated or deactivated based on the output of the phase detector.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[First Embodiment] FIG. 1 shows a main configuration of an image display apparatus according to an embodiment of the present invention. It should be noted that the time axis correction circuit and the time axis correction method according to the embodiment of the present invention are embodied by the image display device of the present embodiment, and thus will be described together.

The image display device 1 includes a luminance / color / timing circuit (hereinafter, referred to as a YCT circuit) 10 and a YC circuit.
An amplifier (AMP) 20 provided on the output side of the T circuit 10
And a low-pass filter circuit 30 provided on the output side of the AMP 20.

The YCT circuit 10 includes a tuner (not shown)
Composite Video Burst Sign (CVBS), which is a composite video signal supplied from a VCR or DVD (Digital Versatile Disc) via a switcher
al) and a Y / C separation function for separating a Y / C signal (S video signal), which is a luminance / color separation signal, into a luminance signal Y and a color signal C, and a separated color signal C as a red color difference signal U. It has a chroma decoder function of converting to and outputting a blue color difference signal V, and a timing pulse generating function of extracting and outputting a vertical synchronizing signal VS and a horizontal synchronizing signal HS from an input video signal. The YCT circuit 10 also receives a YUV signal, which is a video signal separated in advance into a luminance signal Y and color difference signals U and V from a personal computer or the like, and outputs the signal as it is. After all, the YCT circuit 10
Converts the luminance signal Y and the color difference signals U and V into the AMP 20
And the vertical synchronizing signal VS and the horizontal synchronizing signal H
S is supplied to each section at the subsequent stage. In addition,
The color difference signal U is a signal B−Y obtained by subtracting the luminance signal Y from blue (B; Blue), and the color difference signal V is a signal R−Y obtained by subtracting the luminance signal Y from red (R; Red).

The AMP 20 amplifies the luminance signal Y and the color difference signals U and V from the YCT circuit 10 and supplies them to the low-pass filter circuit 30. The low-pass filter circuit 30 functions to cut the high-frequency components of the luminance signal Y and the color difference signals U and V and pass only the low-frequency components.

The image display device 1 also includes an analog / digital (A / D) conversion circuit 40 provided at a stage subsequent to the low-pass filter circuit 30 and a memory circuit 50 provided at a stage subsequent to the A / D conversion circuit 40. , This memory circuit 5
And a texture enhancement circuit 60 as an image processing circuit provided at the subsequent stage of the “0”.

The A / D conversion circuit 40 converts the analog luminance signal Y and the color difference signals U and V output from the low-pass filter circuit 30 into digital signals, respectively, and outputs the digital signals to the memory circuit 50 at the subsequent stage. It has a unit 41 and a switch 42 for outputting the color difference signals U and V in a time division manner while switching.

The A / D conversion circuit 40 also includes a YCT circuit 1
Based on the horizontal synchronizing signal HS supplied from 0, a clock phase CKW having a frequency obtained by multiplying the frequency of the horizontal synchronizing signal HS by a first pull-in time and outputting the generated clock signal CKW. PLL) 43 and W-PL
A frequency divider 44 arranged on the output side of the L circuit 43 to divide the frequency of the clock signal CKW. The clock signal CKW is supplied to the A / D conversion unit 41 and serves as a reference for the A / D conversion operation, and is also supplied to the memory circuit 50 and serves as a reference for the write operation. Hereinafter, this clock signal is referred to as a write clock CKW. W-PLL circuit 43
Is connected to its own input terminal via a frequency divider 44, thereby forming a loop. Divider 4
The output of 4 is fed back to the input terminal of the W-PLL circuit 43, and is also supplied to the memory circuit 50 as a horizontal synchronization signal HDW for writing, and is used for controlling the writing operation. Here, the W-PLL circuit 43 corresponds to a specific example of “first phase locked loop circuit” in the present invention.

The memory circuit 50 includes two line memories 5
1, 52 and a write address generation unit (W-ADRS) 53
And a read address generation unit (R-ADRS) 54. Each of the line memories 51 and 52 is a line memory capable of storing video signals for several lines (here, four lines). Specifically, the line memory 51 stores the luminance signals Y for four lines, and the line memory 52 stores the color difference signals U or V for four lines. The write address generation unit 53 is configured to write the write clock CKW from the W-PLL circuit 43 of the A / D conversion circuit 40.
And the horizontal synchronization signal HDW from the frequency divider 44,
The write address signal AW is supplied to the line memories 51 and 52. The read address generation unit 54 supplies a read address signal A to the line memories 51 and 52 based on a read clock CKR supplied from a texture enhance circuit 60 described later and a horizontal synchronizing signal HDR for reading.
R is supplied. Here, the line memories 51 and 52 correspond to a specific example of “line memory” in the present invention. The line memories 51 and 52 include the W-PLL circuit 43 and an R-PLL circuit 6 described later.
5 together with a main part of the time axis correction circuit according to the embodiment of the present invention.

The texture enhancement circuit 60 includes a texture enhancement (TE) processing unit 61 and a digital / analog (D /
A) It has conversion units 62, 63, 64.

Although not shown, the TE processing unit 61 includes an S / T separation unit that divides the luminance signal Y of the input video signal into a structure component and a texture component, and a structure correction unit that performs a nonlinear correction process on the structure component. , A texture amplifying unit that performs an amplifying process on the texture component, and an adding unit that combines and outputs the output of the structure correcting unit and the output of the texture amplifying unit. Texture enhancement processing for emphasizing only the texture component is performed. Along with this processing, the video signal is delayed by an amount less than one field (for example, about 40 lines).

The D / A converter 62 converts the luminance signal Y output from the TE processor 61 into an analog signal and outputs it. The D / A converters 63 and 64 output the luminance signal Y output from the TE processor 61. The color difference signals U and V are converted into analog signals and output.

The texture enhancement circuit 60 also determines
Based on the horizontal synchronizing signal HS supplied from the CT circuit 10, a read-out phase-locked loop circuit (R) that generates and outputs a clock signal CKR having a frequency obtained by multiplying the frequency of the horizontal synchronizing signal HS in a second pull-in time. -PLL) 65
And a frequency divider 66 arranged on the output side of the R-PLL circuit 65 to divide the frequency of the clock signal CKR. The clock signal CKR is supplied to the TE processing unit 61 and serves as a reference for the texture enhancement operation, and is also supplied to the read address generation unit 54 of the memory circuit 50 and serves as a reference for the read operation. Hereinafter, this clock signal is referred to as a read clock CKR. The output terminal of the R-PLL circuit 65 is connected to its own input terminal via a frequency divider 66, thereby forming a loop. The output of the divider 66 is R-
In addition to being fed back to the input terminal of the PLL circuit 65,
The read-out horizontal synchronizing signal HDR is supplied to the read address generation unit 54 of the memory circuit 50, and is used for controlling the read operation. Here, the R-PLL circuit 6
5 corresponds to a specific example of the “second phase locked loop circuit” in the present invention.

The image display device 1 further includes an adder 70 for adding and superimposing the luminance signal Y output from the texture enhancer circuit 60 and the synchronizing signal SYNC, and a luminance signal with a synchronizing signal output from the adder 70. Y1 and D / A
The color difference signals U output from the conversion units 63 and 64, respectively.
A matrix circuit (not shown) for converting a YUV signal composed of 1 and V1 into an RGB (red-green-blue) signal, and a RGB signal from the matrix circuit to a subsequent CRT (cathode ray tube), LCD (liquid crystal display element), etc. And a drive circuit (not shown) for converting into a drive signal of a voltage suitable for display on the display device. Note that the synchronization signal SYNC is the horizontal synchronization signal H generated by the texture enhancement circuit 60.
D and the vertical synchronization signal VD are generated by an AND circuit 80.

Next, referring to FIGS. 2 and 3, A / D
The configurations of the W-PLL circuit 43 of the conversion circuit 40 and the R-PLL circuit 65 of the texture enhancement circuit 60 will be described.

FIG. 2 shows the configuration of the W-PLL circuit 43. This W-PLL circuit 43 is a YCT circuit 10
, A low-pass filter 432 provided on the output side of the phase detector 431, and a low-pass filter 43.
Voltage-controlled oscillator (VCO) 43 provided on the output side of
3 is provided. The output terminal of the VCO 433 is a frequency divider 44
Is connected to the other input terminal of the phase detector 431 via the.

The phase detector 431 detects the difference between the phase of the horizontal synchronizing signal HDW for writing and the phase of the horizontal synchronizing signal HS obtained by dividing the output of the VCO 433 by the frequency divider 44, and detects the difference. A voltage corresponding to the phase difference is output.

The low-pass filter 432 is connected to the phase detector 4
31 for cutting high-frequency components from the output of the V. 433. A resistor R0 connected between the output terminal of the phase detector 431 and the input terminal of the VCO 433, and a resistor R0 connected between the output terminal of the resistor R0 and the ground. And connected capacitor C0. In the low-pass filter 432, a time constant τ0 (= r ₀ ×) determined by the values of the resistor R0 and the capacitor C0.
In accordance with c ₀ ), a low-pass component passing characteristic for the output of the phase detector 431, that is, a PLL pull-in characteristic is determined. Note that r ₀ and c ₀ indicate the resistance value of the resistor R0 and the capacitance value of the capacitor C0, respectively. Here, the time constant τ0 of the low-pass filter 432 is set to be sufficiently small so that the pull-in time is sufficiently short.

The VCO 433 includes a low-pass filter 432
And outputs a write clock CKW having a frequency corresponding to the output voltage of the memory circuit 50, and supplies the write clock CKW to the frequency divider 44 and also to the write address generator 53 of the memory circuit 50. The frequency of the write clock CKW is, for example, 1
It is set to 3.5 MHz.

The frequency division ratio n of the frequency divider 44 is set to 858 when the video signal is NTSC and 864 when the video signal is PAL.

FIG. 3 shows the configuration of the R-PLL circuit 65. This R-PLL circuit 65 is a YCT circuit 10
Detector 651 that receives the horizontal synchronization signal HS from the first input terminal at one input terminal, a low-pass filter 652 as a first low-pass filter provided on the output side of the phase detector 651, and the output side of the low-pass filter 652 And a VCO 653 provided for the The output terminal of the VCO 653 is connected to the other input terminal of the phase detector 651 via the frequency divider 66. Here, the phase detector 651 and V
CO653 corresponds to one specific example of the phase detector and the voltage-controlled oscillator in the present invention, respectively.

The R-PLL circuit 65 also includes the phase detector 6
A low-pass filter 654 as a second low-pass filter provided in parallel between the first low-pass filter and the VCO 653, and whether to enable the low-pass filter 654 based on the output of the phase detector 651 A diode circuit 655 functioning as switching means for switching.

The phase detector 651 detects the difference between the phase of the horizontal synchronizing signal HDR for reading obtained by dividing the output of the VCO 653 by the frequency divider 66 and the phase of the horizontal synchronizing signal HS, and detects the phase difference. Output a voltage corresponding to.

The low-pass filter 652 is connected to the phase detector 6
A resistor R1 connected between the output terminal of the resistor R1 and the input terminal of the VCO 653, and an output terminal (VCO 653
Side) and the ground, and a resistor R2 and a capacitor C2 connected in series between the output terminal of the resistor R1 and the ground.
And a capacitor C1 connected in parallel with the resistor R2 and the capacitor C2. As the capacitor C2,
A capacitor having a large capacity, for example, an electrolytic capacitor is used.

In the low-pass filter 652, the resistance R
1, R2 and the time constant τ1 determined by the capacitors C1, C2 determine the low-pass component passing characteristic with respect to the output of the phase detector 651, that is, the pull-in characteristic of the R-PLL circuit 65. Here, the low-pass filter 652
Is set to be sufficiently larger than the low-pass filter 432 of the W-PLL circuit 43 so that the pull-in time of the R-PLL circuit 65 is sufficiently long when the low-pass filter 652 operates alone. ing.

The low-pass filter 654 is connected to the phase detector 6
51 includes a resistor Rd connected in parallel with the resistor R1 of the low-pass filter 652 on the output terminal side of the low-pass filter 652, and a capacitor Cd connected between the output terminal (VCO 653 side) of the resistor Rd and the ground. This low-pass filter 65
4 time constant _{τ2 (= r d × c d} ) is set to be sufficiently smaller than the low-pass filter 652. Note that r
_d, c _d, respectively, shows the resistance value of the resistor Rd, the capacitance of the capacitor Cd.

The diode circuit 655 includes a first diode group composed of two diodes D1 and D2 connected in series in a forward direction from the output terminal of the low-pass filter 654 toward the VCO 653, and the first diode group is connected in parallel. And two diodes D3 and D connected in series
4 of the second diode group. With such a configuration, the diode circuit 655 is turned on when the potential difference between both ends exceeds twice the forward ON voltage Von of the diode (for example, about 0.65 V × 2 = about 1.3 V). . Here, twice the forward ON voltage Von corresponds to a specific example of “predetermined level” in the present invention.

The VCO 653 includes a low-pass filter 652
Alternatively, a read clock CKW having a frequency corresponding to the voltage input from the diode circuit 655 is output and supplied to the frequency divider 66 and also to the read address generator 54 of the memory circuit 50. . The frequency of the read clock CKR is set to, for example, 13.5 MHz, like the write clock CKW. The frequency division ratio n of the frequency divider 66 is set equal to that of the frequency divider 44.

Next, the image display device 1 having the above-described configuration will be described.
Will be described.

The YCT circuit 10 includes a tuner (not shown)
A composite signal CVBS or Y / C signal supplied from a VCR or a DVD is separated into a luminance signal Y and a chrominance signal C, and the separated chrominance signal C is decoded and converted into chrominance signals U and V. I do. Further, the YCT circuit 10
Extracts a vertical synchronizing signal VS and a horizontal synchronizing signal HS from these input video signals and outputs them. When a YUV signal is input from a personal computer or the like, the YCT circuit 10 outputs the signal as it is.

The luminance signal Y and the color difference signals U and V from the YCT circuit 10 are respectively amplified by the AMP 20, and the high-frequency component is cut off by the low-pass filter circuit 30, and only the low-frequency component is converted to the A / D conversion circuit 40. Is input to

A / D conversion section 41 of A / D conversion circuit 40
Converts the analog luminance signal Y and the color difference signals U and V output from the low-pass filter circuit 30 into digital signals and outputs the digital signals to the memory circuit 50 at the subsequent stage. At this time, the color difference signals U and V are output in a time division manner while being alternately switched by the switch 42.

W-PLL circuit 43 of A / D conversion circuit 40
(FIG. 2) generates and outputs a write clock signal CKW having a frequency obtained by multiplying the frequency of the horizontal synchronization signal HS based on the horizontal synchronization signal HS supplied from the YCT circuit 10. Since the time constant of the low-pass filter 432 of the W-PLL circuit 43 is sufficiently small, the pull-in time of the W-PLL circuit 43 is sufficiently short. Therefore, the write clock CKW output from the VCO 433 is the horizontal synchronization signal HS of the input video. Lock and follow. Therefore, when a phase change occurs in the horizontal synchronization signal HS, a phase change also occurs in the write clock CKW, but the center frequency of the write clock CKW matches the center frequency of the horizontal synchronization signal HS. This write clock CKW is divided by the frequency divider 44 into 1 / n.
, And is fed back to the phase detector 431.

R-PL of Texture Enhancement Circuit 60
The L circuit 65 (FIG. 3) generates and outputs a read clock signal CKR having a frequency obtained by multiplying the frequency of the horizontal synchronization signal HS based on the horizontal synchronization signal HS supplied from the YCT circuit 10.

Here, the input image is in a steady state (ie,
When the input video signal includes jitter such as phase fluctuations due to switching of the reproducing head, but the video signal is continuously input from the same source), the output voltage from the phase detector 651 is output. Keeps a sufficiently small value, the potential difference between both ends of the diode circuit 655 does not exceed twice the forward ON voltage Von of the diodes D1 and D2 or the diodes D3 and D4. Therefore, the diode circuit 655 remains off, the low-pass filter 654 is disabled, and only the low-pass filter 652 functions. Since the time constant of the low-pass filter 652 is sufficiently large, the pull-in time of the R-PLL circuit 65 is sufficiently long. Therefore, the read clock CKW output from the VCO 653 is locked to the horizontal synchronization signal HS of the input video, and Although the center frequency matches the center frequency of the horizontal synchronizing signal HS, it does not follow the phase fluctuation of the horizontal synchronizing signal HS one by one. That is, the read clock CKR
Is a stable clock that does not receive the phase fluctuation of the input video. The read clock CKR is frequency-divided by the frequency divider 66 to a frequency of 1 / n, and is fed back to the phase detector 651.

On the other hand, when the frequency of the horizontal synchronizing signal HS of the input image fluctuates rapidly, as in the case where the input image signal is switched, the output voltage from the phase detector 651 rises, and the voltage at both ends of the diode circuit 655 is increased. The potential difference exceeds twice the forward ON voltage Von of the diodes D1 and D2 or the diodes D3 and D4. Therefore, the diode circuit 6
55 turns on, and not only the low-pass filter 652 but also the low-pass filter 654 functions. Since the time constant of the low-pass filter 654 is sufficiently small, the combined time constant of the low-pass filters 652 and 654 is also sufficiently small, and as a result, the pull-in time of the R-PLL circuit 65 is sufficiently short. Therefore, the read clock CKW output from the VCO 653 is quickly locked to the horizontal synchronization signal HS of the input video, and its center frequency changes quickly so as to coincide with the center frequency of the horizontal synchronization signal HS.

In the memory circuit 50, the write address generation unit 53 generates a write address based on the write clock CKW from the W-PLL circuit 43 of the A / D conversion circuit 40 and the horizontal synchronization signal HDW from the frequency divider 44. A write address signal AW is generated and supplied to the line memories 51 and 52. In synchronization with the write address signal AW, the luminance signal Y
Are written in the pixel sequence, and the color difference signal U or the color difference signal V is written in the line memory 52 in the pixel sequence. Here, if the horizontal synchronizing signal HS has a phase change such as horizontal skew due to the switching of the reproducing head, the phase of the write clock CKW also changes following the phase change.
2, the luminance signal Y and the color difference signals U and V are written in order according to the write address signal AW generated based on the write clock CKW.

The read address generator 54 generates a read address signal AR based on the read clock CKR supplied from the texture enhancer circuit 60 and the horizontal synchronizing signal HDR for reading, and supplies the read address signal AR to the line memories 51 and 52. . In synchronization with the read address signal AR, the luminance signal Y is read out from the line memory 51 in pixel order, and the color difference signal U or the color difference signal V is read out from the line memory 52 in pixel order.

Here, as described above, the diode circuit 655 of the R-PLL circuit 65 is kept off even if there is a slight phase change such as horizontal skew due to the switching of the reproducing head in the horizontal synchronizing signal HS. , Only the low-pass filter 652 having a large time constant functions, resulting in the R-PLL
The pull-in time of the circuit 65 remains long. For this reason,
As shown in FIG. 5, the phase of the read clock CKR does not change and maintains a stable state. For this reason, the luminance signal Y and the color difference signals U and V are read out from the line memories 51 and 52 in order and stably in accordance with the read address signal AR generated based on the read clock CKR, respectively, and the phase variation is performed. The stable video signal without the signal is sent to the texture enhancement circuit 60 at the subsequent stage. In the texture enhancement circuit 60, a delay of about 40 lines occurs in the video due to the texture enhancement processing in the TE processing unit 61. However, since this video signal does not include a phase change, image distortion such as horizontal skew is displayed on the screen. Does not occur.

On the other hand, when the frequency of the video signal changes abruptly as in the case where the input video signal is switched, the diode circuit 655 of the R-PLL circuit 65 as described above.
Is turned on, and the low-pass filter 6 having a large time constant
As a result, the low-pass filter 654 having a sufficiently small time constant functions as well as the R-PLL circuit 65.
The pull-in time changes sufficiently short, and the read clock CK
W quickly locks to the horizontal synchronization signal HS of the input video after switching. As a result, the time of image disturbance on the screen is significantly reduced. For example, as a comparative example, when the low-pass filter 654 is not used and only the low-pass filter 652 is used, it takes 2 to 3 seconds or more until the image becomes normal. It can be within seconds.

The luminance signal Y thus read from the memory circuit 50 is input to the texture enhance circuit 60, where it undergoes the following processing based on the read clock CKR output from the R-PLL circuit 65. .

FIG. 4 shows T of the texture enhancement circuit 60.
7 conceptually illustrates the content of image processing in the E processing unit 61. In this drawing, the maximum luminance level (100% white level) of the input luminance signal is expressed as 100 IRE, and the minimum luminance level (0% black level) is expressed as 0 IRE.
The IRE (Institute of Radio Engineers) is a unit that relatively represents a voltage level of a video signal, and a 100% white level is 100 IR based on a pedestal level.
E.

As shown in FIG. 4, the input luminance signal Y _IN is separated by an S / T separation circuit into a structure component S1 forming the contour of the image and a texture component T1 forming the details of the image. You. The texture component T1 is amplified by the texture amplification unit to become the texture component T2. The amplitude of the structure component S1 is corrected by the structure correction unit so that the low-frequency side (black side) is lifted and the high-frequency side (white side) is suppressed, and becomes the structure component S2. Further, the structure component S2 and the texture component T2 are added by an adder, and the luminance signal Y
_OUT . At this time, the texture component T2 is superimposed on the corrected structure component S2, and the maximum value and the minimum value of the luminance signal Y _OUT are 0 to 100.
It falls within the range of the IRE. With the above processing, a delay of about 40 lines occurs in the luminance signal.

The luminance signal Y thus corrected by the TE processing unit 61 is converted into an analog signal by the D / A converter 62, and then the synchronizing signal SYNC is added by the adder 70, and the luminance signal Y is added. The signal Y1 is input to a subsequent matrix circuit (not shown).

On the other hand, the color difference signals U and V input to the texture enhance circuit 60 are amplified and output after receiving a delay corresponding to the delay of the luminance signal. The color difference signals U and V are converted into analog signals by D / A converters 63 and 64, respectively, and are input as color difference signals U1 and V1 to a subsequent matrix circuit (not shown).

The luminance signal Y1 input to the matrix circuit
The YUV signal composed of the color difference signals U1 and V1 is converted into an RGB signal here, and then converted into a drive signal by a drive circuit (not shown) at the subsequent stage.
The image is output to a display device such as a CD for image display.

As described above, according to the image display device 1 of the present embodiment, the R-signal for generating the read clock CKR is used.
In the PLL circuit 65, the phase detector 651 and the VCO 6
53, a first low-pass filter 652 having a sufficiently large time constant is provided, and the phase detector 651 and the VCO 6
53 and a second low-pass filter 654 having a time constant sufficiently smaller than the time constant of the first low-pass filter 652 in parallel with the first low-pass filter 652.
And whether or not to enable the second low-pass filter 654 is switched according to the output voltage of the phase detector 651. For this reason, even if the phase of the horizontal synchronizing signal HS fluctuates slightly due to switching of the reproducing head or the like, the diode circuit 655 maintains the off state,
Since only the low-pass filter 652 having a large time constant functions, the pull-in time of the R-PLL circuit 65 is long, and the read clock CKR maintains a stable state. As a result,
The luminance signal Y and the color difference signals U and V read from the line memories 51 and 52 are stable signals without phase fluctuation, and there is no image disturbance such as horizontal skew on the screen.

On the other hand, when the frequency of the video signal changes abruptly as in the case where the input video signal is switched, the diode circuit 655 of the R-PLL circuit 65 is turned on, and the time constant is not sufficient. Small low-pass filter 6
As a result, the pull-in time of the R-PLL circuit 65 becomes sufficiently short, and the read clock CKW is quickly locked to the horizontal synchronization signal HS of the input video after the switching. As a result, the time of image disturbance on the screen is significantly reduced.

Further, in the present embodiment, the diode circuit 655 is used as the switching means. Therefore, only the diode circuit 655 causes a large phase change of the horizontal synchronizing signal HS (that is, a sudden change in the output of the phase detector 651). ) And a switching function of switching the low-pass filter 654 from the invalid state to the valid state. That is, there is no need to provide a circuit for detecting a sudden phase change separately from the changeover switch for switching the validity / invalidity of the low-pass filter 654. Therefore, the two functions of the detection function and the switching function
One function can be realized by a very simple circuit configuration.

As described above, the time axis correction circuit and method according to the present embodiment are effective when the frequency of the input video signal greatly changes due to channel switching.
It may work effectively in other cases.

For example, the time axis correction circuit of the present embodiment is also effective when a macro vision signal is superimposed on an input video signal. As shown in FIG. 6, the macrovision signal is a pseudo-horizontal synchronization signal inserted into a vertical blanking interval when a video signal is recorded on a recording medium. As for the video signal, the automatic gain control (AGC) circuit in the recording section of the VCR malfunctions, and the recorded image quality is deteriorated to an unusable level, so that the "copy" function is substantially disabled.

FIG. 6 shows the vertical blanking period TB of the composite (CVBS) signal. As shown in this figure, the equalizing pulse EQ is inserted before and after the period of the vertical synchronization signal VS. This equalizing pulse is a pulse having a frequency twice as high as that of the horizontal synchronizing signal HS, and is inserted immediately before and after the vertical synchronizing signal VS to reduce the overlapping effect of the horizontal synchronizing signal HS. Is what you do.

In a period TC immediately after the equalizing pulse EQ, a predetermined number of pulses of the macrovision signal MV are applied to the horizontal synchronizing signal H.
It is inserted mixed with S. Therefore, if the pull-in time of the R-PLL circuit 65 is always long, the horizontal synchronizing signal HS in the period TC immediately after the vertical synchronizing signal VS.
Is disturbed, and the disturbance extends to the display period TA following the period TC, resulting in a disturbed display image.

On the other hand, in the time axis correction circuit of the present embodiment, the presence of the macro vision signal MV is detected by the diode circuit 655 of the R-PLL circuit 65, and the low pass filter 654 operates effectively. ,
Since the pull-in time of the R-PLL circuit 65 changes to a sufficiently small value and the read clock CKR is quickly locked to the horizontal synchronizing signal HS immediately after the end of the period TC and stabilized, image disturbance does not extend to the display period TA. Disappears.

The time axis correction circuit according to the present embodiment
This is also effective when special reproduction such as fast-forward search or rewind search is performed. When the fast-forward search or the like is performed, the frequency of the horizontal synchronizing signal HS changes greatly. For example, as shown in FIG. 7, the screen on the screen is shifted in the horizontal direction. The rapid phase change of the horizontal synchronizing signal HS is detected by the diode circuit 655, and the low-pass filter 654 operates effectively. As a result, the pull-in time of the R-PLL circuit 65 changes to a sufficiently small value, and the read clock CKR is read. Screen locks quickly to the horizontal sync signal HS and stabilizes.
The section of the image disorder on the SP is shortened.

Although the present invention has been described with reference to the embodiment, the present invention is not limited to this embodiment, and various modifications are possible. For example, in the above embodiment, the diode circuit 655 is configured by the first diode group or the second diode group. However, depending on the characteristics of the phase detector 651 and the VCO 653, the first diode group or the second diode group Alternatively, it may be constituted by only one of them. For example, the phase detector 651 and the VCO 653
Is good only in one direction (either the increasing direction or the decreasing direction) (ie,
In the case where the gain is high, it is sufficient to provide the diode group only on the side where the response performance is slow.

The first diode group does not always have to be 2
It is not necessary to constitute by one diode D1 and D2, and it is also possible to constitute by one diode, or to connect and connect three or more diodes in series. The on / off threshold level of the diode circuit 655 can be changed by changing the number of diodes connected in series. The same applies to the second diode group. However, when each of the first and second diode groups is configured by one diode,
If the response performance of the R-PLL circuit 65 is high and the loop gain is excessively high, the R-PLL circuit 65 may fall into an oscillation state. On the other hand, in the case of using two diodes, a sufficient time is required from turning on one diode group to turning on the diode group in the opposite direction. Repetitive oscillation phenomenon (inversion phenomenon) can be avoided.

As a modification of the low-pass filter 652, a connection point between the resistor R1 and the capacitor C2 may be connected to the power supply voltage Vcc. In this case, since the charging of the capacitor C2 is performed not only from the ground side but also from the power supply voltage Vcc side, the rise at the time of turning on the power becomes earlier.

In this embodiment, the read clock CKR is generated in the R-PLL circuit 65 based on the horizontal synchronizing signal HS of the input video. Instead, the read clock CKR is generated based on the write clock CKW. Read clock CK
R may be generated. Further, the configuration may be such that either the horizontal synchronization signal HS or the write clock CKW can be appropriately selected.

In this embodiment, the W-PLL circuit 43 is arranged in the A / D conversion circuit 40 and
Although the PLL circuit 65 is arranged in the texture enhance circuit 60, at least one of these PLL circuits is provided outside the A / D conversion circuit 40 and the texture enhance circuit 60 or in the memory circuit 50. It may be arranged. However, both the W-PLL circuit 43 and the R-PLL circuit 65 are connected to the memory circuit 50.
, The mutual interference may occur. Therefore, it is preferable to arrange only one of the W-PLL circuit 43 and the R-PLL circuit 65 in the memory circuit 50. .

In this embodiment, the line memories 51 and 5
Although a memory having a storage capacity of four lines is used as 2, the present invention is not limited to this. However, 3
If the number of lines is equal to or less than the number of lines, an overtaking phenomenon in which the read address overtakes the write address is likely to occur, so that at least four lines are required. On the other hand, a line memory having an excessively large number of lines is disadvantageous in terms of cost.

In the present embodiment, the time axis correction circuit is arranged in an image display device such as a television receiver. However, for example, the time axis correction circuit may be provided inside a reproduction device such as a VCR or a DVD device, or in a video device. It may be arranged inside a video recording device such as a camera.

In the present embodiment, the texture enhancement processing has been described as an example of the image processing that causes a signal delay that is not a field unit. However, the present invention can be applied to other image processing. For example, if m is an arbitrary integer, the time axis correction circuit and method of the present invention can also be applied to image processing involving an amount of signal delay that slightly exceeds m fields.

In this embodiment, the case where the phase locked loop circuit according to the present invention is applied to a time axis correction circuit has been described. However, the application of the phase locked loop circuit is not limited to this. The present invention is also applicable to a signal processing circuit having a processing and memory of about one hundred and several tens of lines.

[0091]

As described above, according to the phase locked loop circuit according to any one of the first to fourth aspects, the first low-pass filter and the voltage controlled oscillator are provided between the phase detector and the voltage controlled oscillator. A second low-pass filter having a time constant smaller than the time constant of the first low-pass filter is provided in parallel, and the second low-pass filter is switched between an operating state and a non-operating state based on an output of the phase detector. Therefore, it is possible to achieve both a gentle and stable frequency pull-in characteristic in a steady state and a frequency pull-in characteristic with good responsiveness when a sudden change occurs in an input signal.

A time axis correction circuit according to any one of claims 5 to 8, a time axis correction method according to claim 9, or an image display apparatus according to claim 10 or 11. For example, a second low-pass filter having a time constant smaller than the time constant of the first low-pass filter is provided between the phase detector and the voltage-controlled oscillator in parallel with the first low-pass filter; Since the second low-pass filter is switched between the operating state and the non-operating state based on the output, in the steady state where the change of the frequency and phase of the input video signal is small, while performing the gradual and stable time axis correction, When a sudden change occurs in the frequency or phase of the input video signal, it is possible to perform time axis correction with good responsiveness. Therefore, it is possible to display a stable output image irrespective of the phase fluctuation occurring in the input video signal due to various factors.

In particular, according to the phase locked loop circuit of the third aspect or the time axis correction circuit of the seventh aspect, the first low pass filter and the voltage controlled oscillator are connected between the second low pass filter and the voltage controlled oscillator.
And at least one of the second diode group in parallel and opposite to the first diode group is arranged, so that the operation state or non-operation state of the second low-pass filter can be extremely simplified. State switching can be performed.

According to the phase locked loop circuit according to the fourth aspect or the time axis correction circuit according to the eighth aspect, each of the first and second diode groups is connected to two series-connected two diodes. Since it is made of a diode, it is possible to avoid an oscillation phenomenon.

Further, according to the image display device of the present invention, when the input video signal is delayed by a non-field unit by the image processing circuit which performs the emphasis processing of the texture component included in the input video signal. At
It is possible to display a stable output image.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of an image display device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of a W-PLL circuit in FIG.

FIG. 3 is a block diagram illustrating a schematic configuration of an R-PLL circuit in FIG. 1;

FIG. 4 is a diagram illustrating an operation of a TE processing unit in FIG. 1;

FIG. 5 is a diagram illustrating the operation of the image display device of FIG. 1;

FIG. 6 is a diagram illustrating another operation of the image display device in FIG. 1;

FIG. 7 is a diagram illustrating still another operation of the image display device in FIG. 1;

FIG. 8 is a diagram illustrating the operation of a time axis correction circuit configured without applying the phase locked loop circuit according to the present invention.

FIG. 9 is a diagram illustrating another operation of the time axis correction circuit configured without using the phase locked loop circuit according to the present invention.

[Explanation of symbols]

10 YCT circuit, 40 A / D conversion circuit, 43 W-
PLL circuit, 50 memory circuit, 51, 52 line memory, 60 texture enhancement circuit, 61 TE processing unit, 65 R-PLL circuit, 66 frequency divider, 651
Phase detector, 652... First low-pass filter, 653
... VCO, 654 ... second low-pass filter, 655 ...
Diode circuits, D1 to D4 ... diodes.

Claims (11)

[Claims] A voltage-controlled oscillator that outputs a signal having a frequency corresponding to an input voltage; and a phase difference between a phase of a signal obtained by dividing an output from the voltage-controlled oscillator and a phase of the input signal, and a phase difference between the phase and the input signal. A phase detector that outputs a voltage corresponding to a phase difference, a first low-pass filter provided between the phase detector and the voltage-controlled oscillator, and a second low-pass filter between the phase detector and the voltage-controlled oscillator. A second low-pass filter provided in parallel with the first low-pass filter and having a time constant smaller than the time constant of the first low-pass filter; and enabling the second low-pass filter based on an output of the phase detector. And a switching means for switching whether or not the phase-locked loop is performed. 2. The switching means, when the output of the phase detector is smaller than a predetermined level, invalidates the second low-pass filter, while the output of the phase detector is higher than the predetermined level. 2. The phase-locked loop circuit according to claim 1, wherein the second low-pass filter is made effective in the case of (1). 3. The switching means includes: a first diode group including at least one diode, provided between the second low-pass filter and the voltage-controlled oscillator; It is characterized by including at least one of a second diode group including at least one diode and provided in a direction opposite to the first diode group in parallel with a voltage controlled oscillator. The phase-locked loop circuit according to claim 1. 4. The first diode group and the second diode group.
4. The phase-locked loop circuit according to claim 3, wherein each of the diode groups comprises two diodes connected in series. 5. A line memory for storing an input video signal, and a write clock used for writing the input video signal to the line memory, a first clock based on the input video signal,
A first phase-locked loop circuit that generates at a pull-in time, and a second clock that generates a read clock used for reading an input video signal from the line memory based on a horizontal sync signal of an input video or the write clock. A second phase locked loop circuit comprising: a voltage controlled oscillator that outputs a signal having a frequency corresponding to an input voltage; and an output from the voltage controlled oscillator. A phase detector that detects a phase difference between the phase of the divided signal and the horizontal synchronization signal of the input image or the phase of the write clock, and outputs a voltage corresponding to the phase difference; and the phase detector and the voltage A first low-pass filter provided between the control oscillator and a time constant corresponding to a second pull-in time longer than the first pull-in time; The first between the voltage controlled oscillator
A second low-pass filter having a time constant smaller than the time constant of the first low-pass filter.
A time-base correction circuit comprising: a low-pass filter according to any one of claims 1 to 4, and switching means for switching whether or not to enable the second low-pass filter based on an output of the phase detector. 6. The switching means disables the second low-pass filter when the output of the phase detector is smaller than a predetermined level, while the output of the phase detector is higher than the predetermined level. 6. The time axis correction circuit according to claim 5, wherein the second low-pass filter is made effective in the case of. 7. The switching means includes: a first diode group including at least one diode, provided between the second low-pass filter and the voltage controlled oscillator; and the second low-pass filter and It is characterized by including at least one of a second diode group including at least one diode and provided in a direction opposite to the first diode group in parallel with a voltage controlled oscillator. A time axis correction circuit according to claim 5. 8. The first diode group and the second diode group.
8. The time axis correction circuit according to claim 7, wherein each of the diode groups includes two diodes connected in series. 9. A write clock is generated based on a horizontal synchronization signal of an input video using a first phase locked loop circuit, and an input video signal is generated based on the horizontal synchronization signal of the input video or the write clock. When the phase fluctuation of the horizontal sync signal of the input video or the write clock is smaller than a predetermined level, the horizontal sync signal of the input video or the horizontal sync signal of the input video is written using a second phase locked loop circuit. While the read clock is generated at the first pull-in time based on the write clock, when the horizontal fluctuation signal of the input video or the phase fluctuation of the write clock is larger than the predetermined level, the second clock is generated. Using a phase locked loop circuit, based on the horizontal synchronization signal of the input video or the write clock, read in a second pull-in time shorter than the first pull-in time. Generates a clock by reading the input video signal from said line memory based on the read clock, time base correction method characterized by correcting the time base fluctuation of the input video signal. 10. A time axis correction circuit for correcting a time axis fluctuation of an input video signal, and an image display unit for displaying an image based on the input video signal subjected to time axis correction by the time axis correction circuit. An image display device comprising: an image processing circuit that performs image processing with a delay that is not a field unit on an input video signal, wherein the time axis correction circuit includes: A first phase-locked loop circuit for generating a write clock used for writing an input video signal to the line memory at a first pull-in time based on a horizontal synchronization signal of an input video; A read clock used for reading an input video signal is set to a second clock longer than the first pull-in time based on a horizontal synchronization signal of the input video or the write clock. A second phase-locked loop circuit that generates a signal having a frequency corresponding to an input voltage, and an output from the voltage-controlled oscillator. A phase detector that detects a phase difference between the phase of the signal obtained by dividing the frequency and the phase of the horizontal synchronization signal or the write clock of the input image, and outputs a voltage corresponding to the phase difference; and the phase detector and the voltage A first low-pass filter provided between the phase detector and the voltage-controlled oscillator, the first low-pass filter having a time constant corresponding to the second pull-in time, provided in parallel with the first low-pass filter; A second low-pass filter having a time constant smaller than a time constant of the first low-pass filter; and enabling the second low-pass filter based on an output of the phase detector. An image display device comprising: a switching unit that switches whether or not to perform the setting. 11. The image display device according to claim 10, wherein the image processing circuit performs a process of enhancing a texture component included in the input video signal.