JP2783609B2 - Image signal processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing apparatus that performs image signal processing and skew compensation processing on an input image signal.

[Conventional technology]

The scanning method of the current television signal is 1
A 2: 1 interlaced scanning method in which scanning is performed by skipping a scanning line every other line is generally used.For example, in the case of the NTSC system, the scanning lines are interlaced with each other every 1/60 second in the television signal. The interlaced scanning is performed in such a manner that a field image formed by one interlaced scanning is used for two screens to form a frame image of one screen every 1/30 second.

In the case of the NTSC television signal, one frame screen is composed of two field screens as described above, and the one frame screen is composed of 525 scanning lines.

In addition, a horizontal synchronizing signal is added to the television signal every one horizontal scanning period, and a vertical synchronizing signal is added every one vertical scanning period. At the boundary of each field period, the continuity of the synchronizing signal is maintained. I'm dripping.

As a device for recording and reproducing the television signal as described above on a recording medium such as a magnetic disk, there is a still video recording / reproducing device.

The still video recording / reproducing apparatus rotates a magnetic disk as a recording medium at 3600 [rpm], and applies one track to a plurality of tracks formed concentrically on the magnetic disk.
A still image signal is obtained by recording an image signal for one field per track and repeatedly reproducing the recorded image signal for one field.

In addition, when reproducing a still image signal as described above, in order to correspond to the television signal scanning method as described above, a half horizontal synchronizing period (1 / 2H) delay element is used for one field. Is delayed by 1 / 2H except for the vertical synchronization period, and the image signal delayed by the delay element and the image signal not delayed are alternately switched and output every one field period to output the horizontal synchronization signal. A so-called skew compensation process is performed to maintain continuity and correspond to the above-described interlaced scanning.

FIG. 6 is a diagram showing a schematic configuration of a conventional still video reproducing apparatus. The operation of the conventional still video reproducing apparatus will be described below.

In FIG. 6, a magnetic disk 100 is driven by a motor 101.
The signal is rotated at 3600 [rpm], and a signal recorded on a track formed on the magnetic head 100 is reproduced by the magnetic head 102 and supplied to the reproducing amplifier 103.

After the signal reproduced by the magnetic head 102 is amplified to a practical amplitude level by the reproduction amplifier 103,
The image signal is supplied to the demodulation circuit 104, demodulated in the demodulation circuit 104, and an image signal for one field to which the composite synchronizing signal is added is output, and supplied to the synchronizing signal separating circuit 105 and the image signal processing circuit 107.

The synchronizing signal separating circuit 105 separates the composite synchronizing signal from the signal supplied from the demodulation circuit 104, and separates the composite synchronizing signal into a timing signal generating circuit 106 and a synchronizing signal adding circuit 1.
Supplied at 08.

A magnetic piece (PG pin) 107 for detecting the rotation phase of the magnetic disk 100 is provided on the circumference of the core of the magnetic disk 100, and the PG pin 107 is rotated by the rotation of the magnetic disk 100. Each time it crosses over the PG coil 108,
A pulse signal is output from the PG coil 108, and the PG coil 1
The pulse signal output from the signal generator 08 is subjected to waveform shaping by the waveform shaping circuit 109, and then, as the PG pulse signal synchronized with the rotational phase of the magnetic disk 100, the timing signal generating circuit
Supplied to 106.

The image signal recorded on each track on the magnetic disk 100 has an added vertical synchronizing signal.
It is recorded so as to be shifted 7H ± 2H in the circumferential direction from the position where 107 is provided.

In the timing signal generation circuit 106, the synchronization signal separation circuit 1
A blanking signal B and a skew compensation gate signal S are formed in synchronization with the composite synchronizing signal supplied from 05 and the PG pulse signal supplied from the waveform shaping circuit 109. The formed blanking signal B is an image signal. The skew compensation gate signal S is supplied to the processing circuit 110 to a switching switch 113 described later. Based on the blanking signal B supplied from the timing signal generation circuit 106, the image signal processing circuit 110
The image signal supplied from the demodulation circuit 104 is subjected to horizontal and vertical blanking processing and supplied to a synchronization signal addition circuit 111.

In the synchronization signal adding circuit 111, the image signal processing circuit 110 in the preceding stage is used.
The composite sync signal separated by the sync signal separation circuit 105 is added to the image signal for one field subjected to the blanking process in the above, and supplied to the 1 / 2H delay circuit 112 and the a terminal of the switching switch 113. The 1 / 2H delay circuit 112 delays the supplied image signal by a 1 / 2H period,
Supply to terminal.

The switching switch 113 switches the connection between the terminal a and the terminal b in the figure alternately every one field period in accordance with the skew compensation gate signal S output from the timing signal generating circuit 106, whereby the switching is performed. Switch
From 113, a frame image signal corresponding to the interlaced scanning method is output via an output terminal 114.

[Problems to be solved by the invention]

However, in the case of the conventional apparatus as described above, the recording start point of the image signal recorded on the magnetic disk is
The positional relationship with the PG pin varies from one magnetic disk to another, and an image signal delayed by 1 / 2H and an undelayed image signal are alternated in synchronization with a PG pulse signal generated by detecting the PG pin. When the skew compensation processing for switching to the output is performed, the continuity of the horizontal synchronizing signal is not always maintained at the boundary point of each field.

In addition, since the composite synchronization signal added to the reproduced image signal is reproduced from the magnetic disk, a part of the composite synchronization signal may be lost due to dropout caused by attachment of dust or scratches, or the composite synchronization signal may be externally received. There is a risk of deterioration due to mixing of noise from the magnetic disk or uneven rotation of the magnetic disk.

By the way, in the conventional apparatus, when an image signal reproduced from a magnetic disk by the still video reproducing apparatus is displayed as a still image by using, for example, a monitor device, a composite signal added to the reproduced image signal as described above is used. Even if the sync signal is degraded, AFC (Auto
Frequency control) circuit, it was possible to display a stable still image, but a degraded composite synchronizing signal was added to an image input device (for example, an image memory device) that did not have the AFC circuit. When a reproduced image signal is input, a normal image signal may not be input because the composite synchronizing signal is deteriorated.

The present invention eliminates the above-mentioned drawbacks of the related art and can output a composite sync signal without deterioration together with an image signal. It is an object of the present invention to provide an image signal processing device capable of performing a skew compensation process while maintaining performance.

[Means for solving the problem]

An image signal processing device according to the present invention is a device for inputting an image signal and processing the input image signal, wherein the first composite synchronizing signal added to the image signal from the input image signal is processed. A composite synchronizing signal separating / separating means for separating and outputting, and an image signal from which the first composite synchronizing signal output from the composite synchronizing signal separating means is input; Image signal processing means for performing processing and outputting; composite synchronizing signal forming means for forming a second composite synchronizing signal phase-synchronized with the first composite synchronizing signal separated by the composite synchronizing signal separating means; Composite synchronizing signal adding means for adding and outputting the second composite synchronizing signal formed by the composite synchronizing signal forming means to the image signal subjected to image processing by the signal processing means; The image signal to which the second composite synchronizing signal is added which is output from the signal adding means is obtained by including a skew compensation processing means for performing a skew compensation process.

[Action]

With the configuration described above, a composite synchronization signal without deterioration can be output together with the image signal, and skew compensation processing is performed on the image signal that has been subjected to the image signal processing while maintaining the continuity of the horizontal synchronization signal. Things become possible.

〔Example〕

 Hereinafter, the present invention will be described using examples of the present invention.

FIG. 1 is a diagram showing, as an embodiment of the present invention, a schematic configuration of a still video reproducing apparatus which handles a still image signal conforming to an NTSC television signal. In FIG. 1, the same components as those in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the embodiment shown in FIG. 1, the magnetic disk 100 rotated by the motor 101 is the same as the conventional example shown in FIG.
The signal reproduced by the magnetic head 102 is amplified by the reproduction amplifier 103, and the amplified reproduction signal is demodulated by the demodulation circuit 104.
, And supplied to the synchronization signal separation circuit 105 and the image signal processing circuit 110.

The synchronization signal separation circuit 105 separates the composite synchronization signal (Csync) from the signal supplied from the demodulation circuit 104, and the separated Csync is supplied to the timing signal generation circuit 115.

As described above, in the present embodiment, Csync separated by the synchronization signal separation circuit 105 as in the conventional example shown in FIG. 6 is added to the image signal supplied from the image signal processing circuit 110 in the synchronization signal addition circuit 111 described later. Instead of adding, Csync formed in the timing signal generation circuit 115 is added.

FIG. 2 is a diagram showing a configuration example of the timing signal generation circuit 115 of FIG.

2, reference numeral 1 denotes an input terminal of a composite synchronizing signal (Csync) reproduced from the magnetic disk 100 shown in FIG. 1, and Csync (see FIG. 3) inputted from the input terminal 1 is a comparator 6, which will be described later, It is supplied to the synchronization signal detection circuit 8.

On the other hand, a clock pulse having a color subcarrier frequency (3.58 MHz) is generated from the reference clock generator 2 and supplied to a clock pulse input terminal CK _H of a horizontal synchronization counter (H counter) 3.

The H counter 3 counts the number of clock pulses input from the clock input terminal CK _H and supplies the count value data (see FIG. 3) to the H decoder 4.

The H decoder 4 sets the levels of the output signals D0 to D6 to high level or low level according to the value of the count value data supplied from the H counter 3, and supplies the output signals D0 to D6 to the data selector 5.

Incidentally, when the count value data supplied from the H counter 3 indicates "226-16 = 210", the H decoder 4 in FIG.
When the output signal is set to D0 high level and the count value data indicates "226-4 = 222", the output signal D1 is set to high level and when the count value data indicates "226-1 = 225", the output is performed. When the signal D2 is at a high level and the count value data indicates “226 + 16 = 242”, the output signal D3 is at a high level. When the count value data indicates “226 + 4 = 230”, the output signal D4 is at a high level. When the count value data indicates "226", the output signal D5 is set to high level, and when the count value data indicates "113", the output signal D6 is set to high level and the count value data indicates "50". , The output signal H _REF (see FIG. 3) is set to a high level.

The data selector 5 responds to select signals S0 to S2 output from the controller 7 to be described later,
The H counter 3 is reset by outputting any one of the signals D0 to D6 supplied thereto and supplied to a reset terminal _RH of the H counter 3, and a vertical synchronization counter (V counter) to be described later. It is supplied to 10 output terminals CK _V.

On the other hand, the output signal H _REF of the H decoder 4 is
The comparator 6 detects the phase difference between the H _REF and Csync supplied from the input terminal 1, and sets the levels of the output signals C0 to C3 to high level or low level according to the phase difference, It is supplied to the controller 7.

That is, the comparator 6 is set to the high level output signal C1 in the case where the phase of the Csync is ahead H _REF, if the delay is set to low level.

The comparator 6 respectively the level of the output signal C0, C2, C3 in accordance with the amount of phase difference between the Csync and H _REF supplied s,
It is set to high level or low level,
The phase difference between the Csync and H _REF is in terms of the number of clock pulses output from the reference clock generator 2, in the case where 8 or more clock component to the output signal C0 to the high level, 4
If it is for 8 clocks, the output signal C2 is at a high level. If it is for 0 to 4 clocks, the output signal C3 is at a high level. The levels of these output signals C0 to C3 are held for one horizontal synchronization period. It is like.

By the way, Csync (see FIG. 4) inputted from the input terminal 1 is also supplied to the vertical synchronizing signal detecting circuit 8 as described above, and the vertical synchronizing signal detecting circuit 8 The vertical synchronization blanking period (b in FIG. 4) is detected.

That is, as shown in FIG. 4, the vertical synchronizing blanking period (b in FIG. 4) is performed during the horizontal synchronizing blanking period (the fourth synchronizing blanking period).
Since the low-level period is longer than a) in the figure, the vertical synchronization signal detection circuit 8 counts the period in which the level of the supplied Csync is low, and the count value is the horizontal synchronization blanking period (FIG. 4). If the period is longer than a), the output signal is set to the high level and supplied to the delay circuit 9 at the subsequent stage.

The delay circuit 9 (the H 1 horizontal synchronizing period) the number H of the output signal of the vertical sync signal detection circuit 8 delays, is supplied to the reset terminal R _V of the vertical synchronization counter (V counter) 10, V counter 10 delay circuits 9 is reset during a high level period.

By the way, an equalizing pulse is added to Csync inputted from the input terminal 1, and a different timing signal from the other periods is set to H during the equalizing pulse period (c in FIG. 4) during Csync. Based on the count value data of the counter 3 and the V counter 10, the vertical synchronization signal detecting circuit 8 detects the vertical blanking period as described above and forms the Csync equalizing pulse because the H decoder 4 and the V decoder 11 form the data. If the V counter 10 is reset during the period, the continuity of the timing signal formed during the equalization pulse period may be lost. Therefore, in this embodiment, the output signal of the vertical synchronizing signal detecting circuit 8 is delayed by several H by the delay circuit 9 as described above, so that the V counter 10 is reset at a timing sufficiently delayed from the equalizing pulse period of Csync. It is configured as follows.

The output signal of the data selector 5 is supplied to the clock pulse input terminal CK _V of the V counter 10 as described above.
The V counter 10 counts the number of times the high level signal output from the data selector 5 is supplied, and outputs count value data to the V decoder 11.

When the count value data supplied from the V counter 10 reaches the number of horizontal synchronization pulses (that is, 263) within one field period, the V decoder 11 outputs the pseudo vertical synchronization signal V _REF, and outputs the V counter 10. When the supplied count value data reaches a predetermined count value, the output signal B0 is set to a high level and supplied to the controller 7.

By the way, the still video reproducing apparatus of the present embodiment
As shown in the figure, the magnetic disk 100 is rotated by a motor 101, and a still image signal for one field period is recorded on one of the recording tracks formed concentrically on the magnetic disk 100. .

Further, the motor 101 is controlled by a motor servo circuit or the like so as to rotate at a predetermined rotation speed. However, since rotation unevenness cannot be completely eliminated, a still image signal on the magnetic disk 100 is not provided. In some cases, the recording start position and the end position do not match exactly, and an unrecorded portion or an overwritten portion may occur.

In the above case, as shown at d in FIG. 4, the switching point between the recording start position and the ending position of the still image signal of Csync separated from the still image signal reproduced from the magnetic disk 100, that is, the switch. not gone 1H is the period of the horizontal synchronizing signal at the position corresponding to the ring points, the phase difference between the Csync and H _REF in this portion is increased.

Therefore, in the V decoder 11 of the present embodiment, when the count value data supplied from the V counter 10 corresponds to the count value corresponding to the vicinity of the switching point in Csync (a period of several H), the output signal B1 is set to the high level. And supplies it to the controller 8.

Hereinafter, the controller 7 in the embodiment shown in FIG.
The signal input / output operation will be described with reference to the operation flowchart of FIG.

In FIG. 2, H _REF output from Csync and H decoder 4 that is input from the input terminal 1 is fed to a comparator 6, where the phase difference between two signals is detected, is detected from the comparator 6 Signal C0-
C3 is supplied to the controller 8 (Fig. 5 step ST ₁
reference).

On the other hand, the V counter 10 counts the output signal of the data selector 5 and outputs count value data corresponding to the count value to the V decoder 11.
When the count value data supplied from 10 reaches a predetermined count value, the output signals B0 and B1 are set to a high level. When the V counter counts "262", the output signal is output from the V decoder 11. B0 goes high, and the controller 7 sends S0: 1, S1: 1, S
A 2: 1 select signal is output, and the data selector 5 selectively outputs the output signal D6 output from the H decoder 4 when the H counter 3 counts "113", resets the H counter 3 and simultaneously outputs the V counter 11 Is counted up.

By the above operation, for example, when the composite synchronizing signal to be handled conforms to the television signal of the NTSC system, since the one field period is "262.5H", the H counter 3 is set to the normal 1H period (reference clock generation). H _REF output from the H decoder 4 is terminated at the end of one field period in order to reset it in a half period (i.e., 113 clocks) with respect to the number of clock pulses output from the decoder 2 in 226 clocks. Even in the part, it will be possible to synchronize with Csync.

When the V counter 10 counts the count value corresponding to the vicinity of the switching point of Csync, the V counter 10
B1 output from 11 is at a high level, the controller 7 to the data selector 5 regardless of the signal C0~C3 corresponding to a phase difference between the Csync and H _REF output from the comparator 6 S0: 0, S1 : 1, S2: 0 and S0: 1, S1: 0, S2: 1 are alternately output every 1H period, and the data selector 5 outputs when the H counter 3 counts “225” or “226”. The output signals D2 and D5 output from the H decoder 4 are alternately selected and output every 1H period, and the H counter 3 is reset and V
The counter 10 is counted up (step ST in FIG. 5).
_{5 to} ST ₇ ).

By the above operation, the H _REF output from the H decoder 4 can be synchronized with the Csync at the position corresponding to the switching point on the magnetic disk 100 in FIG.

Then, the controller 7 in the case of B0 and B1 are both low level is outputted from the V decoder 11, (or delayed or fast) direction of the phase shift of the Csync and H _REF from the comparator 6 and in accordance with the amount of phase difference output Select signals S0 to S2 corresponding to C0 to C3 to be output.

First, the comparator 6, if it in terms of the number of clock pulses to the phase difference amount between Csync and H _REF is outputted from the reference clock generator 2 is 0-4 clock component is detected C0, C2 Is low level, C3 is high level, and when the phase of Csync is ahead of H _REF , C
1 becomes high level, the controller 7 outputs select signals S0: 0, S1: 1, S2: 0 to the data selector 5,
Data selector 5 selects and outputs an output signal D2 output from the H decoder 4 when counting is H counter 3 "225", also, C1 becomes a low level when the phase of Csync is delayed from H _REF The controller 7 outputs select signals S0: 1, S1: 0, S2: 1 to the data selector 5, and the data selector 5 is output from the H decoder 4 when the H counter 3 counts "226". select an output signal D5, the V counter 10 is counted up-as well as resetting the H counter 3 (Fig. 5 step ST ₈ ~ST
₁₄ ).

The H counter 3 is driven by the signal D2 or D5 output from the data selector 5 by the above-described operation to reset the H counter 3 for one clock with respect to a normal reset period (226 clocks converted into the number of clock pulses output from the reference clock generator 2). Since the reset is performed at a shorter timing, the H _REF output from the H decoder 4 can be brought closer to the phase of Csync and synchronized.

Then, if it is 4 to 8 clock component in terms of the number of clock pulses to the phase difference amount between Csync and H _REF is outputted from the reference clock generator 2 in the comparator 6 is detected C0 is low , C2 goes high, further phase of Csync is C1 becomes a high level when the leads the H _REF, the controller 7 to the data selector 5 S0: 1, S1: 0 , S2: 0 select signal And the data selector 5 outputs H when the H counter 3 counts “222”.
Select output signal D1 output from the decoder 4 and C1 becomes the low level when the phase of Csync is delayed from H _REF, the controller 7 to the data selector 5 S0: 0, S1: 0 , S2: 1 is output, and the data selector 5 outputs H when the H counter 3 counts “230”.
The output signal D4 output from the decoder 4 is selected and output.
The counter 3 as well as reset to count the UP and the V counter 10 (see FIG. 5 step _{ST 8, ST 9, ST 15} ~ST 19).

By the above-described operation, the H counter 3 is reset by the signal D1 or D4 output from the data selector 5 for the normal reset period (226 clocks converted into the number of clock pulses output from the reference clock generator 2). Since the reset is performed at a timing short or long by the clock, the H _REF output from the H decoder 4 can be brought close to the phase of Csync and synchronized.

Further C0 when a phase difference amount that is the reference clock generator 2 8 clock or partial in terms of the number of clock pulses output from is detected between Csync and H _REF in the comparator 6 becomes a high level.

In the present embodiment, Csync and H _REF
If it is detected that the phase difference amount from the clock pulse output from the reference clock generator 2 is equal to or more than 8 clocks, noise may be mixed into Csync, or dropout may occur. I assume that you are.

And if the phase of Csync is ahead of H _REF , C
1 becomes high level, the controller 7 outputs select signals S0: 0, S1: 0, S2: 0 to the data selector 5,
Data selector 5 the output signal D0 output from the H decoder 4 selects the output when counting is H counter 3 "210", and when the phase of Csync lags H _REF is C
1 becomes low level, the controller 7 outputs select signals S0: 1, S1: 1, S2: 0 to the data selector 5,
The data selector 5 selectively outputs the output signal D3 output from the H decoder 4 when the H counter 3 counts "242", resets the H counter 3, and outputs the V counter 11
Thereby counting up-(Fig. 5 step ST _8, ST ₂₀ ~ST
₂₄ ).

Even if Csync becomes abnormal due to the above-described operation, the H counter 3 receives the signal D5 output from the data selector 5 so that the normal reset period (226 clocks converted into the number of clock pulses output from the reference clock generator 2) is obtained. ), The self-running state is established, and if the abnormal state continues for 3H, the H counter 3 is reset by the signal D0 or D3 output from the data selector 5 in the normal reset cycle (reference clock generator). in terms of the number of clock pulses output from 2 226 clock minute) for resetting in 16 clock minute shorter or longer time with respect to, Csync the H _REF output from the H decoder 4
And it can be synchronized.

Incidentally, the operation described above in the data selector 5, when the one signal among D0~D6 outputted from H decoder 4 is output, again returns to step ST ₁ of FIG. 4, the comparator 6 phase comparison between Csync and H _REF is performed in, so that the above-described operation is repeated.

Then, it is generated by the H decoder 4 as described above.
V _REF generated from H _REF and V decoder 11 is supplied to the timing signal generator 12, H _REF supplied the timing signal generator 12 as a trigger pulse of V _REF, preset composite synchronizing signal (Csync) A blanking signal B and a skew compensation gate signal S having the specified pulse width are formed and output.

Then, the formed blanking signal B is sent to the image signal processing circuit 110, and the composite synchronization signal Csync is sent to the synchronization signal adding circuit 11
The skew compensation gate signal S is supplied to the switching switch 113.

The image signal processing circuit 110 is based on the blanking signal B supplied from the timing signal generation circuit 115, and
Horizontal and vertical blanking processing is performed on the image signal supplied from 4, and the synchronization signal adding circuit 111 applies the one-field image signal subjected to the blanking processing in the preceding image signal processing circuit 110 to the above-described image signal. The composite synchronizing signal Csync formed in the timing signal generation circuit 115 is added and supplied to the 1 / 2H delay circuit 112 and the terminal a of the switching switch 113. The 1 / 2H delay circuit 112 converts the supplied image signal into 1 / Two
After a delay of H period, the signal is supplied to the terminal b of the switching switch 113.

The switching switch 113 receives the skew compensation gate signal S generated in the timing signal generation circuit 115.
Accordingly, the connection is alternately switched between the terminal a side and the terminal b side in the figure every one field period, so that the switching switch 113 outputs a frame image signal through the output terminal 114.

As described above, in the present embodiment, instead of adding the composite synchronization signal separated from the image signal reproduced from the magnetic disk to the reproduction image signal subjected to the skew compensation processing, the reproduction image signal After forming a composite synchronization signal phase-synchronized with the composite synchronization signal separated from the signal, forming a skew compensation gate signal for controlling the skew compensation process, and adding the formed composite synchronization signal to the reproduced image signal. By performing skew compensation processing on the reproduced image signal to which the formed composite synchronization signal is added based on the skew compensation gate signal, the continuity of the horizontal synchronization signal at the boundary point of each field is improved. This makes it possible to maintain and prevent the deterioration of the composite synchronization signal.

Even when the Csync changes, the phase of the reproduction timing signal is not instantaneously corrected, but is corrected by a predetermined amount, so that stable reproduction can be performed without being disturbed by disturbance such as noise. A timing signal can be obtained.

Further, since the circuit configuration is digitalized as shown in this embodiment, no adjustment or the like is required, and a stable performance can be obtained with respect to environmental changes such as temperature and humidity. Because it is small, it can be easily integrated into an IC,
The number of parts can be reduced.

In the present embodiment, a still video playback apparatus that handles a still image signal based on an NTSC television signal has been described as an example. However, the present invention is not limited to this, and a PAL / SECAM television signal can be used. In the case of an apparatus conforming to the standard, the length of one horizontal synchronization period and the length of one vertical synchronization period, that is, the H counter of FIG. 3. The timing for resetting the V counter 10 may be changed.

〔The invention's effect〕

As described above, according to the present invention, a composite synchronization signal without deterioration can be output together with an image signal, and the continuity of the horizontal synchronization signal is applied to the image signal subjected to the image signal processing. It is possible to provide an image signal processing device capable of performing the skew compensation processing while maintaining the image signal.

[Brief description of the drawings]

FIG. 1 is a diagram showing, as an embodiment of the present invention, a schematic configuration of a still video reproducing apparatus which handles a still image signal conforming to an NTSC television signal. FIG. 2 is a diagram showing a configuration example of the timing signal generation circuit of FIG. FIGS. 3 and 4 are timing charts showing signal waveforms at various parts of the timing signal generating circuit shown in FIG. FIG. 5 is an operation flowchart for explaining the operation of the timing signal generation circuit shown in FIG. FIG. 6 is a diagram showing a schematic configuration of a conventional still video reproducing apparatus. 1 ... Compound synchronization signal input terminal 2 ... Reference clock generator 3 ... Horizontal synchronization counter 4 ... H decoder 5 ... Data selector 6 ... Comparator 7 ... Controller 8 ... Vertical synchronization signal detection circuit 9 ... Delay circuit 10 Vertical sync counter 11 V decoder 12 Timing signal generator

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 5/91-5/956

Claims (1)

(57) [Claims] An apparatus for inputting an image signal and processing the input image signal, comprising: separating a first composite synchronization signal added to the image signal from the input image signal; A composite synchronizing signal separating / separating means, and an image signal from which the first composite synchronizing signal output from the composite synchronizing signal separating means is input, and performs image signal processing on the input image signal; Image signal processing means for outputting; composite synchronizing signal forming means for forming a second composite synchronizing signal phase-synchronized with the first composite synchronizing signal separated by the composite synchronizing signal separating means; Composite synchronizing signal adding means for adding and outputting the second composite synchronizing signal formed by the composite synchronizing signal forming means to the image signal on which image processing has been performed; The image signal to which the second composite synchronizing signal is added to be more outputted, the image signal processing apparatus characterized by comprising a skew compensation processing means for performing a skew compensation process.