JP2003337764A - Information processing device, data transferring method for the same, program, and storage medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent overlapping data transfer on the extension bus side after occurrence of an error in data transfer between a main memory and a hard disk for smoothly transferring data again. <P>SOLUTION: A backup SRAM 114 is newly arranged in a hard disk controller 110, and when data stored in a RAM 102 are transferred to an HDD 111 via an FIFO 113, the same data as those in the FIFO 113 are temporarily stored in the SRAM 114. If the data are transferred normally, the data stored in the FIFO 113 are transferred to the HDD 111. When the data transfer is carried out again as the data transfer is not finished normally and interrupted, an input to an ATA I/F 116 is switched by a selector 115 so that the data backed up in the SRAM 114 are transferred to the HDD 111. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to SRAM, DRAM, or SD inside a computer or office equipment.
Information processing apparatus and information processing apparatus capable of transferring data between a main memory, which is a volatile storage medium such as RAM and RDRAM, and a non-volatile recording medium such as a large-capacity hard disk used as secondary storage The present invention relates to a control method, a program, and a storage medium.

[0002]

2. Description of the Related Art In a personal computer, program data stored in a hard disk device
BACKGROUND ART Transferring data to a volatile main memory, which is a semiconductor memory, and storing calculation results and temporarily unnecessary data in a non-volatile memory such as a hard disk have been performed.

In addition, a copying machine, an MFP (Multi F
In office equipment such as unction peripherals, facsimile machines, and multi-function copiers, data such as images is stored in a volatile memory, and after image processing is performed, the data is transferred to a hard disk device and stored, and then stored in a printer or the like. When transferring to a recording medium such as paper for output, or when transferring to other office equipment or a personal computer via a network, etc., the image data is also read from the hard disk device etc. into the main memory and re-imported to the network interface etc. Transferring is taking place.

The hard disk controller is a DMA
(Direct Memory Access) controller is built in, and ATA (AT Attachm)
ent; official name of IDE) and DMA transfer between the main memories via the I / F according to the standard such as SCSI.
Further, a hard disk controller is mounted on a general-purpose bus, and DMA transfer between a main memory and a hard disk device is also performed via a DMA controller and a FIFO incorporated in the hard disk controller.

Further, the hard disk controller is
It may be connected to an I / O bus or the like for connecting an I / O controller instead of the bus to which the main memory is connected, and via the bus to which the main memory is connected and the I / O bus. When data is transferred, latency time (waiting time) etc. required for data transfer increases,
A FIFO for temporary storage for prefetching data between the main memory and the hard disk, and this FIFO
A DMA controller for performing DMA transfer between O and main memory is provided, and a FIFO and DMA for this temporary storage
Transferring is performed via the controller.

The configuration of the data transfer system in this type of information processing apparatus (office equipment such as personal computer, copying machine, and MFP) will be described below with reference to FIG.

FIG. 8 is a block diagram showing the configuration of a data transfer system in a conventional information processing apparatus.

In the figure, 101 is a CPU for controlling the entire system, which is activated according to a program stored in the ROM 103, and operates by sequentially reading application programs.

The ROM 103 also stores driver software for operating a hard disk device, which will be described later, and is read and executed by the CPU 101 as needed. 102 is a RAM such as SRAM or DRAM
The CPU 101 temporarily stores necessary data here and performs arithmetic processing. It also transfers data to and from a hard disk device described later.

Reference numeral 104 denotes a local bus, which is the CPU 101,
It is for connecting the ROM 103 and the RAM 102. The first bus bridge 105 is a local bus 10
4 and the I / O bus 106 are bridged. The I / O bus 106 is a bus for connecting an I / O controller and is independent of the local bus 104. Therefore, during data transfer between the I / O controllers, the CPU 101 causes the RAM 102 and the ROM 10 to operate.
3 access can be made.

Reference numeral 107 denotes a network interface controller (Network) connected to the I / O bus 106.
rk I / F) for connecting to another host computer or the like via a network.

Reference numeral 108 is a second bus bridge for bridging the I / O bus 106 and the expansion bus 109. The expansion bus 109 is provided to further expand the I / O controller to the system.

110 is a hard disk controller,
A controller for connecting the hard disk device (HDD) 111 and the expansion bus 109.

Next, the hard disk controller 110
The configuration of will be described.

In the hard disk controller 110, 112 is a DMA controller, which is a hard disk device 111 and a RAM 102 via an expansion bus 109.
This is for performing a DMA transfer between them. Next, 11
A FIFO 3 is for temporarily storing transfer data when the DMAC 112 performs DMA transfer.

Reference numeral 116 denotes an ATA interface controller (ATA I / F), which is a hard disk device 111.
And data transfer (control of data input / output of the hard disk device 111), and data transfer is performed according to the ATA standard.

Reference numeral 117 is a register (Registers)
Is for the CPU 101 to read or write for data setting when operating the DMAC 112, and is used for setting parameters for operating the DMAC 112 and determining the status of the DMAC 112. Is.

<Operation at Data Transfer from RAM 102 to Hard Disk Device 111> RAM 102
The operation when data is transferred from the hard disk device 111 to the hard disk device 111 will be briefly described.

First, when the hard disk device 111 is ready to transfer data, the CPU 101 stores the head sector of the hard disk for transferring data to the hard disk device 111 and the total number of sectors to be transferred in the register of the hard disk device 111. Setting is performed, and activation is performed by writing a read or write command to the hard disk device 111.

After the startup of the hard disk device 111, the CPU 101 next sets the data transfer direction to the register 117 and transfers the data to the RAM 1
The start address of 02 and the total number of data to be transferred are set, and the DMAC 112 is activated. D was activated
The MAC 112 reads data from the RAM 102,
Data is sequentially written into the FIFO 113.

The activated hard disk device 111 outputs a data transfer request to the hard disk controller 110 in accordance with the ATA standard.
In response to this, the ATA interface controller 11
6 reads the data from the FIFO 113 and transfers the data to the hard disk device 111 according to the ATA standard.

In this way, data is sequentially transferred to the hard disk device 111 using the DMAC 112,
Data is written in the magnetic substance inside the hard disk device 111. When the data transfer is completed normally, the hard disk device 111 and the DMAC1
A termination interrupt is output from 02, and the CPU 101 is notified.

<Hard disk device 111 to RA
Operation at the time of data transfer to M102> Next, the data stored in the hard disk device 111 is transferred to the RAM10.
2 A brief description will be given of the operation when transferring data to the inside.

The operation up to the startup of the hard disk device 111 is the same as the above-described data transfer operation to the hard disk device 111, and therefore will be omitted.

The activated hard disk device 111 reads data from the internal magnetic material,
Data is started to be written in the hard disk controller 110 in accordance with the standard. The ATA interface controller 116 receives data from the hard disk device 111 and transfers it to the FIFO 113.

After the hard disk device 111 has been started up, the CPU 101 sets the data transfer direction to the register 117 and transfers the data to the RAM.
The start address of 102, the total number of data to be transferred, and the like are set, and the DMAC 112 is activated.

The activated DMAC 112 is FI
Data is sequentially read from the FO 113 and written in the RAM 102. When the data transfer is completed normally, the hard disk device 111 and the DMAC 10
An end interrupt is output from 2 and the CPU 101 is notified.

[0028]

However, the above-mentioned conventional data transfer system has the following problems.

The transfer unit for writing or reading to or from the hard disk device is a sector unit, and transfer is performed in units of several hundreds of sectors at the maximum, that is, several hundreds of kBytes.
Therefore, if the data transfer is interrupted midway, it is necessary to transfer all the data of several hundred kBytes again, and it is inefficient to transfer all the data between the main memory and the hard disk again. there were.

Further, as shown in FIG. 8, the hard disk controller 110 includes a main memory (RAM 10).
I) instead of the local bus 104 to which 2) is connected
I / O bus 106 for connecting an I / O controller
And an expansion bus 109, and a FIFO 113 for prefetching data between the RAM 102 and the hard disk device 111, and this FIFO 113 and RA
When the DMA controller 112 for performing the DMA transfer between the M102 is provided and the transfer is performed via the FIFO 113 and the DMA controller 112, when the data transfer is interrupted, not only the restart of the hard disk device 111 but also the DMA controller 112 is performed. There was also a problem that it was necessary to restart, and it was not possible to transfer data again smoothly.

The present invention has been made to solve the above problems, and an object of the present invention is to store data stored in a volatile storage medium (hereinafter referred to as main memory) such as a main memory. A storage medium such as FIFO for temporary storage (hereinafter,
When data is transferred to a non-volatile storage medium (hereinafter, hard disk) such as a hard disk via a FIFO and a DMA controller, the same data as the data stored in the FIFO is temporarily stored in a storage medium such as SRAM (hereinafter, SRA).
M) is backed up and stored, and when data transfer is normally performed, the data stored in the FIFO is transferred to the hard disk, the data transfer is interrupted without being normally completed, and data transfer is performed again. If you do
The input to the hard disk I / F is controlled so that the data backed up in the RAM is transferred to the hard disk, and when the data is transferred from the hard disk to the main memory, the transfer to the main memory is completed by the DMA controller. When the number of different data lengths is counted and the data is transferred from the hard disk to the main memory, the data transfer is not normally completed and is interrupted and the data is transferred again, the data is read from the hard disk. Of the data, the data for the counted length number is discarded without being input to the FIFO, and the data after the counted length number is input to the FIFO to continue the data transfer to the main memory. By controlling the main memory and hard disk device After the data transfer is interrupted or the like,
An object of the present invention is to provide an information processing device capable of high-speed retransfer, a data transfer method of the information processing device, a program, and a storage medium.

[0032]

A first invention according to the present invention has volatile storage means (RAM 102 shown in FIG. 1) and non-volatile storage means (HDD 111 shown in FIG. 1),
In an information processing device that performs data transfer for writing data stored in the volatile storage means to the non-volatile storage means and data transfer for reading data stored in the non-volatile storage means to the volatile storage means, First storage means (FIF shown in FIG. 1) for temporarily storing data between the volatile storage means and the non-volatile storage means.
O113), a DMA controller (DMAC 112 shown in FIG. 1) for DMA-transferring data between the volatile storage means and the first storage means, and an interface means for controlling input / output to / from the nonvolatile storage means. (ATAI / F 116 shown in FIG. 1), and when transferring the data stored in the volatile storage means to the nonvolatile storage means, the same data as the data stored in the first storage means Second storage means (SRAM 114 shown in FIG. 1) that temporarily stores backup data, and when data is normally transferred from the volatile storage means to the non-volatile storage means. When the data stored in the first storage means is transferred to the non-volatile storage means, the data transfer is interrupted without normally ending, and the data transfer is performed again, It has a switching control means (CPU 101 switches the selector 115) for switching the input source to the interface means so that the data backed up in the second storage means is transferred to the nonvolatile storage means. To do.

A second invention according to the present invention is the length number of data which has been transferred to the volatile storage means by the DMA controller when the data is transferred from the nonvolatile storage means to the volatile storage means. Counting means for counting (the DMAC 112, the register 11 shown in FIG.
7) and, when transferring data from the non-volatile storage means to the volatile storage means, if the data transfer is not normally completed and is interrupted and data is transferred again, the non-volatile storage is performed by the interface means. Of the data read from the means, the data for the number of lengths counted by the counting means is discarded without being input to the first storage means, and the data after the number of lengths counted by the counting means is discarded. Length control means (length controller 11 shown in FIG. 1) for inputting data into the first storage means and controlling to continue data transfer.
8) and are included.

A third invention according to the present invention is a data transfer amount control means for determining a transfer amount of data to be transferred at a time to the non-volatile storage means in accordance with the capacity of the second storage means ( It has a CPU 101) shown in FIG.

According to a fourth aspect of the present invention, when the data transfer is not normally completed and the data is transferred again, the switching control means, the counting means, and the length control means are used to duplicate the data bus. First to prevent transfer on
And a second retransfer mode in which all data is transferred between the volatile storage means and the non-volatile storage means without using the switching control means, the counting means, and the length control means. It is characterized by having a selectable retransfer mode selecting means (a host computer or the like capable of passing a sheet through an operation unit (not shown) or a network).

In a fifth aspect of the present invention, the DMA controller continuously transfers data from a plurality of discrete blocks of the volatile storage means to the first storage means and the second storage means. In addition, the transfer address control means (the DMAC 112 shown in FIG. 1 is set by the CPU 101 to enable the data stored in the first storage means to be transferred to a plurality of discrete blocks of the volatile storage means. “DMA Table Are shown in FIG.
a) is used to control the transfer address).

A sixth invention according to the present invention is a third storage means (second storage means shown in FIG. 4) for temporarily storing data between the volatile storage means and the first storage means. F
IFO 402) and a second DMA controller (second DMAC 401 shown in FIG. 4) for performing DMA transfer between the third storage means and the volatile storage means, and the DMA controller is Data is DMA-transferred between the third storage means and the first storage means.

A seventh invention according to the present invention is the above-mentioned second D.
An MA controller continuously transfers data from the plurality of discrete blocks of the volatile storage means to the third storage means, and further stores the data stored in the third storage means by the volatile storage means. Transfer address control means that enables transfer to a plurality of discrete blocks (see FIG. 4).
"DMA Table Area 2" shown in FIG. 6 in which the second DMAC 401 shown in FIG.
Is used to control the transfer address).

In an eighth aspect of the present invention, the volatile storage means is SRAM or DRAM (RAM1 shown in FIG. 1).
02), and the non-volatile storage means includes a hard disk (the HDD 111 shown in FIG. 1).

In a ninth aspect of the present invention, the nonvolatile storage means is used at the time of image data transfer and image output in which the image data input and stored in the volatile storage means is written in the nonvolatile storage means. An image processing device (image forming apparatus (not shown) such as a copying machine or an MFP (Mula), which transfers image data stored in the
Ti Function Peripheral), a facsimile machine, a compound copier, etc.).

The tenth invention of the present invention is the first invention for temporarily storing data between a volatile storage means, a non-volatile storage means, and the volatile storage means and the non-volatile storage means. The volatile storage means, a DMA controller for DMA-transferring data between the volatile storage means and the first storage means, and an interface means for controlling input / output to / from the nonvolatile storage means. Data transfer method for writing data stored in the non-volatile storage means to the non-volatile storage means and data transfer for reading the data stored in the non-volatile storage means to the volatile storage means In the above, when the data stored in the volatile storage means is transferred to the non-volatile storage means, the same data as the data stored in the first storage means. Temporarily second storage means backup backup storage to steps (not shown step),
When data is transferred normally from the volatile storage means to the non-volatile storage means, the data stored in the first storage means is transferred to the non-volatile storage means. When the data is transferred, the data transfer is not normally completed and is interrupted, and the data is transferred again, the data backed up in the second storage means is transferred to the non-volatile storage means. It is characterized by including a switching step (step S212 shown in FIGS. 2 and 5) for switching the input source.

An eleventh aspect of the present invention is the length number of data which has been transferred to the volatile storage means by the DMA controller when the data is transferred from the nonvolatile storage means to the volatile storage means. And a counting step (not shown) and when transferring data from the non-volatile storage means to the volatile storage means when the data transfer is not normally completed and is interrupted and data is transferred again, Of the data read from the non-volatile storage means by the interface means, the data for the number of lengths counted in the counting step is discarded without being input to the first storage means, and the data in the counting step is discarded. A line for controlling to input the data after the counted number of lengths to the first storage means and to continue the data transfer. And having a scan control step (not shown step).

The twelfth invention of the present invention is the tenth aspect.
Alternatively, the program is a program for executing the data transfer method of the information processing apparatus described in item 11.

The thirteenth invention of the present invention is the tenth aspect.
Alternatively, the program for executing the data transfer method of the information processing apparatus described in 11 is stored in a computer-readable storage medium.

[0045]

BEST MODE FOR CARRYING OUT THE INVENTION The configuration of a data transfer system in an information processing apparatus showing an embodiment of the present invention will be described in detail below with reference to the drawings.

[First Embodiment] <Structure of Data Transfer System> FIG. 1 is a block diagram showing the structure of a data transfer system in an information processing apparatus according to the first embodiment of the present invention, which is the same as FIG. The same symbols are attached to the items.

In the hard disk controller 110, 115 is a selector, which is a RAM
102 to DMAC 112 is hard disk device 1
When transferring the data to the memory 11, the DMAC 112 selects whether to transfer the data temporarily stored in the FIFO 113 to the hard disk device 111 or the data stored in the SRAM 114. The DMAC 112 switches the data. It is a thing.

Reference numeral 118 is a length controller (Leng)
(th controller), when transferring data from the hard disk device 111 to the RAM 102, the number of data read from the hard disk device 111 (the number of data lengths) is counted, and a predetermined number of data It is possible to control so that the transfer of data to the FIFO 113 is not started until the number of is counted.

An example of the first control processing procedure of the data transfer system in the information processing apparatus of the present invention will be described below with reference to FIG.

FIG. 2 is a flowchart showing an example of a first control processing procedure of the data transfer system in the information processing apparatus of the present invention, which is based on the program stored in the ROM 103 shown in FIG. 1 or another storage medium. CP
It is executed by U101 as a whole. In the figure, S2
01 to S214 indicate each step.

<Operation during Data Transfer> When performing data transfer, the CPU 101 first passes the hard disk through the hard disk controller 110 regardless of whether the data is transferred from the RAM 102 to the FIFO 113 or from the FIFO 113 to the RAM 102. The status of the device 111 is read (S201). Note that C
The PU 101 reads the register 117 built in the hard disk controller 110,
It is possible to read the status register of the hard disk device 111 via the ATA interface 116.

Next, the CPU 101 judges the value of the status register of the hard disk device 111 (S2
02), when it is determined that an error state is detected as a result of reading the status register of the hard disk device 111, the CPU 101 sets the control register of the hard disk device 111 via the register 117, and thereby the hard disk device 111
To the hard disk device 11
1 is initialized (S203), the process returns to step S201, and after the initialization is completed, the CPU 101 reads the status register of the hard disk device 111 again.

On the other hand, when it is determined in step S202 that the hard disk device 111 is ready for data transfer, the CPU 101 transfers the data to the hard disk device 111, the start sector address of the hard disk device 111, and The total number of sectors to be transferred is set in the register of the hard disk device 111 (S204). From RAM 102 to F
When data is transferred to the IFO 113, the total number of transfer sectors set in the hard disk device 111 is programmed to be smaller than the capacity of the SRAM 114 inside the hard disk controller 110.

After the setting of the hard disk device 111 is completed, the CPU 101 activates the hard disk device 11 by writing a read or write command to the hard disk device 111 (S205).

<Operation when Writing Data to Hard Disk Device 111> Next, details of transferring the data stored in the RAM 102 to the hard disk device 111 will be described.

After the hard disk device 111 has finished starting up, the CPU 101 next writes the register 117 to operate the DMAC 112, sets the data transfer direction, and sets "D" on the RAM 102 shown in FIG.
The address indicating “MA Table Area” is set, and further, the CPU 101, as shown in FIG.
"DMA Table Area" is set on M102 (S206). This "DMA Table Are
In “a”, the first Address (transfer destination Address) of the area where the data on the RAM 102 for DMA transfer is stored and the transfer length of the data are written. Further, "EOTbit" indicating that the DMA transfer is completed by this transfer is provided in the head bit on the MSB side of the portion indicating the transfer length.
If "t" is disabled, the next set of "DMA Table Area" is read after the first DMA transfer is completed, and the DMAC 112 continues the transfer. This allows the DMAC 11 to (or from) the discrete blocks on the RAM 102.
2 can continuously transfer data.

CPU which has completed the setting to the DMAC 112
Next, the 101 also performs the write operation to the register 117 to activate the DMAC 112 (S207).

DM started in step S207
The AC 112 first reads the setting contents of the register 117 set by the CPU 101 first, and reads the R content shown in FIG.
The "DMA Table Area" on the AM 102 is read.

In the present embodiment, "DATA Table"
If "Area" is described in "7000_0000h", the DMAC 112 first reads "7000_00".
00h ”is read out, and the head address where the data on the RAM 102 is stored is read out. In this embodiment, it is temporarily set to“ A000 — 0000h ”. Next, "7000_
"0004h" is read and the data length to be transferred is read. Through the above operation, the DMAC 112 reads the address from which the data should be read and the total number thereof. Then D
The MAC 112 reads data from “A000 — 0000h” and sequentially writes the data to the FIFO 113.

The DMAC 112 has a FIFO 113.
At the same time that the data is written to, the same data is written to the internal SRAM 114. As described above, the total transfer length of the data transferred to the hard disk at one time is S
Since it is set to be smaller than the total capacity of the RAM 114, it is possible to back up all the data transferred to the hard disk to the SRAM 114.

The hard disk device 111 activated in step S205 outputs a data transfer request to the hard disk controller 110 in accordance with the ATA standard. If the data is in the FIFO 113 inside the hard disk controller 110, the ATA interface controller 116 sends the data to the FIFO 1
The data is read from the hard disk 111 and the data is transferred to the hard disk 111 according to the ATA standard. If data has not yet been input to the FIFO 113, the hard disk device 111 is stopped so as to interrupt the transfer according to the ATA standard. Further, at this time, the selector 115 inside the hard disk controller 110 uses the FIFO.
It is controlled by the DMAC 112 so as to connect the 113 and the ATA interface controller 116.

As described above, the data is sequentially transferred to the hard disk device 111 by using the DMAC 112, and the data is written in the magnetic material inside the hard disk device 111.

When all the data have been normally transferred (that is, the data transfer is completed within a predetermined time (N in S208).
o) and when there is no internal error in the hard disk device 111 (No in S209), the hard disk device 111 and the DMAC 112 output a transfer end interrupt and send this interrupt signal to the DMA controller 110.
When the OR is internally performed and the signal is re-output as an interrupt signal to the CPU 101, and the CPU 101 detects the end of the transfer, the data transfer operation is ended.

However, it is possible that some error (Error) occurs inside the hard disk device 111 during the transfer to the hard disk device 111 and the data transfer does not end normally.

As a result, the data transfer does not end within the predetermined time in step S208, or the hard disk device 111 in step S209.
When the error signal is asserted from the CPU 101 and the CPU 101 reads the status register in the hard disk device 111, and “Error bit” is set, the CPU 101 first determines the hard disk device 1
In order to recover 11 from the error state, in step S210, the hard disk device 111 is reset and the hard disk device 111 is initialized. After that, the status register of the hard disk device 111 is read and it is determined whether data transfer can be performed again (S211). At this time Err again
If the or bit is set, step S2
Returning to the process of 10, the initialization is performed again.

Then, the CPU 101 sets the register 117 and turns on the backup setting for the DMAC 112. Specifically, DM with the same settings as the previous time
A transfer is performed, but the selector 115 is switched to SRAM
DMA transfer can be performed from 114 (S21).
2).

Then, the sector address to be transferred to the hard disk and the total number of sectors to be transferred are set again (S213), the hard disk device 111 is activated (S214), and the process returns to step S208.

The hard disk device 111, which has been started up, starts data transfer from the beginning again, but the ATA interface 116, now the SRAM 1
Data is transferred from 14, and DMA is continued.

From the above, the hard disk device 11
DMAC1 even if an error occurs during data transfer to 1
12 does not need to read data to the RAM 102 again, and the local bus 104 and the I / O bus 10
6. Since the expansion bus 109 is not used, the data transfer to the hard disk device 111 can be continued without reducing the operation speed of other I / O controllers and the CPU 101.

<Operation When Reading Data from Hard Disk Device 111> Next, referring to FIG. 2, the data stored in the hard disk device 111 is stored in the RAM.
Details of the transfer to the inside of the device 102 will be described.

In the flowchart of FIG. 2, the operation of the CPU 101 from step S201 to step S207 has been described above, and will be omitted. However, step S206
The data transfer direction and the like set in the register 117 is the data transfer direction from the hard disk device 111 to the RAM 102.

The hard disk device 111 activated in step S205 reads data from the magnetic material inside the hard disk and starts writing the data to the hard disk controller 110 in accordance with the ATA standard. The ATA interface controller 116 inside the hard disk controller 110 receives the data from the hard disk device 111, and since the selector 115 selects the FIFO 113, the data is further transferred to the FIFO 113.

If all the areas of the FIFO 113 are full and the data transfer cannot be continued any more, the ATA interface controller 116 is set to the ATA interface controller 116.
The DMA 113 is requested to be interrupted according to the sequence defined in the standard, the DMA transfer is temporarily stopped, and the FIFO 113
After the empty area is created, the DMA interruption is canceled again according to the sequence defined in the ATA standard, and the data transfer from the hard disk is continued.

The DMAC 112 activated in step S207 first reads the setting contents of the register 117 set by the CPU 101 first, and then reads "DMA Table Area" on the RAM 102 shown in FIG.
By reading "a", the DMAC 112 reads Address (transfer destination address) to which data is to be transferred and the total number (transfer length) thereof. Next, the DMAC 112 sequentially reads the data from the FIFO 113 and writes it in the RAM 102. Further, the DMAC 112 is the expansion bus 10
The number of data that has been transferred to 9 is counted in the register 117.

When the data transfer is normally completed (that is, the data transfer is completed within a predetermined time (No in S208) and there is no internal error in the hard disk device 111 (No in S209)), the hard disk device 111 is detected. And the end interrupt is output from the DMAC 102 and is notified to the CPU 101.
02, the data transfer does not end within the predetermined time in step S208, or an interrupt signal is asserted from the hard disk in step S209, and the CPU 101 causes the hard disk device 11 to transfer data.
1 When reading the internal status register, “Err
If "orbit" is set, CPU1 is still
01 initializes the hard disk device 111 to cancel the error according to the flowchart of steps S210 to S214 in FIG. 2 (S210, S211), and D
The backup operation is turned on for the MAC 112 (S212). As a result, the DMAC 112 sets the number of pieces of data normally transferred in the previous DMA stored in the register 117 in the length controller 118, and the length controller 118 receives the data from the ATA interface controller 116 as the selector 115.
Even if the data is transferred to, the selector 115 discards only the number of data set in the length controller 118.

The transfer start sector address and the number of sectors are designated for the hard disk device 111 (S213), and the hard disk drive 111 is restarted (S214).
Data retransfer is started, and the process returns to step S208.

Data retransfer is started, and data is transferred from the hard disk device 111 again.
As described above, according to the instruction from the DMAC 112, the number of pieces of data normally transferred in the previous DMA stored in the register 117 is determined by the length controller 11 first.
Set to 8. The length controller 118 is an AT
Even if data is transferred from the A interface controller 116 to the selector 115, the length controller 11
The selector 115 is controlled so that the selector 115 discards only the number of data set to 8.

After that, when the length controller 118 finishes counting the number of data set and the selector 115 discards the data transferred to the expansion bus 109 in the previous DMA, the selector 115 causes the ATA interface controller 116 to stop. FIF the received data
Then, the DMAC 112 continues the data transfer to the RAM 102.

As described above, when transferring data from the hard disk device 111 to the RAM 102,
DM by Error of hard disk device 111
When A transfer is interrupted and another DMA transfer is performed,
The data that was previously DMA-transferred is duplicated on the expansion bus 109,
By not transferring to the I / O bus 106 or the local bus 104, another I / O controller or CPU 1
Data transfer from the hard disk device 111 to the RAM 102 can be continued without reducing the operation speed of 01.

[Second Embodiment] In the first embodiment,
The hard disk controller 110 additionally includes a backup SRAM 114 and a hard disk device 111.
A length controller 118 or the like for counting the number of data read from the RAM is provided so that the data is transferred while being stored in the SRAM 114 during the normal DMA transfer from the RAM 102, or the DMAC 112 transfers the data to the expansion bus during the DMA transfer from the hard disk device 111. The DMAC 112 transfers the transferred data while counting it by operating the register 117, and after the error occurs,
The configuration has been described in which the SRAM 114, the length controller 118, or the like is used to prevent duplicate data transfer from occurring on the expansion bus 109 side. Further, a DMA controller and a FIFO are added to the expansion bus 109 to transfer data to the hard disk device 111. It may be configured to speed up data transfer. The embodiment will be described below. The same components as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 4 is a block diagram showing an example of the overall configuration of the data transfer system in the information processing apparatus showing the second embodiment of the present invention. The same components as those in FIG. 1 are designated by the same reference numerals. is there.

In the figure, reference numeral 401 denotes a second DMA controller (second DMAC) which reads data from the RAM 102 and transfers it to the second FIF when data is transferred from the RAM 102 to the hard disk device 111.
Transfer to O402.

The DMAC 112 is a second FIFO.
It is assumed that the data is read from 402 and the data is transferred to the FIFO 113.

An example of the second control processing procedure in the data transfer system in the information processing apparatus of the present invention will be described below with reference to FIG.

FIG. 5 is a flow chart showing an example of the second control processing procedure in the data transfer system in the information processing apparatus of the present invention, which is the ROM 103 shown in FIG.
Alternatively, the program is centrally executed by the CPU 101 based on a program stored in another storage medium. In the figure, S201 to S214, S501, and S502 indicate each step. Moreover, the same step numbers are assigned to the same steps as in FIG.

In the flowchart of FIG. 5, the operation of the CPU 101 from steps S201 to S205 is the same as in the case of the above-described first embodiment, and therefore its explanation is omitted.

First, as in the first embodiment, the CPU 1
After 01 initializes the hard disk device 111, the hard disk is booted. Next CPU 10
1 indicates the setting of the data transfer direction in a register (not shown) built in the second DMAC 401 and RA shown in FIG.
An address indicating "DMA Table Area 2" on the M102 is set, and further, a "DMA Table Area" in the RAM 102 for data transfer is set.
The area "2" is set (S501). In this embodiment, unlike the first embodiment, the CPU 101 has a second
"DMAC Table Are for the DMAC 401 of
a2 ”is generated in the RAM 102 (see FIG. 6) and the second D
MAC401 is this "DMAC Table Area
2 ”to perform the operation.

Next, the CPU 101 causes the second DMAC 40
1 is activated (S502). The second DMAC 401 which has been activated is the "DMAC 401" shown in FIG.
"Table Area 2" is read out, and RAM 102 is read.
The area where the data of is stored and the transfer length are read,
Start DMA transfer.

If data is transferred from the RAM 102 to the hard disk device 111, the second DM
The AC 401 reads the data from the RAM 102 and
To the FIFO 402. When the data is transferred to all the areas of the second FIFO 402, the data transfer is interrupted, and when the data is transferred to the hard disk device 111 side and an empty area appears in the second FIFO 402, the data transfer from the RAM 102 is performed. To continue.

Next, the CPU 101 performs a write operation to the register 117 to operate the DMAC 112,
The data transfer direction is set and the address indicating “DMA Table Area” on the RAM 102 shown in FIG. 6 is set, and the “DAMC Tab Table” is set in the RAM 102.
"le Area" is set (S206) and activated (S207).

This "DAMC Table Area"
The start address (transfer destination address) of the DMA transfer indicated by is the second FIFO 40 on the expansion bus 109.
It is the address of 2, and the DMAC is activated after the DMAC 112 is activated.
The 112 reads data from the second FIFO 402 and transfers the data to the FIFO 113.

When the data transfer is normally completed (that is, the data transfer is completed within a predetermined time (No in S208) and there is no internal error in the hard disk device 111 (No in S209)), the hard disk device 111 is detected. The transfer end interrupt from the DMAC 112 is asserted, and the data transfer end interrupt is notified from the second DMAC 401 to the CPU 101, whereby the CPU 101 ends the DMA transfer operation.

On the other hand, when some error state occurs inside the hard disk device 111, that is, it is detected that the data transfer is not completed within the preset time in step S208, or the CPU 101 causes the hard disk device 111 to execute in step S209. If Error is detected at the time of reading the status, the hard disk is restarted after the initialization as in the first embodiment, and the data transfer is restarted. In addition, the backup function is turned on for the DMAC 112 and the data transfer is performed again.

In this case, the data transferred to the hard disk controller 110 is not stored in the second FIFO 402 connected to the second DMAC 401, but the data stored in the SRAM 114 by the DMAC 112 is used. Since it is possible to continue the DMA transfer, it is not necessary to restart the second DMAC 401.

As described above, by adding the second DMA controller 401 on the expansion bus 109, it becomes possible to make the DMA transfer speed efficient.
Furthermore, some Er is added to the hard disk device 111.
even if a data transfer is interrupted due to a ror,
By using the backup function using the SRAM 114 inside the DMAC controller 110, it is possible to efficiently retransfer the data.

Next, details of transferring the data stored in the hard disk device 111 to the inside of the RAM 102 will be described with reference to FIG.

In the flowchart of FIG. 5, steps S201 to S205, S501, S502, S206,
The operation of the CPU 101 up to S207 has been described above, and will be omitted. However, steps S501 and S206
The data transfer direction and the like set in step 2 are the data transfer direction from the second FIFO 402 to the RAM 102 and the data transfer direction from the hard disk device 111 to the second FIFO 402.

The hard disk device 111 activated in step S205 reads the data from the magnetic material inside the hard disk and starts writing the data to the hard disk controller 110 in accordance with the ATA standard. The ATA interface controller 116 inside the hard disk controller 110 receives the data from the hard disk device 111, and since the selector 115 selects the FIFO 113, the data is further transferred to the FIFO 113.

If all areas of the FIFO 113 are full and the data transfer cannot be continued any more, the ATA interface controller 116 will
The DMA 113 is requested to be interrupted according to the sequence defined in the standard, the DMA transfer is temporarily stopped, and the FIFO 113
After the empty area is created, the DMA interruption is canceled again according to the sequence defined in the ATA standard, and the data transfer from the hard disk is continued.

The DMAC 112 activated in step S207 first reads the setting contents of the register 117 set by the CPU 101 first, and then reads "DMA Table Area" on the RAM 102 shown in FIG.
By reading "a", the DMAC 112 reads the Address (transfer destination address) of the second FIFO 402 to which the data should be transferred and the total number (transfer length) thereof. Next, the DMAC 112 sequentially reads the data from the FIFO 113 and writes it in the second FIFO 402. Also, the number of data that the DMAC 112 has finished transferring to the expansion bus 109 is counted and stored by operating the register 117.

The second DMAC 401 activated in step S502 reads the setting contents of the register (not shown) previously set by the CPU 101, and the "DMA Table Ar" in the RAM 102 shown in FIG. 6 is read.
second DMAC 401 by reading "ea2"
Is the address of the RAM 102 to which the data should be transferred
(Transfer destination address) and its total number (transfer length) are read.
Then, the second DMAC 401 sequentially outputs the second FIFO 40.
The data is read from 2 and written in the RAM 102.

When the data transfer is normally completed (that is, the data transfer is completed within a predetermined time (No in S208) and there is no internal error in the hard disk device 111 (No in S209)), the hard disk device 111 is detected. , The DMAC 102, and the second DMAC 401 output an end interrupt and notify the CPU 101. In the same manner as in the case of data transfer from the RAM 102 to the hard disk device 111, the step S2 is performed.
If the data transfer is not completed within a predetermined time in 08, or if the interrupt signal is asserted from the hard disk in step S209 and the CPU 101 reads the status register in the hard disk device 111, "Error bit" is set. Again, the CPU 101 executes step S21 of FIG.
Follow the flowchart from 0 to S214 to initialize the hard disk device 111 and release the error (S
210, S211) and the backup operation for the DMAC 112 is turned on (S212). This allows DM
The AC 112 sets, in the length controller 118, the number of pieces of data normally transferred in the previous DMA stored in the register 117, and the length controller 11
In No. 8, even if the data is transferred from the ATA interface controller 116 to the selector 115, the selector 115 discards only the data number set in the length controller 118.

The transfer start sector address and the number of sectors are designated for the hard disk device 111 (S213), the hard disk device 111 is restarted (S214),
Data retransfer is started, and the process returns to step S208.

Data retransfer is started, and data is transferred from the hard disk device 111 again.
As described above, according to the instruction from the DMAC 112, the number of pieces of data normally transferred in the previous DMA stored in the register 117 is determined by the length controller 11 first.
Set to 8 and ATA interface controller 11
Even if data is transferred from 6, the length controller 1
Only the number of data set to 18 is controlled by the selector 115 to be discarded.

After that, when the selector 115 finishes discarding the data transferred to the expansion bus 109 in the previous DMA, the selector 115 transfers the data received from the ATA interface controller 116 to the FIFO 113, and the DMAC 112 transfers it to the RAM 102. Continue data transfer.

As described above, by adding the second DMA controller 401 on the expansion bus 109, it is possible to make the DMA transfer speed efficient.
Furthermore, some Er is added to the hard disk device 111.
When a data transfer is interrupted due to the occurrence of the error, and the DMA transfer is performed again, another data transfer is not performed on the extension bus 109, the I / O bus 106, and the local bus 104 by duplicating the previously DMA-transferred data. Without reducing the operating speed of the I / O controller and CPU 101,
Data transfer from the hard disk device 111 to the RAM 102 can be continued.

[Other Embodiments] Even when the present invention is applied to a system including a plurality of devices (for example, host computer, interface device, reader, printer, etc.), an information processing device including one device (for example, , Personal computer, workstation, copier, MF
P (Mulati Function Periphe
Ral), a facsimile apparatus, an image processing apparatus such as a compound copying machine), or the like. That is, the image data that has been input (and image-processed) and stored in a volatile storage medium such as RAM is written to a nonvolatile storage medium such as a hard disk. At the time of image data transfer and image output (printout, etc.) An image processing apparatus that transfers image data stored in the RAM to the RAM or the like is also included in the present invention.

Further, according to the present invention, an M having an electronic sort function is provided.
When applied to an image processing apparatus such as FP, for example, as shown in FIG.
The hard disk device 111 shown in FIG. 4 is used as a hard disk for electronic sorting of the MFP system, and the hard disk controller 110 newly has an S for backup.
RAM 114 and length controller 118 for counting the number of data transferred to the expansion bus in the MFP system
As described in the first and second embodiments, the SRAM 114, the length controller 118, or the like is used to duplicate the data transfer after the error occurs, and the expansion bus 1
By preventing the error from occurring on the 09 side, it is possible to efficiently retransfer the data even after the error occurs in the electronic sort hard disk used in the MFP.

When the present invention is applied to an MFP system or the like, for example, the hard disk device 111 shown in FIGS. 1 and 4 is used not only for a hard disk for electronic sorting but also for an electronic file function and a personal box function of the MFP system. It can be used as a hard disk.

As described above, when a hard disk controller is newly provided with a storage device composed of a backup SRAM or the like and the data stored in the main memory is written to the hard disk, the MF is used.
The data transferred to the expansion bus in the P system is converted into the normal D
When data is transferred while being stored during MA transfer, and after the occurrence of an error, the above storage device is used to prevent duplicate data transfer from occurring on the expansion bus side, while performing data transfer for reading data from the hard disk to the main memory Is M
The number of data transferred to the expansion bus in the FP system is transferred while counting during the normal DMA transfer, and after the error occurs, the data is transferred to the expansion bus side after discarding the counted number of data and duplication. By preventing the generated data transfer from occurring on the expansion bus side,
Data retransfer is smoothly performed so that data retransfer can be efficiently performed even after an error occurs in a hard disk for electronic sorting used in an MFP system.

When the data transfer is not normally completed and the data is transferred again, as described above, the selector 115 is used.
And the length controller 118, the first retransfer mode for preventing the transfer of duplicate data on the bus, and the selector 115 and the length controller for transferring the data again without the data transfer being normally completed. 118
The second feature that enables all data to be transferred between the RAM 102 and the hard disk device 111 without using
The re-transfer mode may be selectable from an operation unit (not shown) or a host computer or the like that can communicate via a network.

Further, in the above embodiment, the case where the data is transferred between the RAM 102 which is the main memory and the hard disk device 111 which is the secondary storage medium has been described. However, instead of the hard disk as the secondary storage medium,
Other non-volatile storage media such as flexible disk, optical disk, magneto-optical disk, CD-ROM, C
It may be a D-R, a DVD-ROM, a magnetic tape, a non-volatile memory card, a silicon disk, or the like.

The present invention also includes a configuration obtained by combining the above embodiments.

As described above, the main memory (RAM1
02) and the hard disk device 111, and a FIFO 113 for temporarily storing data, and an SRAM.
DMA for performing DMA transfer between 114 and main memory
By providing the controller 112, the data read from the main memory or the data read from the hard disk device is prefetched by the FIFO 113, and a data is transferred between the hard disk device and the FIFO 113 via a hard disk device interface (ATA I / F 116). FIFO11
The data pre-fetched in 3 can be transferred at high speed.

Further, as shown in FIG. 1, when transferring the data stored in the main memory to the hard disk device, the data is stored in the FIFO 113, and further the SRAM 114 is provided for temporarily storing the data. While data is being transferred normally, SRAM1
Data is also transferred to 14, and if the data transfer ends abnormally on the way, the selector 115 switches the data transfer path to read the data from the SRAM 114 and continue the data transfer, while the data from the hard disk device 111 is transferred. When transferring data to the RAM 102, the DMAC 112 operates the register 117 to count the number of lengths of the data that has been transferred to the RAM 102, and the data transfer is interrupted because it does not end normally and data transfer is performed again. When performing, the data counted by the register 117 under the control of the length controller 118 is discarded without being input to the FIFO 113,
To provide a data transfer system in which uncounted data is input to the FIFO 113 and data transfer is continued so that data can be retransferred at high speed after the data transfer is interrupted between the main memory and the hard disk device. You can

Further, the CPU 101 uses the FIFO 113
The amount of data to be sent to the hard disk medium at one time is determined according to the capacity of
The data transfer amount set in the DMA controller 112 built in 0 is adjusted.

When the data transfer is not normally completed and the data is transferred again, the selector 115 and the length controller 118 are not used and all the data are stored in the RAM.
It is also possible to transfer between 102 and the hard disk device 111.

Furthermore, the DMA controller 112 refers to the "DMA Table Area" shown in FIG.
The data is continuously transferred to the FIFO 113 and the SRAM 114, and the data stored in the FIFO 113 is further transferred to the R
It is possible to transfer to a plurality of discrete blocks of the AM 102.

Further, as shown in FIG. 4, a second FIFO 402 for temporarily storing data between the RAM 102 and the FIFO 113 and a second FIFO 402 for performing a DMA transfer between the second FIFO 402 and the RAM 102. DM
By having the A controller 401, the transfer efficiency can be further improved.

Further, the second DMA controller 401
"DMA Table Area 2" shown in FIG.
Data is continuously transferred from the plurality of discrete blocks of the main memory to the second FIFO 402, and the data stored in the second FIFO 402 is further transferred to the plurality of discrete blocks of the RAM 102. It is possible to transfer.

As described above, by providing an area for backing up data in the hard disk controller or storing the transferred data amount, some problem occurs in the hard disk device,
Even if the DMA transfer is performed again, it is not necessary to perform the duplicate data transfer to the RAM or the system bus for transferring the data, so that the efficiency of the data retransfer is improved.

Further, by increasing the number of DMACs, it is possible to improve the efficiency of the DMA transfer itself. In that case, even if the data transfer is interrupted by the error of the hard disk device, the additional DMACs can be added. Since the data can be retransferred without restarting, the effect of high efficiency of retransfer can be obtained.

Therefore, it is possible to provide a data transfer system capable of high-speed retransfer after the data transfer between the main memory and the hard disk device is interrupted.

The configuration of the data processing program readable by the information processing apparatus according to the present invention will be described below with reference to the memory map shown in FIG.

FIG. 7 is a diagram for explaining a memory map of a storage medium for storing various data processing programs readable by the information processing apparatus according to the present invention.

Although not particularly shown, information for managing the program group stored in the storage medium, such as version information, creator, etc. is also stored, and information depending on the OS or the like on the program reading side, such as the program, is stored. In some cases, an icon or the like for identification display may be stored.

Further, data dependent on various programs are also managed in the above directory. Also, if the program or data to be installed is compressed,
A program for decompressing may be stored.

The functions shown in FIGS. 2 and 5 in this embodiment may be performed by the host computer by a program installed from the outside. And in that case, CD-ROM, flash memory, FD
The present invention can be applied to a case where an information group including a program is supplied to the output device from a storage medium such as the above or from an external storage medium via a network.

As described above, the storage medium recording the program code of the software that realizes the functions of the above-described embodiments is supplied to the system or apparatus, and the computer (or CPU or MP of the system or apparatus is supplied.
It goes without saying that the object of the present invention can also be achieved by U) reading and executing the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the novel function of the present invention, and the storage medium storing the program code constitutes the present invention.

As a storage medium for supplying the program code, for example, a flexible disk, hard disk, optical disk, magneto-optical disk, CD-ROM,
A CD-R, a DVD-ROM, a magnetic tape, a non-volatile memory card, a ROM, an EEPROM, a silicon disk or the like can be used.

Further, by executing the program code read by the computer, not only the functions of the above-described embodiment are realized, but also the OS (operating system) running on the computer based on the instruction of the program code. It goes without saying that this also includes the case where the above) performs a part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written in the memory provided in the function expansion board inserted in the computer or the function expansion unit connected to the computer, based on the instruction of the program code, The CPU or the like provided in the function expansion board or function expansion unit performs a part or all of the actual processing,
It goes without saying that the processing includes the case where the functions of the above-described embodiments are realized.

Further, the present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus. In this case, by reading a storage medium storing a program represented by software for achieving the present invention into the system or apparatus, the system or apparatus can enjoy the effects of the present invention. .

Furthermore, by downloading and reading the program represented by the software for achieving the present invention from the database on the network by the communication program, the system or apparatus can be
It is possible to enjoy the effects of the present invention.

[0136]

As described above, the first aspect of the present invention
According to the present invention, when the data stored in the volatile storage means is transferred to the nonvolatile storage means such as a hard disk via the first storage means for temporary storage and the DMA controller, The same data as the data stored in the first storage means is temporarily backed up and stored, and when the data transfer is normally performed, the data stored in the first storage means is stored in the hard disk. When the data transfer is stopped normally and the data transfer is interrupted and the data is transferred again, the input to the interface means of the non-volatile storage means is controlled so as to transfer the backed up data to the hard disk. When the data is transferred from the non-volatile storage means to the volatile storage means, the DMA controller completes the transfer to the volatile storage means. When the data length is counted from the nonvolatile storage means and the data is transferred from the nonvolatile storage means to the volatile storage means, the data transfer is not normally completed and is interrupted and the data transfer is performed again. Of the data read from the data storage means, the data of the counted length number is discarded without being input to the first storage means, and the data after the counted number of lengths is set to the first number. Since it is controlled so as to continue the data transfer to the volatile storage means by inputting to the first storage means, an area for backing up data is provided in the hard disk controller, or the transferred data amount is stored in advance. Even if a problem occurs in a non-volatile storage medium such as a hard disk and the DMA transfer is performed again, the data transfer is performed. It eliminates the need to duplicate data transfer to the volatile storage medium and a system bus of M such, the efficiency at the time of re-transfer of the data is improved.

Furthermore, by increasing the number of DMA controllers, it is possible to improve the efficiency of the DMA transfer itself. In that case, if the data transfer is interrupted due to an error in the nonvolatile storage medium such as a hard disk, Also, since the data can be retransferred without restarting the added DMAC, the retransfer can be performed efficiently.

Therefore, after the data transfer between the main memory and the hard disk device is interrupted, the data can be retransferred at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data transfer system in an information processing apparatus showing a first embodiment of the present invention.

FIG. 2 is a flowchart showing an example of a first control processing procedure of the data transfer system in the information processing apparatus of the present invention.

FIG. 3 illustrates a “DMA Table Ar” set on a RAM in the information processing apparatus according to the first embodiment of the present invention.
It is a schematic diagram explaining "ea".

FIG. 4 is a block diagram showing an example of the overall configuration of a data transfer system in an information processing apparatus showing a second embodiment of the present invention.

FIG. 5 is a flowchart showing an example of a second control processing procedure in the data transfer system in the information processing apparatus of the present invention.

FIG. 6 illustrates a “DMA Table Ar set in a RAM in the information processing apparatus according to the second embodiment of the present invention.
3A and 3B are schematic diagrams illustrating "ea" and "DMA Table Area 2".

FIG. 7 is a diagram illustrating a memory map of a storage medium that stores various data processing programs that can be read by the information processing apparatus according to the present invention.

FIG. 8 is a block diagram showing a configuration of a data transfer system in a conventional information processing apparatus.

[Explanation of symbols]

101 CPU 102 RAM 103 ROM 104 local bus 105 First Bus Bridge 106 I / O bus 107 network controller 108 Second Bus Bridge 109 expansion bus 110 hard disk controller 111 Hard disk device 112 DMAC 113 FIFO 114 SRAM 115 selector 116 ATA interface controller 117 register 118 length controller 401 Second DMAC 402 Second FIFO

Claims (13)

[Claims] 1. A volatile storage means and a non-volatile storage means, and data transfer for writing data stored in the volatile storage means into the non-volatile storage means and storage in the non-volatile storage means. An information processing device for performing data transfer for reading the stored data to the volatile storage means; first storage means for temporarily storing data between the volatile storage means and the non-volatile storage means; A DMA controller that DMA-transfers data between the volatile storage unit and the first storage unit, an interface unit that controls input / output to and from the nonvolatile storage unit, and a volatile storage unit that stores the data. A second storage for temporarily backing up the same data as the data stored in the first storage means when transferring the data to the nonvolatile storage means And when the data is transferred normally from the volatile storage means to the nonvolatile storage means, the data stored in the first storage means is stored in the nonvolatile storage means. When the data is transferred to the storage means and the data transfer is not normally completed and is interrupted and the data transfer is performed again, the interface so that the data backed up in the second storage means is transferred to the non-volatile storage means An information processing device comprising: a switching control unit that switches an input source to the unit. 2. A counting unit that counts the number of lengths of data that has been transferred to the volatile storage unit by the DMA controller when the data is transferred from the nonvolatile storage unit to the volatile storage unit, When transferring data from the non-volatile storage means to the volatile storage means, if the data transfer is interrupted without normal termination and data transfer is performed again, the data is read from the non-volatile storage means by the interface means. Among the data, the data for the length number counted by the counting means is discarded without being input to the first storage means, and the data after the length number counted by the counting means is used as the first data. And a length control means for controlling so as to continue the data transfer by inputting to the storage means. The information processing apparatus according to claim 1, wherein that. 3. According to the capacity of the second storage means,
The information processing apparatus according to claim 1, further comprising a data transfer amount control unit that determines a transfer amount of data to be transferred at a time to the nonvolatile storage unit. 4. When the data transfer is not normally completed and the data is transferred again, the switching control means, the counting means and the length control means are used to prevent transfer of duplicate data on the bus. A retransfer mode of 1 and a second retransfer mode of transferring all data between the volatile storage means and the non-volatile storage means without using the switching control means, the counting means and the length control means. 3. The information processing apparatus according to claim 2, further comprising: a retransfer mode selection unit that can select the. 5. The DMA controller continuously transfers data from a plurality of discrete blocks of the volatile storage means to the first storage means and the second storage means, and further, the first storage. 3. The information processing apparatus according to claim 2, further comprising transfer address control means for transferring data stored in the means to a plurality of discrete blocks of the volatile storage means. 6. A third storage means for temporarily storing data between the volatile storage means and the first storage means, and between the third storage means and the volatile storage means. With DMA
2. A second DMA controller for performing transfer, wherein the DMA controller DMA-transfers data between the third storage means and the first storage means. Alternatively, the information processing device according to item 2. 7. The second DMA controller continuously transfers data from a plurality of discrete blocks of the volatile storage means to the third storage means, and further stores the data in the third storage means. 7. The information processing apparatus according to claim 6, further comprising transfer address control means for transferring the stored data to a plurality of discrete blocks in the volatile storage means. 8. The volatile storage means is SRAM or D.
The information processing apparatus according to claim 1, further comprising a RAM, and the nonvolatile storage means includes a hard disk. 9. The image data stored in the non-volatile storage means at the time of image data transfer and image output in which the image data input and stored in the volatile storage means are written in the non-volatile storage means. The information processing apparatus according to claim 1, further comprising an image processing device that transfers image data to be read to the volatile storage unit. 10. A volatile storage means, a non-volatile storage means, a first storage means for temporarily storing data between the volatile storage means and the non-volatile storage means, and the volatile storage. Means D between the means and the first storage means
A DMA controller for MA transfer, and an interface unit for controlling input / output to / from the non-volatile storage unit, and data transfer for writing data stored in the volatile storage unit to the non-volatile storage unit and the non-volatile unit. A data transfer method of an information processing device for transferring data stored in a volatile storage means to the volatile storage means, wherein the data stored in the volatile storage means is transferred to the non-volatile storage means. In this case, a backup step of temporarily backing up the same data as the data stored in the first storage means in the second storage means, and transferring the data from the volatile storage means to the non-volatile storage means When the data is transferred normally, the data stored in the first storage means is stored in the nonvolatile memory. When the data is transferred to the storage means and the data transfer is interrupted without being normally terminated and the data transfer is performed again, the interface backed up so that the data backed up in the second storage means is transferred to the non-volatile storage means. And a switching step of switching the input source to the means. 11. A counting step of counting the number of lengths of data which has been transferred to said volatile storage means by said DMA controller when transferring data from said non-volatile storage means to said volatile storage means, When transferring data from the non-volatile storage means to the volatile storage means, if the data transfer is interrupted without normal termination and data transfer is performed again, the data is read from the non-volatile storage means by the interface means. Among the data, the data for the length number counted in the counting step is discarded without being input to the first storage means, and the data after the number of lengths counted in the counting step is used as the first data. And a length control step for controlling so as to continue the data transfer by inputting to the storage means of the contractor. Data transfer method of an information processing apparatus of claim 10, wherein. 12. A program for executing the data transfer method of an information processing device according to claim 10. 13. A computer-readable storage medium that stores a program for executing the data transfer method of an information processing apparatus according to claim 10 or 11.