JP2003319338A - Signal processor, and recording device and reproducing device employing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processor for performing DV decode processing by a single clock so as to decrease the number of pins of an LSI and the number of components of peripheral circuits. <P>SOLUTION: A DV decoder of this invention, in order to achieve the purposes above, performs a frame synchronizing at the same time when deshuffling. Specifically the DV decoder is characterized in including: an input section for receiving a video signal; a video decode means for applying decode processing to the video signal to output video data; a memory having three memory areas or more each storing one frame of the video data, a write control means for controlling the sequential write of the video data to the memory areas in the unit of one frame; and a read control means for controlling reading of the video data from the memory areas just after the writing of one frame of the video data is finished under the control of the write control means. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for decoding digitally compressed video and audio signals.

[0002]

2. Description of the Related Art For example, there is an invention described in JP-A-11-317916. The invention described in this publication has an object of "to easily synchronize a digital audio signal which is asynchronous with a video signal with a video signal to prevent deterioration of sound quality and to prevent an increase in size and cost of a device". An input clock generation circuit 10 for generating an input clock signal from an audio signal asynchronous with the signal, an output clock signal generation circuit 20 for generating an output clock signal based on a frame reference signal, and a clock based on the input clock signal for the audio signal. Inputs CH1 and CH2 for interleave processing
Audio signal processing circuits 30 and 31, sample rate conversion circuits 32 and 33 that use an input clock signal as an input reference clock and an output clock as an output reference clock, and interleave processing based on the output clock signal for the audio signal after rate conversion Outputs CH1 and CH2
It has audio signal processing circuits 34 and 35. It is configured with.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention Among digital signal transmission standards that have been actively adopted in recent years, for example,
There is an IEEE1394 standard. The IEEE 1394 standard is attracting attention as suitable for multimedia applications such as connection between digital video cassette recorders and connection between digital video cassette recorder and personal computer.

The formats of the digital video signal and the digital audio signal in the IEEE1394 standard are as follows: Specifications of Consumer-Use Digital VCRs us
ing 6.3mm magnetic tape [HD DIGITAL VCR CONFERENC
E] (hereinafter referred to as DV standard). This D
According to the V standard, the compressed signal is 480 bytes of video,
For audio data, Isochronous header, CIP (Common Is
ochronous Packet) header, CRC (Cyclic Redundancy Che)
It is a standard for transmitting data on a 1394 bus as packet unit data with ck) added. Further, the CIP header includes synchronization time information (SYT: SyncTime) in order to synchronize a plurality of devices that transmit and receive via the 1394 bus. Normally, since the output video signal timing after decoding is generated by referring to this SYT, a video PLL is required for the purpose of creating a clock locked in phase with the SYT.

On the other hand, in the DV standard, there is an unlock mode in which the relationship between the video signal and the audio signal is asynchronous. Therefore, in this case, an audio PLL is required in addition to the video PLL.

By the way, the equipment conforming to the DV standard,
Considering the connection with other systems, there is a case where the audio unlock mode as in the DV standard is not allowed, so that the video and audio signals must be output in synchronization. Therefore, in the above publication, in order to synchronize the audio signal in the DV standard with the video signal as described above, first, the decoding process is performed using the audio PLL, and then the second synchronization using the synchronization on the video signal side is used. We have proposed a configuration that synchronizes a video signal and an audio signal by creating a new synchronization using this audio PLL and performing sample rate conversion processing of the audio signal using this.

However, when a digital circuit is integrated in an LSI, it is desirable to use a single clock in order to improve design efficiency and ensure stable operation. Further, in order to suppress the manufacturing cost of the LSI itself, the ease of designing a board on which the LSI is mounted, the production efficiency, and the defect occurrence rate, it is desirable that the number of pins of the LSI is as small as possible.

However, in the above-mentioned conventional example, at least two or more clocks are used.
There is a drawback that timing design and timing verification at the time of design become complicated.

Further, when guaranteeing stable operation, a plurality of clocks are present not only inside the LSI but also on the substrate on which the clocks are mounted, which increases crosstalk between clocks and causes of noise. Become. In this case, board design technology for suppressing these crosstalk and noise, parts for preventing interference, etc. are required.

Further, in the above-mentioned conventional example, there are at least two clock generating PLLs. When constructing a normal PLL, an external LP is used to integrate the phase comparison output.
F is needed. Furthermore, external pins dedicated to the input and output of these PLLs are required. For this reason, the number of parts on the board inevitably increases, and at the same time, the board design becomes complicated due to the influence of the increase in the number of pins of the LSI, and the total cost also rises.

An object of the present invention is to reduce the number of pins of an LSI and the number of peripheral circuit parts by performing a DV decoding process with a single clock.

[0012]

In order to achieve the above-mentioned object, the signal processing apparatus of the present invention performs frame synchronizing processing at the same time as deshuffling processing. In particular,
Clock generating means for generating a reference clock, and three clock generators which operate at the reference clock and can store the output video data of the video decoding means for three frames when decoding the input video signal. And a memory having a memory area, and an address is generated for deshuffling the video data of the video decoding means, and data is sequentially written into the three memory areas in units of one frame. The writing control circuit that outputs the writing area number in synchronization with the side frame reference signal, and the writing area number described above in synchronization with the output side frame reference signal, and the area offset amount corresponding to each number is stored in the memory. The written video data is added to an address for reading, and the three memory areas are added. It is characterized by comprising a control control circuit for sequentially reading out data in units of 1 frame. As a result, when the output side frame reference signal interval is narrowed with respect to the input side frame reference signal and occurs earlier, the already output frame is repeatedly output, and the frame reference signal is input to the input side frame reference signal. When the signal interval becomes wide and occurs late, a frame synchronizer operation for thinning out frames and outputting is realized.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an example of the configuration according to the present invention.

In FIG. 1, 107 is an IEEE 1394 interface processing unit, 108 is a signal separation processing unit, 109 is a video decoding processing unit, 110 is a video signal synchronization processing unit, 111 is a video signal output terminal, 112 is an audio decoding processing unit, Reference numeral 113 is a sampling conversion processing unit, 114 is an audio signal output terminal, 115 is an input signal processing frequency dividing circuit, 116 is an audio signal output processing frequency dividing circuit, 117 is a video output frame synchronization generation frequency dividing circuit, and 118 is a phase. The comparison unit 106 is a fixed clock generation unit, and this fixed clock is hereinafter referred to as a system clock.

Further, 102 is an input processing unit that collectively 107 and 108, 103 is a video processing unit that is 109 and 110 together, and 104 is 112,1.
13 is collectively referred to as an audio processing unit, and 105 is collectively referred to as a frequency dividing unit including 115, 116, and 117. Further, the portion surrounded by the dotted line indicated by 1, that is, the video processing unit 103, the audio processing unit 104, the frequency dividing unit 105, and the signal separation processing unit 108 is called a DV decoder. This DV decoder is composed of one chip. The DV decoder 1 uses IEEE1394
Interface processing unit 107 is also added to form a single chip D
It is also possible to use a V decoder.

Although not specifically shown in FIG. 1, the system clock is supplied as a clock to all blocks after the output of the IEEE1394 interface processing unit 107.

The IEEE1394 interface processing unit 107
IEEE13 as a basic clock to receive the input signal
24.576 synchronized to 94 interface operating reference frequency
Although MHz is used, in order to facilitate the interface with peripheral devices, a configuration that obtains an output that is asynchronous with the basic clock of the digital signal processing device is adopted. For example, the data existing on the IEEE1394 bus is managed in a unit called one packet.
There is header information called an ochronous header, header information called a CIP header, and DV data. These data are managed with the above basic clock of 24.576 MHz. Also, time information is included in the CIP header information,
This is used to create an input-side frame synchronization signal, and the input-side frame synchronization signal is output in synchronization with an external clock. The input side frame synchronization signal indicates the input side reference timing. Above D
The V data is stored in the FIFO (F
irst In First Out), and the structure is used to read using the reference clock.

That is, the data output clock required here is not necessarily locked to the input frame synchronization. Therefore, in the present invention, the system clock is frequency-divided by the video signal processing frequency dividing circuit 115, and this is used as an input processing clock enable signal and connected to the IEEE1394 interface processing unit 107 in pair with the system clock. That is, the basic clock is the system clock,
When used in combination with the enable signal, the data apparently changes in the cycle of the input processing clock enable.

For example, assume that the system clock is 54 MHz and the input processing clock enable signal is 13.5 MHz.
z, assuming that the output data bus width of the IEEE1394 interface processing 107 is 8 bits, the data transfer capability is 13.5 MHz x 8 bits = 108 Mbps. On the other hand, the compressed signal of DV standard is about 25Mb
The data rate is ps, and the data transfer capability is sufficient as an enable signal for handling this data. Of course, in consideration of the capacity of the above-mentioned FIFO, control is performed so as not to cause overflow or underflow.

The input processing clock enable signal can be easily obtained by dividing the system clock. As described above, the IEEE1394 interface processing unit 107 inputs the system clock and the clock enable for input processing which is generated by frequency division based on the system clock, and the IE
Out of the EE1394 standard input data, the DV standard data is separated and output, and at the same time, the input side frame synchronization signal is output.

The signal separation processing unit 108 separates the DV standard data output from the IEEE1394 interface processing unit 107 into video data and audio data based on header information and outputs the data.

The signal processing of video data will be described in detail below.

In the video processing unit 103, the video decoding processing unit 109 has the configuration shown in FIG. In FIG. 2, 201 and 208 are SRAMs, 202 is SRAM control, 203 is a variable length decoding unit (Variable Length Decoding or less, VLD
), 204 is a VLD conversion table, and 205 is an inverse quantization processing unit.
(Inverse Quantization hereafter referred to as IQ), 206 is an inverse weighting processing unit, 207 is an inverse discrete cosine transform processing unit (Inverse Diquantization).
The screte Cosine Transform is referred to as IDCT hereinafter).

In the video decoding processing unit 109, first, video data for one video segment is stored in the SRAM 201, and while referring to the VLD conversion table 204 in three stages of DCT unit, macroblock unit and video segment unit. Perform VLD processing to decode input data. Next IQ
The processing unit 205 performs data shift processing on a predetermined area within 64 pieces of data, which is one DCT unit. The inverse weighting processing unit 206 performs the inverse weighting processing with a larger coefficient as the distance from the DC component increases in the zigzag scan order within 1 DCT.
The IDCT process 207 performs a process of calculating 64 amplitude components from the 64 frequency components after the inverse weighting process according to a predetermined calculation formula.

All the above processing is managed by the input processing clock enable signal output from the input signal processing frequency dividing circuit 115 and the system clock. still,
Details of each processing in the video decoding processing unit 109 are described above in D.
Since it is described in the V standard, detailed description is omitted here.

Next, the operation of the video signal synchronization processing unit 110 in the video processing unit 103 will be described with reference to FIG. In FIG. 3, 301 is a memory, 302 is a deshuffling write control signal generator, and 303 is a deshuffling read control signal generator.

The memory 301 has a capacity of three frames or more of data (three or more memory areas having a capacity of one frame). If the number of frames is less than 3 frames, new data will be overwritten in the memory area being read when the output-side frame reference timing is later than the input-side frame reference timing, that is, when the reading is later than the writing. In the deshuffling write control signal generation unit 302, the data decoded by 109,
Receives the enable signal and error information accompanying it,
An address for rearranging the data in the frame image is generated and output to the memory 301 together with the enable signal and the data. At this time, the 302 outputs the write area number to the deshuffling read control signal generating section 303 in synchronization with the input side frame reference signal 119 output from 107 every time one frame of data is written. The deshuffling read control signal generation unit 303 generates the read address by synchronizing the write area number transmitted from 301 with the output side frame reference signal 120 output from 117. Then, the address and enable are stored in the memory 30.
The data is transmitted to 1 and the data is fetched in the order of the odd field and the even field and output to 111.

FIG. 4 shows the internal configuration of the deshuffling write control signal generator 302. 401 is a data format conversion circuit, 402 is a frame position information detection circuit, 403 is an SRAM writing circuit, 404 is SRAM, and 405 is memory writing. It is an address generator.

The data format conversion circuit 401 receives the 8-bit data and the enable signal from 109, converts them into 32 bits, and outputs them to 403. 10 in the frame position information detection circuit 402
By receiving the enable signal and error information from 9, and counting the enable, it is detected at which position on the frame image each data should exist, and the position information is written to the SRAM write circuit and memory write of 403. The address information is output to the address generator 405, and the error information is output to the memory write address generator 405. S
In the RAM writing circuit 403, the data sent from the data format conversion circuit 401 is transferred to the frame position information detection circuit 402.
Using the address generated based on the position information sent from, the SRAM 404 is once written. Then, when the writing is completed, the SRAM write end signal is output to the memory write address generation unit 405.

In the operation of the memory write address generation unit 405, the SRAM read circuit 405a receives the SRAM write end signal from the SRAM write circuit 403, and the SRAM is signaled that the SRAM
The enable and the address are output to 404, the data is fetched from the SRAM 404, the data is output to the memory 301, and the address generation instruction is output to the in-frame address generation circuit 405b. In the intra-frame address generation circuit 405b,
An address generation command is received from the SRAM read circuit 405a, and a memory write address in a frame image is generated based on the position information sent from the frame position information detection circuit 402. The area counter 405d operates the counter in synchronization with the input side frame reference signal 119 sent from 107, and outputs the area number of 0 to 2 to the area offset amount generation circuit 405c. Area offset amount generation circuit 405c
Is the area number 0-2 received from the area counter 405d
The value corresponding to is output as the address offset value.
The offset value is added to the memory write address generated by the intra-frame address generation circuit 405b and the memory 30
Output to 1. The flip-flop (FF) 405e takes in the counter value of the area counter 405d in synchronization with the input side frame reference signal 119 sent from 107. Therefore, while the output of the area counter 405d indicates the area number currently being written, the flip-flop 40d
The output of 5e indicates the area number immediately after the writing is completed.

Next, details of the operation of the deshuffling read control signal generator 303 will be described with reference to FIG. FIG. 5 shows a configuration example of the deshuffling read control signal generation unit 303, where 501 is a memory read address generation unit and 502 is SR.
AM and 503 are data format conversion circuits, 504 is a video data interpolation circuit, and 505 is an output control circuit.

In the memory read address generator 501, the write area number sent from 302 by the flip-flop (FF) 501a is fetched in synchronization with the output side frame reference signal 120 sent from 117. The area offset amount generation circuit 501b outputs a value obtained by multiplying the write area number received from the flip-flop (FF) 501a by the address value of one frame, as a read address offset value, as in the case of 405c described above. The in-frame address generation circuit 501c generates a read address in a frame image in order of an odd field and an even field in synchronization with the output side frame reference signal 120 sent from 117. The in-frame address is added to the offset value output from the area offset amount generation circuit 501b and output to the memory 301. Then, at that time, a data transfer instruction is output to the SRAM write circuit 501d.

The SRAM writing circuit 501d receives data from the memory 301 and writes the data to the SRAM 502 in 32 byte units (32 pixel units) in response to a data transfer instruction from the in-frame address generating circuit 501c.

The data format conversion circuit 503 reads the data from the SRAM 502, converts the 32-bit data into 8-bit data, and outputs the 8-bit data to the video data interpolation circuit 504. The video data interpolation circuit 504 interpolates the data and outputs it to the output control circuit 505 in the 4: 2: 2 format. Output control circuit 505
In the above, the data is converted to the BT656 output format and output to 111. By performing the circuit configurations of FIGS. 3, 4, and 5 described above, the video deshuffling process for rearranging the data in the frame and the frame synchronizer operation for synchronizing the data in units of one frame are realized at the same time. I can do things.

Next, an outline of the video deshuffling processing operation and an outline of the frame synchronizer operation performed in the deshuffling processing process will be described with reference to FIGS. 6, 7, 8 and 9.

FIG. 6 is an explanatory view for explaining the video deshuffling principle. In FIG. 6, (a) shows the video processing unit 103.
(B) and (c) are field images in which odd and even lines are respectively collected from the frame image of (a). Further, FIG. 5 shows timings of writing and reading data of the memory 301 in the video deshuffling process, (a) shows the input side frame reference signal 119,
(b) shows a write address of the memory 301, (c) shows a write signal of the memory 301, and (d) shows a read signal of the memory 301, respectively.

The deshuffling process in the video signal synchronization processing unit 110 is a process for rearranging the video signal of the frame image shown in FIG. 6A into the signal of the field image shown in FIGS. 6B and 6C. From the video processing unit 103, as shown in FIG. 6 (a), 1, 2, 3, 4, in FIG.
The signals processed in the order of 5 are output from the top to the bottom.

Deshuffling write control signal generator 30
In No. 2, the writing process is performed while mapping to the position that should be originally displayed on the memory. Therefore, in the order shown in FIG.
Generate vertical address. Since the shuffling process is a standard that makes one cycle for one frame, as shown in FIG.
The data for the frame is written in the memory 301.

The intra-frame address generation at the time of writing data in the memory 301 can be realized by reversing the shuffling rule of the DV standard described above, and in this embodiment, 402 and 405b in FIG. The address in the write frame is generated at.

As described above, the signal processing from the input processing unit 102 up to this point is performed based on the input side frame reference signal 119 output from the IEEE1394 interface processing unit 107.

Next, the deshuffle read control signal generator
Reference numeral 303 denotes a video signal written in the memory 301 in the form of a frame image, which is a video signal (e) of an odd line shown in FIG.
ven field) and even line video signals (odd field) shown in FIG. 6C are read out in this order (FIG. 7).
(d)). At this time, the deshuffle read control signal generator 3
03 starts read control using the output side frame reference signal 120 obtained from the video output frame synchronization generation frequency dividing circuit 117 as a reference signal. Output side frame reference signal 120
Is a signal indicating the output side frame reference timing.

Here, the input side frame reference signal 119,
The relationship of the output side frame reference signal 120 will be described with reference to FIG.

FIG. 8 shows the relationship between the input-side frame reference signal 119, the output-side frame reference signal 120, and the input / output data of the memory 301 during the synchronizing operation. If the output side frame sync signal 120 is generated early because it is narrow,
FIG. 9 is a timing chart separately shown in the case where the output-side frame reference signal 120 is generated later because the output-side frame reference signal interval is wider than the input-side frame reference signal interval. As described above, the input side frame reference signal 119 is created based on the time information (SYT) in the CIP header information, and the output reference signal is used for video output frame synchronization generation based on the reference clock. It is output from the frequency dividing circuit 117. In FIG. 8, (a) is the input side frame reference signal 119,
(b) is write data from 405 in 302 to the memory 301,
(c) is the write area number output from 405 to 303 in 302, (d) is the output side frame reference signal 120, and (e) is 303 to 11
The data output to 1 are shown respectively.

For example, D input through the IEEE1394 bus
Various cases can be assumed for the V data, such as an output of an externally connected digital video cassette recorder and an output of data stored in a personal computer. Therefore, the frequency of the system clock used in the present invention,
If there is a slight difference from the frequency of the oscillator built in the external device, the frame reference signal serving as the reference also deviates. For example, when the system clock used in the present invention has a slightly high frequency, at the timing shown in FIG.
There is a case where the writing and reading of the memory 301 are in a racing relationship at the timing shown in FIG.

Therefore, in the present invention, as shown in FIG. 3, FIG. 4 and FIG. 5 of the circuit configuration example, from the deshuffling write control signal generation unit 302, in synchronization with the input side frame reference signal 119 of FIG. The writing area number (hereinafter referred to as w_end) for which writing has been completed is output to the deshuffle read control signal generation unit 303. In the relationship between (b) and (e) in FIG. 8, at the timing shown in (f), even if the writing of the data (F1) of the second frame is completed, the second frame
Since w_end is not output, read control is performed to output the data of the first frame again. In addition, in FIG.
In the relationship between (b) and (e), at the timing shown in (f),
Even though the data of the first frame has not been read yet, the writing of the second frame has already been completed,
The read control is performed so that the data of the first frame is skipped and the data of the second frame is jumped and output. As described above, in the present embodiment, the read address offset is controlled so that the data immediately after the writing is always read is read by the operations of 501a and 501b in the memory read address generation unit 501. In the process of one-time write / read access to the memory 301, the frame synchronizer operation can be performed at the same time, and the locked output is obtained in the output frame synchronization which is asynchronous with the input DV data. Is possible.

Next, an outline of the signal processing means when a decoding error occurs in the processing performed by the variable length code processing unit 203 inside the video decoding processing unit 109 will be described. FIG. 9 shows a timing chart of signal processing in a case where error data is included in a video signal in a series of deshuffling processing. FIG. 9A shows IDCT data output from the video decoding processing unit 109 to the video signal synchronization processing unit 110. 9B is generated when a decoding error occurs in the VLD unit 203 of the video decoding processing unit 109, the IQ unit 205, the inverse weighting unit 206, and the IDCT unit 20.
The IDCT error signal delayed by 7 and output to the video signal synchronization processing unit 110 is shown and is output to the frame position information detection circuit 402. FIG. 9C shows an error transmission signal output to the memory write address generation unit 405 when the frame position information detection circuit 402 receives the IDCT error signal of FIG. 9B. FIG. 9D shows the SRAM write enable output from the SRAM write circuit 403 to the SRAM 404. FIG. 9E shows the SRAM read circuit 4
Reference numeral 05a shows a memory write cancellation signal which is internally generated when the error transmission signal of FIG. FIG. 9F shows the write enable that occurs inside the SRAM read circuit 405a. Figure 9 (g) shows SRAM
The memory write enable output from the read circuit 405a to the memory 301 is shown. In FIG. 9, the error data exists in the DCT block Y2 of the brightness of the IDCT data (a),
The signal generation form when the IDCT error signal (b) is issued from the video decoding processing unit 109 is shown. In this case, first, the IDCT error signal (b) is received by the flip-flop (FF) in the frame position information detection circuit 402, and the FF outputs a signal of HI (value is 1). This signal is the error transmission signal (c). And the error transmission signal (c)
Is LO (value 0) at the same time as the writing of DCT block Y3 is completed.
Fall to.

Next, the SRAM read circuit 405a takes in the error transmission signal (c) by the flip-flop (FF) at the same time when the writing of the DCT block Y3 is completed, and outputs the signal whose FF is HI (value is 1). This signal is the memory write cancellation signal (e), which is the S of Cr that is one of the next 2DCT units.
It falls to LO at the same time when the RAM writing is completed. Then, the SRAM read circuit 405a writes enable (f).
Select a signal of 0 or 0 according to the value of the memory write cancellation signal (e) and enable the memory write to the memory 301 (g).
Output as. As a selection method, 0 is output while the memory write cancellation signal (e) is HI, and a write enable (f) is output while the memory write cancellation signal (e) is LO. As a result, if 0 is output instead of write enable (f), memory 301
Is not written to, data of 2DCT of the previous frame remains, and the data of the previous frame is output at the error location when outputting the frame including the error DCT.

According to this embodiment, it is possible to decode a signal by using a single asynchronous clock generated by 106 without using a plurality of PLLs and oscillators as shown in the conventional example, and the deshuffling operation and Access to memory 301 for both processes of frame synchronizer operation 1
It can be performed only once, and the memory bandwidth and memory capacity at that time can be effectively used. In addition, even when an error phenomenon occurs during video data decoding, the data of the previous frame is output from the memory 301 without writing to the memory 301 for 2DCT blocks, and thus the disturbance of the image can be reduced. It will be possible.

Next, a hard disk recorder which is an example of a recording device to which the digital signal processing device described in the above embodiment is applied will be described with reference to FIG.

In FIG. 10, the elements having the same numbers as those in FIG. 1 have the same functions, and the description thereof will be omitted. Reference numeral 1101 denotes an analog input terminal, an S input terminal, or a digital input terminal for inputting data output from a satellite broadcast tuner or the like, that is, an analog signal of a format other than IEEE1394 or a digital signal according to BT656. . 1102 is a video / audio signal processing circuit for performing video signal processing and audio signal processing, and 1106 is a switch for selecting the output of the video / audio signal processing circuit 1102 and the DV decoder 1. Reference numeral 1106 denotes an MPEG compression / expansion processing circuit that compresses the data selected by the switch 1104 with MPEG2 and records the data in a hard disk (HDD) 1107 that is a recording medium. The MPEG compression / decompression processing circuit also
It operates with the reference clock output from the CXO106.
The signal recorded in the HDD 1107 is read out and expanded by the MPEG compression / expansion processing circuit 1106. A switch 1105 selects either one of the data selected by the switch 1104 and the data output from the MPEG compression / expansion processing circuit 1106. An output terminal 1108 outputs the data output from the switch 1105 to the outside. The switch 1104 and the switch 1105 are collectively referred to as a switch circuit 1103.

The operation of the hard disk recorder in this embodiment is as follows. First, a video signal and an audio signal are input to an input terminal 1101 from a satellite broadcast tuner or the like, converted by a video / audio signal processing circuit 1102, and output in a predetermined signal format (for example, BT656). The video / audio data output in the IEEE1394 format is processed by the IEEE1394 interface 107 and the DV decoder as described in the above embodiment, and is synchronized with the reference clock 106 asynchronous with the signal input from the outside. Moreover, a signal according to the lock mode in which the audio signal is synchronized with the video signal is obtained. The switch 1104 selects one of the signals. This selection may be performed by automatically detecting the one to which a signal is input, or may be performed according to a selection button indicating which one is selected, which is instructed by a user (not shown). . The data selected by the switch 1104 is compressed by the MPEG compression / expansion processing circuit 1106, and the compressed data is recorded in a hard disk (HDD) 1107 which is a recording medium by a recording unit (not shown). HDD11
The signal recorded in 07 is read out and expanded by the MPEG compression / expansion processing circuit 1106. Note that data compressed according to the DV standard has a lower compression rate than MPEG2, so MPE
By performing compression according to G2, compressed data with a high compression ratio and good recording efficiency can be obtained. The compressed data recorded in the HDD 1107 is read and expanded by the MPEG compression / expansion processing circuit 1106. The switch 1105 selects either one of the data selected by the switch 1104 and the data output from the MPEG compression / expansion processing circuit 1106. This selection may be performed by automatically detecting the input of a signal, or may be performed by a selection button (not shown).

The selected signal is output from the video / audio output terminal 1108 to a device having a display function or a recording function such as a TV and reproduced. In addition, when outputting, Hi Vis
It may be converted into a signal suitable for ionTV or may be subjected to signal conversion processing from NTSC to PAL. The compressed data read from the HDD 1107 can be output to the outside by the IEEE1394 interface and supplied to the personal computer.

Since the DV decoder in this embodiment can be processed by the oscillator of 1 clock and the PLL is not used, other MPE
When constructing a system that uses a DV decoder with a G compression / decompression processing circuit, IEEE1394, etc., it is possible to reduce the interference due to clocks and relax the constraints when designing the base, which increases the degree of freedom in design. There is H
Even in a system product such as a DD recorder, the use of a DV decoder that processes with one clock is meaningful.
If the MPEG compression / expansion processing circuit is integrated with the DV decoder and the oscillator is shared with the DV decoder and the MPEG compression / expansion processing circuit, the circuit can be further simplified.
The total cost of the entire system can be suppressed.

Although the hard disk recorder has been described in this embodiment, the recording medium is not limited to the HDD and may be another medium such as a DVD.

In the above embodiment, an example in which a signal of the IEEE 1394 standard is input and decoded has been described, but a signal other than the signal of the IEEE 1394 standard can be decoded. For example, in FIG. 10, an IEEE 1394 standard signal is input from the input terminal 101 through the 1394 interface processing unit 107 to the DV decoder 1 for decoding, but a reproducing means is used instead of the input terminal 101 and the 1394 interface processing unit 107. With the configuration provided, the signal reproduced by the reproducing means can be input to the DV decoder 1 and decoded. Therefore, for example, it is possible to provide a reproducing apparatus including such reproducing means, the DV decoder 1, and the video output terminal 1108. Here, the reproduction means is
Read signal from storage medium and DV signal to DV decoder
The means provided in 1 may be used, and for example, there is a device for reproducing a DV tape.

[0057]

As described above, according to the present invention, the frame synchronizer operation can be realized in the process of one read / write access to the memory during the deshuffling operation, and the circuit scale can be saved. . In the process, even if the error data is included, the writing to the memory is stopped and the data of the previous frame is replaced, so that the disturbance of the image can be reduced.

Further, since the PLL is not used, the external pins for the PLL can be reduced, the manufacturing cost of the LSI can be suppressed, and at the same time, the number of parts of the board on which the PLL is mounted can be suppressed and the increase of the product cost can be prevented. It becomes possible.

[Brief description of drawings]

FIG. 1 shows a first digital signal processing device according to the present invention.
It is a block diagram showing an embodiment.

FIG. 2 is a block diagram showing details of a video decoding processing unit 109 according to the first embodiment.

FIG. 3 is a block diagram showing details of a video signal synchronization processing unit 110 according to the first embodiment.

FIG. 4 is an explanatory diagram showing a configuration of a deshuffling write control signal generator 302 according to the first embodiment.

FIG. 5 is an explanatory diagram showing a configuration of a deshuffling read control signal generation unit 303 according to the first embodiment.

FIG. 6 is an explanatory diagram showing details of a deshuffling operation in the video signal synchronization processing unit 110 according to the first embodiment.

FIG. 7 is a timing chart showing a deshuffling operation in the video signal synchronization processing unit 110 of the first embodiment.

FIG. 8 is a timing chart showing a frame synchronizing operation in the video signal synchronization processing unit 110 according to the first embodiment.

FIG. 9 is a timing chart showing an operation for an error signal in the video signal synchronization processing unit 110 of the first embodiment.

FIG. 10 is a diagram showing a hard disk recorder using the digital signal processing unit described in the first embodiment.

[Explanation of symbols]

102 ... Input processing unit. 103 ... Video processing section. 104 ... Audio processing section. 105 ... Divider. 106 ... Fixed clock generator. 107 ... IEEE 1394 interface processing unit. 108 ... Signal separation processing unit. 109 ... Video decoding processing unit. 110 ... Video signal synchronization processing unit. 111 ... Video signal output terminal. 112 ... Audio decoding processing unit. 113 ... Sampling conversion processing unit. 114… Audio signal output terminal. 115 ... Frequency divider for input signal processing. 116… Dividing circuit for audio signal output processing. 117… Divider circuit for video output frame synchronization generation. 118 ... Phase comparator. 119 ... Input side frame reference signal. 120 ... Output side frame reference signal. 201 ... SRAM. 202… SRAM control. 203 ... Variable length code processing unit. 204 ... VLD conversion table. 205 ... Inverse quantization processing unit. 206 ... Inverse weighting processing unit. 207 ... Inverse discrete cosine transform processing unit. 208 ... SRAM. 301 ... memory. 302 ... Deshuffling write control signal generator. 303 ... Deshuffling read control signal generator. 401 ... Data format conversion circuit. 402 ... A position information detection circuit on the frame. 403 ... SRAM write circuit. 404 ... SRAM. 405 ... Memory write address generator. 501 ... Memory read address generator. 502 ... SRAM. 503 ... Data format conversion circuit. 504 ... Video data interpolation circuit. 505 ... Output control circuit.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) // H04N 7/08 H04N 7/08 Z 7/081 (72) Inventor Koichi Ono Shinmachi, Ome City, Tokyo 6-chome 3 3 Hitachi Ltd. Device Development Center (72) Inventor Etsuaki Kuroda 3-chome, Shinmachi, Ome-shi, Tokyo 3-16 Hitachi Ltd Device Development Center (72) Inventor Atsushi Hosono Kodaira, Tokyo 5-22-1, Ichijomizuhonmachi F-term in Hitachi Super LSI Systems Inc. (reference) 5C026 DA00 5C053 FA22 GB22 GB26 GB32 LA11 LA15 5C063 AB03 AB07 AC01 CA11 CA23 DA07 DA13 DB10 5D044 AB05 AB07 FG10 FG21 5K047 AA16 DD02 GG44 GG45 GG52 MM24 MM53

Claims (12)

[Claims] 1. An input section for inputting a video signal to which synchronization time information is added, video decoding means for decoding the video signal and outputting video data, and a memory for storing the video data for one frame. Area 3
A memory having more than one memory, a writing control means for sequentially writing the video data to the memory area in units of one frame, and outputting an area number corresponding to the memory area for which the writing is completed, and the synchronization time information. The area number is fetched in synchronization with the output-side frame reference signal generated without reference, and the area offset amount corresponding to the area number is added to the address for reading the video data from the memory area. And a read control unit for controlling the sequential reading of the video data in units of one frame. 2. The signal processing device according to claim 1, wherein the write control unit generates an address for deshuffling the video data, and controls the write of the video data based on the address. . 3. The clock generation means for generating a reference clock without referring to the synchronization time information according to claim 1, wherein the video decoding means, the write control means and the read control means are used as the reference. A signal processing device characterized by being operated by a clock. 4. The signal processing device according to claim 3, wherein the output-side frame reference signal is generated from the reference clock. 5. The write control means according to claim 1, wherein the write control means outputs the area number in synchronization with an input side frame reference signal generated from the synchronization time information. Signal processing device. 6. The read control means according to claim 5, wherein when the timing of the output-side frame reference signal is earlier than the timing of the input-side frame reference signal, read-out control is performed so as to thin out frames. A signal processing device, wherein when the timing of the output-side frame reference signal is later than the timing of the input-side frame reference signal, read control is performed so that the already read frame is read again. 7. A signal processing device for decoding and outputting a DV compressed signal transferred with a predetermined data amount in packet units, to which synchronization time information has been added, wherein a reference clock is used without reference to the synchronization time information. A clock generating means for generating, a video decoding means for operating with the reference clock to decode the input video signal, and three output video data of the video decoding means capable of storing three frames. A memory having a memory area, and operating to the reference clock, and performing control to sequentially write data in the three memory areas in units of one frame while generating an address for deshuffling the video data of the video decoding means. , Write control that outputs the area number corresponding to the memory area for which writing has been completed A circuit for reading the video data written in the memory, taking in the writing area number in synchronization with the output side frame reference signal obtained by dividing the reference clock, and reading the area offset amount corresponding to the area number. A signal processing device, comprising: a read control circuit for performing a control of sequentially adding data to an address and sequentially reading data from the three memory areas in units of one frame. 8. An input section for inputting a video signal, video decoding means for decoding the video signal to output video data, and a memory area for storing the video data for one frame.
A memory having more than one memory, a write control means for sequentially writing the video data to the memory area in units of one frame, and a memory area immediately after the writing of one frame is completed by the control of the write control means. A signal processing apparatus comprising: a read control unit that controls reading of video data. 9. A signal processing for processing a DV compressed signal to which synchronization time information is added by the reference clock output from a clock generating means for generating a reference clock without referring to the synchronization time information and outputting the processed signal. The device is a frequency dividing means for dividing the reference clock to generate an output frame synchronization signal, an input means for inputting a DV compressed signal to which the synchronization time information is added, and the input DV. Separation means for separating the compressed signal into a video signal and an audio signal, a video processing means for decoding the video signal, performing a deshuffling process, and outputting in synchronization with the output frame synchronization signal, and a decoding process for the audio signal A signal processing device comprising: 10. The video decoding means according to claim 1, wherein the video decoding means generates an error signal when the correct decoding cannot be performed, and the write control circuit outputs the error signal to the memory in response to the error signal. A signal processing device characterized by stopping writing. 11. A signal processing apparatus according to claim 1, compression means for compressing a video signal output from the signal processing apparatus to generate compressed data, and output by the compression means. And a recording unit for recording the compressed data. 12. A signal processing apparatus according to claim 1, and a signal processing apparatus that reproduces a storage medium to perform D recording on the signal processing apparatus.
A reproducing apparatus comprising: a reproducing unit that outputs a V signal.