JP2003317400A - Controller for magnetic tape unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a controller for a magnetic tape unit in which data processing for the unit of a plurality of bytes is made possible, the width of a bus for data to be processed is expanded without complicating a circuit and expanding circuit scale and data transfer is accelerated. <P>SOLUTION: Data processing is performed for the unit of the plurality of bytes by a remaining byte preparing circuit 1 for preparing remaining bytes required for suiting data from a host 10 with a tape format, an error-correcting coding circuit 3 for preparing an error-correcting code for error correction, a deskew circuit 5 for correcting a deviation between data read out of an MTU 12, a syndrome preparing circuit 6 for preparing a syndrome for deciding the presence/absence of error in the read data, and a frame buffer 8 for holding (delaying) the data. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a magnetic tape device, and more particularly to a control device for realizing a large capacity, high functionality and high transfer speed of the magnetic tape device.

[0002]

2. Description of the Related Art With the increase in speed of computer systems in recent years, there has been a demand for higher speed in magnetic tape devices, which are peripheral devices. Therefore, it is necessary to increase the data bus width and improve the control method.

FIG. 2 is a block diagram of the tape subsystem. The tape subsystem is a host 1 as a host device.
0 and a magnetic tape unit (MTU:
A magnetic tape unit (MTC) that intervenes between the host computer 10 and the MTU 12 to perform data format conversion (MTC: Mag).
and a nete tape controller 11). When writing data, host 1
The data from 0 is input to the MTC 11, where the format conversion is performed and then the data is transferred to the MTU 12. When reading data, the read data from the MTU 12 is transferred to the MTC 11, where error correction is performed and format conversion is performed, and then the data is sent to the host 10. The MTC 11 is the host 1
Interface unit 1 for sending and receiving data with 0
1a, a data format section 11b that performs processing such as format conversion and error correction, and data D / A conversion / A
And a data conversion unit 11c that performs / D conversion.

FIG. 1 is a block diagram showing the internal structure of the data format section 11b of the MTC 11. The data format section 11b includes a write format section 11d for formatting for recording on the magnetic tape in the MTU 12. It is divided into a read format section 11e for correcting track deviation of data read from the magnetic tape and for detecting and correcting data errors.

The write format section 11d has a residual byte creation circuit 1, multiplexers 2 and 4, and an error correction coding circuit 3. The residual byte creating circuit 1 is a residual byte (RESIDUAL-BYT) necessary for adjusting the data from the host 10 to the tape format.
Create E). The multiplexer 2 has custom (CUSTOM) data from the host 10, residual bytes from the residual byte generation circuit 1, block (BLOCK) ID,
Pad (PAD) bytes, which are redundant bytes, are combined. The error correction coding circuit 3 uses an error correction code (ECC: Error Co) which is a check character for error correction.
redirection code). The error correction code is AXP (Adaptive Cross).
Parity code or Reed-Solomon (Reed-
The Solomon) code is often used. The multiplexer 4 includes the multiplexer 2 and the error correction coding circuit 3.
Combine the outputs of.

On the other hand, the read format section 11e is
The deskew circuit 5, the syndrome generation circuit 6, the error correction circuit 7, and the frame buffer 8 are included. The deskew circuit 5 corrects the deviation between the data read from the MTU 12. When the data recorded on the magnetic tape is read, the magnetic tape and the magnetic head are not generally perpendicular to each other, and an error angle is generated to some extent, and accordingly a shift (skew) between the data occurs. The deskew circuit 5 corrects the deviation between the data. The syndrome creating circuit 6 creates information called a syndrome for determining whether or not there is an error in read data. The error correction circuit 7 corrects an error in read data. The frame buffer 8 rearranges the data according to the data reading direction of the magnetic tape, and holds (delays) the data while the error correction circuit 7 calculates the error coefficient.

In the tape subsystem, one frame is generally composed of 18 bytes (14 bytes of data etc. and 4 bytes of error correction code (ECC)). In the conventional example, 8 bits or 9 bits are 1 As bytes, data is transferred byte by byte. The conventional configuration and operation of each circuit in the data format section 11b will be described below.

(Residual Byte Creating Circuit 1) FIG. 55 is a diagram showing an example of a data block format recorded on a magnetic tape. The data block starts with an "IBG" frame and an "ALL1" frame, then a "SYNC" frame for synchronization, and a "PREFIX0" and "PREFIX1" frame indicating the start of the data area are recorded. "SYNC" frame or "R"
The data group is repeated every 72 frames starting with the "ESYNC" frame.

69 frames of data (DATA) are recorded in the first data group, and 71 frames of data (DAT) are recorded in the second and subsequent data groups.
A) is recorded. Then, in the final data group, the remaining (n-1) frame data (DAT)
A) is recorded. After that, "RESID1""RES
Each frame of ID2, "COMP1", "COMP2", and "SYNC" is recorded, and finally "SYNC" and "ALL" are recorded.
Each frame of "1" is recorded.

"SYNC" frame and "RESYN"
The same 9-bit special code (100010001) is recorded in each of the "C" frames, and both frames have the same code. The sync signal or the resync signal is detected based on the "SYNC" frame or the "RESSYNC" frame. The synchronization signal or the re-synchronization signal is a signal that notifies the start of the data group and that triggers skew correction in the deskew circuit 5.

Block ID (BLOCK ID: BI
D) is composed of 4 bytes and is a block serial number. Since 1 frame has 14 bytes as a unit, depending on the number of bytes of custom data from the host 10, a byte (0 to 13 bytes) for the pawl is required to configure 14 bytes. It is called a pad byte (PAD BYTE). One byte of the residual byte count (RESIDUAL BYTE COUNT) indicates how many bytes the pad bytes are packed by the lower 4 bits, and the upper 4 bits contain other information.

[0012] Concretely, the data formats when the custom data from the host 10 is 12 bytes and 7 bytes are shown in FIGS. 56 and 57, respectively. In the case of 12 bytes shown in FIG. 56, the pad byte is 9 bytes, and 9 is entered in the remaining byte count. In the case of 7 bytes shown in FIG. 57, there is no need for pad bytes, so 0 is entered in the remaining byte count. As mentioned above,
Depending on the length of the custom data, a value from 0 to 13 will be in the residual byte count.

FIG. 58 shows the configuration of a conventional example of the residual byte forming circuit 1. The residual byte creation circuit 1 includes an AND (logical product) circuit 13, a NOR circuit 14, and a MOD 14 counter 1.
5 and. CK is a clock for operating the counter 15. -RSYNC is a RESYNC control signal that is generated every 72 frames, and when this signal is low, the operation of the counter 15 is stopped. WRB
K is a signal set from the register and is set only when the write block is started. SMDC
Indicates the end of the selection of the block ID when the frame data is created, and when this signal is low, it indicates that the block ID has ended, and the operation of the counter 15 is stopped. C
USTBLK goes high if it is a custom data or block ID. -CLR is a signal that is set from the register to clear the counter value, and is set at device initialization and during the "IBG" frame. -M
OD1 to -MOD8 are signals that represent the number of pad bytes, and the values represented by these signals are 1 of the residual byte count.
Reflected in the lower 4 bits of the byte.

One byte of the remaining byte count is mod1
4 counter 15 and the output value of the counter 15 represents the number of pad bytes. This counter 15 counts up the number of custom data and block ID,
The operation is stopped in the "RESSYNC" frame and when the ECC has 4 bytes.

The operation when the custom data is 8 bytes will be described. FIG. 59 shows the timing chart in that case, and FIG. 60 shows the output of the mod 14 counter 15.

The counter 15 is initialized at the time of device initialization and during the "IBG" frame. The counter value at this time is "0000". The firmware sets the WRBK signal from the register only at the beginning of the write block. The counter value at this time is "00
10 ". When it comes time to process custom data,
The CUSTBLK signal is set, and the counting operation of the counter 15 is started. When the block ID ends, SM
The DC signal is reset and the counting operation is stopped. Counter value when the count operation is stopped ("0010")
Value of "-MOD1" to "-MOD8"("11
01 "= 13) enters the lower 4 bits of the residual byte count.

(Error Correction Coding Circuit 3) In the error correction system using the AXP code, 14 out of 18 tracks are used.
One frame of data is written in each of the 14 tracks, and error correction codes for the data of these 14 tracks are written in the remaining 4 tracks. The error correction code is DRC (Diagonal Redundancy).
y Check) character and VRC (Vertic)
al Redundancy Check) character. All 18 tracks are divided into set A of 9 odd tracks and set B of even tracks.

The DRC is recorded on the 0A track and the 0B track in the error correction code track. This DR
The 2 bytes of C are calculated from other than VRC (15 bits) recorded in another track, and the m-th value is as follows.

A0 _m = (A1 _m-1 + A2 _m-2 + A3 _m-3 + ... + A7 _m-7 + B7 _m-8 + B6 _m-9 + B5 _m-10 + ... + B0 _m-15 ) _MOD2 B0 _m = (B1 _m-1 + B2 _m-2 + B3 _m-3 + ... + B7 _m-7 + A7 _m-8 + A6 _m-9 + A5 _m-10 + ... + A0 _m-15 ) _MOD2

FIG. 61 is a diagram for explaining the principle of a conventional DRC creating method, and FIG. 62 is an actual DR of user data.
FIG. 63 is a diagram showing a result of calculating CA and DRCB, and FIG. 63 is a diagram showing a configuration of a conventional DRC creating circuit. The DRC creation circuit has a circuit system consisting of one bit matrix array 81 for obliquely taking in data by adjusting the clock timing and three FF arrays 82 corresponding to each frame, one for set A and one for set B. We have each group,
The output from each circuit system is the VR from the VRC creating circuit 83.
Together with CA and VRCB at multiplexer 84.

Since the DRC is a diagonal redundancy check, the data is checked by adding redundant data in the diagonal direction. At this time, since the data is taken in diagonally, the DRC is created across the data of three adjacent frames, and even parity is taken bit by bit for the data in the diagonal direction excluding VRC. Create a DRC with.

VRC is recorded on the 8A track and the 8B track in the track for error correction code. This VR
2 bytes of C are set A (7-bit data + DRC
A) and set B (7-bit data + DRCB) are calculated, and the m-th value is as follows.

A8 _m = (A0 _m + A1 _m + A2 _m + ...
. + A7 _m ) _MOD2 However, A0 _m : DRCA A1 _m , A2 _m , ... A7 _m : Data B8 _m = (B0 _m + B1 _m + B2 _m + ... + B7 _m )
_MOD2 However, B0 _m : DRCB B1 _m , B2 _m , ... B7 _m : Data

FIG. 64 is a diagram for explaining the principle of a conventional VRC creating method, and FIG. 65 is an actual VR of user data.
FIG. 66 is a diagram showing a result of calculating CA and VRCB, and FIG. 66 is a diagram showing a configuration of a conventional VRC creating circuit. The VRC creating circuit 85 is divided into a VRCA creating circuit 86 for creating VRCA and a VRCB creating circuit 87 for creating VRCB, each of which has eight JK flip-flops for toggle operation.

Since VRC is a vertical redundancy check,
Data is checked by adding redundant data in the vertical direction. At this time, since data is taken in in the vertical direction, VRC is created within one frame. Two creation circuits 86 and 87 for VRCA and VRCB as a whole
It is composed of (8 bits), and when 1 byte is input in set A, it is input to the circuit corresponding to each bit of VRCA, and when 1 byte is input in set B, it is input to the circuit corresponding to each bit of VRCB. . VRC
A bit 1 is byte 1, 2, 3, 4, 5, 6, 7, DR
Input bit 1 of CA. The VRCA bit 2 receives the bytes 1, 2, 3, 4, 5, 6, 7, and bit 2 of DRCA as an input. Others are the same.

Since data is input byte by byte, only 1 bit is input to the 1 bit VRC generation circuit at one timing. 1 bit each of set A and set B is 7 bits of vertical data and DRC1.
This is the same as having even parity for bits.
That is, VRCA is the same as taking even parity between data bytes 1-7 and DRCA, and VRCB is the same as taking even parity between data bytes 8-14 and DRCB.

In the circuit configuration shown in FIG. 66, the data acquisition timing is controlled by CK and the timing signal.
Even parity is taken by inputting the data to the JK flip-flop which operates in the toggle mode. The data input order in one frame is as follows, and 18 timings are required to operate one frame. Data input order Timing (1) (2) (3) (4) (5) (6) Byte 1 2 3 4 5 6 Timing (7) (8) (9) (10) (11) (12) Byte 7 DRCA VRCA 8 9 10 Timing (13) (14) (15) (16) (17) (18) Byte 11 12 13 14 DRCB VRCB

A Reed-Solomon code is used as an error correction code for a 36-track magnetic tape device. When the primitive element on the Galois field GF (q) is α, α ^h , α ^{h + 1} , α ^{h + 2} , ..., α ^{h + d-2} (0 ≦ h <q
-1, 2, ≤ d ≤ q) is a Reed-Solomon code, which is a q-ary cyclic code with a code length n = q-1 and is a device that handles digital signals.
In the case of q = 2 ^m and h = 0, which are important for practical use, code length n = 2 ^m −1 information points k = 2 ^m −d inspection points n−k = d−1 minimum distance d _min = d = n−k + 1 becomes 2 ^m original code, generator polynomial G (x), G (x) = (x -α d-2) ··· (x-α 2) (x-
α) (x-1), which is a polynomial whose roots are α ^d-2 , ..., α ² , α, 1. Arbitrary code polynomial C of Reed-Solomon code
(X) has α ^d−2 , ..., α ² , α, 1 as a root.

In other words, GFs of order n−1 or less
The necessary condition for the polynomial C (x) on (2 ⁸ ) to be a code polynomial is that C (α ⁰ ) = 0 C (α ¹ ) = 0 ... C (α ^d-2 ) = 0 , i _j a (0 ≦ j ≦ k-1 ) as the original ^{GF (2 8), k ≦} 2 8 k pieces of information word i ₀ is -d, i _1, ··
., I _k-1 is encoded, I (x) = i _k-1 x ^k-1 + ... + i ₂ x ² + i ₁ x +
An information polynomial I (x) called i ₀ is created.

Next, I (x) is multiplied by x ^d-1, and the remainder polynomial when divided by the generator polynomial G (x) is D (x). If the quotient polynomial in this case is Q (x), the relationship between these polynomials is as follows. I (x) × x ^d−1 = Q (x) × G (x) + D (x) Here, since the remainder polynomial D (x) is a polynomial of order x ^d−2 or less, D (x) = d _d-2 × x ^d-2 + ・ ・ ・ + d ₂ × x ² + d ₁
Let xx + d ₀ . The polynomial (code polynomial) corresponding to the code is G
Since it must be divisible by (x), C (x) = Q (x) × G (x) = I (x) × x ^d-1 + D (x) [subtraction and addition on GF are the same] , C (x), the n-dimensional vector on GF (2 ⁸ ) is C = (c _n−1 , ..., C ₂ , c ₁ , c ₀ ) = (i _k−1 , ... .., i ₂ , i ₁ , i ₀ , d _d-2 , ..., d ₁ , d ₀ ). This is the code word of the Reed-Solomon code for the information words i ₀ , i ₁ , ..., I _k-1 . The inspection words d _d-2 , ..., d ₁ , d ₀ are information words i ₀ , i ₁ ,.
.., i _k-1 is obtained using the polynomial division as described above. Also, the inspection bytes d ₃ , d ₂ , d ₁ , d ₀
Can be derived using a check matrix.

If a polynomial of degree n−1 or less on GF (2 ^m ) has α ^d-2 , ..., α ² , α, 1 as a root, the parity check matrix H and the Reed-Solomon code are The product of the code word C and the transposed matrix C ^t is a zero matrix.

[0032]

[Equation 1]

Here, this determinant can be rewritten as follows.

[0034]

[Equation 2]

This equation is expressed as the following determinant, and using the Kramel formula, d _d-2 , ..., d ₁ , d
_{If 0} is solved, the check word can be obtained by a multiplication process and an addition process using a _{0 to} a _d-2 and a power of α.

[0036]

[Equation 3]

A circuit configuration for executing the above encoding will be described. FIG. 67 shows a circuit configuration in the case of performing division by a generator polynomial, which employs a feedback register called LFSR (linear feedback shift register), and is composed of an adder circuit 25, a register 26, and a power-of-α multiplication circuit 27. , Information words are sequentially input in 1-byte units, that is, division is performed with the first input byte for constructing an information polynomial as the most significant byte,
Find the remainder when the least significant byte is input.

The circuit for encoding by the check matrix is the circuit for calculating the sum of information words shown in FIGS. 68 and 69 and a ₀ , a ₁ , ..., _Ad-2 , d ₀ , d _1. ,,, d
_A circuit for performing multiplication and addition of powers of α to obtain _d-2 is required.

At this time, the circuit for calculating the total sum needs to sequentially multiply each byte of the information word by the power of α,
^{Usually, α 0, α 1, α} 2, ···, a simple multiplication circuit 27 is configured to multiply the alpha ^n-1 combination of an adder circuit 25 and the register 26, multiplied by 1 byte - adding ─ The sum is obtained by repeatedly calculating the retention.

(Syndrome creating circuit 6) The target code word is {D ₀ , D ₁ , D ₂ , ..., D _n-2 , D _n-1 }.
And This is first stored in memory. For example, in the case of performing error correction processing with the Reed-Solomon code, when the Hamming distance is D _min , the error correction capability is the maximum integer that does not exceed D _min / 2. Such an integer is (D _min −
1), and when obtaining this, the following syndrome calculation is performed.

When the polynomial representing the received word is R (x), the decoding of the Reed-Solomon code is based on this R (x) and the syndrome Si = R (α ⁱ ) (i = 0, 1, 2, 3, ... .., d-
2) Start by calculating This is GF (2
^m ) The constant multiplication above, that is, the multiplication of α ⁱ .

As a calculation method of such a syndrome,
A method has been performed in which n pieces of data stored in the memory are sequentially input to the multiplication circuit of α ⁱ one by _one from D _n−1 and the output is obtained as a result of the syndrome after inputting all the data.

According to the conventional technique, since data is read one by one (1 byte) from the memory, there is a problem that a processing time is significantly delayed when a memory with a slow access is used.

(Deskew Circuit 5) FIG. 70 is a view showing an example of a data block format recorded on a slanted track of a magnetic tape, and FIG. 71 is a partially enlarged view of FIG. 70 showing the data block format in bit units. is there. 70 and 71, the same frames as those in FIG. 55 are given the same abbreviations such as SYNC and RESYNC. As shown in FIG. 70, it is the forward (FWD) direction (forward direction) that records or reproduces frames sequentially from the beginning from left to right, and the opposite direction is the backward (BWD) direction (reverse direction). Direction).

FIG. 72 is a block diagram showing the internal structure of the conventional deskew circuit 5. The data (DATA) sent from the MTU 12 that employs the data block format shown in FIGS. 70 and 71 has irregularities between tracks, and these data are once written to a memory called a deskewing buffer, and skewed. After the correction, the data is read from the deskewing buffer and transmitted to the syndrome creating circuit 6 and the buffer memory 8 for error correction.

In order to reduce the memory capacity used for the deskewing buffer, as shown in FIG. 72,
Three deskewing buffers 42A, 42B, 42
It is composed of C. Each deskewing buffer 42
A, 42B and 42C are 6 out of the data of 18 tracks.
Each is responsible for each track. Further, deskew control circuits 41A, 41B, 41C and multiplexers 43A, 43B, 43C associated with the deskewing buffers 42A, 42B, 42C are also constituted by three systems for every 6 tracks. 44 is each multiplexer 43
It is a 9-8 conversion circuit that converts the 9-bit output of A, 43B, and 43C into 8-bit.

Each deskewing buffer 42A, 42
B and 42C divide the internal memory area into 6 according to the address (A, B, C, D, E, F), and divide the sync signal (resync signal) from one track into the sync signal (resync signal) in each of the divided areas. Data of 72 frames up to the synchronization signal) is written.

73 to 76 are diagrams showing write / read control in the FWD direction in the deskewing buffers 42A, 42B and 42C, and FIGS. 77 to 80 are
It is a figure which similarly shows write / read control in the BWD direction.

As an example, the operation of the deskew control circuit 41A and deskewing buffer 42A in the FWD direction will be described. In each inclined track on the magnetic tape, a track in which 1-byte data (9-bit data) is complete is sequentially written into each divided memory area. First, the 1A-track data is written to the memory area (position A) allocated to the 1A-track of the deskewing buffer 42A. Similarly, 4A-
Track data is position B, 7A-track data is position C, 7B-track data is position D, 4B
-The data of the track is written in the E position and the data of the 1B-track is written in the F position (see Fig. 73).

Similarly, the deskewing buffer 4
Also in 2B and 42C, the data of each track is written in the corresponding memory area (FIGS. 74 and 75).
reference). As described above, the writing of data for 18 tracks is completed.

When the writing of data is completed, the reading of each 1-byte data (1-byte data transfer) starts.
According to the read order shown in FIGS. 73 to 75, the read data from the deskewing buffers 42A, 42B and 42C are transferred to the multiplexers 43A, 43B and 43, respectively.
It is selected by C and output to the 9-8 conversion circuit 44 in the order shown in FIG. 76 which is suitable for the error correction method. Since the data on the magnetic tape is 9-bit data, the 9-8 conversion circuit 4
It is converted to 8-bit data at 4 and sent to the error correction processing system at the subsequent stage.

In the BWD direction, the data write position of each track is different from that in the FWD direction, but since the basic processing procedure is the same, its description is omitted.

The data sent from the MTU 12 is once written into the deskewing buffer and then read out to perform skew correction and data transfer. At this time, since 1 byte data transfer is used conventionally, 1
It takes 18 reads from the deskewing buffer to transfer the frame data. Therefore, there is a problem that it is not suitable for high-speed processing. Also, FWD
The data sent from the MTU 12 have different bit definitions depending on the direction and the BWD direction, and there is a difference in the track order in which 1-byte data (9-bit data) is aligned. It was necessary to transfer 1-byte data in the order corresponding to. As described above, in the conventional example, the allocation of the six divided memory areas in each deskewing buffer is different in the FWD direction and the BWD direction, and different write / read control is required in the FWD direction and the BWD direction. There is a problem.

(Data Transfer Control in Read Format Unit 11e) Conventionally, when transferring data, as a method of temporarily storing the data and switching the transfer timing, an element such as a multiplexer (selector) or a flip-flop is used. A method of controlling the transfer method using is generally used. However, in order to perform error correction corresponding to high-density and high-speed data transfer, and to support data writing / reading operations in the FWD and BWD directions, simply add a memory element or use a selector to handle each case. However, the method of performing the switching control has a problem that the circuit becomes complicated and the scale of the circuit is increased.

As described above, in the control device of the conventional magnetic tape device, the write format section 11d and the read format section 11 in the data format section 11b.
In e, since processing is performed in 1-byte units,
There is a problem that the processing speed is slow. In order to increase the processing speed, it is conceivable to add an element configuring each circuit in the data format section 11b to speed up the data transfer, but in this case, the circuit scale increases and the complexity increases. There is a problem of inviting.

The data from the host device is compressed and output to the magnetic tape device, and the compressed data from the magnetic tape device is restored and output to the host device. There is known a magnetic tape control device in which the format is converted and is output in parallel to the magnetic tape device in units of 18 bits (for example, refer to Patent Document 1). There is also known a magnetic tape control device that determines whether the number of bytes of data read from a connected magnetic tape is an even number or an odd number, and switches the processing based on the determination result (for example, Patent Document). Reference 2).

[0057]

[Patent Document 1] JP-A-5-204552

[Patent Document 2] Japanese Patent Laid-Open No. 63-211169

The present invention has been made in view of the above circumstances, and is capable of processing in units of a plurality of bytes, does not complicate the circuit, and does not increase the circuit scale, and the data bus width to be processed. It is an object of the present invention to provide a control device for a magnetic tape device, which is capable of increasing the number of times and speeds up data transfer.

[0059]

According to a first aspect of the present invention, a control device for a magnetic tape device adds an error correction code to data input from a host device, converts the format, and transfers the format-converted data to a magnetic tape unit. In addition, in the controller of the magnetic tape device that performs error correction on the data read from the magnetic tape unit, performs format conversion, and transfers the format-converted data to the upper device, a plurality of bytes for the input data from the upper device. It is characterized in that error correction encoding processing is performed in units and / or error correction processing is performed in units of a plurality of bytes with respect to read data from the magnetic tape unit.

In the present invention, the configuration of each circuit in the control device of the magnetic tape device is devised so that the data from the host device and the read data from the magnetic tape unit can be processed in units of a plurality of bytes. Therefore, the speed of data processing is increased as compared with the conventional example in which processing is performed in 1-byte units.

According to a second aspect of the present invention, in the magnetic tape device control apparatus according to the first aspect, the number of bytes in each frame is predetermined when the data from the host device is formed into one frame of a predetermined number of bytes. A counting means for counting the number of remaining bytes so that the number becomes a number, and the counting means determines whether the number of bytes of the data from the higher-order device is an odd number or an even number; and depending on the determination result. Means for switching the counting method of the remaining bytes.

The counting means for counting the remaining bytes changes the counting method according to whether the number of bytes of the data from the host device is odd or even, and inputs from the host device in units of 2 bytes. It can correspond to the data that is

According to a third aspect of the present invention, a control device for a magnetic tape device according to the first aspect comprises error correction coding means for creating an AXP error correction code for the data from the higher-level device, and the error correction coding is provided. The means is configured to input a plurality of bytes of data from the host device to create an AXP error correction code.

According to a fourth aspect of the present invention, there is provided a magnetic tape device control apparatus according to the third aspect, wherein the error-correction coding means uses AXP error-correction code D from data over a plurality of frames.
As a circuit for creating an RC, one selection circuit that selects data from a plurality of frames and a control circuit that controls masking of data from each frame to the selection circuit are provided, It is characterized in that it is configured so as to be selected separately for each.

According to a fifth aspect of the present invention, there is provided a magnetic tape device control apparatus according to the third aspect, wherein the error correction coding means uses the AXP error correction code D from data over a plurality of frames.
As a circuit for creating the RC, it has the same number of selection circuits as the number of a plurality of frames for selecting data for each frame, and a switching circuit for switching the outputs of the plurality of selection circuits. It is characterized in that it is configured so as to be distinguished and selected.

In order to correspond to the data of a unit of a plurality of bytes from the host device, it is only necessary to take the parity for a plurality of bits at the same time when creating the DRC and VRC of the APX error correction code.
That is, it suffices to select each of a plurality of bits required to create the DRC and VRC, and obtain the parity with the selected plurality of bits.

Specifically, when a DRC is created from data over a plurality of frames, unnecessary data in each frame is masked, and only the necessary data in each frame is selected and selected for each frame. The parity of the plurality of data is calculated. Alternatively, the necessary data for each frame is selected by a selection circuit provided corresponding to each frame, the output of each selection circuit is switched, and the parity of the obtained plurality of data is obtained.

According to a sixth aspect of the present invention, there is provided a magnetic tape device control apparatus according to the first aspect, further comprising error correction coding means for creating a Reed-Solomon error correction code for the data from the higher-order device. The digitizing means is configured to process a plurality of summations of information words in parallel.

When a Reed-Solomon error correction code is created, since a plurality of summations of information words are processed in parallel, the coding processing time is shortened and it is possible to handle data input in units of a plurality of bytes.

According to a seventh aspect of the present invention, in a magnetic tape device control apparatus according to the first aspect, there is provided a syndrome creating means for creating a syndrome necessary for correcting an error in data read from the magnetic tape unit according to the Reed-Solomon method. The syndrome creating means has a plurality of circuits for multiplying a received word by a check matrix, and is configured to create a syndrome in parallel for a plurality of bytes of data.

When a syndrome is created, a plurality of circuits for multiplying a received word by a check matrix are operated in parallel, whereby a syndrome can be created in parallel for a plurality of bytes of data. It is possible to handle read data in units of multiple bytes from the unit.

[0072]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be specifically described below with reference to the drawings showing the embodiments thereof.

FIG. 2 is a block diagram of the tape subsystem, FIG.
Is the data format section 11b of the MTC 11 shown in FIG.
3 is a block diagram showing the internal configuration of FIG. The tape subsystem is composed of a host 10 as a host device, an MTU 12 that records data, and an MTC 11 that is interposed between the host 10 and the MTU 12 to perform data format conversion. At the time of writing data, the data from the host 10 is input to the MTC 11, where the format conversion is performed and then the data is transferred to the MTU 12. When reading data, the read data from the MTU 12 is transferred to the MTC 11, where error correction is performed and format conversion is performed, and then the data is sent to the host 10.

The MTC 11 has an interface section 11a for transmitting / receiving data to / from the host 10, a data format section 11b for processing such as format conversion and error correction, and D / A conversion / A / D conversion of data. The data conversion unit 11c. Data format section 11
Reference numeral b denotes a write format unit 11d that performs formatting for recording on a magnetic tape, and a read format unit 11 that corrects a track deviation of data read from the magnetic tape and performs error detection and correction of data.
It is divided into e and.

The write format section 11d has a residual byte forming circuit 1, multiplexers 2 and 4, and an error correction coding circuit 3. The residual byte creation circuit 1 creates the residual bytes required to match the data from the host 10 to the tape format. Multiplexer 2
Combines the custom data from the host 10, the residual byte from the residual byte generation circuit 1, the block ID, the pad byte which is a redundant byte, and the like. Error correction coding circuit 3
Creates an error correction code that is a check character for error correction. An AXP code or a Reed-Solomon code is often used as the error correction code. The multiplexer 4 couples the outputs of the multiplexer 2 and the error correction coding circuit 3.

On the other hand, the read format section 11e
The deskew circuit 5, the syndrome generation circuit 6, the error correction circuit 7, and the frame buffer 8 are included. The deskew circuit 5 corrects the deviation between the data read from the MTU 12. When the data recorded on the magnetic tape is read, the magnetic tape and the magnetic head are generally not perpendicular to each other, and an error angle is generated to some extent, so that a deviation between the data occurs accordingly. The deskew circuit 5 corrects the deviation between the data. Syndrome creation circuit 6
Creates information called a syndrome for determining whether or not there is an error in read data. Error correction circuit 7
Corrects an error in read data. The frame buffer 8 rearranges the data according to the data reading direction of the magnetic tape, and holds (delays) the data while the error correction circuit 7 calculates the error coefficient.

As described above, the tape subsystem in the present invention and the MTC 11 have the same basic configuration as the conventional example, but the internal configuration and processing operation of each circuit constituting the data format section 11b in the MTC 11 are different. . That is, in the conventional example, processing is performed with a width of 1 byte, but in the present invention, processing is performed with a width of a plurality of bytes to speed up data processing. Therefore, in the present invention, the data bus in FIG.
Is an integer greater than or equal to 2) times.

The configuration and operation of each circuit in the data format section 11b according to the present invention will be described in detail below.
In the following embodiments, a case will be described in which the write format unit 11d can perform processing with a 2-byte width and the read format unit 11d can perform processing with a 3-byte width.

(Residual Byte Creating Circuit 1) In the present invention, the write format section 11d performs processing by doubling the data width from the conventional 1 byte width to 2 bytes width.
High-speed (twice as much as conventional) data processing can be performed. Therefore, the residual byte creating circuit 1 of the present invention can cope with the conventional 2-byte processing from the conventional 1-byte processing. In the present invention, mod14 used in the conventional example
The operation of the counter corresponds to the 2-byte processing.

The configuration of the present invention of the residual byte forming circuit 1 is shown in FIG. The residual byte creation circuit 1 has two AND circuits 13a and 13b, a NOR circuit 14, and a MOD 14 counter 15. CK is a clock for operating the counter 15. -RSYNC is a RESYNC control signal that is generated every 72 frames, and when this signal is low, the operation of the counter 15 is stopped. WR
BK is a signal that is set from the register and is set only when the write block is started. SMD
C indicates the end of the selection of the block ID when the frame data is created, and when this signal is low, the block ID
Indicates that the counter has finished, and the operation of the counter 15 is stopped.
CUSTBLK is custom data or block ID
Goes high if. -CLR is a signal that is set from the register to clear the counter value, and is set at device initialization and during the "IBG" frame. B
ID3 is a signal generated in the write format unit 11d, and is set when the third byte of the block ID is being processed. ODD is a signal generated in the write format unit 11d and is used by the host 10
When the custom data is transferred from, it is determined whether it is an odd byte or an even byte, and if it is an odd byte, it is set. -MOD1 to -MOD8 are signals representing the number of pad bytes, and the values represented by these signals are reflected in the lower 4 bits of 1 byte of the residual byte count.

4 and 5, the custom data is 8 bytes,
Timing chart for 9 bytes, MO for FIG.
The outputs of the D14 counter 15 are shown. The byte of the remaining byte count is mod14 that supports 2-byte processing.
It is realized by the counter 15, and the output value of the counter 15 represents the number of pad bytes. This counter 15 counts up the number of custom data and block ID, and
The operation is stopped during the "ESYNC" frame and when the error correction code (ECC) is 4 bytes. Further, depending on the number of bytes of custom data, there are cases of even bytes and cases of odd bytes, and it is necessary to satisfy two types of operations, even and odd.

Next, the operation when the custom data is 9 bytes will be described. At device initialization and "IB
The counter 15 is initialized during the "G" frame.
The counter value at this time is "0000". The firmware sets the WRBK signal from the register only at the beginning of the write block. The counter value at this time is "0010". When it comes time to process the custom data, the CUSTBLK signal is set and the counting operation of the counter 15 is started. The counter operation counts up by +2. When the BID3 signal is set and the ODD signal is set, the operation of the counter 15 transits to the table on the right side of FIG. When the block ID ends, the SMDC signal is reset and the counting operation is stopped. -MOD1 to -MO, which are inverted signals of the counter value ("0011") when the counting operation is stopped
The value of D8 ("1100" = 12) enters the lower 4 bits of the residual byte count.

(Error Correction Encoding Circuit 3) [AXP Encoding System] FIGS. 7 and 8 are diagrams showing the configuration of the DRC creating circuit of the present invention, and FIG. 9 is a diagram showing the configuration of the VRC creating circuit of the present invention. is there. This configuration example is an example when a plurality of bytes (2 bytes) are input. The DRC creation circuit is divided into two systems, one for set A (FIG. 7) and one for set B (FIG. 8). The DRC creation circuit for set A (for set B) is the data selection unit 21A (21B). A data parity creation unit 22A (22B) and a frame control unit 23A (2
3B), a data mask section 24A (24B), and a timing control circuit (not shown).

The DRC and VRC basically take the parity of the bits in the diagonal direction and the vertical direction, respectively. 1
VRC, a conventional DRC generation circuit that inputs bytes by byte
In the creating circuit, the parity was taken for each bit in each circuit, but the DRC of the present invention in which a plurality of bytes are input
In the creating circuit and the VRC creating circuit, it is only necessary to simultaneously take a plurality of bits of parity in each circuit. This is DRC, V
This can be realized by selecting each of a plurality of bits required to create the RC and obtaining the parity with the selected plurality of bits.

Next, the operation will be described. The formula for calculating DRC and VRC of AXP code is the same when inputting one byte at a time and when inputting a plurality of bytes at a time, so the m-th value calculated in each of set A and set B of DRC and VRC. Is as follows.

DRC A0 _m = (A1 _m-1 + A2 _m-2 + A3 _m-3 + ... + A7 _m-7 + B7 _m-8 + B6 _m-9 + B5 _m-10 + ... + B0 _m-15 ) _MOD2 B0 _m = (B1 _m-1 + B2 _m-2 + B3 _m-3 + ... + B7 _m-7 + A7 _m-8 + A6 _m-9 + A5 _m-10 + ... + A0 _m-15 ) _MOD2

VRC A8 _m = (A0 _m + A1 _m + A2 _m + ... + A7 _m )
_MOD2 However, A0 _m : DRCA A1 _m , A2 _m , ... A7 _m : Data B8 _m = (B0 _m + B1 _m + B2 _m + ... + B7 _m )
_MOD2 However, B0 _m : DRCB B1 _m , B2 _m , ... B7 _m : Data

Since the input data is 2 bytes each, 1
The frame timing is 9 timings. FIG. 10 is a chart showing the relationship between the input data and timing, and FIG. 11 is a diagram for explaining the principle of the DRC creating method of the present invention. When data is input as shown in FIG. 10 when creating a DRC, the input data is 2 bytes (B
S1, 2, 3, 4, 6, 7, ECC1) or 1
Although it is a byte (in the case of BS5 and ECC2), it is 1 bit out of the input even (EVEN) byte and odd (OD
D) Select 1 bit of the byte to select data and create 1 bit of DRC. Data frame 3-DR
Since the CA bit 7 is created for the data bits c1 to cF, the other data bits do not have any value. The same applies to the data frame 4-DRCA bit 7 and the data frame 5-DRCA bit 7.

For example, the data targeted when creating the DRCA-bit 7 of the data frame 3 is data frame 2-byte 8-bit 7 (c8), byte 9-bit 6 (c9), byte 10-. Bit 5 (cA), byte 11-bit 4 (cB), byte 12-bit 3 (c
C), byte 13-bit 2 (cD), byte 14-bit 1 (cE), DRCB-bit 0 (cF), data frame 3-byte 1-bit 6 (c1), byte 2-
Bit 5 (c2), byte 3-bit 4 (c3), byte 4-bit 3 (c4), byte 5-bit 2 (c
5), byte 6-bit 1 (c6), byte 7-bit 0 (c7). Similarly, the DRC of data frame 4
The data targeted when creating the A-bit 7 is the data frame 3-byte 8-bit 7 (a8), byte 9-bit 6 (a9), byte 10-bit 5 (a
A), byte 11-bit 4 (aB), byte 12-bit 3 (aC), byte 13-bit 2 (aD), byte 14-bit 1 (aE), DRCB-bit 0 (a
F), data frame 4-byte 1-bit 6 (a
1), byte 2-bit 5 (a2), byte 3-bit 4 (a3), byte 4-bit 3 (a4), byte 5-
Bit 2 (a5), byte 6-bit 1 (a6), byte 7-bit 0 (a7). Further, the data targeted when creating the DRCA-bit 7 of the data frame 5 is the data frame 4-byte 8-bit 7 (b
8), byte 9-bit 6 (b9), byte 10-bit 5 (bA), byte 11-bit 4 (bB), byte 12-bit 3 (bC), byte 13-bit 2 (b
D), byte 14-bit 1 (bE), DRCB-bit 0 (bF), data frame 5-byte 1-bit 6
(B1), byte 2-bit 5 (b2), byte 3-bit 4 (b3), byte 4-bit 3 (b4), byte 5-bit 2 (b5), byte 6-bit 1 (b6),
Byte 7-bit 0 (b7).

If even parity is taken with respect to the data in the diagonal direction as the target as described above, one bit of DRCA is created. Then, the DRC can be created by sequentially performing the same processing for each bit.

Considering the DRCA bit unit, as can be seen from FIG. 11, since the DRC is created for diagonal data, it extends over a plurality of frames (2 to 3 frames). Therefore, the data to be selected is divided into three control frames. For example, data frame 3
Considering the above, the data in the one frame is divided into three as data for creating the DRCA of the control frames 0, 1 and 2, and the data selected does not overlap.

Comparing the data frames 3, 4, and 5,
It can be seen that depending on how the data is selected, the bit of the byte and the bit of the DRC are always selected. Although the control frame selected is different, it can be seen which bit of the DRC is selected. For example byte 1
Bit 6 of the data frame 3 (c1) is DRCA
7 of the data frame, data frame 4 (a1) is selected as bit 7 of DRCA, and data frame 5 (b1) is selected as bit 7 of DRCA. Also, bit 0 of byte 1 is bit 1 of DRCA in data frame 3, bit 1 of DRCA in data frame 4, and DR in data frame 5.
Selected as bit 1 of CA.

Therefore, bit 1 of byte 1 is always D
Bit 2 of RCA is selected and bit of byte 2 is DR
Selected as bit 2 of CA. Therefore, it suffices to control whether or not the data is taken in by the DRC generation circuit of the control frames 0, 1. Another point to consider is that the DRC is created over three frames, so for example, the DRC output when the data frame 3, 4 or 5 is actually handled.
Is the point that must be created at the same time. Therefore, it is understood that it is necessary to have a DRC creation circuit for at least 3 frames.

The method of selecting data will be described in a little more detail. When the data of the data frame 3 (control frame 2) is input, which bit should be selected as the generation circuit of the DRCA will be described.

Bit 0 of byte 1 is D of control frame 2
RCA-bit 1, bit 1 is DRCA-bit 2, bit 2 is DRCA-bit 3, bit 3 is DRCA-bit 4, bit 4 is DRCA-bit 5, bit 5 is D
RCA-bit 6, bit 6 (c1) is DRCA-bit 7, bit 7 is DRCA-bit 0 of control frame 0, bit 0 of byte 2 is DRCA- of control frame 2
Bit 2, Bit 1 is DRCA-bit 3, Bit 2 is DRCA-bit 4, Bit 3 is DRCA-bit 5,
Bit 4 is DRCA-bit 6, bit 5 (c2) is D
RCA-bit 7, bit 6 is DRC of control frame 0
A-bit 0, bit 7 is DRCA-bit 1, bit 0 of byte 3 is DRCA-bit 3 of control frame 2,
Bit 1 is DRCA-bit 4, bit 2 is DRCA-
Bit 5 and bit 3 are DRCA-bit 6 and bit 4
(C3) is DRCA-bit 7, bit 5 is DRCA-bit 0 of control frame 0, bit 6 is DRCA-bit 1, bit 7 is DRCA-bit 2, bit 0 of byte 4 is DRCA-bit of control frame 2 4, bit 1
Is DRCA-bit 3, bit 2 is DRCA-bit 2, bit 3 (c4) is DRCA-bit 1, bit 4
Is DRCA of control frame 0-bit 0, bit 5 is D
RCA-bit 1, bit 6 is DRCA-bit 2, bit 7 is DRCA-bit 3, bit 5 of byte 5 is DRCA-bit 5 of control frame 2, bit 1 is DRC
A-bit 6, bit 2 is DRCA-bit 7, bit 3 is DRCA-bit 0 of control frame 0, bit 4 is DRCA-bit 1, bit 5 is DRCA-bit 2,
Bit 6 is DRCA-bit 3, bit 7 is DRCA-
Bit 4, bit 0 of byte 6 is DR of control frame 2
CA-bit 6, bit 1 (c6) is DRCA-bit 7, bit 2 is DRCA-bit 0 of control frame 0,
Bit 3 is DRCA-bit 1, bit 4 is DRCA-
Bits 2 and 5 are DRCA-bit 3, Bit 6 is DRCA-bit 4, Bit 7 is DRCA-bit 5,
Bit 0 of byte 7 is DRCA-bit 7 of control frame 2, bit 1 is DRCA-bit 0 of control frame 0, bit 2 is DRCA-bit 1, bit 3 is DRC.
A-bit 2, bit 4 is DRCA-bit 3, bit 5 is DRCA-bit 4, bit 6 is DRCA-bit 5, bit 7 is DRCA-bit 6, bit 0 of byte 8 is DRCA-bit of control frame 0 0, bit 1 is DRCA-bit 1, bit 2 is DRCA-bit 2,
Bit 3 is DRCA-bit 3 and bit 4 is DRCA-
Bit 4 and bit 5 are DRCA-bit 5, bit 6 is DRCA-bit 6, bit 7 (a8) is DRCA-bit 7, bit 0 of byte 9 is DRC of control frame 0
A-bit 1, bit 1 is DRCA-bit 2, bit 2 is DRCA-bit 3, bit 3 is DRCA-bit 4, bit 4 is DRCA-bit 5, bit 5 is DRC
A-bit 6, bit 6 (a 9) is DRCA-bit 7, bit 7 is DRCA-bit 0 of control frame 1,
Bit 0 of byte 10 is DRCA-bit 2 of control frame 0, bit 1 is DRCA-bit 3, bit 2 is D
RCA-bit 4, bit 3 is DRCA-bit 5, bit 4 is DRCA-bit 6, bit 5 (aA) is DR
CA-bit 7 and bit 6 are DRCA of control frame 1
-Bit 0, bit 7 is DRCA-bit 1, byte 1
Bit 0 of 1 is DRCA-bit 3 of control frame 0,
Bit 1 is DRCA-bit 4, bit 2 is DRCA-
Bit 5 and bit 3 are DRCA-bit 6 and bit 4
(AB) is DRCA-bit 7, bit 5 is DRCA-bit 0 of control frame 1, bit 6 is DRCA-bit 1, bit 7 is DRCA-bit 2, bit 0 of byte 12 is DRCA-bit of control frame 0 4, bit 1 is DRCA-bit 5, bit 2 is DRCA-bit 6, bit 3 (aC) is DRCA-bit 7, bit 4
Is DRCA of control frame 1-bit 0, bit 5 is D
RCA-bit 1, bit 6 is DRCA-bit 2, bit 7 is DRCA-bit 3, bit 0 of byte 13 is DRCA-bit 5 of control frame 0, bit 1 is DR
CA-bit 6, bit 2 (aD) is DRCA-bit 7, bit 3 is DRCA-bit 0 of control frame 1,
Bit 4 is DRCA-bit 1, bit 5 is DRCA-
Bit 2 and bit 6 are DRCA-bit 3, bit 7 is DRCA-bit 4, bit 0 of byte 14 is DRCA-bit 6 of control frame 0, and bit 1 (cE) is DR.
CA-bit 7, bit 2 is DRCA of control frame 1
-Bit 0, bit 3 is DRCA-bit 1, bit 4
Is DRCA-bit 2, bit 5 is DRCA-bit 3, bit 6 is DRCA-bit 4, bit 7 is DRC
A-bit 5, bit 0 (aF) of DRCB is DRCA-bit 7 of control frame 0, bit 1 is DRCA-bit 0 of control frame 1, bit 2 is DRCA-bit 1, bit 3 is DRCA-bit 2, Bit 4 is DRC
A-bit 3, bit 5 is DRCA-bit 4, bit 6 is DRCA-bit 5, and bit 7 is DRCA-bit 6.

When the above selection relationships are summarized in a table,
12 and 13, respectively. When this is tabulated at the timing of FIG. 10 when 2 bytes are input, it becomes as shown in FIG. 14 and FIG. 16 to 19 show configuration examples of circuits for realizing such a table relationship.

Since 2 bytes of data are input, DR
At the time of creating C, it is necessary not to input data that is unnecessary for creating data. Since the DRC is created in bit units, if only one bit of the 1st bit of the 1st byte and the 1st bit of the 2nd byte is required, the data that is not captured becomes unnecessary data.

Unnecessary data will be exemplified with reference to the DRC creation format shown in FIG. DR of control frame 0
Consider the case of finding CA bit 1. When byte 1 and byte 2 of control frame 0 are input, only bit 0 of byte 1 is used for creating the DRCA and byte 2 is not used. When creating DRCA bit 1, the data is bit 0 of byte 1 and bit 2 of byte 2.
Although and are selected, only the data to be used (bit 0 of byte 1) may be selected. To make this selection, the input unwanted data (bit 2 of byte 2) is masked. As another example, when determining the DRCA bit 3 of the control frame 0, the timing B
S2, bit 0 of byte 3 and bit 7 of byte 4 are input, but unnecessary bit 7 of byte 4 is masked.

In this way, when the data input is 1 bit, the data masking section 24A, 24B of FIGS. 7 and 8 masks the data. Figure 2 shows the details of the data mask
0, shown in FIG. The data mask section 24 shown in FIGS.
The signals input to A and 24B are MAO-0? , MA
E-0? , MAO-1? , MAE-1? , MAO-2
? , MAE-2? And MBO-0? , MBE-0? , M
BO-1? , MBE-1? , MBO-2? , MBE-2
? And. This signal is created by the control frame and the timing signal when creating the DRC. 22 and 2 for details of the internal circuits of the data mask units 24A and 24B.
3, shown in FIGS. 24 and 25.

The data to be input is the data selection section 21.
Since it is determined by A and 21B and the data mask sections 24A and 24B, the timing of taking in data will be described. D
Each of the RCA creation circuit and the DRCB creation circuit has a circuit for three frames, but since the timing of loading each data is different, timing control is necessary.
26 to 31 show timing charts for fetching data. It indicates which data is to be fetched for each output frame 0, 1 and 2 when the DRC is created.

The control frames 0, 1 and 2, which indicate which frame is currently being processed, and the output frame which outputs the DRC at three frame timings, indicate which bit of data is to be fetched. A circle indicates that the bit at the place with the mark is taken in. × indicates that the DRC was created. If a table is created as a timing for taking in the circles, it becomes as shown in FIGS. Based on this table, a signal CE0F for controlling the flip-flop set conditions of the data parity creation units 22A and 22B of FIGS.
A? , CE1FA? , CE2FA? , CE0FB? , C
E1FB? , CE2FB? To create.

As described above, the data selectors 21A, 21
Select the data with B, and the data mask parts 24A, 24B
Then, unnecessary data is masked, and the data parity creation units 22A and 22B take the diagonal parity of the data to create the DRC.

Next, VRC will be described. The theory of creating VRC is the same when inputting 1 byte at a time and when inputting 2 bytes at a time. That is, even parity for each bit of set A and set B may be taken. VRC can be created by using the circuit configuration shown in FIG.

First, the JK flip-flop is cleared before inputting data. In the set A, each bit of the first byte and the second byte is EOR (exclusive OR) and input to the JK flip-flop of the toggle circuit. 3rd, 4th byte, 5th, 6th byte, 7th byte + D
If RCA is input in the same way, VR will be input to the flip-flop.
CA is created. In set B, the 8th byte is input and input to the JK flip-flop of the toggle circuit.
The bits of the 9th and 10th bytes are EORed and input to the JK flip-flop of the toggle circuit. Similarly, the 11th, 12th and 13th, 14th bytes are input. And D
EORing the RCB and the output of the JK flip-flop creates VRCB.

In the configuration of the DRC creating circuit described above,
As shown in FIG. 8, the data selection section for three frames is common, and data is selected by the set control of the data mask section and the flip-flop. However, there is another method for performing data selection. There are three types of groups for data selection, as shown by shading in FIG. Data can be selected by sequentially selecting these three types. The circuit configuration in such an example is as shown in FIG.

In the above example, the case of inputting 2 bytes each to create the AXP correction code has been described.
It is also possible to input a plurality of bytes other than 2 bytes and obtain the diagonal parity of DRC and the vertical parity of VRC.

[Reed-Solomon Code] Next, speeding up of the Reed-Solomon code of the present invention will be described. The coding calculation using the check matrix will be specifically shown by using the following codes. Code length n = 18 Number of information points k = 14 Number of check points n−k = 4 Minimum distance d _min = 5 Primitive polynomial g (x) = x ⁸ + x ⁴ + x ³ + x ² +1 Generator polynomial G (x) = (x−α ³ ) (x−α ² ) (x−α) (x−1) = x ⁴ + α ⁷⁵ x ³ + α ²⁴⁹ x ² + α ⁷⁸ x + α ⁶ d _{0 to} d ₃ are represented by the following matrix.

Here, the sum total shown below,

[0109]

[Equation 4]

[0110] That is, a ₀ if deployed _{~a 3, a 0 = i 13} + i 12 + i 11 + i 10 + i 9 + i 8 + i 7 + i 6 + i 5 + i 4 + i 3 + i 2 + i 1 + i 0 a 1 = i ₁₃ × α ¹⁷ + i ₁₂ × α ¹⁶ + i ₁₁ × α ¹⁵ + i ₁₀ × α ¹⁴ + i ₉ × α ¹³ + i ₈ × α ¹² + i ₇ × α ¹¹ + i ₆ × α ¹⁰ + i ₅ × α ⁹ + i ₄ × α ⁸ + i ₃ × α ⁷ + i ₂ × α ⁶ + i ₁ × α ⁵ + i ₀ × α ⁴ a ₂ = i ₁₃ × α ³⁴ + i ₁₂ × α ³² + i ₁₁ × α ³⁰ + i ₁₀ × α ²⁸ + i ₉ × α ²⁶ + i ₈ × α ²⁴ + i ₇ × α ²² + i ₆ × α ²⁰ + i ₅ × α ¹⁸ + i ₄ × α ¹⁶ + i ₃ × α ¹⁴ + i ₂ × α ¹² + i ₁ × α ¹⁰ + i ₀ × α ⁸ a ₃ = i ₁₃ × α ⁵¹ + I ₁₂ × α ⁴⁸ + i ₁₁ × α ⁴⁵ + i ₁₀ × α ⁴² + i ₉ × α ³⁹ + i ₈ × α ³⁶ + i ₇ × α ³³ + i ₆ × α ³⁰ + i ₅ × α ²⁷ + i ₄ × α ²⁴ + i ₃ × α ²¹ + I ₂ × α ¹⁸ + i ₁ × α ¹⁵ + i ₀ × α ¹² .

Here, the information word i₁₃~ I₀In units of 2 bytes
(I₁₃And i₁₂, I₁₁And i_Ten, I₉And i ₈, I₇And i₆，
i_FiveAnd i_Four, I₃And i₂, I₁And i₀), Find the sum
Input to the circuit₁~ A₃As below
Change to the formula summarized in the common section.   a₁= Α^Five(I₁₃× α¹²++ i₁₁× α^Ten+ I₉× α⁸+ I₇× α⁶               + I_Five× α^Four+ I₃× α²+ I₁× α⁰) +         α^Four(I₁₂× α¹²++ i_Ten× α^Ten+ I₈× α⁸+ I₆× α⁶               + I_Four× α^Four+ I₂× α²+ I₀× α⁰)   a₂= Α^Ten(I₁₃× α^{twenty four}++ i₁₁× α²⁰+ I₉× α¹⁶+ I₇× α¹²               + I_Five× α⁸+ I₃× α^Four+ I₁× α⁰) +         α⁸(I₁₂× α^{twenty four}++ i_Ten× α²⁰+ I₈× α¹⁶+ I₆× α¹²               + I_Four× α⁸+ I₂× α^Four+ I₀× α⁰)   a₃= Α¹⁵(I₁₃× α³⁶++ i₁₁× α³⁰+ I₉× α^{twenty four}+ I₇× α¹⁸               + I_Five× α¹²+ I₃× α⁶+ I₁× α⁰) +         α¹²(I₁₂× α³⁶++ i_Ten× α³⁰+ I₈× α^{twenty four}+ I₆× α¹⁸               + I_Four× α¹²+ I₂× α⁶+ I₀× α⁰)

This equation shows that when inputting in units of 2 bytes, the circuit for obtaining the sum can be simplified by multiplying each of the even bytes and the odd bytes by a constant. Further, the multiplication constant in the multiplication circuit for obtaining a ₁ from this equation is α ² for both even and odd bytes, and the multiplication constants for a ₂ are α ⁴ , a ₃
In the case of, the multiplication constant is the same value that is common to α ⁶ and even bytes and odd bytes. Therefore, the value in the parentheses of each expression can be obtained by sequentially repeating multiplication-addition-holding. That is, it becomes possible to obtain the sum total of the information words at twice the speed as compared with the conventional circuit.

[0113] Then, a ₀ from ~a ₃ to obtain the test word d ₀ to d ₃ may be a circuit to solve the above matrix equation, conventional multiplying circuit which sets a predetermined multiplicative constant as well And an adder circuit can be used to implement the operation according to the following arithmetic expression. d ₀ = α ²¹⁸ × a ₀ + α ¹⁵⁸ × a ₁ + α ¹⁵⁶ × a ₂ + α ²¹² × a ₃ d ₁ = α ¹⁵⁸ × a ₀ + α ¹³⁸ × a ₁ + α ² × a ₂ + α ¹⁵³ × a ₃ d ₂ = α ¹⁵⁶ × a ₀ + α ² × a ₁ + α ¹³⁵ × a ₂ + α ¹⁵² × a ₃ d ₃ = α ²¹² × a ₀ + α ¹⁵³ × a ₁ + α ¹⁵² × a ₂ + α ²⁰⁹ × a ₃

FIGS. 40 and 41 show the above a₀~ A
₃And d₀~ D₃It is a block diagram of a circuit that is designed to obtain
It An addition circuit 25 on the Galois field composed of EOR;
Power of constant term on Galois field composed of EOR and AND
The arithmetic circuit 27 and the multiplication-added data (information word) are stored.
And a register 26 for holding. When encoding
In case of information, enter the information word in 2-byte units and
When is input a ₀~ A₃Is calculated by the circuit in Figure 40
And calculated a₀~ A₃Is input to the circuit of Figure 41
And the inspection word d₀~ D₃Is required. That is, it is necessary for encoding.
The required time is information word length / 2, which is incorrect compared to the conventional example.
The correction coding processing time is cut in half.

In the above description, the input data is in units of 2 bytes for simplification of description, but for example, 4 bytes, 6 bytes, ... (Unit is an even number).
If so, the encoding circuit can be configured in the same way.

(Syndrome Creating Circuit 6 for Reed-Solomon Code) FIG. 42 is a block diagram showing the configuration of the syndrome creating circuit 6 of the present invention. The syndrome creating circuit 6 includes a memory 31, a bit weight conversion section 32, and It has a parallel syndrome calculation unit 33, a syndrome result storage unit 34, and a controller unit 35.

Before the syndrome calculation, the Galois field GF of the data read from the memory 31 is changed according to the traveling direction.
However, it may be necessary to exchange the bit weights. In this case, the bit weight converter 32 replaces the bit weight of the data and outputs it to the parallel syndrome calculator 33. The parallel syndrome calculation unit 33 obtains the syndrome of the data after the bit weight conversion. The syndrome result storage unit 34 stores the calculation result of the syndrome. The controller unit 35 controls the arithmetic processing in the parallel syndrome arithmetic unit 33.

FIG. 43 shows the internal structure of the parallel syndrome arithmetic unit 33 and the controller unit 35 of FIG. The parallel syndrome arithmetic unit 33 includes an EOR unit 36 and a multiplier 37.
The controller section 35 has a byte switch 35a and a pulse generator 35b.

The operation according to the following conditions will be described. Body code is present: GF (2) the original total primitive polynomial constituting 256 ^{bodies: g (x) = x 8} + x 4 + x 3 + x 2 +1 RS code generator polynomial: G (x) = x ⁴ + Α ⁷⁵ x ³ + α ²⁴⁹ x ² + α ⁷⁸ x + α ⁶ = (x + α ⁰ ) (x + α ¹ ) (x + α ² ) (x + α ³ ) Code length n = 18 bytes Information points k = 14 bytes Inspection points m = 4 bytes Minimum distance d _min = 5 correction capability error correction = 2 or error detection = 4 possible

First, the 18-byte codewords stored in the memory 31 are collected every 3 bytes, and the 3-byte data is simultaneously taken into the bit weight converter 32. The Galois field differs depending on the traveling direction, and the bit weights are exchanged. Swap bit weights when needed. The data after bit weight conversion is input to the parallel syndrome calculator 33 to calculate the syndrome. The result of each EOR is the multiplier 3
The syndrome is obtained by multiplying with a power of 7 table. The multiplexer 38 is necessary for switching the number of bytes at the time of data transfer, and the number of bytes is switched by information from the outside by the byte switch 35a for syndrome calculation of the controller unit 35. The register 39 is necessary for temporarily storing the calculated syndrome result and outputting it accurately. After the 18-byte data is input, the calculated syndrome result is the pulse generator 35b after the 18-byte data is input.
Are stored in the syndrome result storage unit 34 in accordance with the timing pulse generated from

As described above, since the processing is performed in units of 3 bytes, the syndrome calculation can be performed at high speed.

(Deskew Circuit 5) In the present invention, the process of simultaneously reading three deskewing buffers and transferring data of 3 bytes at a time is performed six times so that the transfer rate of the data of one frame can be reduced to the conventional example. 3 times higher. Further, by changing the allocation of each track of the deskewing buffer and changing the control method, data transfer can be performed by the same control method in the FWD direction and the BWD direction.

FIG. 44 is a block diagram showing the internal structure of the deskew circuit 5 of the present invention. Deskew control circuit 4
1A (41B, 41C), deskewing buffer 42A (42B, 42C), multiplexer 43A
(43B, 43C) and the 9-8 conversion circuit 44A (44
B, 44C) and three circuits
3 bytes of data can be transferred at one time.

45 to 48 are diagrams showing data write / read control in the deskewing buffers 42A, 42B and 42C. In the present invention, unlike the conventional example, the writing / reading control is common in the FWD direction and the BWD direction.

As an example, the control operation of the deskew control circuit 41A and deskewing buffer 42A will be described. In each inclined track on the magnetic tape, a track in which 1-byte data (9-bit data) is complete is sequentially written into each divided memory area. First, the 1A-track data is written to the memory area (position A) allocated to the 1A-track of the deskewing buffer 42A. Similarly, 4A-track data is at B position, 7A-track data is at C position, 5B-track data is at D position, 2B-track data is at E position, and 0A-track data is at F
Write at the position (see FIG. 45).

Similarly, the deskewing buffer 4
Also in 2B and 42C, the data of each track is written in the corresponding memory area (FIGS. 46 and 47).
reference). As described above, the writing of data for 18 tracks is completed.

When the data writing is completed, the 3-byte data transfer is started. The data of the block (position A) having the first reading order of the deskewing buffers 42A, 42B, and 42C shown in FIGS. 45 to 47 is read at the same time, and 3-byte transfer is realized at one timing.
The read 3-byte data is transferred to the 9-8 conversion circuits 44A, 44B, and 44C independent of the three systems, and converted into 8-bit data. Next, the 1st block of data for 18 tracks is read at a total of 6 times, such as the block (position B) having the second reading order of the deskewing buffers 42A, 42B, 42C, and the third reading order. It is transmitted (see FIG. 48).

With the above-described method, it is possible to transfer data of one frame at triple speed as compared with the conventional example.
The processing speed can be improved. Also, in the FWD direction,
The deskew process can be performed by the same control method regardless of the BWD direction.

(Data Transfer Control in Read Format Unit 11e) Error correction processing is performed on data transferred with a width of 3 bytes, which is three times as large as that of the conventional technique, before being transferred to the circuit (host 10) in the next stage. In that case, a means for temporarily storing data is required. In order to minimize the use of elements such as memories, flip-flops, and selectors as the storage means, and to support read operations in the FWD and BWD directions, it is necessary to devise a method for controlling the memory address. .

When the data read from the medium such as the magnetic tape is stored in the memory, the address counter is controlled by the counter control circuit which controls the memory address to be stored. The output value of the counter is input to the address line of the memory, and the address is controlled so that the data is stored in a predetermined area of the memory. Further, the counter control circuit can switch the address order depending on the magnetic tape reading direction (FWD direction or BWD direction). When performing the error correction process, the input data order is opposite between the BWD direction and the FWD direction, but by switching the address order by the counter control circuit, the BWD direction can be changed.
It is not necessary to provide separate error correction circuits for the direction and the FWD direction.

FIG. 49 is a block diagram showing the structure of the data transfer control system of the present invention. The data transfer control system shown in FIG. 49 has an S having a memory area for storing data.
RAM 51, address load value setting circuit 52 for setting a specific address value, and FWD / BW for switching the order of transfer data in each of the FWD direction and the BWD direction.
D switching circuit 53, address counter circuit 54 for controlling write and read addresses, medium 55 such as magnetic tape, and error correction processing circuit 5 for error correction
6, a traveling direction determination circuit 57 for determining the FWD direction and the BWD direction, and 3 in the same address in the BWD direction.
And a BWD byte data conversion circuit 58 for rearranging the data order of bytes. The address counter circuit 54 has a write counter 54a and a read counter 54b.

FIG. 50 is a diagram showing a memory map in the SRAM 51, showing a memory storage area for each group. In FIG. 50 ,,, are group numbers of data in frame units, 00, 05, 06, 0B, 0
C, 11, and 12 are address initial values (load values) representing areas for storing the data of each group.

FIG. 51 is a diagram showing the format of one frame of data transferred from the medium 55 in 3-byte units. FIG. 51 (a) shows the case of reading in the FWD direction, and FIG. The respective data formats at the time of reading in the BWD direction are shown. Further, FIG. 52 is a timing chart of writing and reading of data in frame units, and FIG. 53 is an FWD in a specific frame data.
Detailed timing chart for writing and reading
FIG. 54 is a detailed timing chart of writing and reading during BWD in specific frame data.

When the data read from the medium 55 in the FWD direction is sent in parallel in the format (3 byte width: 1A, 2A, 3A) as shown in FIG. 51A, the address load value setting 3 bytes of data are stored in the determined storage address (load value) of the SRAM 51 for each group of frame units (18 bytes from 1A to 8B) set by the circuit 52. In this case, 00 is loaded first, and the address 00 has 1A,
3 bytes of 2A and 3A are stored.

After that, the address is incremented by the address counter circuit 54, and data is stored in units of 3 bytes according to the incremented address. When the data is stored in the addresses incremented to 05, the storage of one frame of data, that is, the group is completed. Similarly, data storage processing is performed for each group, such as addresses 06 to 0B for groups and groups 0C to 11 for groups.

Next, a description will be given of the case where the same address stored (written) in the SRAM 51 is read out for each group. At this time, as shown in FIG. 52, a delay of two frames occurs at the timing of writing and reading. This is because it takes 1 frame to complete the writing of the frame data (18 bytes) and 1 frame to perform error correction processing on the written data. The reason why the group is divided into three groups at the time of data storage and the respective start addresses and end addresses are set as load values is for coping with the shift of these two frames.

Since reading the same address written in the SRAM 1 is delayed by two frames, as shown in FIG. 52, the group is read when the group is being written and the group is read when the group is being written. The address counters 54a and 54b for writing and reading are controlled such that the group is read when writing is written.
FIG. 53 shows the detailed timing of this address counter control. In FIG. 53, 00 is written when 0C is written.
Is read, and when 08 is written, 0C is read.

Although the above-mentioned example describes the writing in the FWD direction, in the case of writing in the BWD direction, the read data read from the medium 55 is in the FWD direction in the previous stage for the sake of error correction processing. The data has been converted in the order of data, and when outputting to the next stage, it has to be converted again in the BWD direction. FWD / BWD that determines the traveling direction by the traveling direction determination circuit 57 that determines the traveling direction of each of FWD / BWD and controls the reading / writing order
Switching is performed by the switching circuit 53. That is, in the case of the FWD direction, the start address of the group is loaded and the counter value is increased, but in the case of the BWD direction, the final address of the group is set as the load value and the counter value is decreased.

For example, in FIG. 54, the group is B
When reading in the WD direction, the read address counter is controlled so that the last address of the group is used as the load value and down counting is performed such that 05 is read when 0C is written. Moreover, at the time of BWD, FIG.
As shown in (b), since the arrangement of 3 bytes in the same address changes in addition to the order of output data, BWD is used during BWD.
The byte data conversion circuit 58 controls byte conversion.

According to the method described above, speeding up of data transfer (3-byte transfer), high-performance error correction processing when the reading order of data from the tape medium changes in the FWD direction or the BWD direction. When the data transfer control method is becoming more sophisticated and complicated, even when data shift occurs in frame units, the above-mentioned factors can be dealt with comprehensively. By controlling the address counter by switching it between the FWD direction and the BWD direction, the counter load value is set, and depending on whether the counter is up-counting or down-counting, the read operation in the FWD direction and the BWD direction can be handled. By dividing the data into three groups, it is possible to perform the write operation and the read operation at the same timing even in the above-described phenomenon that two frames are deviated during writing and reading, and it is possible to support 3-byte data high-speed transfer. You can

In contrast to the conventional method of improving conventional data transfer control methods, which involves adding a large number of elements such as flip-flops and selectors for data storage or buffer control, the present invention has been described above. Since data transfer control is performed by various methods, the absolute number of elements used for data storage and buffer control can be minimized to prevent an increase in circuit scale and complexity, shorten development time, and reduce development costs. Can be reduced and the test items can be simplified, and efficiency can be improved in many fields.

[0142]

As described above, according to the present invention,
The function of each circuit in the data format section of the magnetic tape control device can be increased, the data bus can be expanded without complicating the circuit, and the data transfer speed can be increased. It greatly contributes to the performance improvement of.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an internal configuration example of a data format unit of a magnetic tape control device.

FIG. 2 is a block diagram showing a configuration example of a tape subsystem.

FIG. 3 is a diagram showing a configuration example of a residual byte creation circuit of the present invention.

FIG. 4 is a timing chart (8 bytes of custom data) of the residual byte creating circuit of the present invention.

FIG. 5 is a timing chart (9 bytes of custom data) of the residual byte creation circuit of the present invention.

FIG. 6 is a chart showing a mod14 counter output of the residual byte generation circuit of the present invention.

FIG. 7 is a diagram showing a configuration example of a DRC creation circuit of the present invention.

FIG. 8 is a diagram showing a configuration example of a DRC creation circuit of the present invention.

FIG. 9 is a diagram showing a configuration example of a VRC creation circuit of the present invention.

FIG. 10 is a chart showing the relationship between input data and data timing when creating a DRC in the present invention.

FIG. 11 is a diagram showing an example of DRC creation in the present invention.

FIG. 12 is a chart showing data selection in a DRC creation circuit of a conventional example.

FIG. 13 is a chart showing data selection in the DRC creation circuit of the conventional example.

FIG. 14 is a chart showing data selection in the DRC creation circuit of the present invention.

FIG. 15 is a chart showing data selection in the DRC creation circuit of the present invention.

FIG. 16 is a diagram showing a configuration example of a data selection unit in the DRC creation circuit of the present invention.

FIG. 17 is a diagram showing a configuration example of a data selection unit in the DRC creation circuit of the present invention.

FIG. 18 is a diagram showing a configuration example of a data selection unit in the DRC creation circuit of the present invention.

FIG. 19 is a diagram showing a configuration example of a data selection unit in the DRC creation circuit of the present invention.

FIG. 20 is a chart showing data mask timing in the data mask section of the DRC creation circuit of the present invention.

FIG. 21 is a table showing data mask timing in the data mask section of the DRC creation circuit of the present invention.

FIG. 22 is a diagram showing a configuration example of a data mask unit of the DRC creation circuit of the present invention.

FIG. 23 is a diagram showing a configuration example of a data mask section in the DRC creation circuit of the present invention.

FIG. 24 is a diagram showing a configuration example of a data mask unit of the DRC creation circuit of the present invention.

FIG. 25 is a diagram showing a configuration example of a data mask section in the DRC creation circuit of the present invention.

FIG. 26 is a diagram showing a data capture timing in the DRC creation circuit of the present invention.

FIG. 27 is a diagram showing a data capture timing in the DRC creation circuit of the present invention.

FIG. 28 is a diagram showing a data capture timing in the DRC creation circuit of the present invention.

FIG. 29 is a diagram showing a data capture timing in the DRC creation circuit of the present invention.

FIG. 30 is a diagram showing a data fetch timing in the DRC creation circuit of the present invention.

FIG. 31 is a diagram showing a data capture timing in the DRC creation circuit of the present invention.

FIG. 32 is a diagram showing a data set timing in the DRC creation circuit of the present invention.

FIG. 33 is a diagram showing a data set timing in the DRC creation circuit of the present invention.

FIG. 34 is a diagram showing a data set timing in the DRC creation circuit of the present invention.

FIG. 35 is a diagram showing a data set timing in the DRC creation circuit of the present invention.

FIG. 36 is a diagram showing a data set timing in the DRC creation circuit of the present invention.

FIG. 37 is a diagram showing a data set timing in the DRC creation circuit of the present invention.

FIG. 38 is a diagram showing data selection in the DRC creation circuit of the present invention.

FIG. 39 is a diagram showing a configuration example of a data selection unit of the DRC creation circuit of the present invention.

FIG. 40 is a diagram showing a configuration example of an encoding circuit of the present invention.

FIG. 41 is a diagram showing a configuration example of an encoding circuit of the present invention.

FIG. 42 is a block diagram showing a configuration example of a syndrome creating circuit of the present invention.

43 is a diagram showing an internal configuration example of a parallel syndrome computing unit and a controller unit shown in FIG. 42.

FIG. 44 is a block diagram showing a configuration example of a deskew circuit of the present invention.

FIG. 45 is a diagram showing the operation of the deskewing buffer in the deskew circuit of the present invention.

FIG. 46 is a diagram showing the operation of the deskewing buffer in the deskew circuit of the present invention.

FIG. 47 is a diagram showing the operation of the deskewing buffer in the deskew circuit of the present invention.

FIG. 48 is a diagram showing the operation of the deskewing buffer in the deskew circuit of the present invention.

FIG. 49 is a block diagram showing a configuration example of a data transfer control system of the present invention.

FIG. 50 is a diagram showing a memory map in the data transfer control system of the present invention.

FIG. 51 is a diagram showing a frame data format in the data transfer control system of the present invention.

FIG. 52 is a diagram showing frame data transfer timing in the data transfer control system of the present invention.

FIG. 53 is a timing chart of writing / reading (during FWD) in the data transfer control system of the present invention.

FIG. 54 is a timing chart of writing / reading (during BWD) in the data transfer control system of the present invention.

FIG. 55 is a diagram showing a data format recorded on a magnetic tape.

FIG. 56 is a diagram showing a data format when custom data is 12 bytes.

FIG. 57 is a diagram showing a data format when custom data is 7 bytes.

FIG. 58 is a diagram showing a configuration example of a residual byte creation circuit of a conventional example.

FIG. 59 is a timing chart of a residual byte creation circuit of a conventional example.

FIG. 60 is a chart showing a mod14 counter output of the conventional residual byte generation circuit.

FIG. 61 is a diagram showing a DRC creation format of a conventional example.

FIG. 62 is a chart showing an example of DRC calculation in a conventional example.

FIG. 63 is a diagram showing a configuration example of a DRC creation circuit of a conventional example.

FIG. 64 is a diagram showing a method of creating a VRC in a conventional example.

FIG. 65 is a chart showing an example of VRC calculation in a conventional example.

FIG. 66 is a diagram showing a configuration example of a conventional VRC creation circuit.

[Fig. 67] Fig. 67 is a diagram illustrating a configuration example of a coding circuit using a conventional LFSR.

[Fig. 68] Fig. 68 is a diagram illustrating a configuration example of a coding circuit using a conventional check matrix.

[Fig. 69] Fig. 69 is a diagram illustrating a configuration example of a coding circuit using a conventional check matrix.

FIG. 70 is a diagram showing a data format on a magnetic tape.

71 is a partial enlarged view of the data format shown in FIG. 70. FIG.

FIG. 72 is a block diagram showing a configuration example of a deskew circuit of a conventional example.

FIG. 73 is a diagram showing a movement (during FWD) of a deskewing buffer in a deskew circuit of a conventional example.

FIG. 74 is a diagram showing movement of the deskewing buffer (during FWD) in the deskew circuit of the conventional example.

FIG. 75 is a diagram showing movement (during FWD) of the deskewing buffer in the deskew circuit of the conventional example.

FIG. 76 is a diagram showing movement of the deskewing buffer (during FWD) in the deskew circuit of the conventional example.

FIG. 77 is a diagram showing movement of the deskewing buffer (during BWD) in the deskew circuit of the conventional example.

FIG. 78 is a diagram showing movement (during BWD) of the deskewing buffer in the deskew circuit of the conventional example.

FIG. 79 is a diagram showing movement of the deskewing buffer (during BWD) in the deskew circuit of the conventional example.

FIG. 80 is a diagram showing movement (during BWD) of the deskewing buffer in the deskew circuit of the conventional example.

[Explanation of symbols]

1 Residual byte creation circuit 2,4 multiplexer 3 Error correction coding circuit 5 Deskew circuit 6 Syndrome creation circuit 7 Error correction circuit 8 frame buffer 10 hosts 11 Magnetic tape controller (MTC) 12 Magnetic tape unit (MTU) 11b Data format section 11d write format section 11e Read-out format section 21A, 21B data selection section 22A, 22B data parity creation unit 23A, 23B frame control unit 24A, 24B data mask section 25 adder circuit 26 registers 27 Multiplier circuit 33 Parallel Syndrome Operation Unit 41A, 41B, 41C deskew control circuit 42A, 42B, 42C deskewing buffer 51 SRAM 52 Address load value setting circuit 53 FWD / BWD switching circuit 54 address counter circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G11B 20/10 301 G11B 20/10 301Z 20/18 532 20/18 532C 572 572B 572G 574 574N H03M 13/11 H03M 13/11 13/15 13/15 (72) Inventor Hiroyuki Hieda No. 35 Saho, Shrine-cho, Kato-gun, Hyogo Prefecture (no address) Inside Fujitsu Peripherals Co., Ltd. (72) Yoshinori Nagai Saho, Kato-gun, Hyogo Prefecture No. 35 (no address) In Fujitsu Peripherals Co., Ltd. (72) Inventor Katsuhiko Fukuda Saho, Kato-gun, Hyogo Prefecture Saho No. 35 (no addresses) In Fujitsu Peripherals Co., Ltd. (72) Inventor Kawa ▲ saki ▼ Hyogo Prefecture No. 35 Saho, Shrine-cho, Kato-gun (No house number) Within Fujitsu Peripheral Machine Co., Ltd. (72) Inventor, Daiao Konishi, No. 35 Saho, Shrine-machi, Kato-gun, Hyogo Prefecture ) Fujitsu Peripheral Machinery Limited (72) Inventor Yasunori Nishimura 35, Saho, Shrine Town, Kato-gun, Hyogo Prefecture (No address) Fujitsu Peripheral Machinery Limited (72) Inventor, Masahiko Katada 35, Saho, Kato-gun, Hyogo Prefecture ( No address) Fujitsu Peripheral Co., Ltd. (72) Inventor Sayuri Tanaka 35, Saho, Kato-gun, Hyogo Prefecture (No address) Fujitsu Peripheral Co., Ltd. F-term (reference) 5B001 AA13 AB02 AB03 AC01 AD04 AE02 5B065 BA07 CA11 EA03 5D044 BC01 CC01 DE03 DE12 DE69 HL01 HL11 5J065 AA01 AB01 AC02 AD01 AD11 AH06 AH09

Claims (7)

[Claims] 1. An error correction code is added to data input from a host device, format conversion is performed, the format-converted data is transferred to a magnetic tape unit, and error correction is performed on the data read from the magnetic tape unit. In a control device of a magnetic tape device which performs format conversion and transfers the format-converted data to the host device, an error correction encoding process in units of a plurality of bytes for input data from the host device and / or the magnetic tape unit A controller for a magnetic tape device, wherein the controller is configured to perform error correction processing in units of a plurality of bytes on read data from the device. 2. When the data from the higher-level device is formed into one frame of a predetermined number of bytes, a counting means is provided for counting the remaining bytes so that the number of bytes in each frame is a predetermined number. The counting means includes means for determining whether the number of bytes of the data from the higher-order device is odd or even, and means for switching the remaining byte counting method according to the determination result. The control device for the magnetic tape device according to claim 1. 3. AX for data from the host device
An error correction coding means for creating a P error correction code is provided,
2. The control device for a magnetic tape device according to claim 1, wherein the error correction coding means is configured to input a plurality of bytes of data from the host device to create an AXP error correction code. 4. The selection circuit for selecting data from a plurality of frames as a circuit for the error correction coding means to create a DRC of an AXP error correction code from data over a plurality of frames, and to each of the selection circuits. 4. A control device for a magnetic tape device according to claim 3, further comprising a control circuit for controlling masking of data from a frame, wherein the data is selected from a plurality of frames separately for each frame. 5. The error correction coding means, as a circuit for creating a DRC of an AXP error correction code from data over a plurality of frames, a selection circuit having the same number as a plurality of frames for selecting data for each frame, 4. A control device for a magnetic tape device according to claim 3, further comprising a switching circuit for switching outputs of a plurality of selection circuits, wherein the data is selected from a plurality of frames separately for each frame. 6. An error correction coding means for creating a Reed-Solomon error correction code for the data from the higher-order device, wherein the error correction coding means processes a plurality of summations of information words in parallel. 2. The control device for the magnetic tape device according to claim 1, wherein 7. A syndrome creating means for creating a syndrome required to correct an error in data read from the magnetic tape unit according to a Reed-Solomon method, and the syndrome creating means multiplies a received word by a check matrix. The control device for a magnetic tape device according to claim 1, wherein the control device has a plurality of circuits and is configured to create a syndrome in parallel for a plurality of bytes of data.