JP5667408B2 - Reed-Solomon code / decoding circuit, Reed-Solomon code / decoding method, and storage device - Google Patents

Description

  The present invention relates to a Reed-Solomon code decoding circuit, a Reed-Solomon code decoding method, and a storage device including the Reed-Solomon code decoding circuit.

  In recent years, an SSD (Solid State Drive) storage device composed of a semiconductor flash memory has attracted attention as a storage device that replaces a hard disk storage device. Since the SSD storage device does not include moving parts, it has many advantages such as high operation reliability, short access time, and easy miniaturization. On the other hand, in the SSD storage device, the flash memory, which is a component of the SSD storage device, is manufactured using ultra-fine processing technology. For this reason, there is a disadvantage that the number of data writing is limited (for example, 100,000 times). Therefore, in the SSD storage device, various techniques such as a data error correction technique and a data writing frequency leveling technique have been introduced to cover these drawbacks.

  A so-called Reed-Solomon code is used as a code for error correction in the SSD storage device. Reed-Solomon code is a code that can correct errors in multiple words and has excellent correction capability, and has already been widely applied in fields such as DVD (Digital Versatile Disk), satellite communications, and terrestrial digital broadcasting. Yes. On the other hand, in particular, the decoding procedure and circuit in the Reed-Solomon code are never simple, and therefore have a weak point that the time required for the decoding becomes long.

  Reed-Solomon code encoding / decoding procedures and circuits are described in textbooks (for example, Non-Patent Document 1) that explain coding theory and its application. Patent Document 1 discloses a technique for simplifying the circuit configuration of a chain search circuit (chain search circuit) that is particularly complicated among Reed-Solomon code decoding circuits.

JP-A-6-314978

Toshinobu Kaneko, 9 others, "Error correction code and its application", 1st edition, Ohmsha, December 25, 1996, p. 107-122, p. 177-189

  The time required to decode the Reed-Solomon code in the SSD storage device means that the access time of data stored in the SSD storage device increases, and the increase in the access time reduces the main performance of the SSD storage device. It means to lower. In many cases, an SSD storage device is used as an auxiliary storage device of a computer like a hard disk storage device. However, for many users of a computer, it is preferable that an access time of an auxiliary storage device such as an SSD storage device is short. This is because the processing power of the computer is often limited by the performance of the auxiliary storage device.

  Accordingly, an object of the present invention is to provide a Reed-Solomon code / decoding circuit, a Reed-Solomon code / decoding method, and a Reed-Solomon code / decoding circuit that can shorten the decoding time of the Reed-Solomon code. To provide a storage device.

  A Reed-Solomon code / decoding circuit according to the present invention uses a Reed-Solomon code generator polynomial to calculate a syndrome for an input symbol sequence composed of a plurality of symbols, and a syndrome calculated by the syndrome calculation unit Is used to calculate the number of error symbols included in the input symbol sequence and the coefficient of the error locator polynomial, and to the input symbol sequence based on the error locator polynomial having the calculated coefficient. An error position search unit that searches for an error position that is the position of the included error symbol and an error correction unit that corrects an error symbol at the searched error position are configured.

The error position search unit sequentially changes position data representing the position of the symbol of the input symbol sequence, and searches for an error position where the value of the error position polynomial is 0, Each of the plurality of chain search circuits is provided so as to correspond to each of the plurality of chain search circuits. When the position data is sequentially changed, the number of the error positions searched by each of the plurality of chain search circuits is counted. A plurality of counters, an adder that adds and outputs the values of the plurality of counters, and a search control circuit that controls operations of the plurality of chain search circuits, the search control circuit including the input symbol string The plurality of chain search circuits execute an error position search for each different symbol position independently and in parallel with each other. There when it becomes equal to the number of the error symbols, characterized in that to terminate the search for the error location in the Chien search circuit.

  In the Reed-Solomon encoding / decoding circuit of the present invention, the error position search time is shortened because the error position search is performed independently and in parallel by a plurality of chain search circuits. In addition, when the number of error positions detected by the plurality of chain search circuits becomes the same as the number of error symbols obtained by the error position polynomial coefficient calculation unit, the error position search in the plurality of chain search circuits is performed. Is terminated, the error location search time is further shortened. As described above, as a result of shortening the error position search time, the decoding time in the Reed-Solomon code / decoding circuit of the present invention is shortened.

  According to the present invention, a Reed-Solomon code / decoding circuit, a Reed-Solomon code / decoding method, and a storage device including the Reed-Solomon code / decoding circuit can shorten the decoding time of the Reed-Solomon code. Is provided.

The figure which showed the example of the structure of the functional block of the SSD memory | storage device which concerns on embodiment of this invention. The figure which showed the example of the structure of the block, page, and sector in NFC (NAND type flash memory chip) concerning the embodiment of the present invention. The figure which showed the example of the structure of RS encoding / decoding circuit which concerns on embodiment of this invention. The figure which showed the example of the flow of a process of the error position search in RS encoding / decoding circuit which concerns on embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing an example of a functional block configuration of an SSD storage device according to an embodiment of the present invention.
As shown in FIG. 1, the SSD storage device 2 is used by being connected to the host device 1 via the host bus 3. Here, the host device 1 is a computer that stores data and programs in the SSD storage device 2, or various control devices to which the computer is applied. At this time, as the host bus 3 for connecting the host device 1 and the SSD storage device 2, a small computer system interface (SCSI) bus, an integrated drive electronics (IDE) bus, or the like is usually used.

  In FIG. 1, the SSD storage device 2 includes an SSD control unit 4 and an SSD storage medium unit 5. The SSD control unit 4 includes a host interface unit 41, a command processing control unit 42, a page data writing unit 43, a page data reading unit 45, a block state management unit 47, and the like. The page data writing unit 43 includes a Reed-Solomon code (hereinafter abbreviated as RS code) / encoding circuit 44, and the page data reading unit 45 includes an RS code / decoding circuit 46. On the other hand, the SSD storage medium unit 5 includes a plurality of NAND flash memory chips (hereinafter abbreviated as NFC) 51. In the example of FIG. 1, the SSD storage medium unit 5 includes 24 NFCs 51. In FIG. 1, a thick line with an arrow indicates a data flow, and a broken line with an arrow indicates a schematic control signal flow.

  FIG. 2 is a diagram illustrating an example of the configuration of blocks, pages, and sectors in the NFC 51 according to the embodiment of the present invention. As shown in FIGS. 2A and 2B, the NFC 51 is composed of Nb blocks 52, and one block 52 is composed of N pages 53. In the NFC 51, the block 52 is a data erasing unit, and the page 53 is a data writing or reading unit.

  Subsequently, as shown in FIG. 2C, page data including a header (26B) and eight sectors (each 536B) is stored in one page 53 (hereinafter, B is an abbreviation of a byte). , B is an abbreviation for bits, and 1B = 8b). Furthermore, as shown in FIG. 2 (d), one sector includes data (512B), a CRC (Cyclic Redundancy Check) check code (4B), and an RS correction code (20B).

  Accordingly, 4 kB of data is stored in one page 53. At this time, if the number N of pages 53 constituting one block 52 is N = 64, 256 kB of data is stored in one block 52. When the storage capacity of one NFC 51 is, for example, 4 GB, the number Nb of blocks 52 constituting one NFC 51 is 16 KB (Nb = 16, 384).

Returning to FIG. 1 again, the operation of the SSD control unit 4 will be described.
In FIG. 1, the host interface unit 41 matches the electrical interface to the host bus 3 and transmits and receives commands and data to and from the host device 1 according to the communication protocol defined in the host bus 3. .

  The command processing control unit 42 receives various commands (for example, a page data write command, a page data read command, etc.) transmitted from the host device 1 via the host interface unit 41, and in advance according to each command. Execute the specified process.

  For example, when the command processing control unit 42 receives a page data write command from the host device 1, the command processing control unit 42 attaches or follows the page data write command to the host interface unit 41. The page address and data transmitted from 1 are received, and the received page address and data are instructed to be stored in a temporary data storage unit (not shown). Further, it instructs the page data writing unit 43 to write the data stored in the temporary data storage unit to the page 53 in the NFC 51 specified by the page address.

  When the page data writing unit 43 receives a page data write instruction from the command processing control unit 42, the page data writing unit 43 formats the data stored in the temporary data storage unit (not shown) into the page data in the format shown in FIG. To do. The page data writing unit 43 generates a CRC check code (4B) by using a CRC generation circuit (not shown) for each sector data when shaping the page data, and the RS code / encoding circuit 44 The RS correction code (20B) is generated by using this.

  Further, the page data writing unit 43 uniquely assigns the page address (logical address) attached to the page data write command to the page 53 included in all the NFCs 51 in the SSD storage medium unit 5 according to a predetermined conversion rule. The page data is converted into an identifiable physical address, and the formatted page data is written to the page 53 in the NFC 51 identified by the physical address.

  When the command processing control unit 42 receives a page data read command from the host device 1, the command processing control unit 42 instructs the page data reading unit 45 from the page 53 in the NFC 51 specified by the page address attached to the command. Instructs to read page data. Further, when the page data reading unit 45 reads the page data from the NFC 51, the command processing control unit 42 sends the header, CRC check code, and RS to the host interface unit 41 from the read page data. An instruction to transmit data from which the correction code has been removed to the host device 1 is given.

  When the page data read unit 45 receives a page data read instruction from the command processing control unit 42, the page data read unit 45 assigns the page address (logical address) attached to the page data read command in the SSD storage medium unit 5 according to a predetermined conversion rule. The page 53 included in all the NFCs 51 is converted into a uniquely identifiable physical address, and page data is read from the page 53 in the NFC 51 identified by the physical address.

  The page data reading unit 45 uses the RS code / decoding circuit 46 to remove the header, CRC check code, and RS correction code from the read page data, using the sector data shown in FIG. The data error in the data and the CRC check code portion is corrected, and the presence or absence of the data error in the data portion (that is, the presence or absence of error correction) is further checked using a CRC check circuit (not shown).

  The block state management unit 47 has a defective block table (not shown) and the like, and stores the address (physical address) of the block for identifying the defective block in the defective block table. When writing page data, management is performed so that the defective block is not used. A defective block includes a block 52 in which block data cannot be erased, a page 53 in which page data cannot be written, and a page 53 in which an uncorrectable error occurs in the read page data. This refers to block 52 and the like.

  In addition to the above, the SSD control unit 4 includes various functional blocks such as a functional block having a function of leveling the number of times of writing page data to each page 53. Description of those functional blocks is omitted.

Then, the outline | summary of RS code used by this embodiment is demonstrated. The RS code is well known as a code that can correct a plurality of symbol errors. Here, the symbol is, for example, m-bit data, and error correction is performed in units of symbols. When the symbol is m bits, the maximum value of the code length that can be corrected by the RS code (including a redundant symbol for correction to be added) is 2 ^m −1 symbols.

  In general, one symbol is often associated with 1-byte data. However, in the present embodiment, as shown in FIG. 2D, one sector data is 536B, so in the data of 536B. In order to enable error correction, m = 10. That is, in this embodiment, it is assumed that one symbol is 10-bit data. Therefore, predetermined 2-bit data such as “00” is added to the data (8 bits) of each byte constituting the sector, and is handled as 10-bit data, that is, a symbol.

  Further, in the RS code, it is necessary to add 2t redundant symbols in order to correct t symbol errors. The value of t can be determined as appropriate according to the error rate included in the data to be corrected. Here, for example, it is assumed that t = 8. Therefore, the total number of bits of the redundant symbol is 10 bits × 2 × 8 = 160 bits. In order to store the 160-bit redundant symbol data, the sector data shown in FIG. 20B (= 160 bits) is prepared.

  That is, in the present embodiment, the RS code / encoding circuit 44 (see FIG. 1) converts the 512B data and the data of each byte of the 4B CRC check code into 10 bits in the sector data (see FIG. 2). Using 516 symbols as an input symbol string, a 16-symbol RS correction code is generated and added to the input symbol string.

Here, according to the definition of the RS code, a generator polynomial G (X) for generating a 16-symbol RS correction code is expressed by the following equation (1).

G (X) = (X−α) (X−α ² ) (X−α ³ ) (X−α ¹⁶ ) Formula (1)

Here, α is an element of a so-called Galois extension field GF (2 ¹⁰ ) and a root of a 10th-order primitive polynomial (for example, X ¹⁰ + X ³ + 1 = 0).

Further, a message polynomial M (X) represented by an input symbol string (hereinafter referred to as an input message) to the RS code / encoding circuit 44 is represented by a polynomial of the order (number of symbols of input message-1) ( In this embodiment, it is a 515th order polynomial). Then, the coefficient of the message polynomial is represented by an element of the Galois extension field GF (2 ¹⁰ ) corresponding to each symbol.

Here, when a polynomial representing an RS correction code (hereinafter referred to as a parity polynomial) is represented as P (x), the parity polynomial P (x) can be obtained by the following equation (2).

P (X) = X ¹⁶ M (X) modulo G (X) Formula (2)

Here, X ¹⁶ M (X) modulo G (X) represents a remainder obtained by dividing the polynomial X ¹⁶ M (X) by the polynomial G (X).

Therefore, the parity polynomial P (X) is a 15th-order polynomial at most, and can be specifically expressed by the following equation (3).

P (X) = a ₁₅ X ¹⁵ + a ₁₄ X ¹⁴ +... + A ₁ X + a ₀ formula (3)

Here, the coefficients a ₁₅ , a ₁₄ ,..., A ₁ , a ₀ of the parity polynomial P (X) are all elements of the Galois extension field GF (2 ¹⁰ ). These 16 coefficients are nothing but the 16 symbols (= 160 bits = 20B) RS correction code added to the input message.

Therefore, the encoding polynomial C (X) obtained by adding the RS correction code to the input message can be expressed by the following equation (4).

C (X) = X ¹⁶ M (X) + P (X)
= Q (X) G (X) Formula (4)

That is, the encoding polynomial C (X) can be divided by the generator polynomial G (X). Q (X) is a polynomial representing the quotient at that time.

  As can be seen from the above description, the RS code / encoding circuit 44 is configured by a circuit that calculates the coefficient of the parity polynomial P (X) according to the equation (2). Since the circuit for calculating the coefficient of the parity polynomial P (X) is generally a well-known circuit, detailed description thereof is omitted here.

  Next, an outline of an RS code decoding procedure for correcting an error of a plurality of symbols will be described. In the present embodiment, the decoding of the RS code, that is, the error correction of the read data from the SSD storage medium unit 5 is performed by using the sector data of the page data read from the page 53 of the NFC 51 (see FIG. 2D). Done as a unit.

  In the sector data decoding, as in the case of encoding (RS correction code generation), the data (512B) + CRC check code (4B) in the sector data of the read page data is as follows. For example, predetermined 2-bit data such as “00” is added to the data (8 bits) of each byte, and the data is handled as 10-bit data, that is, a symbol. Also, the 20B (160 bits) RS correction code is converted into 16 symbols of 10 bits.

  Accordingly, all 532 symbols are input to the RS code / decoding circuit 46 (see FIG. 1). Therefore, when a polynomial having a symbol input to the RS encoding / decoding circuit 46 as a coefficient is hereinafter referred to as a reception polynomial R (X) according to common usage, the reception polynomial R (X) is expressed by the 531st order of X. Expressed in polynomial form.

Hereinafter, the RS code / decoding circuit 46 performs decoding, that is, correction of error symbols, according to the following procedure.
(Procedure 1) Based on the reception polynomial R (X), syndromes (S ₁ , S ₂ ,..., S ₁₆ ) are calculated.
(Procedure 2) Using the calculated syndromes (S ₁ , S ₂ ,..., S ₁₆ ), the highest order (hereinafter simply referred to as the order) and coefficient of the error position polynomial σ (X) are obtained.
(Procedure 3) The position of the error symbol is obtained using the error position polynomial σ (X).
(Procedure 4) Correct the error symbol.

  FIG. 3 is a diagram showing an example of the configuration of the RS encoding / decoding circuit 46 according to the embodiment of the present invention. As shown in FIG. 3, the RS code / decoding circuit 46 includes a syndrome calculation unit 461, an error position polynomial coefficient calculation unit 462, an error position search unit 463, and an error correction unit 464. The functions of these blocks substantially correspond to the above (Procedure 1) to (Procedure 4). In FIG. 3, the input symbol string input to the RS encoding / decoding circuit 46 is composed of a total of 532 symbols based on the sector data of the page data read from the page 53 of the NFC 51, and the reception polynomial R (X ).

The syndrome calculation unit 461 includes a known syndrome calculation circuit for realizing (Procedure 1). Here, the syndrome S _i (i = 1, 2,..., 16) is a value calculated by the following equation (5).

S _i = R (α ⁱ ) (i = 1, 2,..., 16) Equation (5)

Α ⁱ (i = 1, 2,..., 16) is the root of the generator polynomial G (X) = 0. That is, the syndrome S _i (i = 1, 2,..., 16) is a value obtained by substituting the root of the generator polynomial (G (X) = 0) into the reception polynomial R (X). be able to.

Here, when there is no error in the reception polynomial R (X), the reception polynomial R (X) and the encoding polynomial C (X) are the same, that is, R (X) = C (X). . At this time, as can be easily understood by referring to the equations (4) and (1), all the syndromes S _i are 0, that is, S _i = 0 (i = 1, 2,..., 16). . In other words, when all the syndromes S _i (i = 1, 2,..., 16) are 0, there is no error to be corrected. It is not necessary to perform ((Procedure 2) to (Procedure 4)).

On the other hand, if any one of the syndromes S _i (i = 1, 2,..., 16) is not 0, it means that there is an error in the reception polynomial R (X). Therefore, next, as the processing of (Procedure 2), the error locator polynomial coefficient calculation unit 462 obtains the order and coefficient of the error locator polynomial σ (X).

The error locator polynomial σ (X) is defined by the following equation (6).

σ (X) = 1 + σ ₁ X + σ ₂ X ² +... + σ _k X ^k equation (6)

Here, the order k of the error locator polynomial σ (X) is the number of error symbols. Further, the coefficient σ _j (j = 1, 2,..., K) of the error position polynomial σ (X) is defined by the following equation (7).

First, the error locator polynomial coefficient calculation unit 462 obtains the order k of the error locator polynomial σ (X) from Equation (7). First, the error locator polynomial coefficient calculation unit 462 sets k ′ = t (t = 8: the maximum number of correctable symbols) as an initial value of the provisional order k ′, and syndromes S _i (i = 1, 2). , ..., 2k-1), the value of the determinant on the left side of equation (7) is obtained. If the value of the determinant is not 0, the order k = k ′ = t is determined.

  On the other hand, when the value of the determinant on the left side of Expression (7) is 0, the error locator polynomial coefficient calculation unit 462 sets k ′ = k′−1 in the same manner as the left side of Expression (7). The value of the determinant is obtained, and thereafter, the same processing is repeated while subtracting k ′ one by one until the value of the determinant is not zero. Then, the value of k ′ when the value of the determinant on the left side of Equation (7) is no longer 0 is determined as the order k of the error position polynomial σ (X) (that is, k = k ′). The degree k of the error position polynomial σ (X) thus determined is the number of error symbols existing in the reception polynomial R (X) (hereinafter, the number of error symbols is also expressed as k).

As described above, when the order k of the error locator polynomial σ (X) is determined, the error locator polynomial coefficient calculator 462 calculates the coefficient σ _j (j of the error locator polynomial σ (X) based on the equation (7). = 1, 2, ..., k).

As specific algorithms for obtaining the coefficients σ _j (j = 1, 2,..., K) of the error locator polynomial σ (X), various algorithms such as the Balecamp Massey method (BM method) have been developed. A circuit based on the algorithm has also been developed. Therefore, since the error locator polynomial coefficient calculation unit 462 can be configured using such a known circuit, description thereof is omitted here.

Next, the error position search unit 463 obtains the position of the error symbol using the error position polynomial σ (X) as the processing of (Procedure 3). The error locator polynomial σ (X) expressed by the equation (6) has the following equation (8) when k error positions are β _j (j = 1, 2,..., K). Is known to hold.

σ (X) = (1 + β ₁ X) (1 + β ₂ X) (1 + β _k X) Equation (8)

That is, according to equation (8), the error position β _j (j = 1, 2,..., K) is given by the inverse of the root of the error position polynomial (σ (X) = 0).

A chain search circuit is known as a specific circuit for obtaining an error position β _j (j = 1, 2,..., K) that is the inverse of the root of the error position polynomial (σ (X) = 0). The Chien search circuit is a circuit that calculates the equation (6). When the inverse number (1 / β _j ) of all error positions β _j is substituted into the circuit, β when σ (X) = 0 is obtained. _j is searched.

Here, in this embodiment, the root of the error locator polynomial (σ (X) = 0) can be 1023 elements (α ⁰ , α ¹ , α ² ) of the Galois extension field GF (2 ¹⁰ ). ,..., Α ¹⁰²² ). Therefore, if an error position β _j (j = 1, 2,..., K) is to be obtained using the chain search circuit, 1023 operations are required by the chain search circuit, and the error position search time is long. Become. Therefore, in the present embodiment, by using a plurality of chain search circuits and using the fact that the number k of error positions is known at this time, that is, by using the error position search unit 463 shown in FIG. Shorten the search time for error locations.

  As shown in FIG. 3, the error position search unit 463 includes a search control circuit 4631, two chain search circuits 4632 (CS # 0, CS # 1), and two chain search circuits 4632 (CS # 0, CS #). # 1) are detected by two error counters 4633 (EC # 0, EC # 1) and two chain search circuits 4632 (CS # 0, CS # 1), which respectively count that the error position has been detected. An error position storage register 4634 that stores error position data and an adder 4635 that adds the contents of two error counters 4633 (EC # 0 and EC # 1) are configured.

  FIG. 4 is a diagram showing an example of the flow of error position search processing in the RS encoding / decoding circuit 46 according to the embodiment of the present invention. Here, the flow of error position search processing performed by the error position search unit 463 will be described with reference to FIG. 3 and FIG. 4.

As illustrated in FIG. 4, the error position search process in the error position search unit 463 is started by receiving a predetermined activation instruction signal from the error position polynomial coefficient calculation unit 462. When the activation signal is supplied from the error locator polynomial coefficient calculator 462, the error symbol number k and the coefficient σ _{j of the} error locator polynomial σ (X) obtained by the error locator polynomial coefficient calculator 462 (j = 1, 2, ..., k) are supplied together.

  Therefore, when receiving the activation instruction signal from the error position polynomial coefficient calculation unit 462, the search control circuit 4631 first initializes counters included in the error position search unit 463 (step S11). Here, the counters are error position counters (not shown) included in two error counters 4633 (EC # 0, EC # 1) and two chain search circuits 4632 (CS # 0, CS # 1), respectively. In the following, the value is represented by j0, j1). Therefore, the counters are initialized by clearing the two error counters 4633 (EC # 0, EC # 1) to zero and setting the value 266 in the error position counter included in one of the chain search circuits 4632 (CS # 0). This means that the value 532 is set to the error position counter included in the other chain search circuit 4632 (CS # 1) (j1 = 532).

  The value 532 means the data length of 10-bit sector data (including the CRC check code and RS correction code) in this embodiment, that is, the number of symbols in the input symbol string. The value 266 is a value that is ½ of the number of symbols in the input symbol string. That is, in this embodiment, an error position in the first half of the input symbol string is searched for by the chain search circuit 4632 (CS # 0), and an error in the second half of the input symbol string is searched by the chain search circuit 4632 (CS # 1). Search for a location.

  Next, when the two chain search circuits 4632 (CS # 0, CS # 1) receive an instruction to start searching for an error position from the search control circuit 4631, the error position corresponding to the given error position (j0, j1). The values of the polynomial σ (X) are calculated independently and in parallel with each other (steps S12 and S12a), and whether or not the value of the error locator polynomial σ (X) is 0 is determined independently ( Steps S13 and S13a).

  If the error position polynomial σ (X) is 0 as a result of the determination (Yes in steps S13 and S13a), the chain search circuit 4632 (CS # 0, CS # 1) 4633 (EC # 0, EC # 1) is counted up (steps S14, S14a), and the error position counter value (j0, j1) at that time is stored in the error position storage register 4634 (steps S15, S15a). ). On the other hand, if it is determined in steps S13 and S13a that the value of the error locator polynomial σ (X) is not 0 (No in steps S13 and S13a), the chain search circuit 4632 (CS # 0 and CS # 1) , Steps S14 and S14a to Steps S15 and S15a are skipped.

  Next, the search control circuit 4631 acquires the sum of the count values of the two error counters 4633 (EC # 0, EC # 1) via the adder 4635, and the sum of the count values is calculated as an error locator polynomial coefficient. It is determined whether or not the number k of error symbols given from the unit 462 is equal (step S16). If the sum of the count values of the two error counters 4633 (EC # 0, EC # 1) is equal to the number of error symbols k as a result of the determination (Yes in step S16), the search control circuit 4631 Since the same number of error positions as the number of error symbols k has been acquired, the chain search circuit 4632 (CS # 0, CS # 1) is instructed to end the search for the error position, and the error position search unit 463 executes the error position search. The error position search process is terminated.

  On the other hand, if the sum of the count values of the two error counters 4633 (EC # 0, EC # 1) is not equal to the number k of error symbols (No in step S16), the search control circuit 4631 further determines the error position. It is determined whether or not the counter value (j0) has reached 1 (step S17). In the determination, if the error position counter value (j0) has reached 1 (Yes in step S17), all the errors are detected by the two chain search circuits 4632 (CS # 0, CS # 1). Since the determination is made as to whether or not the value of the error position polynomial σ (X) is 0 for the position, the search control circuit 4631 selects the chain search circuit 4632 (CS # 0, CS # 1). An instruction to end the search for the error position is given, and the error position search process in the error position search unit 463 is ended.

  If it is determined in step S17 that the error position counter value (j0) has not reached 1 (No in step S17), the search control circuit 4631 and the two chain search circuits 4632 (CS # 0, CS # 0,. CS # 1) counts down each error position counter (j0 = j0-1, j1 = j1-1: step S18), and then returns to steps S12 and S12a, and repeats the processes in steps S12 and S12a. Run.

  When the above error position search processing is completed, the error position storage register 4634 stores data of the same number of error positions as the number k of known error symbols. The error position search unit 463 transmits an activation signal notifying the error correction unit 464 to that effect.

When receiving the activation signal, the error correction unit 464 receives the error position data stored in the error position storage register 4634 and the syndrome S _i (i = 1, 2,...) Supplied from the syndrome calculation unit 461. , 16) to calculate an error pattern, correct an error symbol included in the input symbol string input to the RS code / decoding circuit 46 based on the error pattern, and output a corrected symbol string To do.

  Note that the error pattern calculation processing in the error correction unit 464 can be realized using a well-known Forney algorithm or the like. Since the calculation circuit is also well known, the description thereof is omitted here.

  As described above, according to the present embodiment, the RS code / decoding circuit 46 can halve the error position search time because the two chain search circuits 4632 independently search for an error position in parallel. In the present embodiment, when searching for an error position, using the fact that the number k of error symbols is known, the search process is terminated when the same number of error positions are searched for as the number k of error symbols. The search process is terminated halfway. Therefore, the search time is shortened by the amount that the search process is terminated early. The shortening effect is probabilistic, but if the probability is simply averaged, it becomes 1/2.

  As described above, in the RS encoding / decoding circuit 46 according to the present embodiment, two chain search circuits 4632 are operated in parallel, and the search is performed as soon as the same number of error symbols k as known error positions are searched. By aborting the processing, the error position search time can be shortened to about ¼ compared to the case where one conventional chain search circuit is used. Therefore, the RS code decoding time in the RS code / decoding circuit 46 can be shortened. Further, in the SSD storage device 2 having such an RS encoding / decoding circuit 46, the page data read time is shortened, so the average access time of the SSD storage device 2 is shortened.

  In the embodiment described above, the RS encoding / decoding circuit 46 includes two chain search circuits 4632. However, for example, the RS code / decode circuit 46 includes more chain search circuits 4632 such as four or five. It doesn't matter. In that case, the search time for an error position can be shortened accordingly. However, it should also be noted that the number of chain search circuits 4632 cannot be increased unnecessarily because the chain search circuit 4632 itself is a circuit having a considerable circuit scale.

  In the embodiment described above, the SSD storage device 2 is described as an example of the storage device to which the RS code / decoding circuit 46 is applied. However, the storage device to which the RS code / decoding circuit 46 is applied is described. For example, a hard magnetic disk storage device, a DVD storage device, or a Blu-ray Disc (registered trademark) storage device may be used.

1 Host device 2 SSD storage device 3 Host bus 4 SSD control unit 5 SSD storage medium unit 41 Host interface unit 42 Command processing control unit 43 Page data writing unit 44 RS code / encoding circuit 45 Page data reading unit 46 RS code / Decoding circuit 47 Block state management unit 51 NFC
52 blocks 53 pages 461 syndrome calculation unit 462 error position polynomial coefficient calculation unit 463 error position search unit 464 error correction unit 4631 search control circuit 4632 chain search circuit 4633 error counter 4634 error position storage register 4635 adder

Claims (3)

Using a root of the Reed-Solomon code generator polynomial, a syndrome calculation unit that calculates a syndrome for an input symbol sequence composed of a plurality of symbols;
An error locator polynomial coefficient calculator that calculates the number of error symbols and the coefficient of an error locator polynomial included in the input symbol sequence using the syndrome calculated by the syndrome calculator;
An error position search unit that searches for an error position that is a position of an error symbol included in the input symbol sequence based on the error position polynomial having the calculated coefficient;
An error correction unit that corrects an error symbol at the searched error position;
A Reed-Solomon encoding / decoding circuit comprising:
The error position search unit includes:
A plurality of chain search circuits for sequentially searching for an error position where the value of the error position polynomial is 0 by sequentially changing position data representing a position of a symbol of the input symbol sequence;
Each of the plurality of chain search circuits is provided so as to correspond to each of the plurality of chain search circuits, and when the position data is sequentially changed, the number of error positions searched by each of the plurality of chain search circuits is counted. Multiple counters to
An adder that adds and outputs the values of the counters;
A search control circuit for controlling operations of the plurality of chain search circuits;
With
The search control circuit includes:
A search for error positions for different symbol positions in the input symbol sequence is performed in parallel by the plurality of chain search circuits independently of each other;
The Reed-Solomon encoding / decoding circuit, wherein when the output of the adder becomes equal to the number of error symbols, the error search in the chain search circuit is terminated. Using a root of the Reed-Solomon code generator polynomial, a syndrome calculation unit that calculates a syndrome for an input symbol sequence composed of a plurality of symbols;
An error locator polynomial coefficient calculator that calculates the number of error symbols and the coefficient of an error locator polynomial included in the input symbol sequence using the syndrome calculated by the syndrome calculator;
A plurality of chain search circuits that sequentially change position data representing the positions of symbols in the input symbol sequence, and search for the position of a symbol where the value of the error position polynomial having the calculated coefficient is 0 as an error position; Each of the plurality of chain search circuits is provided so as to correspond to each of the plurality of chain search circuits. When the position data is sequentially changed, the number of the error positions searched by each of the plurality of chain search circuits is counted. A plurality of counters, an adder for adding and outputting the values of the plurality of counters, and a search control circuit for controlling operations of the plurality of chain search circuits, and searching for an error position included in the input symbol string An error location search unit to perform,
An error correction unit that corrects an error symbol at the searched error position;
A Reed-Solomon encoding / decoding method in a Reed-Solomon encoding / decoding circuit comprising:
In the error position search unit, the search control circuit includes:
A search for error positions for different symbol positions in the input symbol sequence is performed in parallel by the plurality of chain search circuits independently of each other;
The Reed-Solomon encoding / decoding method, wherein when the output of the adder becomes equal to the number of error symbols, the search for the error position in the chain search circuit is terminated. A storage device comprising a Reed-Solomon code / encoding circuit for encoding write data and a Reed-Solomon code / decoding circuit for decoding read data,
The Reed-Solomon encoding / decoding circuit is
Using a root of the Reed-Solomon code generator polynomial, a syndrome calculation unit that calculates a syndrome for an input symbol sequence composed of a plurality of symbols;
An error locator polynomial coefficient calculator that calculates the number of error symbols and the coefficient of an error locator polynomial included in the input symbol sequence using the syndrome calculated by the syndrome calculator;
An error position search unit that searches for an error position that is a position of an error symbol included in the input symbol sequence based on the error position polynomial having the calculated coefficient;
An error correction unit that corrects an error symbol at the searched error position;
Comprising
The error position search unit includes:
A plurality of chain search circuits for sequentially searching for an error position where the value of the error position polynomial is 0 by sequentially changing position data representing a position of a symbol of the input symbol sequence;
Each of the plurality of chain search circuits is provided so as to correspond to each of the plurality of chain search circuits, and when the position data is sequentially changed, the number of error positions searched by each of the plurality of chain search circuits is counted. Multiple counters to
An adder that adds and outputs the values of the counters;
A search control circuit for controlling operations of the plurality of chain search circuits;
With
The search control circuit includes:
A search for error positions for different symbol positions in the input symbol sequence is performed in parallel by the plurality of chain search circuits independently of each other;
When the output of the adder becomes equal to the number of error symbols, the search for the error position in the chain search circuit is terminated.

Images