JP2003272983A - Program for extracting candidate for defect source and inspection system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a program for efficiently narrowing down a manufacturing device in which a malfunction has been caused by using defect-inspection data to a small number of wafers, although a great number of data are required in the prior art in a manufacturing process for semiconductors integrated circuits, etc. <P>SOLUTION: A candidate for a manufacturing device in which a malfunction has been caused is output by successively carrying out the following treatments, that is, a selection treatment 11 of a plurality of object wafers, a defect- coordinate data input treatment 12, a defect-coordinate data filtering treatment 13, an inspection process selection treatment 14, a classification treatment 15 for abnormal/normal wafers, a treatment-history data input treatment 16, an extraction treatment 17 for a part of treatment history data, a search treatment 18 for a common treatment device, and an output treatment 19 of a defect- source candidate list. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor integrated circuit,
We search for sources of foreign particles or pattern defects that are generated during the manufacturing of products such as thin film magnetic heads, optical devices, and liquid crystal displays.

[0002]

2. Description of the Related Art The prior art will be described below with reference to the manufacture of semiconductor integrated circuits. A semiconductor integrated circuit is generally divided into a pre-process for manufacturing a plurality of chips (elements) by layering layers such as a circuit pattern on a silicon wafer, and a post-process for separating individual chips to complete individual products. . Most of the defects that occur during manufacturing occur in a long preprocess involving fine processing, and improving the yield in the preprocess is an important issue for low-cost production. Here, the yield in the previous process is
It is the non-defective rate determined by the result of electrical inspection, which is the final test of the previous process, that is, the ratio of non-defective chips to the total number of chips on the wafer.

In the pre-process, a circuit pattern is broken or short-circuited due to foreign matter or pattern defects (hereinafter collectively referred to as defects) that occur during manufacturing, which lowers the yield. For the purpose of monitoring defects, foreign matter inspection equipment and visual inspection equipment are used. Generally, a foreign matter inspection device is a device that irradiates a wafer with laser light obliquely from above and detects the scattered light, and is sometimes called a dark field inspection device. An appearance inspection device is a device that takes an image of a circuit pattern and detects abnormal points by image processing.
There are bright field inspection devices and SEM type inspection devices. These are described in the article "Inspection System Supporting Improvement of Semiconductor Yield" published in the October 1999 issue of the magazine "Hitachi Kenroku". However, the foreign substance inspection device and the appearance inspection device are
There is no clear distinction other than the difference in detection principle.
The term generically referred to as a defect inspection device hereinafter.

There is an analysis method called commonality analysis as one means for searching for a defect source using the inspection data which is the inspection result of the defect inspection apparatus. The commonality analysis is, for example, a method to find out that the number of defects is generally large in the wafer processed by the first machine of the etching apparatus, and the number of defects is generally small in the wafer processed by the second machine.

Inspection systems equipped with a communality analysis function are already commercially available from several companies. The methods installed in these are statistical methods such as analysis of variance (ANOVA). For example, the 1999 International Conference “Ad
Vanced Semiconductor Manu
Pro of “Facturing Conference”
Ceedings “A New Systematic Yiel” on pages 21 to 24
d Ramp Methodology ", Japanese Patent Laid-Open No. 2000-12640, and" International Symposium "at the 2000 international conference.
on SemiconductorManufactu
"Proceedings of the Ring", pages 249 to 252, "Yield Ana"
lysis and Improvement by
Reducing Manufacturing Fl
There is a description of the method in "Actuation Noise".

On the other hand, although it is not a commonality analysis, as in Japanese Patent Laid-Open No. 2001-85491, information (processing history data) indicating which device the wafer has passed through is simply retrieved from the database and presented to the operator. Others,
It is known to be effective.

[0007]

Since the commonality analysis function installed in the conventional inspection system uses a statistical method, a large amount of inspection data is required. Since the final electrical inspection is performed on all wafers and a wealth of inspection data is often obtained, the conventional communality analysis function can be effectively used. However, the defect inspection is rarely performed on all wafers and is often a sampling inspection. Further, in a production line for high-mix low-volume production, it is not easy to collect a large amount of inspection data necessary for statistical analysis even if the inspection frequency is increased. Therefore, a method and information system for conducting a communality analysis with a small amount of inspection data have been desired.

Further, the commonality analysis function installed in the conventional inspection system utilizes the inspection data as it is. However, inspection data often includes a large amount of data that is unnecessary for analysis. When using a large amount of data, this is not a problem in many cases, but when analyzing with a small amount of data, it is important how to efficiently remove unnecessary data and perform analysis. For example, in FIG.
Is an example showing the distribution of defects generated in the chips formed on the wafer surface. The rectangular frame 330A represents the outer frame of the chip. Black circles 331A to 335A, 341 to 3
Denoted at 44 is the defect coordinates detected by the defect inspection apparatus. However, the black circles 341 to 344 are false detections (also referred to as pseudo defects) in which the defect inspection apparatus erroneously determines a defect that is not a defect to be a defect.
If unnecessary data such as false information is not excluded at the time of analysis, the chip 330A may be determined as an abnormal wafer with many defects. Therefore, false reports 341 to 344
Is efficiently excluded, and only the true defects 331B to 335B are analyzed like the chip 330B, and this wafer is judged to be a wafer having only five defects. If the commonality analysis is performed while including unnecessary data like 330A, it is not possible to correctly find a defective device by erroneously determining a wafer having an abnormality and a wafer having no abnormality.

The present invention provides a program for effectively conducting a commonality analysis by utilizing inspection data with few defect inspections, and an inspection system equipped with the program. In addition, a program that efficiently excludes unnecessary data included in the inspection data to perform effective analysis, and an inspection system equipped with the program are provided.

[0010]

[Means for Solving the Problems] In order to solve the above problems, the following points were mainly considered. (1) Prior to the commonality analysis, the wafers to be analyzed are classified into those having anomalies and those having no anomalies, and the difference is used for the analysis. (2) In order to classify the wafers with abnormalities and the wafers without abnormalities of (1), defects are selected by various methods. In particular, by using the circuit layout data and selecting only the defects in the designated area in the chip, it is possible to effectively exclude the inspection data unnecessary for the analysis. (3) Two defect inspection processes are selected to effectively narrow down the communality analysis target range from long processing history data. (4) Select a device through which an abnormal wafer passes in common, and give priority to defect source candidates in consideration of the device through which a normal wafer passes. (5) A graphical user interface for efficiently performing the above processing is provided.

Based on the above, the present invention is obtained by inspecting a plurality of inspected objects with an inspection device in a program executed to find out the source of foreign matter or pattern defect of the inspected object. Inspection data input processing for inputting a plurality of inspection data, and for each inspection object,
An abnormality is included from the processing history data input process for inputting the processing history data in which the history of the device that has been inspected for each manufacturing process is stored, and the plurality of inspection data input in the inspection data input process. From the object to be inspected, the object to be inspected classification process for classifying into the object to be inspected that does not include any abnormality, the result of classification in the object to be inspected process, and the history of the device included in the process history data It is characterized in that a source extraction process for extracting a candidate of a pattern defect source and an output process for outputting the source candidate extracted by the source extraction process are performed.

Also provided is an inspection system having the above-mentioned features.

More specifically, it is constructed as described in the claims.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the embodiments of the present invention, a pre-process manufacturing line for semiconductor integrated circuits and a wafer processing procedure will be described with reference to the drawings.

FIG. 2 is an example of a block diagram showing an apparatus group existing in the pre-process manufacturing line. Reference numeral 31 is a first CVD apparatus, 32 is a second CVD apparatus, 41 is a first coating apparatus, 42 is a second coating apparatus, and 51 is an exposure apparatus 1.
Reference numeral 52 is an exposure apparatus No. 2, 53 is an exposure apparatus No. 3, 54 is an exposure apparatus No. 4, 61 is an etching apparatus No. 1, 62 is an etching apparatus No. 2, 63 is an etching apparatus No. 3, 71 is the first implanter device, 72
No. 2 of the implanter device, 81 is No. 1 of the cleaning device, 8
2 is the second cleaning device, 83 is the third cleaning device, 91
Is the first developing device, 92 is the second developing device, 101
Is the first heat diffusion device, 102 is the second heat diffusion device,
111 is the first resist removing device, 112 is the second resist removing device, 113 is the third resist removing device, 121 is the first sputtering device, 122 is the second sputtering device, 131 is a defect inspection device, 141 Is the first tester for electrical inspection, 142 is the second tester, 1
43 is an inspection database, 144 is a progress management system,
An analysis unit 145 is connected to these devices and systems via a local area network 146 and exchanges data with each other. For example, when a wafer is processed by a certain device, the fact that the processing is completed from the device is notified via the local area network 146.
Notify progress management system 144, progress management system 1
At 44, processing history data is stored for each wafer. The processing history data will be described later. Further, the result of inspection by the defect inspection device 131 is stored in the inspection database 143 via the local area network 146. In the analysis unit 145, the inspection result of the inspection database 143 is read and the analysis for improving the yield is performed. It is general that there are more devices than the ones shown in FIG. 2 in the actual pre-process manufacturing line, but in this document, the above-mentioned device group will be used for the description below.

FIG. 3 is an example of a block diagram showing a wafer processing procedure in the pre-process manufacturing line. In FIG. 3, the wafer advances from left to right. Actually, although it depends on the type of integrated circuit, the previous process is completed after about 500 processes, but in FIG. 3, for convenience of explanation, it is abbreviated as 15 processes. There is. Squares in the figure indicate the devices that pass through them. Further, the vertically elongated rectangles 21 to 23 indicated by the diagonal lines are defect inspection devices, and defect inspection is performed here. The white vertically long rectangle 24 is a tester, and an electrical inspection is performed here.
For example, a wafer passes through various devices along the route indicated by the thick line to complete the pre-process. This passing device
It varies from wafer to wafer. Where the black square 2
When the device of 0 has a defect and a large number of defects occur, the defect inspection of 22 detects a large number of defects. It is an object of the present invention to quickly find this black square 20 device.

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is an example showing a processing procedure of the program of the present invention. FIG. 6 is an example of the main graphical user interface of the program of the present invention. The processing procedure of FIG. 1 will be described with reference to FIG.

First, in step 11, a plurality of target wafer selection processes are executed. For example, a wafer to be analyzed is selected under a condition such as "a wafer that has been subjected to a defect inspection after etching the wiring first layer from February 1st to February 2nd". In this embodiment, from February 1st to February 2nd,
In the defect inspection process called D07, the wafer IDs inspected are A001, A002, A003, A004, A0.
An example in which six wafers of 05 and A006 are selected will be described. In addition, the selected wafer will be described as an example in which all the defect inspection steps are inspected in principle, but the method of the present invention can be applied even if it is not inspected in all the defect inspection steps. it can.

Next, in step 12, a defect coordinate data input process for the target wafer is executed. The defect coordinate data is data such as 150 in FIG. 4 for each wafer.
In the defect coordinate data 150, the defect number, the position X, Y of the defective chip in the wafer, the coordinates X, Y of the detailed defect in the chip, the diameter of the defect, the defect category, etc. are written. In the case where the defect coordinates in the wafer surface are represented not only by dividing them into the chip position in the wafer surface and the detailed coordinates in the chip like the defect coordinate data 150, but also by expressing one coordinate system in the wafer surface. There is also. Further, the data items included in the defect coordinate data are different from the example of 150, and do not include diameter information or category information, and vary depending on the model of the defect inspection apparatus. FIG. 5 illustrates defect positions in the defect coordinate data 150. 160 represents the outer frame of the wafer, and 161
Nos. 1 to 168 are the dots printed based on the chips X and Y and the in-chip coordinates X and Y of the defect numbers 1 to 8 of the defect coordinate data 150. Even if the condition of the defect coordinate data input in step 12 is “wafer subjected to defect inspection after etching the wiring first layer from February 1 to February 2” in step 11, In some cases, only the defect coordinate data of the defect inspection after the etching of the first layer may be input, but not only that, but it is desirable to also input the other date and time of the target wafer and the defect coordinate data of the other defect inspection process at the same time. By this simultaneous processing, FIG.
It is possible to quickly display the inspection history for each target wafer as shown in FIG. This process is also necessary to extract adder defects described later.

FIG. 6 shows an example in which the result of inputting defect coordinate data is displayed on the graphical user interface 170. Wafer IDs (A001 to A006) are vertically arranged in 171 and a defect inspection process (D01
To D10) are arranged side by side and the defect coordinate data are displayed in a matrix. For example, the defect coordinate data of the defect inspection process of wafer ID A006 and D03 is 173. The round frame 173 represents the wafer, and the dots 174 and the like inside represent the coordinates of the defect. The thing like FIG. 5 is displayed small. In this example, it can be seen that the wafer A001 has already been completed up to the defect inspection D09 and that there are defect coordinate data from the defect inspections D01 to D09 and these are input. Wafers A002 and A003 have been completed up to defect inspection D08. However, it can be seen that the wafer A003 is being manufactured without performing the defect inspection D03. This means that when the wafer A003 should be subjected to the defect inspection D03, the defect inspection apparatus 131 is stopped due to a trouble, and the defect inspection D03 is omitted to proceed with the manufacturing. Also, the wafer A0
From 04 to A006, the defect inspection D07 has already been completed.

Next, in step 13 of FIG. 1, the defect coordinate data filtering process is executed. The defect coordinate data filtering process is the defect coordinate data 150.
Of these, if there is unnecessary data for analysis, it is the process of excluding it. For example, the target data may be limited to defects existing in a few chips in the wafer surface, defects existing in a specific circuit in the chip, or the defect diameter of the defect coordinate data 150 may be set to the defect diameter. It can be used to limit defects to a certain size or more, or to use defect coordinate data 150
Using the category information of the above, it is possible to limit the defects to a certain category or to exclude the defects already detected by the inspection performed on the same wafer before the inspection from the defects detected by the certain inspection. This is a process of limiting only defects. Of course, all defect coordinate data may be targeted without such filtering.

In the graphical user interface 170 of FIG. 6, the pull-down menu of 181 is limited to "adder defect". Pull-down menu 1
At 81, it is possible to select to use all the detected defects. Further, in the pull-down menu 182, the defect diameter is selected to be limited to defects of "0.1 micrometer or more". In the pull-down menu 182,
The size of the defect can be set without limitation, or different diameters such as 0.2 micrometer or more can be selected. This processing uses information on the diameter of the defect in the defect coordinate data 150 of FIG. Reference numeral 183 denotes a button that activates a graphical user interface for limiting the analysis area within the wafer surface. When the button 183 is clicked with the mouse, a new graphical user interface 210 shown in FIG. Defects existing in several chips can be limited to analysis targets. Details of FIG. 7 will be described later. In FIG. 6, 184 is a button that activates a graphical user interface for limiting the analysis area in the chip. When the button of 184 is clicked with the mouse, a new graphical user interface 220 in FIG. Defects existing in a region where a certain circuit exists can be limited as analysis targets.
Details of FIG. 8 will be described later. In 186, the defects to be analyzed are limited by the defect category. This processing uses the category of the defect coordinate data 150 of FIG. In FIG. 6, “al
“L” is displayed, and the setting is for all categories.

FIG. 7 is an example of a graphical user interface for limiting the analysis area within the wafer surface. The graphical user interface 210 displays the outer frame 211 of the wafer, the arrangement of the square chips 212, and the like. Here, the display color can be changed by clicking the chip with the mouse, and the four actually changed are the four chips such as 213. In this graphical user interface 210, the defect coordinate data can be read and displayed at the same time by clicking a “Read Coordinate Data” button 214.
An example in which the defect coordinate data 150 is read and displayed is a black circle such as a dot 215. Chips to be analyzed are limited by referring to the distribution of hit points. By clicking “execute”, the display returns to the graphical user interface 170 in FIG. 6, and the hit point of the defect coordinates such as 174 is changed based on the set contents. This processing uses the information of the chips X and Y of the defect coordinate data 150 of FIG. on the other hand,
If you click "Back", the contents set in the graphical user interface 210 will not be reflected.
Return to the 0 graphical user interface.

FIG. 8 is an example of a graphical user interface for limiting the analysis area in the chip. The graphical user interface 220 includes
An outer frame 221 of the chip is displayed based on the size of the chip. Also, by clicking the “Read Layout” button 224, CAD (Computer Aided)
Design) The circuit layout data of the integrated circuit created by the system is read and displayed. As a result of reading and displaying the circuit layout data, 231 and 232
The layout of the SRAM circuit block, the logic circuit block 234, and the microcomputer core circuit block 235 is displayed. Further, when the "Read Coordinate Data" button 225 is clicked, the defect coordinate data is read and the black circles 241 to 248 are marked at the defect positions. The analysis target area in the chip is set by referring to the layout of these circuit layouts and the coordinates of defects. For example, in the example of FIG. 8, the area of the microcomputer core circuit block is set and the display color is changed. Select whether you want to analyze only the area whose display color is changed or conversely exclude the area whose display color is changed from 2
22 "Mauku" or 223 "Unused in the mask"
Select one of them and decide. In this example, since “use in mask” is selected, only defects existing in the area 235 of the microcomputer core circuit block are to be analyzed. By clicking "Run", click 1 in Fig. 6
Returning to the graphical user interface 70, the hit point of the defect coordinates such as 174 is changed based on the set contents. This processing is performed by the defect coordinate data 150 of FIG.
The information on the in-chip coordinates X and Y is used. On the other hand, if you click "Back", the contents set in the graphical user interface 210 will be canceled and
Return to 70 graphical user interface. In this way, by the filtering process that limits only the defects in the designated area in the chip, for example, the commonality analysis can be performed only for the defects that frequently occur in a specific circuit. On the contrary, the commonality analysis can be performed by excluding the defects peculiar to a specific circuit. For example, in order to eliminate a false alarm detected in a region where a circuit block in the chip does not exist, a commonality analysis can be efficiently performed by performing a filtering process that specifies the region. At this time, the area can be set efficiently by displaying the circuit layout data. As described above, by specifying the block area and executing the commonality analysis, it is possible to accurately extract the candidate of the manufacturing apparatus that causes a defect occurring in a certain block area.

Next, in step 14 of FIG. 1, a process of selecting a defect inspection process to be analyzed is executed. On the graphical user interface of FIG. 6, two defect inspection processes are selected by clicking with a mask. In this example, D0
Two defect inspection processes of 6 and D07 are selected, and as a result,
A frame 193 and a frame 194 are drawn. A defect source candidate extraction process is performed on a wafer-by-wafer basis, a chip-by-chip basis, and a circuit block-by-circuit block targeting a manufacturing process between the two defect inspection processes selected by this selection process. In this example, the selected wafer is shown by a frame, but another method such as changing the display color may be used. Moreover, only one defect inspection process is selected, and 2
In the second defect inspection process, the defect inspection process immediately before that may be automatically determined. For example, when D07 is selected, D06 is also automatically selected. Further, the method is not limited to the manual selection of the defect inspection process, and a method of automatically selecting a wafer in which the number of defects exceeds a predetermined threshold and automatically setting the defect inspection process immediately before that may also be used.

Next, in step 15, classification processing is performed on the wafers having an abnormality and the wafers having no abnormality. Here, the defect coordinate data of the target of the classification process is the step 14
D07 on the right side of the two defect inspection processes selected in
Data. Also, only the defects defined in step 13 are of interest. Wafers with a limited number of defects equal to or greater than a predetermined threshold are classified as “abnormal”, and wafers less than the threshold are classified as “abnormal”. As a result of the classification, in the example of FIG. 6, the number of defects in the defect inspection process D07 of the wafers A004 and A005 is large, and these two wafers are “abnormal”, the wafers A001, A002, and A00.
3, A006 is the result classified as "no abnormality",
Frames 191 and 192 are displayed on the "abnormal" wafer. In this example, “abnormality” and “abnormality” are classified according to the magnitude relationship with the threshold value, but the operator of the graphical user interface 170 selects wafers A004 and A005 without setting the threshold value. You may.

Next, in step 16, the process history data input process for the target wafer is executed. The processing history data is, as indicated by 261 in FIG. 9, information in chronological order that each manufacturing process has been processed for each wafer in what manufacturing process at what time on which day of the month. Data. For example, in the example of 261, 1 on August 5, 2001
At midnight, manufacturing process code 10010 (locos surface oxidation)
It is described that the process was performed using the manufacturing apparatus code 0101 in the process of. This process history data also includes the inspection process. For example, in the example of 261,
It is described that at 9:30 on August 25, 2001, the process was performed using the manufacturing apparatus code 0131 in the manufacturing process code 20090 (defect inspection D06). In this way, both the manufacturing process and the manufacturing apparatus are coded, and the code of the manufacturing apparatus is defined by marking the apparatus code and the apparatus name as indicated by 262 in FIG.

Next, in step 17, partial processing history data extraction processing is executed based on the defect inspection process. In the partial process history data extraction process, the data written between the two defect inspection steps selected in step 14 is extracted from the process history data. For example, in step 14, the defect inspection processes D06 (process code 20090) and D07
When (process code 20180) is selected, the partial process history data 263 of FIG.
Is extracted.

Next, at step 18, a common processor searching process is executed. In step 17, every wafer (A0
01-A006), the partial processing history data extracted,
The manufacturing equipment that passed through each wafer is compared. Step 1
Wafers with "abnormal" classified in 5 and "no abnormal"
Compare the differences between the wafers. Specifically, the manufacturing process in which multiple “abnormal” wafers pass through the same manufacturing equipment, and “no abnormal” wafers use equipment different from the “abnormal” wafers is the most abnormal. Is likely to be the cause. Extract such manufacturing processes.

Next, at step 19, output processing of the defect source candidate list is executed. FIG. 12 is an example of a graphical user interface of output results. The partial processing history data extracted in step 17 is displayed, and the result in step 18 is displayed in a list. In the example of the graphical user interface 270, the process name of the partial process history data extracted in step 17
It is displayed vertically. Also, the target wafers A001 to A
006 are arranged side by side, and the corresponding manufacturing device codes are displayed at 273 to 278. Since wafers A004 and A005 are wafers classified as “abnormal” in step 15, in order to distinguish them, 276 and 2
The 77 list is displayed in a thick frame. of course,
You may change the display color instead of enclosing it with a thick frame. Also,
As a defect source candidate, the processing result in step 18 is set to 27
Listed in 2. The circle indicates two "abnormal"
Wafers are processed by the same manufacturing apparatus, and "abnormal" wafers are processed by different manufacturing apparatuses from the "abnormal" wafers. In this example, a circle is attached in two steps. For example, in the wiring 1 exposure process, the wafers A004 and A005 are processed by the device of the device code 0053, and the wafers A001 and A00 are processed.
No. 2, A003, A006 are not processed by the device code 0053, and therefore are circled. Further, the triangle marks are processes in which all of the "abnormal" wafers and at least one of the "abnormal" wafers are processed by the same manufacturing apparatus. The circled process has a high priority as a defect source candidate, the triangular process has a lower priority than the defect as a defect source candidate, and the unmarked process has a lower priority. The graphical user interface 270 returns to the graphical user interface 170 of FIG. 6 by clicking on the “Back” button 282.

As described above, according to the present invention, even when the frequency of defect inspection is low and only a small number of defect coordinate data exist, partial process history data is efficiently extracted from the long process history data, and further, It is possible to automatically narrow down the manufacturing process and manufacturing equipment of defect source candidates. Further, instead of simply using only the number of defects detected in the wafer surface, the number of chips in the wafer surface is limited, the target area in the chip is limited, and the size of defects is limited.
By extracting the adder defect, it is possible to accurately analyze the defect to be analyzed by excluding the data of the defect unnecessary for the analysis.

Next, FIG. 13 shows an example of a system configuration for executing the program of the present invention. Reference numeral 131 is a defect inspection apparatus, 143 is an inspection database, 144 is a progress management system, and 145 is an analysis unit. These are connected via a local area network 146, and data are mutually exchanged. The analysis unit 145 is a general computer including a control unit 301, a secondary storage device 302, a main storage device 303, a calculation unit 304, a user interface 305, a network interface 306, and the like. The program of the present invention is stored in the secondary storage device 3
02, and when the program of the present invention is activated by the operator from the user interface 305, the program is read from the secondary storage device 302 to the main storage device 303,
It is executed using the arithmetic unit 304. In steps 11 to 12 in FIG. 1, the defect coordinate data is retrieved from the inspection database 143 based on the information input by the operator through the user interface 305,
The defect coordinate data input from the network interface 306 is stored in the secondary storage device 302 or the main storage device 30.
3 is stored. In step 13, the calculation unit 304 processes the defect coordinate data stored in the main storage device 303. In step 14, the operator selects an inspection process from the user interface 305,
Information on the selected inspection process is stored in the main storage device 303. Step 15 uses the defect coordinate data and the inspection process information stored in the main storage device 303 to calculate the calculation unit 3
04 is used. In step 16, the processing history data stored in the secondary storage device 302 is read out and stored in the main storage device 303. Generally, before the program of the present invention is executed, the processing history data existing in advance management system 144 is stored in secondary storage device 302, but in some cases, it is stored in secondary storage device 302. No, step 1 of the program of the present invention
6, the progress management system 144 is searched, the processing history data is input from the network interface 306 via the network, and the processing history data is 2
It is stored in the next storage device 302 or the main storage device 303. In steps 17 to 19, the process history data and the inspection process information stored in the main memory 303 are used to
The result is processed by using the arithmetic unit 304, and the result is stored in the main memory 3
03 and the secondary storage device 302, and the result is output to the user interface 305.

In this example, the inspection database 143 and the analysis unit 145 are constructed by different computers and are connected by the network, but they may be constructed by the same computer. Similarly, the inspection database 143 and the analysis unit 145 are also provided.
May be realized by a computer inside the defect inspection apparatus 131.

Further, in the above-mentioned example, an example of an analysis method using a small amount of inspection data is shown instead of the conventional commonality analysis for finding a defect source statistically performed using a large amount of inspection data. However, even if there is a large amount of inspection data, as shown in FIG. 8, the conventional statistical communality analysis is performed after the unnecessary data is excluded by limiting the analysis target area in the chip. Is also effective.
At that time, the area setting can be efficiently performed by using the circuit layout data created by the CAD system.

FIG. 14 is an example showing a processing procedure when the present invention is applied to statistical commonality analysis. Steps 11 to 14 are the same as those in FIG. In FIG. 14, step 16 is skipped and step 16 and step 17 are performed. In FIG. 14, step 311 is performed instead of step 18 in FIG. In step 311, analysis of variance for each manufacturing process is performed. Finally,
In step 19, a defect source candidate list is output based on the result of the analysis of variance. FIG. 15 illustrates an example of analysis of variance for each manufacturing process performed in step 311. This is an example of variance analysis in the wiring 1 etching process of the processing history data 261 in FIG. Histograms 321, 322, 323 are created from the processing history data of a large number of wafers and the defect coordinate data limited in step 13. The histogram 321 is a wafer frequency histogram in which the number of defects counted from the defect coordinate data limited in step 13 is plotted on the horizontal axis for the wafer processed by the etching device No. 1 machine 61 in the wiring 1 etching process. It was created. Similarly, the histogram 322 is a histogram created for a wafer processed by the etching apparatus No. 2 machine 62 in the wiring 1 etching process, and the histogram 323 is obtained by using the etching apparatus No. 63 machine in the wiring 1 etching process. It is a histogram created for the processed wafer. Analysis of variance is a method of quantifying the difference between these three distributions. Using the formulas 1 to 5, the F of the formula 5
To find the value. It is determined that a manufacturing process having a larger F value has a higher probability of being a defect source, and several processes having a large F value are output in step 19.

[0037]

[Equation 1]

[0038]

[Equation 2]

[0039]

[Equation 3]

[0040]

[Equation 4]

[0041]

[Equation 5]

Here, k is the number of devices in the target manufacturing process, n _i
Is the number of wafers that have passed through the device i in the target manufacturing process,
X _ij is the number of defects on the j-th wafer of device i, and N is the total number of wafers.

[0043]

As described above, according to the present invention,
Even if the frequency of defect inspection is low, it is possible to efficiently narrow down the candidates of defect generation sources from a long manufacturing process. Further, instead of simply using only the number of defects detected in the wafer surface, the chips in the wafer surface are limited, the target area in the chip is limited, the size of defects is limited, and By extracting defects, data of defects unnecessary for analysis can be efficiently excluded, and the source of defects can be accurately analyzed from the defects to be analyzed.

[Brief description of drawings]

FIG. 1 is an example showing a processing procedure of a program of the present invention.

FIG. 2 is an example of a block diagram showing an apparatus and a system in a pre-process manufacturing line of an integrated circuit.

FIG. 3 is an example simply showing a front-end manufacturing process of an integrated circuit.

FIG. 4 is an example of defect coordinate data.

FIG. 5 is an example of visually displaying defect coordinate data.

FIG. 6 is an example of a graphical user interface.

FIG. 7 is an example of a graphical user interface for limiting an analysis target area within a wafer surface.

FIG. 8 is an example of a graphical user interface for limiting an analysis target area in a chip.

FIG. 9 is an example of processing history data.

FIG. 10 is an example of device code definition data.

FIG. 11 is an example of partial processing history data.

FIG. 12 is an example of a graphical user interface for displaying results.

FIG. 13 is an example of a configuration of an inspection system.

FIG. 14 is another example showing the processing procedure of the program of the present invention.

FIG. 15 is a diagram showing a concept of analysis of variance.

FIG. 16 is an example showing an occurrence distribution of defects in a chip formed on a wafer surface.

[Explanation of symbols]

A001 to A006 ... Wafer ID, D01 to D10 ...
Defect inspection process, 11 ... Target wafer selection process, 12 ... Defect coordinate data input process, 13 ... Defect coordinate data filtering process, 14 ... Inspection process selection process, 15 ... Abnormal / non-abnormal wafer classification process, 16 ... Process history data Input process, 17 ... Process history data partial extraction process, 18 ... Common processing device search process, 19 ... Defect source candidate list output process, 20 ... Defect device, 21-23 ... Defect inspection, 24 ...
Electrical inspection, 31 ... No. 1 of CVD apparatus, 32 ... No. 2 of CVD apparatus, 41 ... No. 1 of coating apparatus, 42 ... No. 2 of coating apparatus, 51 ... No. 1 of exposure apparatus, 52 ... No. 2 of exposure apparatus , 53 ... No. 3 of exposure apparatus, 54 ... No. 4 of exposure apparatus
No. 61, etching machine No. 1, 62 ... etching machine No. 2, 63 ... etching machine No. 3, 71
... No. 1 of the implanter device, 72 ... No. 2 of the implanter device, 81 ... No. 1 of the cleaning device, 82 ... No. 2 of the cleaning device, 83 ... No. 3 of the cleaning device, 91 ... No. 1 of the developing device, 92 ... Development No. 2 of the equipment, 101 ... 1 of the heat diffusion equipment
No. 102, No. 2 of heat diffusion device, 111 No. 1 of resist removing device, 112 ... No. 2 of resist removing device, 113 ... No. 3 of resist removing device, 121 ... No. 1 of sputtering device, 122 ... Sputtering device No. 2 machine, 1
31 ... Defect inspection device, 141 ... Tester No. 1 machine, 142
… Tester No. 2 machine, 143… Inspection database, 144
… Progress management system, 145… Analysis unit, 146…
Local area network, 150 ... Defect coordinate data, 160 ... Wafer outer frame, 161-168 ... Defect coordinates, 170 ... Graphical user interface, 1
71 ... Wafer ID list, 172 ... Defect inspection process list, 173 ... Wafer outer frame, 174 ... Defect coordinates, 18
1 ... pull-down menu for selecting adder defect / detection defect, 182 ... pull-down menu for limiting defect size, 183 ... button for specifying wafer in-plane area, 1
84 ... In-chip area designation button, 185 ... Defect category designation button, 191, 192 ... Abnormal wafer,
193, 194 ... Selected defect inspection step, 211 ... Wafer outer frame, 212 ... Chip, 213 ... Chips selected as non-analyzing target, 214 ... Coordinate data read button, 215 ... Defect coordinate, 216 ... Execute button, 217
... Return button, 220 ... Graphical user interface, 221 ... Chip outer frame, 222 ... Mask used selection button, 223 ... Mask unused selection button, 22
4 ... Circuit layout data read button, 225 ... Defect coordinate data read button, 231, 232 ... SRA
M circuit block area, 234 ... Logic circuit block area, 235 ... Microcomputer core circuit block area, 241 ...
248 ... Defect coordinates, 251 ... Execution button, 252 ... Return button, 261 ... Processing history data, 262 ... Device code definition data, 263 ... Partial processing history data, 270 ... Graphical user interface, 271 ... Manufacturing process list, 272 ... Malfunction Device candidate list, 273-27
8 ... Partial processing history data for each wafer, 279 ... Return button, 301 ... Control unit, 302 ... Secondary storage device, 303
... main storage device, 304 ... arithmetic unit, 305 ... user interface, 306 ... network interface,
311 ... ANOVA for each manufacturing process, 321-323 ... Histogram of wafer frequency with respect to number of defects

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 2G051 AA51 AB01 AB02 EA11 EA12                       EA14 EA21 EC02 FA01                 4M106 AA01 AA02 CA38 DJ20 DJ26                       DJ38 DJ40

Claims (18)

[Claims] 1. A program executed to find a source of a foreign substance or a pattern defect of an object to be inspected, in which a plurality of inspection data obtained by inspecting a plurality of objects to be inspected by an inspection apparatus are input. Data input processing, processing history data input processing for inputting processing history data in which the history of the apparatus through which the inspection object has passed through each manufacturing process is stored, and the inspection data input processing From the plurality of inspection data, an inspection target that includes an abnormality, an inspection target classification process that classifies the inspection target that does not include an abnormality, a result of classification by the inspection target classification process, and the processing history From the device history included in the data,
A defect source candidate extraction program, which executes a source extraction process for extracting a candidate of a source of a foreign substance or a pattern defect, and an output process for outputting a candidate of a source extracted by the source extraction process. 2. The defect source candidate extraction program according to claim 1, wherein in the inspection data input process, inspection data in a plurality of inspection steps are input for each inspection target. 3. In the inspecting object classification process, an inspecting object having a number of foreign particles or pattern defects equal to or more than a predetermined threshold is set as an inspecting object including an abnormality, and the number of foreign particles or pattern defects is determined. 2. The defect source candidate search program according to claim 1, wherein the inspection target that is less than the threshold is an inspection target that does not include any abnormality. 4. The number of foreign matters or pattern defects,
4. The defect source candidate search program according to claim 3, wherein only foreign substances or pattern defects detected in the wafer surface are present in a designated chip in the wafer surface. 5. The number of foreign matters or pattern defects,
4. The defect source candidate search program according to claim 3, wherein only those existing in a designated area in the chip are counted. 6. The number of foreign matters or pattern defects,
4. The defect source candidate search program according to claim 3, wherein only foreign substances or pattern defects having a size larger than a specified size are counted. 7. The number of foreign matters or pattern defects,
4. The defect source candidate search program according to claim 3, wherein among the foreign matters or pattern defects, the foreign matters or pattern defects are classified into several types in advance and only the designated types are counted. 8. The defect source candidate search according to claim 1, wherein the processing history data input in the processing history data input processing is data in which a pair of a manufacturing process and a manufacturing apparatus is stored in time series. program. 9. The defect source candidate search program according to claim 8, wherein the manufacturing process includes an inspection process. 10. The manufacturing process according to claim 1, wherein in the source extraction process, a manufacturing process in which all the inspection target objects including the abnormality are processed by the same apparatus is extracted from the processing history data. Defect source candidate search program. 11. In the source extraction processing, a manufacturing process in which all the inspection objects that do not include the abnormality are processed by an apparatus different from the inspection object that includes the abnormality is extracted from the processing history data. The defect source candidate search program according to claim 10. 12. In the process history data input process, two inspection processes that have inspected an object to be inspected are selected from the input process history data and are limited to manufacturing processes between the two inspection processes. The defect source candidate search program according to claim 1, wherein the source extraction processing is executed. 13. In the inspection object classification process, a graphical user interface is provided to visually display foreign matters or pattern defects of the inspection object,
The defect source candidate search program according to claim 1, wherein the program can be classified into an inspection target including an abnormality and an inspection target including no abnormality. 14. In the inspection target classification processing, a graphical user interface for displaying circuit layout data is provided, and a target area in a chip can be designated.
The defect source search program according to claim 1, wherein the inspection data is limited. 15. A program executed to find a source of a foreign substance or a pattern defect of an object to be inspected, in which a plurality of inspection data obtained by inspecting a plurality of objects to be inspected by an inspection device are input. Data input processing, specified area data extraction processing for extracting inspection data of a specified area in a chip from the inspection data input in the inspection data input processing, and each inspected object, inspected object for each manufacturing process A process history data input process for inputting process history data in which the history of the device that has passed to the storage device, and a plurality of the inspection data extracted in the designated region data extraction process,
Statistical source extraction processing for statistically extracting candidates for the source of foreign matter or pattern defects from the history of the device included in the processing history data, and source candidates extracted by the statistical source extraction processing And a defect source candidate extracting program for executing an output process for outputting. 16. In the specified area data extraction processing,
The defect source candidate search program according to claim 15, further comprising a graphical user interface, displaying circuit layout data, and designating an area in a chip. 17. An inspection apparatus for detecting a foreign substance or a pattern defect possessed by an object to be inspected, and a production management system for managing the history of the apparatus through which the object to be inspected passes in each manufacturing process.
An input unit connected to the inspection apparatus and the production management system via a network, for inputting a plurality of inspection data obtained by inspection by the inspection apparatus and a plurality of processing history data managed by the production management system; The inspection data is classified into an inspection target that includes an abnormality and an inspection target that does not include an abnormality, and a foreign substance or a pattern defect is generated based on the classification result and the history of the apparatus included in the processing history data. An inspection system comprising: a calculation unit that extracts a source candidate; and an output process that outputs a source candidate extracted in the source extraction process. 18. An inspection apparatus for detecting foreign matters or pattern defects possessed by an object to be inspected, and a production management system for managing the history of the apparatus through which the object to be inspected passes through each manufacturing process.
An input unit connected to the inspection apparatus and the production management system via a network, for inputting a plurality of inspection data obtained by inspection by the inspection apparatus and a plurality of processing history data managed by the production management system; , Extracting inspection data in a specified area in the chip from the inspection data, and statistically determining candidates of a source of foreign particles or pattern defects from the inspection data in the specified area and the history of the apparatus included in the processing history data. An inspection system comprising: a calculation unit that selectively extracts a source; and an output process that outputs a candidate of a source extracted by the source extraction process.