JP2003258082A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which a silicon oxide film that does not deteriorate in a form is buried in an element separation groove. <P>SOLUTION: An etching resistant mask 13 is formed on a semiconductor substrate 11. By etching the semiconductor substrate 11, an element separation groove 15 is formed. On the semiconductor substrate 11 on which the element separation groove 15 is formed, a coating film of perhydrogenated silazane polymer solution is formed. Then it is chemically reacted to form a silicon oxide film 18. After the formed silicon oxide film 18 is removed while it is left in the element separation groove 15, the buried silicon oxide film 18 is densified by heat treatment. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an element isolation structure.

[0002]

2. Description of the Related Art In recent years, S has been used as an element isolation method for semiconductor devices.
The TI (Shallow Trench Isolation) method is widely used. This is a method in which a groove is formed in an element isolation region of a semiconductor substrate and a silicon oxide film or the like to be an element isolation insulating film is embedded in the groove. The high-density plasma CVD method (HDP method), which has an excellent embedding property, is used to fill the element isolation trench.
The silicon oxide film according to US Pat. However, as the element is miniaturized and the element isolation groove becomes 0.1 μm or less, it becomes difficult to sufficiently fill the groove even by the HDP method.

On the other hand, there is a method of using a coating film as a groove burying method which does not depend on the HDP method. For example,
A STI groove filling method using a perhydrogenated silazane polymer solution has been proposed (see Japanese Patent No. 3178410 and US Pat. No. 6,191,002). This method applies a perhydrogenated silazane polymer solution to a semiconductor substrate having an element isolation groove, modifies the coating film into a silicon oxide film by a chemical reaction, and performs a densification treatment to remove unnecessary portions. This is to remove and fill the groove with a silicon oxide film.

Specifically, the chemical reaction of the coating film of the perhydrogenated silazane polymer solution is carried out by evaporating the solvent in the coating film and then performing a heat treatment in a steam atmosphere. By this heat treatment, the perhydrogenated silazane polymer [(SiH ₂ NH) _n ] reacts with oxygen obtained by decomposition of water vapor to be modified into a silicon oxide film to generate ammonia. Thereafter, the silicon oxide film is subjected to heat treatment at 700 ° C. to 1100 ° C. in an inert atmosphere to remove impurities such as ammonia and water,
Densified.

According to this method, even when it is applied to the filling of a fine element isolation groove having a width of about 0.1 μm,
(A) The silicon oxide film can be embedded without generating voids, and (b) the modification of the perhydrogenated silazane polymer into the silicon oxide film does not cause volume shrinkage, so that cracks do not occur. c) Since the embedded silicon oxide film has a high etching resistance, it is said that a recess due to unnecessary etching will not occur in the wet etching process of the silicon nitride film or the like.

[0006]

The device isolation trench filling method using the above-mentioned perhydrogenated silazane polymer solution is promising for application to LSI, which is further miniaturized in the future. Therefore, there are still problems to be solved. One of them is that the resistance of the silicon oxide film embedded in the element isolation trench to wet etching varies depending on the trench width.

Specifically, in a portion where the width of the element isolation groove is narrow, the etching rate in wet etching of the embedded silicon oxide film does not sufficiently decrease, and the silicon oxide film to be embedded is larger than that in a portion where the groove width is wide. The surface position of is lowered. Therefore, the silicon oxide film cannot be embedded in the element isolation trenches of various widths with a uniform thickness.

Another problem is that the wet etching resistance of the portion of the silicon oxide film formed by the chemical reaction which is in contact with the silicon nitride film is low. The silicon nitride film is used as a mask for forming the element isolation trench, and is left until the trench is filled with the silicon oxide film. The coating film of the perhydrogenated silazane polymer solution is modified into a silicon oxide film by a chemical reaction, and then the densified silicon oxide film is embedded in the groove by CMP treatment. Then, a step of removing the silicon nitride film with phosphoric acid and further removing the silicon oxide film with buffer hydrofluoric acid is performed. In this wet etching process using buffered hydrofluoric acid, the etching rate of the portion of the silicon oxide film embedded in the groove that was in contact with the silicon nitride film is high, and a dent occurs at the boundary of the element isolation region.

Specifically, FIG. 15 shows a state of the silicon oxide film 4 buried in the element isolation trenches having different widths by the above-mentioned conventional method. The silicon oxide film 4 is obtained by performing a densification treatment at 900 ° C. or lower after the reaction. In FIG. 15, after the silicon oxide film 4 is densified, unnecessary portions are removed by CMP to planarize it.
Further, it shows a state of being etched by buffered hydrofluoric acid. As shown in the figure, the height of the embedded silicon oxide film 4 varies depending on the width of the element isolation trench. Also,
In the element isolation groove having a narrow width of 0.1 μm, a portion in contact with the silicon nitride film 3 is largely etched, and a dent is generated.

It is an object of the present invention to provide a method of manufacturing a semiconductor device, which can embed a silicon oxide film in an element isolation groove without deterioration of shape.

[0011]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming an etching resistant mask on a semiconductor substrate and element isolation by etching the semiconductor substrate through an opening of the etching resistant mask. A step of forming a groove, and a semiconductor substrate in which the element isolation groove is formed,
A step of forming a coating film of a perhydrogenated silazane polymer solution,
The coating film is subjected to a chemical reaction after volatilizing a solvent to form a silicon oxide film, a step of removing the silicon oxide film by leaving it inside the element isolation trench, and a step of leaving the silicon oxide film in the element isolation trench. And a step of densifying the silicon oxide film by heat treatment.

According to the present invention, the step of densifying the silicon oxide film obtained by chemically reacting the perhydrogenated silazane polymer solution is performed after the unnecessary portion is removed by leaving only the element isolation trench, thereby narrowing the process. Embed as a silicon oxide film with excellent etching resistance even in the element isolation trench,
The shape deterioration can be prevented.

In the present invention, the etching resistant mask for forming the element isolation trench is formed to include, for example, a silicon nitride film. In this case, it is preferable to add a step of forming a silicon oxide film on the surface of the silicon nitride film after forming the element isolation groove and before forming a coating film of the perhydrogenated silazane polymer solution. This prevents the silicon oxide film obtained by chemically reacting the perhydrogenated silazane polymer solution from directly contacting the silicon nitride film, and uniformly densifies the silicon oxide film embedded in the element isolation trench.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIGS. 1 to 8 show an element isolation process of a semiconductor device according to one embodiment. As shown in FIG. 1, a silicon oxide film 12 having a thickness of about 5 nm is formed on the surface of a silicon substrate 11 by a thermal oxidation method, and a reduced pressure CV is formed thereon.
A silicon nitride film 13 is deposited to a thickness of about 200 nm by the D method.

The silicon nitride film 13 is formed on the silicon substrate 11
It is used as an etching resistant mask when forming the element isolation trench. As shown in FIG. 2, the silicon nitride film 13 and the silicon oxide film 12 are selectively etched by a lithography process and RIE to form a mask opening 14. In this state, the silicon substrate 11 is etched by RIE to form the element isolation groove 15 as shown in FIG.

Thereafter, thermal oxidation is performed to form a silicon oxide film 16 on the inner surface of the element isolation trench 15 as shown in FIG. At this time, preferably, the silicon oxide film 6 is also formed on the surface of the silicon nitride film 13. Therefore, in this embodiment, radical oxidation is used. The reason why the silicon oxide film 16 is formed on the surface of the silicon nitride film 13 is to avoid a situation in which the perhydrogenated silazane polymer film formed thereafter is in direct contact with the silicon nitride film.

Thereafter, as shown in FIG. 5, the perhydrogenated silazane polymer solution 17 is applied onto the substrate by spin coating. Then, heat treatment is performed in an inert gas atmosphere to volatilize the solvent in the perhydrogenated silazane polymer solution 17, and then heat treatment is performed in an oxidizing atmosphere such as steam to chemically react the perhydrogenated silazane polymer. The silicon oxide film 18 is reacted to be modified as shown in FIG.

Before the heat treatment for densification, the silicon oxide film 18 thus formed is filled with the element isolation trenches 15 by removing unnecessary portions by the CMP method. In this way, a heat treatment for densifying the silicon oxide film 18 is performed in a state where it is embedded only in the element isolation trench 15. This densification heat treatment is performed at 900 ° C to 1 in an inert atmosphere.
It is preferably carried out in the range of 100 ° C.

Then, the silicon nitride film 13 is removed by wet etching with phosphoric acid, and the silicon oxide film 12 is removed by wet etching with buffer hydrofluoric acid to obtain the state shown in FIG.

According to this embodiment, the element isolation insulating film can be embedded at a uniform height regardless of the width of the element isolation trench. The reason is as follows. As shown in FIG. 6, a thick silicon oxide film 18 is formed on the entire surface of the substrate before the CMP process.
When the densification treatment is performed in the state where the element isolation trench is covered, the etching rate is not sufficiently reduced in the narrow portion of the element isolation groove. On the other hand, in this embodiment, as shown in FIG. 7, the unnecessary silicon oxide film 1 on the substrate is processed by the CMP process.
By removing 8 and then densifying the silicon oxide film 18, the etching rate of the silicon oxide film 18 becomes sufficiently low even in the narrow portion of the element isolation trench.

FIG. 9 shows a state in which the silicon oxide film 18 is buried in the element isolation trenches of different widths at a substantially uniform height according to this embodiment, corresponding to FIG.
Further, in this embodiment, the surface of the silicon nitride film 13 is covered with the silicon oxide film 16 so that the perhydrogenated silazane polymer solution does not directly contact the silicon nitride film 13. As a result, it is possible to reliably prevent the situation where the etching rate of the portion in contact with the silicon nitride film is high and the shape deterioration occurs in this portion as in the conventional case.

[Second Embodiment] Another embodiment will be described with reference to FIGS. 1 to 3 are the same as those of the previous embodiment. In this embodiment, after the element isolation trenches 5 are formed, as shown in FIG. 10, the silicon nitride film 13 is wet-etched to slightly recede the opening end face thereof. After that, the same steps as those in the previous embodiment are performed.

That is, as shown in FIG. 11, the element isolation groove 1
A silicon oxide film 16 is formed on the inner surface of 5 and the surface of the silicon nitride film 13. Then, a perhydrogenated silazane polymer solution is applied, and a heat treatment in a steam atmosphere causes a chemical reaction of the solution to transform it into a silicon oxide film 18 as shown in FIG. Further, a CMP process is performed to flatten the silicon oxide film 18 in the element isolation trench 15 as shown in FIG. 13, and then a heat treatment for densification is performed.

According to this embodiment, the same effect as that of the previous embodiment can be obtained, and the edge portion of the silicon oxide film 18 embedded in the element isolation trench 15 is etched in the subsequent wet etching process. The inconvenience caused by is avoided. That is, in the wet etching process of the silicon nitride film 13 and the silicon oxide film 12, some receding of the silicon oxide film 18, which is an element isolation insulating film, cannot be avoided. FIG. 16 shows a state in which the edge portion of the silicon oxide film 4 to be buried by the conventional method is largely etched, and a large dent is generated at the boundary of the element isolation region. This causes leakage or short circuit of the element formed later. In the case of this embodiment, since the silicon oxide film 18 covers a wider area than the element isolation groove 15, the inside of the element isolation groove 15 is reliably covered with the silicon oxide film 18 without causing the state shown in FIG. Can be filled.

[Third Embodiment] In the above embodiments, a radical oxidation method is used as a method for forming the silicon oxide film 16 on the surface of the silicon nitride film 13. In addition to this, using the low pressure CVD method or the plasma CVD method,
As shown in FIG. 14, the silicon oxide film 21 may be thinly deposited from the inner surface of the element isolation groove 15 to the surface of the silicon nitride film 13. However, also in this case, it is preferable to previously form the silicon oxide film 16 by thermal oxidation on the surface of the element isolation groove 15.

[0026]

As described above, according to the present invention, the densification treatment of the silicon oxide film formed in the device isolation trench filling using the perhydrogenated silazane polymer solution is performed.
By performing after removing the unnecessary portion, it becomes possible to embed the silicon oxide film without deterioration of shape.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a silicon nitride film deposition step according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a step of etching a silicon nitride film of the same embodiment.

FIG. 3 is a cross-sectional view showing a step of etching an element isolation groove of the same embodiment.

FIG. 4 is a cross-sectional view showing a step of forming a silicon oxide film on an element isolation trench and a silicon nitride film of the same embodiment.

FIG. 5 is a cross-sectional view showing a step of applying the perhydrogenated silazane polymer solution according to the same embodiment.

FIG. 6 is a cross-sectional view showing a chemical reaction step of the perhydrogenated silazane polymer solution according to the same embodiment.

FIG. 7 is a cross-sectional view showing a CMP process and a densification process of the same embodiment.

FIG. 8 is a cross-sectional view showing a wet etching step of the silicon nitride film and the silicon oxide film of the same embodiment.

FIG. 9 is a cross-sectional view showing how a silicon oxide film is embedded in element isolation trenches of different widths according to the same embodiment.

FIG. 10 is a cross-sectional view showing a silicon nitride film etching step after forming element isolation trenches according to another embodiment.

FIG. 11 is a cross-sectional view showing a step of forming a silicon oxide film on an element isolation trench and a silicon nitride film of the same embodiment.

FIG. 12 is a cross-sectional view showing a silicon oxide film forming step using the perhydrogenated silazane polymer solution according to the same embodiment.

FIG. 13 is a cross-sectional view showing a CMP process and a densification process step of the same embodiment.

FIG. 14 is a cross-sectional view showing a step of forming a silicon oxide film on a silicon nitride film according to another embodiment.

FIG. 15 is a cross-sectional view showing a state of embedding an element isolation groove by a conventional method.

FIG. 16 is a cross-sectional view showing the deterioration of the shape of an element isolation insulating film by a conventional method.

[Explanation of symbols]

11 ... Silicon substrate, 12 ... Silicon oxide film, 13 ... Silicon nitride film, 14 ... Opening, 15 ... Element isolation groove, 16 ...
Silicon oxide film, 17 ... Perhydrogenated silazane polymer solution,
18 ... Silicon oxide film, 21 ... Silicon oxide film.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Atsuko Kawasaki             8th Shinsugita Town, Isogo Ward, Yokohama City, Kanagawa Prefecture             Ceremony company Toshiba Yokohama office (72) Inventor Satoshi Matsuda             8th Shinsugita Town, Isogo Ward, Yokohama City, Kanagawa Prefecture             Ceremony company Toshiba Yokohama office (72) Inventor Kazukazu Matsumori             8th Shinsugita Town, Isogo Ward, Yokohama City, Kanagawa Prefecture             Ceremony company Toshiba Yokohama office F term (reference) 5F032 AA35 AA44 AA45 AA69 AA77                       DA03 DA04 DA10 DA23 DA24                       DA33 DA53 DA74                 5F058 BA02 BC02 BF46 BH02 BH07                       BH20 BJ06

Claims (4)

[Claims] 1. A step of forming an etching resistant mask on a semiconductor substrate, a step of etching the semiconductor substrate through an opening of the etching resistant mask to form a device isolation groove, and the device isolation groove being formed. Forming a coating film of the perhydrogenated silazane polymer solution on the semiconductor substrate, a step of forming a silicon oxide film by chemically reacting the coating film after volatilizing the solvent, and forming the silicon oxide film. A method of manufacturing a semiconductor device, comprising: a step of removing the silicon oxide film left inside the element isolation groove and a step of densifying the silicon oxide film left in the element isolation groove by heat treatment. 2. The etching resistant mask is formed to include a silicon nitride film, and the silicon nitride film is formed after forming the isolation trench and before forming a coating film of the perhydrogenated silazane polymer solution. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a silicon oxide film on the surface of the. 3. The etching resistant mask is formed to include a silicon nitride film, and the silicon nitride film is formed after forming the isolation trench and before forming a coating film of the perhydrogenated silazane polymer solution. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming a silicon oxide film on the surface of the silicon nitride film after performing etching for retreating the opening end face of 1. 4. The step of forming a silicon oxide film on the surface of the silicon nitride film is performed by radical oxidation or low pressure CVD.
4. The method for manufacturing a semiconductor device according to claim 2, wherein the method is a plasma CVD method or a plasma CVD method.