JP2003242788A - Nonvolatile semiconductor memory device and control method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device in which write can be performed and a lifetime can be lengthened. <P>SOLUTION: This device has a memory cell array having a plurality of blocks being writable and erasable, a control means having an erasing flag indicating whether each of a plurality of blocks is already erased or not, a control means detecting unused blocks out of a plurality of blocks and writing new data in the unused blocks, a means setting an erasing flag corresponding to a block in which old data to be rewritten is recorded to 'erased', an erasing means erasing selectively a block in which an erasing flag is set, a means corresponding a logic address corresponded to a physical address of a block having old data to a physical address of a block in which new data is written. Each of a plurality of blocks is an erasing unit as a unit being smaller than a nonvolatile semiconductor memory chip in which a memory cell array is realized. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a NAN in an electrically rewritable nonvolatile semiconductor memory device (EEPROM).
The present invention relates to a non-volatile semiconductor memory device using a D-type EEPROM and its control method.

[0002]

2. Description of the Related Art Generally, a rewritable storage device (storage element) in a computer system has a physical limit in its capacity, and therefore, it is used by overwriting new information on unnecessary information. The rewritable memory device (memory element) can be roughly divided into two types according to the method of overwriting. One of them is a random access memory (RAM), a hard disk, a floppy disk, or a magnetic tape that can overwrite new information as it is with old information. The other is that, like some types of optical storage devices and EEPROMs, old information to be overwritten cannot be written until new information must be erased.

There are two methods of erasing the NAND type EEPROM, one of which is, for example, a flash E manufactured by Intel Corporation.
This is a method of erasing the information of the entire chip at one time like EPROM. The other is a method of selectively erasing only the information of a part of the chip.

In the NAND type EEPROM, a plurality of structurally continuous storage cells for reading data continuously and writing data are called in units of pages. For example, in a 4M bit EEPROM, 1
A page is composed of 4096-bit storage cells. A plurality of pages that are structurally continuous are referred to as a block. For example, in a 4-Mbit EEPROM, one block is composed of storage cells for 8 pages (4 kbytes). In the NAND type EEPROM, the unit for selectively erasing only the information of a part of the chip is
It matches this block.

Since the NAND type EEPROM can erase only a part of the data as described above, it is a non-volatile memory element in which the operation of rewriting only the data for one sector can be performed relatively easily as in the magnetic disk device. . Therefore, by taking advantage of the characteristics of semiconductor memory such as reliability regarding mechanical strength, low power consumption, and fast read time, it has been used for applications that replace conventional magnetic disk devices.

However, while the EEPROM has a high access time for reading data, it takes time to write data. For example, in the case of a 4M-bit NAND type EEPROM, the time required to read one block of data is about 490 μsoc, but to erase and rewrite one block, it takes about 10 msec to erase.
It takes about 4 msec to write data.

Further, the current technology limits the number of times data is rewritten, and the life is reached by rewriting 10 4 to 105 times. Therefore, if overwriting of data is concentrated on the same block, the life of the chip itself is shortened.

[0008]

As described above, the NAND is used.
In the conventional nonvolatile semiconductor memory device using the type EEPROM, it takes a longer time to write data than a data read time, and moreover, there is a limit in the number of times of rewriting. there were.

An object of the present invention is to provide a non-volatile semiconductor memory device which can solve such a problem, can perform writing at high speed, and can prolong the life thereof, and a control method thereof.

[0010]

In order to solve the above-mentioned problems, the present invention has a first feature that (a) a memory cell array having a plurality of blocks each of which can be selectively written and erased. (B) management means having an erase flag indicating whether or not each of the plurality of blocks has been erased; and (c) control means for determining an unused block from the plurality of blocks and writing new data into the unused block. (D) means for setting an erase flag corresponding to a block in which old data to be rewritten is recorded to erased, and (e) means for selectively erasing a block in which an erase flag is set, ( F) A method of associating the logical address that was associated with the physical address of the block that had the old data with the physical address of the block where the new data was written. And (g) each of the plurality of blocks is an erasing unit as a unit smaller than a non-volatile semiconductor memory chip in which a memory cell array is realized. Use as a summary.

A second feature of the present invention is a data rewrite control method for a non-volatile semiconductor memory device including a memory cell array having a plurality of blocks each of which can be selectively written and erased. Each of the blocks is an erase unit as a unit smaller than a nonvolatile semiconductor memory chip in which a memory cell array is realized, and (b) a step of determining an unused block among a plurality of blocks, and (c) rewriting Writing new data in an unused block without erasing the block having the old data; and (d) selectively erasing the block in which the old data was recorded,
(E) a step of associating a logical address associated with a physical address of a block having old data with a physical address of a block in which new data is written. The gist is that it is a method of controlling the device.

[0012]

According to the first feature of the present invention, new data is written to unused block areas which have been erased in advance as much as possible. As a result, in the non-volatile semiconductor memory device, the erasing operation, which originally needs to be performed prior to the writing and inevitably increases the access time, is omitted, and high-speed writing becomes possible. Further, even when the same data is updated / changed, the physical writing position changes each time writing is performed, so that it is possible to avoid an increase in the number of times of writing to a specific block and to prolong the life.

According to the second aspect of the present invention, new data is written to an unused block area which has been erased in advance as much as possible. As a result, in the non-volatile semiconductor memory device, the erasing operation, which originally needs to be performed prior to the writing and inevitably increases the access time, is omitted, and high-speed writing becomes possible. Further, even when the same data is updated / changed, the physical writing position changes each time writing is performed, so that it is possible to avoid an increase in the number of times of writing to a specific block and to prolong the life.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a nonvolatile semiconductor memory device. In the figure, reference numeral 1 denotes a NAND type EEPROM module as a memory means, which is composed of a memory cell array divided into blocks composed of a plurality of pages. The EEPROM module 1 is connected to a host system (not shown) via a host interface 2 connected by a data line. A multiplexer 9 and a data buffer 10 are provided on the data line. In the host interface 2,
A data register 3, an address register 4, a count register 5, a command register 6, a status register 7 and an error register 8 are provided. 11 is a control logic, 12 is an ECC (error correction code) generator / checker, 13 is an address generator, 14
Is a CPU having a function as an erasing unit and a control unit,
Reference numeral 15 is a work RAM, and 16 is a control program ROM. The control program ROM 16 is adapted to store a series of control programs for writing data.

The memory device of this embodiment uses a management table for allocating and managing the position of the data recorded in the EEPROM module 1 which is a non-volatile memory area. Although this table is recorded in the EEPROM module 1 together with other user data, it is automatically read into the work RAM 15 when the device is started up. The content of this table is updated each time writing is performed to the EEPROM module 1, and the updated table is written back to the EEPROM module 1 each time or when the use of the device is finished. Be decided.

One of the tables is a table (management table) for managing unused blocks, the structure of which is shown in FIG. The other is a comparison table between the addresses designated by the host system shown in FIG. 4 and the physical addresses on the memory module.

First, an example of the table for managing the unused blocks in FIG. 3 will be described. First 210 in table
Is for managing unused data blocks in a chain, and is a pointer to the first block of the chain. The second 211 in the table is a pointer for the same purpose but to the end of the chain. The third to n + 2th columns of the table correspond to the first to nth physical blocks of the NAND type EEPROM module 1. These contents are further composed of a pointer 213 to the next unused block and an erase flag 214, as illustrated in 212. M on the table
The contents are "-1" like the pointer in the 218th.
If it is, it means that it is the end of the chain. Therefore, in this example, the last pointer 211 points to the m-th 218 of the table, so the content is set to m. The erasure flag 214 indicates whether or not the corresponding block has been erased, and is "0" here.
The case is erased, and the case of "1" is not erased.

An outline of operation when data is recorded will be described using a specific example. Now, assume that the chain of unused blocks is as shown in FIG. To record data, first, the contents of the head pointer 101 are checked. Figure 2
In (a), since it points to the 53rd table, the physical block address on the writable NAND type EEPROM module 1 is 51 after subtracting the offset 2. After writing to block 51,
The table 10 corresponding to the block 51 is set by resetting the value of the head pointer 101 to the point destination 33 of 102.
Remove 2 from this chain. The results are shown in Fig. 2 (b).

When the data of the existing block is no longer needed due to this writing, the data of FIG.
The table is updated as shown in.
If it is assumed that the block 45 records the unnecessary data, the pointers in the 151st 104 of the table pointed to by the last pointer 105 and the values of the last pointer 105 correspond to the block 45. Reset to table number 47. 47th on table 10
The pointer in 7 is "-1", and the erase flag is "-1".
Is set to.

Since the block immediately after being added to the chain of unused blocks is not erased, when the read / write access is interrupted, the chain is sequentially rotated and erased, and the erase flag of the table corresponding to the block is erased. Is set to "0".

Next, the comparison table of FIG. 4 will be described.
The length n of the table is equal to or less than the block of the NAND type EEPROM module 1. For example, for the sake of simplicity, here, the EEPROM module 1 is a 4M bit EEP
Assuming that it is composed of one ROM, the capacity of one block is 4 kbytes, so the total number of blocks is 12
There will be eight, and the number of items n in the control table is 128 or less.

In this device, the EEPROM module 1
E is the unit of the amount of data corresponding to the capacity of the block
The physical location on the EPROM module 1 is assigned. That is, the first item in the table indicates the physical position where the first 4 kbytes of data designated by the host system is actually recorded. In the example of FIG. 4, 203
Is the third item in the table, so 4 kbytes from the 8 kth byte of the address (hereinafter referred to as logical address) specified by the host system is actually EE
It is shown that it is assigned to the 101st block of the PROM module 1. Also, 201, 202
As described above, the table in which "-1" is written indicates that the physical area is not allocated because the writing to the logical address corresponding to the position has not been executed yet.

Next, the operation of this device will be described. The host system sets the access start address in the address register 4 in the host interface 2 of FIG. 1, sets the sector length of the data to be accessed in the count register 5, and finally sets the read / write command in the command register 6. . When an access command is written in the command register 6 of the host interface 2, the CPU 14 in the controller reads the command in the command register 6 and executes a series of control programs for command execution stored in the control program ROM 16. In the following description, for simplicity, it is assumed that the sector length designated by the host system and the page length in the EEPROM module 1 match.

FIG. 5 is a flowchart showing a procedure for reading data from the EEPROM module 1. First, the CPU 14 of FIG. 1 refers to the start address set in the host interface 2 and the address conversion table in the management table, and reads EEPRO.
The physical address on the M module 1 is determined (step 301). Next, the data is read from the EEPROM module 1 to the data buffer 10 (step 30).
2). Next, error processing and data transfer from the data buffer 10 to the host system, which will be described later, are executed (steps 303 to 305).

FIG. 6 is a flow chart showing a procedure for reading data from the EEPROM module 1 to the data buffer 10. The CPU 14 accesses the EEPROM module 1 through the multiplexer 9 to set the read mode, and sets the data buffer 10 in the read mode (steps 401 and 402). A physical address of the EEPROM module 1 to be read is set in the address generator 13 (step 40).
3). Then, an area in which the read data is to be stored is determined in the data buffer 10 and its head address is set as a write address to the data buffer 10 (step 404). After that, the control logic 11 is instructed to execute a predetermined sequence for reading data.

The control logic 11 sets the multiplexer 9 so that the read data from the EEPROM module 1 flows to the data buffer 10 and increments the contents of the address generator 13 while
Data for one sector is read (step 405). Further, the EEC generator / checker 12 is controlled to detect an error by using these data and the ECC code read together with the data. When the data for one sector is read out, the CPU 14 checks the ECC generator / checker 12 for an error in the data (step 406). If no error is detected, or if it is detected and corrected, the data buffer 1
Transfer data from 0 to the host system. If an uncorrectable error is detected, the CPU 14 does not transfer data to the host system, and the CPU 14 sends a code indicating that an error has occurred to the status register 7 in the host interface 2 to the error register 8 A code indicating the content of the error is set in, the host system is notified that the execution of the instruction has terminated abnormally, and the processing ends (steps 407 to 410).

FIG. 7 is a flowchart showing the procedure for transferring data from the data buffer to the host system. The CPU 14 sets the head address of the area where the data read out to the data buffer 10 is stored as the read address from the buffer (steps 501, 50).
2) Instruct the control logic 11 to transfer data for one sector to the host system. The control logic 11 uses the data buffer 10
By controlling the host interface 2 and transferring one sector of data to the host system (step 50).
3) When this is completed, the address register 4 is advanced by one sector, 1 is subtracted from the count register 5, and the CPU 14
Notify that the transfer is complete. The CPU 14 repeats this control as long as data to be transferred remains in the host system. When all the read data has been transferred, C
The PU 14 sets a code indicating that there is no error in the status register 7 in the host interface 2, notifies the host system that the instruction has been executed, and ends the process.

FIG. 8 and FIG. 9 are flowcharts showing the procedure for writing data to the EEPROM module 1. The CPU 14 refers to the start address set in the host interface 2 and the address conversion table in the management table to determine the block on the EEPROM module 1 allocated to the address to which the host system is trying to write (step 601). ).
EEPR corresponding to the address designated by the host system
If the block on the OM module 1 is already allocated and the request from the host system does not rewrite all the data of the block, the unrewritable data in the block is read into the data buffer 10 (step 602). ~ 604). The procedure for reading data from the EEPROM module 1 to the data buffer 10 has been described above with reference to the flowchart of FIG. The processing of FIG. 6 is repeated until all the data of the portion in the block which is not overwritten is read into the data buffer 10. Then, the write data transfer from the host system to the data buffer 10, the data write processing from the data buffer 10 to the EEPROM module 1 and the error processing, which will be described later, are executed (steps 605 to 611).

FIG. 10 shows a procedure for transferring write data from the host system to the data buffer 10. The CPU 14 sets the data buffer 10 in the write mode (step 701), and sets the address on the data buffer 10 where the data transferred from the host system is stored as the write address to the buffer (step 702). After that, the control logic 11 is instructed to transfer data for one sector from the host system. The control logic 11 controls the data buffer 10 and the host interface 2 to receive one sector of data from the host system, and when this is completed, notifies the CPU 14 that the transfer is completed (step 703). The process of FIG. 10 is continued as long as the data to be transferred from the host system remains and the data for the block in which the EEPROM module 1 is to be written is insufficient in the data buffer 10. When the transfer from the host system is completed, the CPU 14 refers to the start address set in the host interface 2 and the table that manages the unused blocks, and manually chains the unused blocks as described above to obtain the data. Buffer 1
The unused block on the EEPROM module 1 to which the data for one block stored in 0 is to be written is determined, and writing is performed on the EEPROM module 1.

FIG. 11 is a flow chart showing a procedure for writing one page of data in the data buffer 10 into the EEPROM module. CPU14 is EEPR
After initializing the OM module 1 and the data buffer 10 if necessary (steps 801, 802), the start address of the page to be written is set in the address generator 13 (step 803), and the data buffer 10 is set.
Is set as the read address of the buffer (step 80).
4). Then, the control logic 11 is instructed to execute a predetermined sequence for writing data. The control logic 11 sets the multiplexer 9 so that the write data from the data buffer 10 flows to the EEPROM module 1, and writes the data while incrementing the content of the address generator 13 (step 805). Also, ECC
EC from generator / checker 12 from these data
It is controlled to generate a C code, and this code is recorded together with the data (step 806). The process of FIG. 11 is continued until a write error occurs or writing of data for one block is completed (step 80).
7). If the data cannot be written normally, error processing is performed, the block on the EEPROM module 1 into which the data for one block should be written is reassigned, and the writing is performed again. When the writing is completed normally, the contents of the management table are updated.

When the recording of all the data requested by the host system is completed or the processing is interrupted because the recovery from the error is impossible, the CPU 14 causes the host interface 2
A predetermined code is set in the status register 7 therein to notify the host system that the execution of the instruction is completed.
At an appropriate timing when the access command is not written in the command register 6 of the host interface 2, the CPU 14 in the controller sequentially erases the unerased blocks while handing the chain of the unused block management table, as described above. Go on.

In the above embodiment, the EEPROM module 1 is controlled by the controller capable of operating in parallel with the host system via the host interface 2.
It may take a form directly controlled by U. Other,
The present invention can be variously modified and used without departing from the spirit thereof.

[0033]

As described above, according to the present invention,
New data is written to unused blocks that have been erased in advance as much as possible.Therefore, it is necessary to write new data before writing, and the erase operation that forces an increase in access time is omitted and writing is omitted. It can be done at high speed. Further, even when the same data is updated / changed, the physical writing position changes every time writing is performed, so that an increase in the number of times of writing to a specific block is avoided and a long life can be achieved. An apparatus and a control method thereof can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a diagram (No. 1) for explaining an operation of a table for managing unused blocks in the present embodiment.

FIG. 3 is a diagram (No. 2) for explaining the operation of the table for managing the unused blocks in the present embodiment.

FIG. 4 is a diagram showing a configuration of a comparison table for address conversion in the present embodiment.

FIG. 5 is a flowchart for explaining a process of reading data from the EEPROM module 1 in this embodiment.

FIG. 6 is a flowchart for explaining a process of reading data from the EEPROM module 1 to the data buffer 10 in this embodiment.

FIG. 7 is a flowchart for explaining a read data transfer process from the data buffer 10 to the host system in the present embodiment.

FIG. 8 is a flowchart (part 1) for explaining a process of writing data to the EEPROM module 1 in the present embodiment.

FIG. 9 is a flowchart (part 2) for explaining a process of writing data to the EEPROM module 1 in the present embodiment.

FIG. 10 is a flowchart for explaining a write data transfer process from the host system to the data buffer 10 in the present embodiment.

FIG. 11 is a flowchart for explaining the process of writing the data in the data buffer 10 to the EEPROM module 1 in the present embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... EEPROM module (memory means) 2 ... Host interface 3 ... Data register 4 ... Address register 5 ... Count register 6 ... Command register 7 ... Status register 8 ... Error register 9 ... Multiplexer 10 ... Data buffer 11 ... Control logic 12 ... EEC Generator / Checker 13 ... Address Generator 14 ... CPU that executes erase processing, write processing, copy processing, etc. of an unerased block 15 ... Work RAM 16 ... Control program ROM

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Claims (2)

[Claims] 1. A memory cell array having a plurality of blocks each of which is selectively writable and erasable, management means having an erase flag indicating whether each of the plurality of blocks has been erased, and the plurality of blocks. Of the unused blocks,
Control means for writing new data to the unused block; means for setting the erase flag corresponding to a block in which old data to be rewritten is recorded to erased; and a block for which the erase flag is set. Means for selectively erasing, and means for associating the logical address associated with the physical address of the block having the old data with the physical address of the block in which the new data is written, A nonvolatile semiconductor memory device, wherein each of the plurality of blocks is an erase unit as a unit smaller than a nonvolatile semiconductor memory chip in which the memory cell array is implemented. 2. A data rewrite control method for a non-volatile semiconductor memory device including a memory cell array having a plurality of blocks each of which can be selectively written and erased, wherein each of the plurality of blocks implements the memory cell array. An erase unit as a unit smaller than a nonvolatile semiconductor memory chip that is present, and a step of determining an unused block among the plurality of blocks, and a block having old data to be rewritten to the unused block without erasing. Writing new data; associating a logical address associated with the physical address of the block having the old data with a physical address of the block in which the new data is written; When writing to the block is complete, And notifying the system, after the step of notifying the control method of the nonvolatile semiconductor memory device characterized by comprising the step of erasing the block in which the were recorded old data selectively.