JP2003179585A - Phase pulling method and equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform phase pulling at a high speed when timing phase information is extracted from a power spectrum of a receiving signal which is subjected to amplitude modulation by a frame unit or a subframe unit and timing phase synchronization of the receiving signal is performed by using the timing phase information. <P>SOLUTION: A vector signal of the power spectrum is produced, multiplied by the other vector signal, and rotated. Sign decision of the rotated vector signal is performed, and the results are integrated and outputted as a timing phase signal. The integrated value is vector-converted and fed back as the other vector signal. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase lead-in method and apparatus, and more particularly to a phase lead-in method and apparatus for time equalization used in a modem used for ultra-high-speed data transmission using a metallic line. It is a thing.

[0002]

2. Description of the Related Art Generally, a modem has been used for transmitting data using a telephone line, a private line, a metallic line on a premises, etc., but in recent years, there has been a strong demand for speeding up the processing of the modem. Has been.

A field in which such a modem is used is, for example, power line carrier communication. In this power line carrier communication, an extremely large amount of random noise (white noise) generated by home appliances such as an inverter device is included, which impedes the practical application of high-speed data communication.

As a countermeasure against such noise, recently, a DMT (Discrete MutiTone) system and an OFDM (Ortho
The gonal FrequencyDivision Multiplexing method has been proposed. The DMT method and the OFDM method adopt a multi-carrier (multi-channel) modulation method, which is a technique of avoiding a noisy carrier band and avoiding it. However, since the multi-carrier is used, FIG. Even if the signals of the respective channels are simultaneously transmitted on the transmitting side as shown in (), a group delay occurs as shown in (2) of FIG. As shown, the arrival time of each channel is different on the time axis. Therefore, on the receiving side,
Inter-channel interference occurs on the time axis.

That is, as shown in FIG. 13, in the DMT system and the OFDM system, since a low-speed rectangular wave is transmitted, a normal transmission signal as shown in FIG. (Tone) is obtained, but in the portion where the rectangular wave changes, as shown in (1) and (3) of the figure, the unnecessary band of each channel becomes a waveform that is attenuated by the function sinx / x.

As described above, under the line characteristic in which the group delay occurs, the signals of the individual channels interfere with each other on the time axis, and the inter-channel interference is avoided only in the portion where the line characteristic is flat. On the other hand, on the transmitting side, the time corresponding to the interference part (that is, the time corresponding to the changing part of the rectangular wave)
, Can be avoided from inter-channel interference by masking as a guard time GT as shown in FIG. 13, but data cannot be transmitted by the guard time GT.
It makes high-speed transmission difficult.

Therefore, it is necessary to equalize each channel on the time axis in order to solve such a line group delay problem. On the other hand, even in the same device, the static characteristics greatly differ depending on the ON / OFF state of the power supply. For example, in a home electric appliance using a switching power supply such as a television, as shown in FIG. 14 (1), two transfer functions A (or C) and B (or D) are determined depending on whether the voltage is below a certain value or above a certain value. ) Is 120
It will be switched alternately every Hz (when the used frequency is 60 Hz). That is, the transfer function is switched 240 times per second.

When the transfer function changes in this way, the frequency characteristic (amplitude / phase) is divided into a solid line showing the transfer functions A and C and a dotted line showing the transfer functions B and D, as shown in FIG. And they are very different from each other. Such fluctuations in the phase characteristics include fluctuations on the time axis.

Therefore, in a modem or the like used for power line carrier communication, since high-speed follow-up performance for a transmission line is required, not only high-speed equalization on the time axis but also on the frequency axis as described above. Although equalization is also necessary, equalization on the time axis also contributes to equalization on the frequency axis.

FIG. 15 shows a conventional technique for realizing the equalization on the time axis and the equalization on the frequency axis as described above. The time equalizer 1, the guard time remover 2, and the FFT ( Fast Fourier transform) DMT distribution unit 3, frequency equalization unit (FEQ) 4, determination unit (DEC) 5, and code conversion unit 6
It has a configuration in which and are connected in series.

In this configuration, the time equalization unit 1 performs equalization on the received signal on the time axis, after which the guard time removal unit 2 removes the guard time added on the transmission side, and further DMT. The distribution unit 3 performs FFT conversion. After that, the frequency equalization unit 4 equalizes the amplitude and phase of the carrier, and the determination unit 5 determines the code, and then the code conversion unit 6 performs natural (N) / Gray code (G) conversion and parallel. The received data RD is obtained by performing (P) / serial (S) conversion and code conversion such as descramble (DSCR).

Prior art document information related to the present invention is as follows.

[0013]

[Patent Document 1] Japanese Unexamined Patent Publication No. 2000-68973

[0014]

[Patent Document 2] Japanese Patent Laid-Open No. 2000-261406

[0015]

[Patent Document 3] Japanese Patent Laid-Open No. 2000-286817

[0016]

In such a conventional technique, a special training signal is required for the phase equalization on the time axis in the time equalization unit 1, and this training signal is long. Not only was it time consuming, but it also required complex processing associated with this training.

That is, with 1: n multipoint,
As described above, since high-speed tracking capability is required for the line characteristics that vary in units of 120 Hz, it is not possible to give a long training time to each point, and the processing must be simple.

Therefore, an object of the present invention is to provide a phase pulling method and apparatus for time equalizing the line group delay of a received signal in a short training time.

[0019]

First, a time equalization method using the phase lead-in method according to the present invention will be described below. Frequency signals simultaneously transmitted on different channels are received at different times as shown in FIG. 1A due to the group delay characteristics of the line.

Then, by performing the timing phase control shown in FIG. 2B, the signal waveforms that have reached different times shown in FIG. 1A are time-equalized in accordance with the group delay characteristics of the line. Then, the signal arrival times are aligned as shown in FIG. Looking at this by focusing on the waveform in one channel, as shown in FIG. 2A, before the timing phase equalization, the original reception point may deviate from the sample point. Recognize. In this state, the channels interfere with each other.

Therefore, after equalizing the timing phase as shown in FIG. 2B in all channels, the reception point and the sampling point coincide with each other, and inter-channel interference disappears. Since the problem shown in 13 is solved, high-speed transmission becomes possible.

Here, in the case of performing amplitude modulation on a frame-by-frame basis, two reference points including a zero point on the transmission carrier are provided for each frame, which is the master frame shown in FIG. 3A, as shown in FIG. By inserting R1 and R2, timing phase synchronization can be performed only with these two reference point signals R1 and R2.

Further, in the case of performing amplitude modulation on a subframe basis, amplitude modulation can be performed on a subframe, which is a modulation unit, between frames, which are master frames shown in FIG. 4A. Therefore, regardless of the frame unit or the sub-frame unit, the timing phase information is extracted from the power spectrum of the amplitude-modulated received signal, and the timing phase synchronization of the received signal is performed based on this, so this timing phase information is used. The extraction time is short and does not require long training signals.

The FFT transform can be performed after the second step, or the FFT transform can be divided before and after the FFT transform. In the latter case, there is a merit that time equalization can be performed with the amount of calculation being halved. Further, in the latter stage of the second step, frequency equalization can be executed by extracting carrier amplitude information and phase information from the received signal and performing timing phase and carrier amplitude and phase pull-in. 14 problems are solved.

Here, the above-mentioned first step is a phase pull-in step according to the present invention, in which a vector signal of the power spectrum is generated and a step of multiplying the vector signal by another vector signal and rotating the vector signal. And a step of determining the sign of the rotated vector signal,
The step of integrating the result of the sign determination and outputting it as the timing phase information, and the step of vector-converting the integrated value and feeding back as another vector signal can be configured.

That is, since only the timing phase information is calculated and no other parameters are required, the amount of calculation is small and the timing phase can be pulled in at high speed. Further, if the step of performing the above-mentioned code determination halves the result of the code determination for each arithmetic processing, it is possible to pull in the timing phase at a higher speed.

An apparatus for implementing the above-described phase acquisition method according to the present invention comprises means for generating a vector signal of a power spectrum of a received signal, means for multiplying the vector signal by another vector signal and rotating the vector signal. Means for determining the sign of the rotated vector signal, means for integrating the result of the sign judgment and outputting as the timing phase information, and means for converting the integrated value into a vector and feeding it back as the other vector signal. It is characterized by having and.

[0028]

FIG. 5 shows an embodiment of a modem in a time equalization method and apparatus using the phase acquisition method and apparatus according to the present invention. In this modem 10, the transmission system includes a code conversion unit 11, a signal point generation unit 12, a DMT multiplexing unit (IFFT) 13, an amplitude modulation unit 14, and a D / D unit.
The A converter 15 and the low pass filter (LPF) 16 are connected in series in this order.

In the receiving system, a bandpass filter (BPF) 17, an A / D converter 18, a time equalizer 1, a guard time remover 2, and a DMT distributor (FFT) 3 are provided.
The frequency equalization unit (FEQ) 4, the determination unit (DEC) 5, and the code conversion unit 6 are serially connected in this order. Each unit of this reception system includes a DMT master frame synchronization unit 19 A master frame signal is provided.

First, regarding the operation in the transmission system,
The code conversion unit 11 performs scramble processing (SCR), serial (S) / parallel (P) conversion, gray (G) / natural (N) code conversion, and Japanese sentence operation on the transmission signal SD. Then, the signal point generator 12 outputs the signal as a transmission signal having sample points with Nyquist intervals (12 kB) as shown in FIG.

The output signal from the signal point generator 12 is DMT.
In the multiplexing unit 13, the transmission signal as shown in FIG. 3B is multiplexed between the master frames shown in FIG. 3A by the inverse FFT (IFFT) operation. This multiplexed signal is sent to the amplitude modulation section 14 at (3) in FIG.
A guard time is added in each subframe as shown in (1) and (2), and two reference points R including a zero point for performing amplitude modulation as shown in FIG. 3D.
1 and R2 are added to the DMT multiplexed signal (each DMT signal is composed of 16 symbols = channel DMT signal).

One reference point R1 is (1 + j0), and the other reference point R2 is (0 + j0), which means that both are used for amplitude modulation. Timing phase information is extracted from this and the former one is used. The amplitude and phase of the carrier are extracted using the reference point R1 (for one subframe). Therefore, since time equalization and frequency equalization can be realized with two subframes, a long training signal becomes unnecessary.

The output signal of the amplitude modulator 14 is converted into an analog signal by the D / A converter 15, and the low-pass filter 16 outputs only the low frequency band including the frequency band (10 to 450 kHz) of the power carrier, for example. The signal is extracted and sent to the transmission line.

Next, regarding the operation of the receiving system, the received signal received from the receiving line is subjected to a predetermined frequency band component (10 in the case of a power carrier modem) by the bandpass filter 17.
.About.450 kHz) is extracted and converted into a digital signal in the A / D converter 18.

After that, the received signal is sent to the time equalization unit 1. An example of this time equalizer 1 is shown in FIG.
In this embodiment, a timing phase control unit 7 that inputs a reception signal from the A / D conversion unit 18, and a subframe extraction unit 8 that extracts timing phase information θ from the reception signal and gives the timing phase control unit 7 to the timing phase control unit 7. It is composed of.

The sub-frame extractor 8 is further 90 °
It is composed of a section extraction unit 81, a power calculation unit (PWR) 82, and a θ extraction unit 83. The master frame extraction unit 9 extracts a master frame from the received signal and supplies it to the DMT master frame synchronization unit 19 shown in FIG. 5 to use it as various synchronization signals.

As shown in FIG. 7, the timing phase control section 7 shown in FIG. 6 delays the received signal at every sampling point interval and a coefficient for the output signal from the delay circuit 71. Multiplier circuit 72 for multiplying C1 to Cn
And an adder circuit 7 for adding the output signal of the multiplier circuit 72
3 and a conversion unit 74 composed of, for example, a table for converting the timing phase information θ from the subframe extraction unit 8 into the above-mentioned coefficients C1 to Cn (for example, Japanese Patent Laid-Open No. 10-224271). The transversal filter can be used.

The operation of the time equalizer 1 will be described with reference to FIGS.
This will be described below with reference to FIG. First, in the 90 ° section extraction unit 81 in the subframe extraction unit 8, FIG.
When the reference points R1 and R2 inserted in the two subframes as shown in (1) and (2) are received in a state where the reference points R1 and R2 are subjected to amplitude modulation with a modulation rate of 100% as shown in (3) in the figure, Assuming that the two sub-frames are 360 °, in this case, as shown in (4) to (7) of FIG.
A section is cut out and given to the power calculation unit 82.

In the case of FIG. 4 (4), the power calculation unit 82 performs power calculation in the 90 ° section only at the reference point R1, so the integrated average value is "1", and in FIG. 5 (5). The same applies to the case of shifting by 90 ° as shown. In the case of (6) in the figure further shifted by 90 °, the reference point R
Since 1 and the reference point R2 are each halved, the integrated average value becomes "0.5", and if this is further shifted by 90 °, as shown in FIG. It is "0" because it is the integrated average value of power calculation.

Since the calculation result of the power calculator 82 is a scalar, adjacent integrated average values are added together for vectorization. As a result, when the power integrated average values of (4) and (5) in the figure are vectorized, it becomes (1 + j1) as shown on the right side of the figure. Similarly, in the cases of (5) and (6) in the figure, (1 + j0.5),
In the cases of (6) and (7) in the figure, it is output as (0.5 + j0).

If the power calculation is continued in this way, as shown in the figure, the vector O rotates (clockwise) with respect to the origin O, and the central point O and the point (0 + j) at this time.
0) is a reference line, and the angle θ ′ with respect to this is a reference line, and the θ extraction unit 8 as a phase pull-in device shown in FIG.
3 as a vector signal. The received signal is the reference line L
The timing and phase control is performed so that

As described above, by calculating and integrating the powers of the received signals having different time axes, the time phase (reference point phase) of the received signal is obtained, and if the time equalization is performed based on this, the DMT multiplexing is performed. Since 16-channel DMT signals are multiplexed in each subframe in the signal, the arrival times of the respective channels match as shown in FIG. 1 (3).

The θ extraction unit 83 is composed of a multiplication circuit 83a, a sign determination unit 83b, an addition circuit 83c, a delay circuit 83d and a vector signal generation unit 83e. First, the multiplication unit 83a.
At this, this vector signal θ ′ is multiplied by another vector signal having phase information of radius = 1.0 generated by the vector signal generation unit 83e.

Then, the vector signal θ'has a phase rotation of Δθ, and the multiplying circuit 83a extracts only the imaginary number component from this signal and sends it to the code judging section 83b. Code determination unit 8
In 3b, if the sign of this imaginary number signal is +, [FFF
F] is output, and if the sign is −, [0001] is output as the determination result and is given to the adder 83b. Adder circuit 83
In c, the phase information previously sampled through the delay circuit 83d is added to give new phase information.

Since the adder circuit 83c and the delay circuit 83d constitute an integrator circuit, when the integrated value θ is sent to the vector signal generator 83e, the vector signal generator 8e.
In 3e, cos / sin conversion is performed and scalar input θ
Is converted into an output θ, and θ information of radius = 1.0 is given to the multiplication circuit 83a.

By repeating such an operation a plurality of times until the next vector signal θ ′ is input, the complex conjugate value θ (corresponding to the correction amount of θ ′) of the vector signal θ ′ is used as the timing phase information. It can be output from the delay circuit 83d. Note that this operation is performed in the two sub-frame sections of the reference points R1 and R2 shown in FIG. 8, and the timing phase information θ is output every time the vector signal θ ′ is given to the extraction unit 83, which is sufficient. This timing phase information can be pulled in. Therefore, it does not require a long training signal.

Further, in the embodiment of the code judging section 83b shown in FIG. 9, a constant judgment result is always output depending on whether it is + or −, but by changing this judgment result, the pull-in can be performed at a higher speed. It can be carried out. In other words, the vector signal θ to the vector signal generation unit 83e first changes the point (0 + j0) of the reference line L shown in FIG. 8 to the point (−0.5 + j0.
5) and the reference vector R (1 + j0) corresponding by rotating 135 °,
As shown in (1), θ coincides with the reference vector R (1 + j0), and at this time, the multiplication circuit 83a
For the incoming vector signal θ ′, the multiplication circuit 83
Since it is not rotated by a, the input signal of the code determination unit 83b remains θ ′, and this θ ′ is +, as shown in FIG.

Therefore, as shown in FIG. 3C, the code determination unit 83b outputs the determination result of rotating θ by 90 ° in the negative direction (clockwise direction). Therefore, FIG.
As shown in, the vector signal θ ′ is rotated in the 90 ° − direction to approach the reference point R. In this state, the vector signal θ ′ is still in the + state, and therefore, as shown in (5) of the figure, by further rotating θ ′ in the − direction by 45 °, as shown in (6) of the figure. , The vector θ ′ becomes − this time.

Therefore, this time, as shown in FIG.
When rotated in the + direction by 22.5 °, the vector signal θ ′ comes closer to the reference point R, as shown in FIG. Thus, ± 90 ° → ± 45 ° → ± 22.5 °
If the determination angle is halved, such as → ± 11.25 ° → ..., higher-speed timing phase pull-in can be realized.

In the example of FIG. 10, timing phase information θ = −
An integrated value of 90 ° -45 ° + 22.5 ° + 11.25 ° + ... Is obtained. In this case, the θ extraction unit 83
If it is configured with a DSP (Digital Signal Processor), the value that can be taken by the DSP is usually ± 2.0 with respect to an angle of ± 180 °, so the value output by the code determination unit 83b is “2”. The complement display of is as shown below.

+2.0 → + 180 ° [7FFF] +1.0 → + 90 ° [4000] +0.5 → + 45 ° [2000] 0.0 → 0 ° [0000] -1.0 → -90 ° [ C000] −2.0 → −180 ° [8000] The timing phase information θ obtained in this way is given to the timing phase controller 7 shown in FIG. In the timing phase controller 7, as shown in FIG. 7, the timing phase information θ is converted into the coefficients C1 to Cn in the converter 74 and given to the multiplication circuit 72. This multiplication circuit 72 has coefficients C1 to C1 for each sampling output from the delay circuit 71.
Multiply by Cn.

Then, the time equalized signal is obtained by adding the multiplication result of the multiplication unit 72 in the addition unit 73.
The timing phase control section 7 can output the time equalization signal based on the timing phase information θ by the known configuration as described above.

After this, as shown in FIG. 6, the time equalized signal from the timing phase controller 7 is sent to the guard time remover 2.
Is sent to the DMT distribution unit 3, the frequency equalization unit 4, the determination unit 5, and the code conversion unit 6, and these operations are the same as those shown in FIG. Further, in the frequency equalization unit 4, FIG.
Frequency equalization is executed using only the reference point R1 shown in (2).

FIG. 11 shows a modification of the embodiment shown in FIG. In the embodiment of FIG. 6, the time-equalized signal from the timing phase control unit 7 is subjected to the FFT operation by the DMT distribution unit 3 via the guard time removal unit 2, but in the modification of FIG. 11, this FFT operation is performed. Is divided into two parts, and the DMT distributor 3a is provided in front of the timing phase controller 7 to
FFT calculation is performed, and the DMT distribution unit 3b is provided in the subsequent stage to perform the second FFT calculation.

As a result, the DMT distribution unit 3a temporarily switches the FF.
Since T processing is performed, the sampling frequency becomes low,
There is an effect that the arithmetic processing in the timing phase controller 7 can be speeded up. In this case, it is preferable that the guard time removing unit 2 is provided in the preceding stage of the DMT distributing unit 3a.

Although the guard time is added in the above description, the guard time period can be greatly shortened as compared with the example shown in FIG. 13 by the time equalization, which does not hinder the speedup. .

[0057]

As described above, according to the phase pulling method and apparatus of the present invention, a vector signal of the power spectrum is generated, this vector signal is multiplied by another vector signal, and the vector signal is rotated. The sign of the vector signal is judged, the result is integrated, the result is output as a timing phase signal, and the integrated value is vector-converted and fed back to the other vector signal to realize the phase pull-in at a higher speed. It becomes possible to do.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of a time equalization method and apparatus using the phase acquisition method and apparatus according to the present invention.

FIG. 2 is a waveform diagram showing a time equalization method using the phase acquisition method and apparatus according to the present invention and a timing phase equalization at the apparatus level, focusing on one channel.

FIG. 3 is a time chart diagram showing reference point transmission for amplitude modulation in the time equalization method and apparatus using the phase acquisition method and apparatus according to the present invention.

FIG. 4 is a waveform diagram for explaining amplitude modulation in subframe units in the time equalization method and apparatus used in the phase acquisition method and apparatus according to the present invention.

FIG. 5 is a block diagram showing an embodiment of a modem in the time equalization method and apparatus used in the phase acquisition method and apparatus according to the present invention.

FIG. 6 is a block diagram showing a specific example of a phase pull-in unit in a receiving system of the time equalization method and apparatus used in the phase pull-in method and apparatus according to the present invention.

FIG. 7 is a circuit diagram showing an embodiment of the timing phase controller shown in FIG.

FIG. 8 is an explanatory diagram showing a process of obtaining a vector signal of a power spectrum in the subframe extraction unit shown in FIG.

9 is a circuit diagram showing an embodiment of a timing phase information (θ) extraction unit shown in FIG.

10 is a graph showing a modified operation example of the code determination unit shown in FIG.

FIG. 11 is a block diagram showing a modification of the time equalization method and apparatus using the phase acquisition method and apparatus according to the present invention.

FIG. 12 is a waveform diagram for explaining a problem of conventional line group delay.

FIG. 13 is a waveform diagram for explaining inter-channel interference when a signal point changes.

FIG. 14 is a waveform diagram showing a change in frequency characteristic when a transfer function changes due to an ON / OFF state of a power supply.

FIG. 15 is a block diagram showing a conventional time equalization system.

[Explanation of symbols]

1 hour equalizer 2 Guard time remover 3, 3a, 3b DMT distributor (FFT) 4 Frequency equalizer (F
EQ) 5 Judgment unit (DEC) 6, 11 Code conversion unit 7 Timing phase control unit 8 Subframe extraction unit 9 Master frame extraction unit 10 Modem 12 Signal point generation unit 13 DMT multiplexing unit (IFFT) 14 Amplitude modulation unit 15 D / A conversion unit 16 Low pass filter (LPF) 17 Band pass filter (BPF) 18 A / D conversion unit 19 DMT master frame synchronization unit 71 Delay circuit 72 Multiplication circuit 73 Addition circuit 74 Coefficient conversion circuit 81 90 ° section extraction unit 82 Power calculation Unit (PWR) 83 timing phase information (θ) extraction unit 83a multiplication circuit 83b code determination unit 83c addition circuit 83d delay circuit 83e vector signal generation unit In the drawings, the same reference numerals indicate the same or corresponding portions.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hideo Miyazawa             4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa             No. 1 within Fujitsu Limited F term (reference) 5K004 AA05 FG02 FH08                 5K047 AA02 BB01 BB04 EE02 GG09                       MM12

Claims (2)

[Claims] 1. A step of generating a vector signal of a power spectrum of a received signal, a step of multiplying the vector signal by another vector signal to rotate, and a step of determining a sign of the rotated vector signal. And a step of integrating the result of the sign determination and outputting it as the timing phase information; and a step of converting the integrated value into a vector and feeding back the value as another vector signal. . 2. A means for generating a vector signal of a power spectrum of a received signal, a means for multiplying the vector signal by another vector signal to rotate, and a means for judging the sign of the rotated vector signal. A phase pull-in device comprising: means for integrating the result of the code determination and outputting it as the timing phase information; and means for converting the integrated value into a vector and feeding it back as the other vector signal. .