JP2003179490A - Fractional n-frequency synthesizer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the occurrence of a spurious due to mixing of the output signal generated by a fractional operation with the input side signal of a phase comparator. <P>SOLUTION: A modulator 7 outputs a signal REFM delayed by a predetermined time width (Δt) in the time-base direction once every two times the period of a reference signal. A harmonic wave component included in the signal REFM is set to (N+1/2)×fref, by setting the modulation width Δt to (2p-1) 2 times (p: an integer) of the period of N-th harmonics of the reference signal. Thus, the frequency components of the spuriousness, generated by mixing becomes Δf=|F/M--1/2|×fref and hence attenuation is facilitated in a LPF (3). <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer for performing fractional control, and more particularly to a fractional frequency synthesizer capable of reducing spurious of VCO output.

[0002]

2. Description of the Related Art In a wireless communication device such as a mobile phone, a method of switching a transmission / reception frequency channel (CH) by using one type of frequency synthesizer is used in order to reduce the number of components and current consumption of a wireless section. ..

FIG. 27 shows a conventional frequency synthesizer that performs integer frequency division, in which (a) shows a basic configuration and (b) shows a frequency spectrum. In addition, in the parentheses in the figure, specific numerical examples are shown. As shown in FIG. 3A, the frequency synthesizer is configured as a PLL circuit, and includes a phase comparison circuit 1A, a charge pump 2A, a low pass filter (LPF) 3A, and a voltage controlled oscillator (VC).
O) 4A and a frequency dividing circuit 5A capable of switching the frequency dividing number with an integer.

The phase comparison circuit 1A inputs a reference signal REF having a frequency of fref and a comparison signal SIG obtained by dividing the output signal of the VCO (4A) by the frequency division circuit 5A.
The phase difference between the two is detected. The phase comparison circuit 1A outputs a delayed or advanced phase error signal having a pulse width corresponding to the phase difference between the input signals, and supplies it to the charge pump 2A via the corresponding output terminal. Charge pump 2A is V
The voltage value of the input node of CO (4A) is controlled, and its oscillation frequency is controlled. Here, the charge pump 2A outputs a current signal CPOUT having polarities different from each other according to the delayed or advanced phase error signal and having a pulse width corresponding to the pulse width of the phase error signal, and removes a high frequency component L
The charge amount of the input node of the VCO (4A), that is, its voltage value is controlled via the PF (3A). VCO (4A)
Oscillates at an oscillation frequency according to the voltage value of the input node. The frequency dividing circuit 5A divides the output signal of the VCO (4A) by N (N is an integer) and outputs a comparison signal SIG.

The frequency synthesizer feeds back the comparison signal SIG obtained by dividing the output of the VCO (4A) by N to the phase comparison circuit 1A, and outputs the reference signal REF and the comparison signal SIG.
It locks when and the phase match. That is, the reference signal R
The EF and the comparison signal SIG are signals of the same frequency (fref), and the output signal of the VCO (4A) is N of fref.
The frequency is doubled (N × fref). Using such a frequency synthesizer, for example, the frequency band used is 128
When the channel switching of a mobile phone having an inter-channel frequency of 0 MHz and a frequency of 100 kHz is realized, by changing the frequency division number N to 12801 or 12802, the frequency fref is changed as shown in FIG.
It is possible to switch and output a plurality of frequency channels that are an integral multiple of (100 kHz).

In the above frequency synthesizer, since the frequency division number is an integer, the frequency of the output signal is only an integral multiple of the frequency fref of the reference signal. Therefore, when switching and using a plurality of frequency channels, it is necessary to set the frequency fref of the reference signal to the same frequency as the frequency difference between the channels. Here, in order to shorten the time until the frequency synthesizer locks, the loop band of the frequency synthesizer may be set wide. On the other hand, in order to obtain a stable locked state, it is necessary to set the band of the frequency synthesizer sufficiently narrower than the frequency fref of the reference signal. As in the numerical example of FIG. 27, the frequency channel spacing is narrow and the frequency fref of the reference signal is
Is low, the loop band of the frequency synthesizer cannot be wide, and therefore frequency channel switching cannot be performed at high speed.

A fractional-N frequency synthesizer that performs non-integer frequency division (fractional frequency division) is known as a technique for realizing switching between narrow frequency channel intervals by using a high-frequency reference signal. The fractional N frequency synthesizer divides the frequency division ratio of the frequency dividing circuit into different frequency division numbers by dividing the time,
It is possible to obtain an output signal having a frequency that is a non-integer multiple of the reference signal by performing non-integer frequency division on a time average. Such a fractional-N frequency synthesizer is used in many mobile phones and the like.

FIG. 28 shows the structure of a conventional fractional-N frequency synthesizer. The fractional N frequency synthesizer uses the frequency division number of the frequency division circuit 5B as the signal sequence n.
The frequency dividing circuit 5B includes a frequency dividing number control circuit 6B for time-sequential control, and the frequency dividing circuit 5B switches a plurality of frequency dividing numbers to perform non-integer frequency division on a time average basis. It differs from a synthesizer.

The frequency division number control circuit 6B inputs a non-integer frequency division number setting value (N + F / M) (N, M: natural number, F: integer equal to or greater than 0), and the time series frequency division number is input. The signal train n is output to fractionally control the frequency dividing circuit 5B. The frequency dividing circuit 5B switches the frequency dividing number according to the signal sequence n to perform the frequency dividing operation. The signal sequence n output from the frequency division control circuit 6B takes, for example, a binary combination of N and N + 1, and is set to N = 200, F = 1, and M = 64 as shown in FIG. Divides N = 200 among 64 divisions (M
-F) = 63 times, (N + 1) = 201 frequency division is performed F = 1 time. The average frequency division number during this period is (200 x 63 + 2
01 × 1) ÷ 64, and the frequency dividing circuit 5B becomes (200+
This is equivalent to 1/64) frequency division. Therefore, it is possible to use a reference signal (6.4 MHz in the example in the figure) in which the frequency between channels becomes (1 / M) × fref, and high-speed locking becomes possible by setting the reference frequency high.

In the fractional-N frequency synthesizer, spurious (pattern noise) is generated in the output signal when the frequency division number N or N + 1 is periodically switched, but when the frequency division number is switched randomly, It is known that the occurrence can be suppressed to a low level. Therefore,
The frequency dividing number control circuit 6B is configured by using a sigma-delta modulator so that the frequency dividing circuit 5B is provided with a signal train n whose frequency dividing number changes randomly. The frequency division number control circuit 6B as described above gives the fractional N frequency synthesizer a noise shaping effect for removing pattern noise.

FIG. 29 shows a configuration example of the frequency division number control circuit 6B having the noise shaping effect. The frequency division control circuit 6B outputs three outputs of each of the sigma-delta modulators 1C, 2C, and 3C, which are cascaded and are composed of an accumulator that feeds back the output to the input by the delay circuit D. A three-stage primary MASH is provided with a weighting adder 4C that adds directly or via the delay circuit D, and an adder 5C that adds the output of the weighting adder 4C and N. The delay circuit D adds a delay of one cycle of a clock (not shown) which gives the operation timing of each sigma-delta modulator.

The first-stage sigma-delta modulator 1C accumulates a predetermined integer input F by an accumulator at each clock timing, and outputs an overflow signal when the accumulated value becomes M or more, and the accumulated value. To reset. That is,
The overflow signal is output F times during M clocks, and the output value of the weighting adder 4C at that time is set to +1. Second-stage and third-stage sigma-delta modulators 2C, 3
The weight of the weighting adder 4C is set so that the average value of each overflow output of C becomes 0. For example, when the overflow signal of the third stage sigma-delta modulator 3C is output, the value becomes +1 in the first clock cycle, the value becomes -2 in the next clock cycle, and further in the next clock cycle. Value is +1
And the time average value becomes zero. In other words, sigma
The delta modulators 2C and 3C have a function of giving randomness to the output of the weighting adder 4C and not affecting the average value thereof.

The adder 5C outputs a time-series signal sequence n obtained by adding N to the output of the weighting adder 4C. The output of the weighting adder 4C is the average of M clocks,
The operation described above results in F / M, and the output of the adder 5C becomes (N + F / M). Here, the possible values of the signal sequence n are in the range from the value obtained by adding all the negative values of the weighting adder 4C to the value obtained by adding all the positive values, and the weighting of the weighted adder 4C is illustrated. When set as 29, the range is N−3 ≦ n ≦ N + 4.

The fractional N frequency synthesizer is
In the steady state, the phase difference between the comparison signal SIG and the reference signal REF is locked around 0, and the output signal is a signal having a frequency of (N + F / M) times the reference signal REF. By configuring the frequency division number control circuit 6B to have the above-described noise shaping effect, the frequency division number randomly changes, and the generation of pattern noise in the output signal can be suppressed.

In Japanese Patent Laid-Open No. 10-163860, the phase difference between the reference signal REF and the comparison signal SIG is
A reference signal REF or comparison is performed by a PLL circuit using a phase comparison circuit having a dead band characteristic in which a phase difference is regarded as zero and a frequency divider circuit (n is an integer of 1 or more) when the difference is within a certain range near zero. A technique is described in which a modulation circuit is provided on either side of the signal SIG to prevent the occurrence of jitter in the VCO output caused by the dead zone characteristic in the phase locked state.

[0016]

As described above, in the fractional N frequency synthesizer, the frequency division number N or N is used.
The pattern noise generated due to the +1 switching operation can be sufficiently suppressed by the frequency division control circuit or the like having a noise shaping effect.

However, in the fractional-N frequency synthesizer, a phenomenon that another spurious noise different from the pattern noise is generated is recognized. FIG. 30 shows the spectrum characteristic of the output of the fractional-N frequency synthesizer. The spurious component is VCO (4
Frequency of output signal of B) fvco = (N + F / M) × f
Fvco and N × fref (or N), which is the N harmonic of the reference signal REF (comparison signal SIG), centered on ref.
(F / M) × f corresponding to the frequency of the difference from (× fsig)
It is generated at positions vertically separated by the amount of ref. In this example, fref = 6.4 MHz, N = 200, M =
64, F = 1, and spurious is generated at 1280.0 MHz and 1280.2 MHz vertically (F / M) × fref = 100 kHz apart from fvco = 1280.1 MHz.

When the spurious noise different from the pattern noise as described above is generated, a part of the output signal of the VCO (4B) is phased through the power source line of the package or the board, the earth line, or other circuits. It is considered to be generated by sneaking into the input side of the comparison circuit 1B.
Spurious noise is not preferable because it deteriorates the noise characteristics of the frequency synthesizer. However, this spurious noise is a noise having a property that is essentially different from the above-described pattern noise, and cannot be removed even by frequency division control that gives a conventional noise shaping effect.

31A and 31B show how the output signal of the frequency synthesizer and the reference signal are mixed. FIG. 31A shows the frequency characteristic of the frequency synthesizer with integer division, and FIG. 31B shows the frequency characteristic of the fractional N frequency synthesizer. Shows. Hereinafter, the principle of generation of the spurious noise described above will be described with reference to FIG.

In the integer frequency dividing synthesizer, the output frequency fvco is N × fref as described above. In addition, the harmonic component of the reference signal REF is also an integral multiple of the reference frequency fref (in the phase locked state, the comparison signal SI
The harmonic component of G is also an integral multiple of fref, but here, the relationship of the reference signal REF will be described as an example). That is, as shown in FIG. 31A, it can be said that the reference signal and the output signal have the same frequency component. Therefore, in the frequency synthesizer shown in FIG. 27, the phase comparison circuit (1
Even if the output signal of the VCO (4A) wraps around to the input side of (A), there is no problem that spurious occurs as a result of mixing with the reference signal REF.

On the other hand, in the case of a fractional-N frequency synthesizer that performs non-integer frequency division, as described above, the VCO
The frequency fvco of the output signal of (4B) is (N + F /
M) × fref. That is, as shown in FIG. 31B, it can be said that the reference signal and the output signal have different frequency components. Therefore, when the output signal of the VCO (4B) goes around to the input side of the phase comparison circuit 1B, spurious is generated as a result of mixing with the reference signal REF. As described above, this spurious is caused by the frequency Δ of the difference between fvco and the N harmonic (= N × fref) of the reference frequency.
It is known to occur by f = (F / M) × fref. This frequency component Δf is present in the low frequency region as shown in FIG. 7B, especially when F / M has a value close to 0 or 1, so it is difficult to remove it with a filter. The component Δf is included in the control signal of the VCO as it is. For this reason, spurious noise is located at a position vertically apart by f from the center of fvco.

In Japanese Patent Laid-Open No. 10-163860, negative feedback control is performed in the dead zone because the phase comparison output of the phase comparison circuit has a dead zone characteristic of zero even in the phase locked state. It is described that it does not work and prevents the VCO output from generating jitter. However, in this PLL circuit, the frequency dividing circuit is not fractionally controlled, and the integer n (n is 1
Since the above frequency division is performed, spurious noise due to the generation of the low frequency component is not removed.
Further, it is apparent from the above that the jitter described in the publication and the low frequency component described above are essentially different.

The present invention solves the above problem and provides a fractional-N frequency synthesizer for reducing the spurious noise generated by the VCO output sneaking into the input side of the phase comparator in a frequency synthesizer for fractional control. With the goal.

[0024]

In order to achieve the above object, a fractional-N frequency synthesizer according to a first aspect of the present invention is a signal obtained by switching the oscillation output of a voltage controlled oscillator by a plurality of frequency division numbers. , A frequency dividing circuit that outputs a comparison signal, a frequency dividing number control circuit that controls the time average of the frequency dividing numbers of the frequency dividing circuit to a non-integer value, and a phase difference signal that indicates the phase comparison result of the reference signal and the comparison signal. In the fractional N frequency synthesizer for controlling the oscillation frequency of the voltage controlled oscillator based on the phase difference signal, a periodic signal of a predetermined frequency is transmitted for a T period (T is an integer of 2 or more). ) Once in the time axis direction for modulation by a predetermined modulation width and input to the phase comparison circuit as the reference signal.

In the fractional-N frequency synthesizer of the first aspect of the present invention, when the value of the non-integer part in which spurious is a problem is a value close to 0 or 1, the reference signal input to the phase comparison circuit has a period. Of the frequency synthesizer by adopting a reference signal that is modulated by a predetermined modulation width that is (2p-1) / 2 times (p is a natural number) the cycle of the N harmonic of the frequency of the reference signal. Even when the output signal wraps around to the input side of the phase comparison circuit, the frequency of the spurious component becomes higher than that when no modulation is applied, and can be easily removed by the low-pass filter. Therefore, a fractional N frequency synthesizer with reduced spurious is realized.

The fractional-N frequency synthesizer according to the second aspect of the present invention is a frequency dividing circuit for switching the oscillation output of the voltage controlled oscillator by a plurality of frequency dividing numbers to output a frequency-divided signal, and the frequency dividing circuit. A frequency dividing number control circuit for controlling the time average of the frequency dividing number to a non-integer value, and a phase comparison for outputting the phase comparison result of the comparison signal and the reference signal as a phase difference signal using the output of the frequency dividing circuit as a comparison signal A fractional-N frequency synthesizer for controlling the oscillation frequency of the voltage-controlled oscillator based on the phase difference signal,
A modulation means is provided for modulating the output of the frequency dividing circuit once in a T cycle (T is an integer of 2 or more) by a predetermined modulation width in the time axis direction and inputting the modulated signal to the phase comparing circuit. Characterize.

In the fractional-N frequency synthesizer of the second aspect of the present invention, instead of the reference signal side input to the phase comparison circuit, a signal input as a comparison signal is modulated with a predetermined modulation width. This configuration also realizes a fractional-N frequency synthesizer with reduced spurious noise, as in the case where modulation is applied to the reference signal side.

In the fractional-N frequency synthesizer of the present invention, the outputs of the frequency division control circuit are N-n1 and N +.
n2 (N is a natural number, n1 and n2 are integers equal to or greater than 0), and the larger one of n1 and n2 is N1, the two different addends are smaller than -N1 and + N1.
And a larger value. Alternatively, the frequency division number of the frequency dividing circuit fluctuates between N−n1 and N + n2, and the predetermined modulation width is set to be larger than the period of the input side of the frequency dividing circuit × (n1 + n2) / 2. May be adopted. The frequency dividing number control circuit increases or decreases the frequency dividing number with a set fluctuation width in order to give a noise shaping effect to the fractional operation of the frequency dividing circuit. If the increase / decrease range is N−n1 ≦ n ≦ N + n2, and if the larger of | −n1 | and | + n2 | Is also set to a large value. Alternatively, the modulation width of the reference signal is set to a value larger than the period of the input side of the frequency dividing circuit × (n1 + n2) / 2. By setting as described above, the edges of the reference signal and the comparison signal do not fall or rise at the same timing, and mixing of both signals does not occur. Therefore, the modulation width applied to the reference signal or the comparison signal is (2p) times the period of the N harmonic of the frequency of the reference signal.
Even if it is not -1) / 2 times (p is a natural number), the generation of spurious can be suppressed.

In the fractional-N frequency synthesizer of the present invention, the modulating means receives the periodic signal and delays it by the predetermined modulation width, a counter that divides the output of the delay circuit by two, and the counter. A selector that selects the periodic signal or the output of the delay circuit depending on the output of the. in this case,
The modulation means includes a periodic signal for each cycle of the periodic signal,
The delay circuit alternately switches and outputs the signal modulated by a predetermined modulation width. Therefore, the reference signal is a signal in which every other pulse of the periodic signal is delayed.

Further, in the fractional-N frequency synthesizer of the present invention, the modulating means receives the output of the frequency dividing circuit and delays it by the predetermined modulation width, and a counter which divides the output of the delay circuit by two. And a selector for selecting and outputting the output of the frequency dividing circuit or the output of the delay circuit depending on the output of the counter. When modulation is applied to the comparison signal instead of the reference signal side, the modulation means modulates the output signal of the frequency divider circuit and the delay circuit with a predetermined modulation width for each cycle of the output signal of the frequency divider circuit. The added signal is output alternately. Therefore, the comparison signal is a signal delayed by every other pulse of the output signal of the frequency dividing circuit.

Further, in the fractional-N frequency synthesizer of the present invention, the modulating means converts the periodic signal into two.
A periodic signal frequency divider that divides by any one of the two frequency division numbers, and a modulation control circuit that switches the frequency division number of the periodic signal frequency divider for each cycle that is equal to or greater than the output cycle of the periodic signal frequency divider. It is also possible to output the reference signal from the periodic signal frequency divider. In this case, the reference signal is, for example, a periodic signal,
By dividing the frequency by a frequency divider that switches and divides two frequency division numbers only once in the T cycle, a signal with a predetermined modulation width is added.

In the fractional-N frequency synthesizer of the present invention, the modulation control circuit comprises a counter for dividing the output of the periodic signal frequency divider by two, and the periodic signal frequency divider depending on the output of the counter. It is preferable to include a switching unit that switches the frequency division number. In this case, by controlling the frequency division number of the periodic signal frequency divider for each cycle on the output side, a reference signal modulated with a predetermined modulation width is generated.

The fractional-N frequency synthesizer of the present invention selects either the periodic signal or the modulation output of the modulation means depending on the non-integer value input to the frequency division control circuit to select the reference signal. A signal selection circuit may be further provided, or either the modulation output of the modulation means or the output of the frequency division circuit is selected depending on a non-integer value input to the frequency division control circuit. A selection circuit for inputting to the comparison circuit may be further provided. In the reference signal or the comparison signal, the period of the N harmonic of the frequency of the reference signal is (2p-1)
By adding / 2 (p is a natural number) modulation, the frequency component of spurious becomes higher frequency band when the value of the non-integer part is closer to 0 or 1 compared to before the modulation. When the non-integer part has a value close to ½, it shifts to a lower frequency band. Therefore, by selecting either a modulated signal or a non-modulated signal according to the value of the non-integer part, the frequency of the spurious component is prevented from becoming a low frequency in all non-integer ranges.

In the fractional-N frequency synthesizer of the present invention, the selection circuit selects the modulation output when the non-integer value is 0 or more and less than ¼ and 3/4 or more and less than 1. , The non-integer value is 1
When / 4 or more and less than 3/4, it is preferable to select the periodic signal. If the non-integer value is F / M, 0
In the range of <F / M <1/4 and 3/4 <F / M <1, the frequency of the spurious component when the modulation of the predetermined modulation width is applied is the spurious component when the modulation is not applied. In the range of 1/4 <F / M <3/4, the frequency of spurious components when no modulation is applied is higher than the frequency when modulation of a predetermined modulation width is applied. Disappear. Also, F / M = 1/4 and F / M = 3/4
When, the frequencies of the spurious components of both are the same. The selection circuit selects a signal with or without a modulation having a predetermined modulation width according to which range the non-integer value belongs to, and prevents the frequency of the spurious component from becoming a low value.

In the fractional-N frequency synthesizer of the present invention, the selection circuit selects a modulation output when the non-integer value is 0 or more and less than 1/4 and when it is 3/4 or more and less than 1. The non-integer value is 1/4
As described above, it is preferable to select the comparison signal when it is smaller than 3/4.

In the fractional-N frequency synthesizer of the present invention, a plurality of the modulation means are provided, and a selection for selecting any one of the plurality of modulation means depending on a non-integer value input to the frequency division number control circuit. Circuitry may be further included. The frequency of the spurious component changes according to the modulation width. Therefore, by preparing a plurality of modulation means with the modulation width set appropriately and selecting any one of the modulation means according to the value of the non-integer part, the frequency of the spurious component is prevented from becoming a low frequency.

In the fractional-N frequency synthesizer of the present invention, the frequency of the periodic signal or the reference signal is set to fr.
ef, the modulation means is (2p-1) / (2x
At least one first modulation means having a modulation width of N × fref) (p and N are natural numbers); and q / (N × fre
f) at least 1 having a modulation width of (q, N is a natural number)
Preferably, two second modulation means are included. The modulation width of at least one modulation means is set to (2p-1) / 2 times (p is a natural number) the cycle of the N harmonic of the frequency of the reference signal, and the modulation width of at least one modulation means is set to the frequency of the reference signal. Is set to 2q times (q is a natural number) the cycle of the N harmonic of, and these are switched and used. This enables spurious reduction in the entire range of non-integer values.

In the fractional-N frequency synthesizer of the present invention, the selection circuit includes the first modulation means when the non-integer value is 0 or more and less than 1/4 and when it is 3/4 or more and less than 1. It is preferable to select the second modulator when the non-integer value is 1/4 or more and smaller than 3/4. If the non-integer value is F / M, 0 <F / M <1/4 and 3/4 <F / M <
In the range of 1, (2p−1) / (2 × N × fref)
It is q / (N × fref) (q and N are natural numbers) to use the first modulation means for applying modulation of (p and N are natural numbers).
The frequency of the spurious component becomes higher than that of the case where the second modulating means for adding the modulation of 1/4 <F / M <3 /
In the range of 4, the frequency of the spurious component is not higher when using the second modulating means than when using the first modulating means. Also, F / M = 1/4 and F / M = 3 /
When the frequency is 4, the frequencies of both spurious components are the same. The selection circuit selects the first or second modulation circuit according to which range the non-integer value belongs to so that the frequency of the spurious component does not become a low value.

In the fractional-N frequency synthesizer of the present invention, the non-integer denominator is 2 ⁿ (n is an integer of 2 or more), and the selection circuit selects the most significant bit and the most significant bit of the non-integer numerator. It is preferable that the exclusive control with the bit one lower is used as the selection control signal. When a non-integer value is expressed by a fraction and the denominator is 2 ⁿ , the numerator can take a value between 0 and 2 ⁿ −1. At this time, when the exclusive OR of the values of the upper 2 bits of the numerator is taken, it becomes 0 when the value of the non-integer is 0 or more and less than 1/4, and 3/4 or more and less than 1 1 /
It becomes 1 when 4 or more and less than 3/4. Therefore, the exclusive OR of the values of the upper 2 bits of the numerator can be used as the selection control signal of the selection circuit.

In the fractional-N frequency synthesizer of the present invention, the modulation means may include modulation width switching means for controlling the predetermined modulation width depending on a non-integer value input to the frequency division number control circuit. .. In this case, the modulation width can be controlled according to the value of the non-integer part. Therefore, it is possible to prevent the frequency of the spurious component from decreasing.

In the fractional-N frequency synthesizer of the present invention, it is preferable that the modulation width switching means includes a delay circuit that outputs a delay amount according to the non-integer value.
In this case, the modulation width is controlled by controlling the delay amount of the delay circuit so that the frequency of the spurious component does not become a low frequency.

In the fractional-N frequency synthesizer of the present invention, the delay circuit sets the delay amount to (2p when the non-integer value is 0 or more and less than 1/4 and when it is 3/4 or more and less than 1). -1) / (2 × N × fre
f) (p and N are natural numbers), and the non-integer value is ¼
When the above is less than 3/4, the delay amount is set to q / (N
Xfref) (q is an integer of 0 or more and N is a natural number). If the non-integer value is F / M, 0 <F /
In the range of M <1/4 and 3/4 <F / M <1, when the delay amount is (2p−1) / (2 × N × fref) (p and N are natural numbers), The amount of delay is q / (N × fre
f) (q is an integer greater than or equal to 0 and N is a natural number), the frequency of the spurious component is higher, and 1/4 <F /
In the range of M <3/4, the delay amount is q / (N × fref)
When the delay amount is (2p−1) / (2 × N × f)
ref), the frequency of the spurious component will not be higher. Also, F / M = 1/4 and F / M = 3 /
When the frequency is 4, the frequencies of both spurious components are the same. The delay circuit sets the delay amount to (2p−1) / (2 × N × fref) according to which range the non-integer value belongs to.
Alternatively, q / (N × fref) is set so that the frequency of the spurious component does not become a low value.

In the fractional-N frequency synthesizer of the present invention, the modulation means switches the frequency division number output by the frequency division number control circuit between two different addends at every cycle equal to or greater than the output cycle of the frequency division circuit. A modulation control circuit for adding and adding may be provided. In this case, the frequency dividing circuit switches two different addends to the signal sequence output from the frequency dividing number control circuit to perform frequency division by the added frequency dividing number to generate a modulated comparison signal.

In the fractional-N frequency synthesizer of the present invention, the modulation control circuit includes a counter that divides the output of the frequency dividing circuit by two, and a selector that switches between the two different addends depending on the output of the counter. Preferably, an adder for adding the frequency division number output by the frequency division number control circuit to the output of the selector. In this case, the frequency dividing circuit performs frequency division by the frequency division number added by alternately switching between two different addends for each cycle of the output.

In the fractional-N frequency synthesizer of the present invention, it is preferable that the phase difference signal is reset at the edge of the signal whose phase is delayed between the reference signal and the comparison signal. When it becomes clear which of the reference signal and the comparison signal has the advanced phase by applying the modulation, the phase difference signal can be reset by the signal having the delayed phase. Therefore, the operation of the charge pump is improved, and the characteristics of the floor C / N ratio are improved.

In the fractional-N frequency synthesizer of the present invention, the phase difference signal is obtained by adding an addend smaller than -N1 of the two addends to the divide number output from the divide number control circuit. Sometimes it is preferable to reset with the reference signal, and when adding an addend larger than + N1, it is preferable to reset with the comparison signal. Of the two different addends, the phase of the reference signal is always delayed when a value smaller than −N1 is added, and the phase of the comparison signal is always delayed when a value larger than + N1 is added. Therefore, it becomes clear which signal should be used to reset the phase difference signal.

In the fractional-N frequency synthesizer of the present invention, the reference signal is a periodic signal having a predetermined frequency,
It is preferable that the signal is modulated once in the U cycle (U is an integer of 2 or more) in the time axis direction by a predetermined modulation width. When only one of the reference signal and the comparison signal is modulated, the operation timing of the internal circuit of the frequency dividing circuit or the frequency dividing number control circuit may overlap the edge of the reference signal REF, which causes spurious emission. .. By mixing both signals input to the phase comparison circuit, mixing of the signals is avoided.

[0048]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments will be described in detail below with reference to the drawings.

(First Embodiment) FIG. 1 shows the configuration of a fractional-N frequency synthesizer according to the first embodiment of the present invention. Fractional N of this embodiment example
The frequency synthesizer includes a phase comparison circuit 1, a charge pump 2, a low pass filter (LPF) 3, a voltage controlled oscillator (VCO) 4, a frequency dividing circuit 5 capable of fractional control, and a frequency dividing circuit 5. Frequency division control circuit 6 to control
And a modulation circuit 7. The fractional-N frequency synthesizer of the present embodiment example is different from the conventional frequency synthesizer shown in FIG.

The phase comparison circuit 1 uses the frequency divider circuit 5 to generate a signal REFM obtained by modulating a periodic signal having a frequency of fref (hereinafter referred to as a reference signal REF) by the modulation circuit 7 and the output signal of the VCO (4). The divided comparison signal SIG is input and the phase difference between the two is detected. The phase comparison circuit 1 outputs a delayed or advanced phase error signal having a pulse width according to the phase difference of the input signal, and supplies it to the charge pump 2A via the corresponding output terminals up and down. The charge pump 2 controls the voltage value of the input node of the VCO (4) and controls its oscillation frequency. Charge pump 2
Outputs a current signal CPOUT having a pulse width different from that of the phase error signal and having a pulse width corresponding to the pulse width of the phase error signal according to the delayed or advanced phase error signal, and passes through the LPF (3) for removing high frequency components. It controls the amount of charge at the input node of VCO (4), that is, its voltage value.

The VCO (4) oscillates at an oscillation frequency corresponding to the voltage value of the input node and outputs the output signal OUT. The frequency dividing circuit 5 receives the output signal OUT of the VCO (4), divides the input signal by a frequency dividing number according to the output signal string n of the frequency dividing number control circuit 6, and outputs the divided signal as a comparison signal SIG.
The frequency dividing number control circuit 6 fractionally controls the frequency dividing number of the frequency dividing circuit 5 by the signal sequence n, and sets the frequency dividing number of the frequency dividing circuit 5 to a value of a ratio integer (fractional number) on a time average basis. The frequency division control circuit 6 is configured by using a circuit having a noise shaping effect, such as a kind of sigma-delta modulator, in order to remove pattern noise.

The modulation circuit 7 inputs the reference signal REF,
The position of the pulse of the reference signal REF is controlled periodically, for example, once every two cycles, and the signal REFM modulated (moved) in the time axis direction by an arbitrary constant time width Δt is used as the phase comparison circuit 1.
Output to. In the modulation circuit 7, the frequency component of the VCO output sneaking into the input side (the signal REFM and / or the comparison signal SIG) of the phase comparison circuit 1 changes the frequency of the beat component generated by mixing with the signal REFM or the comparison signal SIG, Shifted to the high band outside the pass band of the LPF (3),
It is not included in the frequency control signal of the VCO (4). As described above, the phase comparison circuit 1 receives the signal REFM and the comparison signal SIG, and both signals have the same frequency in the locked state. Therefore, the output signal OUT of the VCO (4) is a signal whose frequency is (N + F / M) times the reference frequency fref, which is the frequency of the reference signal, and in which spurious due to mixing is reduced.

FIG. 2 shows a basic operation of this embodiment as a timing chart. In addition, the inside of the parenthesis of the figure has shown the concrete numerical example. As described above, the modulation circuit 7 delays every other pulse signal of the reference signal REF backward by the modulation width Δt in the time axis direction.
Output FM. In the example of the figure, Δt is 390 ps. The phase comparison circuit 1 uses the signal REFM and the comparison signal SIG.
And the phase error signal is output. The charge pump 2 outputs current signals CPOUT having polarities different from each other according to the phase error signal, and the LPF
Control VCO (4) via (3).

In the normal PLL operation, the phase difference between the two signals input to the phase comparator disappears, and feedback control is performed so that the edges of both signals coincide with each other, resulting in a locked state. In the frequency synthesizer, the signal RE
The FM and the comparison signal SIG are feedback-controlled so that their average phases coincide with each other, and enter a locked state. As a result, in the locked state, if the randomness of the frequency division number added by the frequency division number control circuit 6 is not considered, the comparison signal SI
The edge of G is the signal RE when the delay is not added.
It shifts backwards compared to the edges of the FM and shifts forwards compared to the edges of the signal REFM when the delay is added. That is, the signal REFM and the comparison signal SIG are alternately advanced and delayed.

As described above, the charge pump 2 outputs the current signal CPOUT having a pulse width depending on the advance or delay of the phase based on the signals from the two output terminals of the phase comparison circuit 1, and LPF ( 3) via VCO
The voltage of the input node is controlled in (4). The output signal CPOUT of the charge pump 2 is, as shown in FIG.
When the phase of the comparison signal SIG is delayed from the EFM, the polarity is positive and the current signal has a pulse width corresponding to the phase difference between the two signals. When the phase is advanced, the polarity is negative and both signals are The current signal has a pulse width corresponding to the phase difference between the two.
As described above, the signal REFM and the comparison signal SIG are
Since the lead and the lag occur alternately, the charge pump 2 outputs pulse signals whose polarities are alternately different.

Next, the operation of spurious emission and its removal according to the present embodiment will be described in detail. Figure 3
The spectrum characteristic of the calculation result by the Fourier series expansion of the signal REFM is shown as a graph. In addition, specific values are shown in parentheses. The horizontal axis of the graph is the modulation width (Δt = D / (N × fref)) standardized by the period 1 / (N × fref) of the N harmonic component of the reference signal, and the vertical axis is the harmonic of each signal. Shows the power level of.

When the modulating circuit 7 modulates the reference signal REF every other pulse, the harmonic components of the signal REFM are N × fref components and (N + 1/2) × fre.
The component of f appears. As shown in FIG. 3, the two harmonic components have the delay width added by the modulation circuit 7 as a variable.
The cycle of the power of N × fref component shown by the solid line and the power of (N + 1/2) × fref component shown by the dotted line is 1
/ (N × fref), the phases change 180 degrees with respect to each other. The closer the modulation width is to an integer multiple of 1 / (N × fref), the greater the power of the N × fref component,
The closer (2p-1) / 2 times (p is a natural number) to 1 / (Nxfref), the smaller the power of the Nxfref component.

FIG. 4 shows the frequency characteristics of each signal as a spectrum. (A) shows the frequency characteristics of the reference signal REF, and (b) shows the modulation of Δt = 0.5 / (N × fref). The frequency characteristic of the signal REFM when
Shows the frequency characteristic of signal mixing in the phase comparator 1. As shown in FIG.
F is the fundamental wave component fref and its harmonic component 2 × fr
ef, ... N × fref, (N + 1) × fref ,. Further, the signal REFM has a component of fref and fref / 2 in the low frequency region as shown in FIG.
And a component of N × fref and a component of (N + 1/2) × fref are generated in the harmonic component.
Note that the power of the N × fref component and (N + 1/2)
As shown in FIG. 3, the modulation width Δt determines which component of the xfref component has the stronger power.

In the phase comparison circuit 1 of this embodiment,
For example, the output signal OUT of the VCO (4) is the comparison signal S
Consider the case of wrapping around in the IG. In the phase comparison circuit 1, the sneak signal having a frequency of fvco = (N + F / M) × fref and the signal REFM harmonic component are mixed. As described above, when Δt is 0.5 times 1 / (N × fref), the harmonic component of the signal REFM is N
The component of × fref is small, and (N + 1/2) × fref
Has a large component. Therefore, in the phase comparison circuit 1, (N
+ F / M) × fref component and (N + 1/2) × fr
The ef component is mixed, and as shown in FIG. 4C, Δf = | F / M− corresponding to the frequency component of the difference between the two.
A component of ½ | × fref appears in the output of the phase comparison circuit 1.

As a concrete numerical example of the frequency component appearing in the output of the phase comparison circuit 1, fref = 6.4 MHz, N
= 200, M = 64, F = 1, Δ
f = | 1 / 64-1 / 2 | × 6.4 MHz = 3.1 MH
z. When this component is included in the signal CPOUT, 1
Spurs are generated at a frequency deviated by 3.1 MHz above and below 280.1 MHz. However, the spurious component (100 kHz) of the above-mentioned conventional frequency synthesizer is used.
Compared with the above, since the spurious component of the present embodiment has a high frequency, the LPF (3) can easily remove the signal of this frequency component. Therefore, the generation of spurious can be suppressed low.

Regarding the modulation width Δt, the power of the N × fref component is the smallest when (2p−1) / 2 times (p is a natural number) of 1 / (N × fref) which is the period of the reference signal. Therefore, it is easy to suppress the generation of spurious,
The effect of spurious suppression weakens as it deviates from the modulation width. This is because in the present embodiment, the frequency components mixed in the phase comparison circuit 1 are changed from N × fref to (N +
This is to suppress the generation of spurious by shifting to 1/2) × fref. In the conventional frequency synthesizer, spurious generation becomes a problem when F / M at which the spurious frequency becomes low is close to 0 or when F / M is close to 1. LPF (3) easily by increasing the frequency of spurious components
Can be removed with.

Here, the modulation width Δt is 1 every T times.
There is no particular problem as long as the relationship of the edge of the signal REFM being synchronized with the comparison signal SIG is maintained at least once (T is an integer of 2 or more). However, as compared with the time width of the modulation width Δt, the spurious that appears at the frequency ± (F / M) × fref away from the oscillation frequency becomes large.
The range that can be sufficiently attenuated in (3) is the limit time of Δt.

FIG. 5 shows the fractional N of this embodiment.
The frequency spectrum characteristic of the frequency synthesizer is shown. In this example, the modulation width Δt of the modulation circuit 7 is set to 0.5
/ (1280 × 10 ⁶ ) = 390 ps is set.
By providing the modulation circuit 7, as shown in FIG. 30, which is generated in the conventional frequency synthesizer, 1280.
Spurious that appears at 100 kHz above and below centering on 1 MHz is sufficiently attenuated.

FIG. 6 shows a concrete configuration example of the modulation circuit 7. FIG. 6A shows a configuration example of the modulation circuit, and FIG. 6B shows a configuration example of a counter in the modulation circuit. The modulation circuit 7 is
A delay circuit 71 that delays the reference signal REF by a predetermined modulation width Δt, and a counter 73 that counts the output of the delay circuit 71.
And a selector 72.

The counter 73 feeds the inverted output QB of the D-type flip-flop to the D terminal and delays the reference signal REF by the delay circuit 71, as shown in FIG.
The EFD is input to the clock input terminal and the positive phase output Q is output. The counter 73 constitutes a divide-by-2 circuit by counting up 2 counts (frequency division number 2) and outputs the signal RSEL to the selector 72. The selector 72 uses the reference signal R
EF and the signal REFD are input, and for example, the signal REFD is output while the signal RSEL from the counter is at the H level and the reference signal REF is output during the L level. In the present embodiment example, the counter 73 is set to divide by 2, so that the signal R
The EFM outputs the reference signal REF and the signal REFD alternately.

FIG. 7 shows the operation of the modulation circuit 7 shown in FIG. 6 as a time chart. The delay circuit 71 delays the reference signal REF by a predetermined modulation width Δt to delay the signal REFD.
Output as. The counter 73 counts the signal REFD and divides this by two to output a signal RESL. The selector 72 keeps the reference signal REF while RSEL is at L level.
To output the reference signal REF, and when the RSEL is at the high level, the signal REFD is selected to output the signal REFD,
Output as signal REFM. This causes the signal REF
M is a signal delayed by Δt for every other pulse of the reference signal REF.

As described above, the fractional-N frequency synthesizer of the present embodiment modifies the frequency mixed by the phase comparison circuit 1 from N × fref by modulating the reference signal REF by the predetermined modulation width Δt. N
+1/2) × fref to increase the frequency of the beat component. The frequency of this beat component can be sufficiently attenuated by the LPF (3), and a frequency synthesizer with reduced spurious noise can be obtained.

(Second Embodiment) FIG. 8 shows a frequency synthesizer according to a second embodiment of the present invention. The fractional-N frequency synthesizer of this embodiment is
A signal REFM is a clock source that generates a clock signal,
The frequency synthesizer differs from the frequency synthesizer of the previous embodiment in that it is generated by a frequency divider 8 that can control the frequency division number from the outside and a modulation control circuit 9 that inputs a set value and controls the frequency divider 8. .

Signal REFM input to the phase comparison circuit 1
Is obtained by dividing the frequency of the clock signal output from the clock source by the frequency divider 8. The modulation control circuit 9 uses the set value R,
Inputs 1 and m (R, l and m are integers), outputs a signal sequence r, and controls the frequency divider 8. The signal sequence r is, for example, R + 1,
Alternately take the value of R + m. The frequency divider 8 switches the frequency division ratio according to the signal sequence r, and divides the clock signal by any of the frequency division ratios R + 1 and R + m. In this case, the modulation width Δt is | l−m | of the cycle of the clock signal.
/ 2 times the value. The cycle of the signal REFM is the cycle of the clock signal divided by (R + (l + m) / 2). An offset may occur in the cycle depending on the combination of l and m.

FIG. 9 shows a concrete example of the structure of the modulation control circuit 9, where (a) is the example of the structure of the modulation control circuit 9, and (b) is.
Shows a configuration example of a counter in the modulation control circuit 9.
The modulation control circuit 9 outputs the signal REFM output from the frequency divider 8.
A counter circuit 91 that counts, a selector 92 that is controlled by the output of the counter 91, and an adder 93 that adds R to the output of the selector 92. The counter 91 is
As shown in FIG. 3B, it is configured using a D-type flip-flop and operates as a divide-by-2 circuit. Selector 92
Inputs different integer values l and m, selects one of the input values according to the output RSEL of the counter circuit 91, and outputs it.

FIG. 10 is a timing chart showing the operation of the modulation circuit section shown in FIGS. 8 and 9 when R = 6, l = -1, and m = + 1. The counter circuit 91 counts the low-level side pulses of the output signal REFM of the frequency divider 8, and the signal RS that switches the output level every time the pulse is counted.
Output EL. The selector 92 is controlled by the signal RSEL and outputs m = + 1 while the signal RSEL is at the H level and outputs l = −1 during the L level. The output of the selector 92 is added to R = 6 by the adder 93 and output as a signal string r. The frequency divider 8 outputs the clock signal
When r = 7, divides by 7, when r = 5, divides by 5,
The signal REFM is output. In the present embodiment, since the counter 91 performs the frequency division operation by 2, the frequency division ratio alternates between frequency division 7 and frequency division 5, the average frequency division number is 6, and the modulation width Δ
t is one cycle of the clock signal.

(Third Embodiment) The first and second embodiments described above show a fractional-N frequency synthesizer which reduces spurious generation by applying modulation to the reference signal side of the phase comparison circuit 1. However, spurious can also be reduced by adding modulation to the comparison signal SIG. This is because the generation of beats due to mixing of the signals input to the phase comparison circuit 1 occurs because the output signal OUT wraps around to either one of the signals input to the phase comparison circuit 1 or both signals. Is. That is, the output signal OUT of the VCO (4) is added to the reference signal REF.
Is not only generated and spurious is generated, but also because the REF signal is spilled to the comparison signal SIG side,
Spurious is generated by the same principle as that described above.

FIG. 11 shows the configuration of a fractional-N frequency synthesizer according to the third embodiment of the present invention. In the fractional-N frequency synthesizer of the present embodiment example, the modulation circuit 7 of FIG. 1 is provided after the frequency divider 5 on the comparison signal SIG side instead of being provided on the reference signal REF side. This is different from the first embodiment. The modulation circuit 10 of FIG. 11 delays every other pulse of the input signal by Δt, similarly to the modulation circuit 7 of FIG. FIG. 12 shows a specific configuration example of the modulation circuit 10, where (a) is the modulation circuit 1.
0 shows a configuration example of 0, and (b) shows a configuration example of the counter in the modulation circuit 10. The modulation circuit 10 has the same configuration as the modulation circuit shown in FIG. 6 except that the input signal is different, and inputs the comparison signal SIG and outputs the signal SIGM.

In this embodiment, the modulation circuit 10 is provided on the side of the comparison signal SIG, and the comparison signal SIG is delayed by Δt at every other pulse thereof. This Δt is the first and second
1 / (N × fref) (2p
When it is -1) / 2 times (p is a natural number), the spurious reduction effect is large. The frequency of the beat component generated by mixing the higher harmonic wave of the comparison signal and the output signal OUT by modulating the signal on the comparison signal SIG side instead of the reference signal REF side as in the present embodiment example. Can be shifted to the higher frequency side, and spurious can be prevented from occurring as in the first embodiment. Here, with respect to the cycle serving as the reference of the modulation width Δt,
1 / (N × fref), which is the period of the N harmonic of the reference signal
Rather than 1 / ((N +
F / M) × fref). However, since N is sufficiently larger than 1 and F / M is smaller than 1, fvco = (N + F / M) × fref≈N × fref, and 1 / (N × fref) may be used as a reference. .

(Fourth Embodiment) FIG. 13 shows the configuration of a fractional-N frequency synthesizer according to a fourth embodiment of the present invention. In the fractional-N frequency synthesizer of this embodiment, instead of providing the modulation circuit 10 shown in FIG. The difference from the third embodiment is that a modulation control circuit 11 is provided. FIG. 14 shows a specific configuration of the modulation control circuit 11, (a) shows a configuration example of the modulation circuit, and (b) shows a configuration example of a counter in the modulation circuit. The modulation control circuit 11 is the same as the modulation control circuit shown in FIG. 9 except that the input / output signals are different.
The modulation control circuit 11 uses the signal train n and set values l and m (l, m
Is an integer) and outputs, for example, a signal sequence n ′ in which n + 1 and n + m are alternately switched. In this embodiment, the comparison signal SIG is modulated by periodically controlling the frequency division number of the frequency dividing circuit 5. The modulation width Δt is | lm− / 2 times the cycle of the output signal OUT.

(Fifth Embodiment) FIG. 15 shows a fractional-N frequency synthesizer according to a fifth embodiment of the present invention. The fractional-N frequency synthesizer of this embodiment is different from the fourth embodiment in that the values of l and m input to the modulation control circuit 11 are large. In the present embodiment, if the signal sequence output from the frequency division number control circuit 6 is n = N + Δn1 and the maximum absolute value of Δn1 is Δn1 (max), for example, when l> m,
l> + Δn1 (max) and m <−Δn1 (ma
x). Weighting adder 4 of frequency division control circuit 6
When C is set as shown in FIG. 29, as described above,
Since −3 ≦ Δn1 ≦ 4, Δn1 (max) becomes 4.

FIG. 16 shows an edge of a signal input to the phase comparison circuit 1. (a) shows an edge when no modulation is applied, (b) shows l, m where l> Δn1 (max), m <-
The edge when set to Δn1 (max) is shown. Since the frequency division number of the signal SIGM changes according to Δn1 described above, the signal SIGM has a width corresponding to the change of the frequency division number of the frequency division number control circuit 6 described above and is detected at an edge at any time point indicated by a dotted line in the figure. Get down. If the width at this time is ΔT, ΔT
Is a value obtained by multiplying the cycle of the output signal OUT of the VCO (4) by the difference between the maximum value of Δn1 and the minimum value of Δn1.

When no modulation is applied, that is, when both l and m in FIG. 15 are set to 0, the signal SIGM becomes
As shown in FIG. 16A, the reference signal REF falls at any time centering around the falling edge. On the other hand, when the values of l and m are set to values larger than the range of change in the frequency division number, that is, l and m are set to 1> Δn1 (ma
x) and m <−Δn1 (max), the signal SIGM has the frequency division number of (n + 1) regardless of the value of the change amount Δn1 of the frequency division number, as shown in FIG. When the frequency division number is (n + m), the reference signal REF falls after the falling edge of the reference signal REF.
It falls ahead of the falling edge of F.

In the fourth embodiment, when the values of l and m are not set as in this embodiment, the reference signal REF is set.
16A and the edge of the signal SIGM overlap as shown in FIG. 16A, and spurious occurs due to the mixing between both signals. In the present embodiment example, the reference signal RE
The edge of F and the edge of the signal SIGM are shown in FIG.
By setting l and m in the non-overlapping range as shown in, the mixing between both signals is eliminated, and the modulation width Δt
Spurious can be reduced without depending on the value of.

Further, in the third embodiment, the modulation width Δt
Value of the period of N harmonics of the reference frequency fref (2p-
1) / 2 times, the effect of reducing spurious is obtained. Here, the harmonic component of the signal SIGM has a steep characteristic similar to the characteristic shown in FIG. 3, and even if the modulation width Δt slightly changes, its frequency component greatly changes.
For this reason, the modulation width Δt needs to be generated with high accuracy. For example, in the example of FIG. 2 in which the reference signal REF is modulated, the modulation width Δt is 390 ps, which is an extremely short time. It is difficult to maintain that value. In the present embodiment, since the mixing does not occur as described above, high accuracy is not required for the modulation width Δt, and spurious can be easily reduced.

FIG. 17 shows the output current characteristics of the charge pump 2. FIG. 17A shows the operating range of the charge pump when no modulation is applied, and FIG.
It shows the operating range of the charge pump when (max) and m <−Δn1 (max) are set. In the charge pump 2, when the difference between the phase comparison results of the phase comparison circuit 1 is in the vicinity of 0, that is, when the phase difference is very small, the output current characteristic thereof is not linear but causes distortion (non-linearity). Generally, in a frequency synthesizer that operates in a fractional manner, the average phase of the output is synchronized with the reference signal, so the phase is not synchronized as shown in FIG. Works with. Figure 1
If the operating range of the charge pump includes a range of non-linearity as shown in 7 (a), the floor C / N ratio of the frequency synthesizer deteriorates. In the present embodiment, as shown in FIG. 6B, since the operation is performed while avoiding the non-linear range of the charge pump, a good floor C / N ratio, which is almost the same as that of the frequency synthesizer that performs integer frequency division, is obtained. To be

Further, in the fractional-N frequency synthesizer of the present embodiment, the operation of the charge pump 2 is improved as follows by setting the edge on the reference signal side and the edge on the comparison signal side so as not to overlap each other. This also improves the floor C / N ratio. FIG.
Shows the operation of the charge pump as a timing chart, (a) shows the reset timing of the conventional charge pump, and (b) shows the reset timing of the charge pump of the present embodiment. Generally, a charge pump has two current sources with different polarities inside. For example, when a delayed phase error signal is input, the current source that causes a current to flow in the positive direction is operated and the charge pump advances. When the phase error signal of is input, the current source that causes a current to flow in the negative direction is operated. As a conventional method of resetting the phase error signal of the phase comparison circuit 1, in JP-A-63-204540, when both phase error signals are input, the output currents cancel each other out, and A technique for detecting that one current source has operated and sending a reset signal to the phase comparison circuit to reset both phase error signals is described. FIG. The operation timing is shown.

Considering, for example, falling edge comparison, the phase comparison circuit 1 outputs a delayed phase error signal when the signal SIGM falls, and outputs a lead phase error signal when the reference signal REF falls. . In the example of FIG. 18A, the signal SIGM falls earlier than the reference signal REF. Therefore, the delayed phase error signal Idow
n is output, and then the leading phase error signal Iup is output. When such a phase error signal is input, the charge pump 2, as described above, operates the current source that supplies the current in the positive direction and then operates the current source that supplies the current in the negative direction. A reset signal is sent to the phase comparison circuit 1 after both current sources operate. The time τup shown in the figure indicates the time required for detecting that both current sources are operating, sending the reset signal to the phase comparison circuit 1, and resetting the lead and lag phase error signals. There is. As described above, in the conventional resetting of the phase error signal, both phase error signals are output at the same time, and until the reset is applied, the outputs of the charge pump are simultaneously operated by current sources that flow currents having different polarities. That output was canceled.

In the present embodiment, as shown in FIG. 16B, the values of l and m for modulation are set to be larger than the fluctuation width Δn1 of the fractional operation. , N + 1, the reference signal REF is always
The phase of the signal SIGM lags behind that of the signal SIGM, and when n + m, the phase of the signal SIGM always leads the phase of the reference signal REF. Therefore, when the frequency division number is n + m in FIG.
In the example of 8 (b), the reset signal can be generated at the timing of the signal on the phase delay side, that is, the timing of the falling edge of the reference signal REF. By doing so, the leading phase error signal Iup is not output. When the frequency division number is n + 1, the reset signal can be generated at the timing of the falling edge of the signal SIGM, and the delayed phase error signal Idown is not output.

In the charge pump, when the two current sources operate at the same time, there is a difference between the rising and falling waveforms of the output current, a timing shift at the start of the operation, etc., and the output current is not completely canceled. / N
It led to deterioration of the ratio. In this embodiment, since it is clear which signal falls first and which signal falls afterwards, it is possible to generate the reset signal without simultaneously outputting the delay and lead phase error signals. Becomes By doing so, as described above, the spurious is reduced, the floor C / N ratio is improved, and the floor C
The / N ratio can be further improved.

FIG. 19 shows the characteristics of the fractional-N frequency synthesizer of this embodiment and the characteristics of the conventional fractional-N frequency synthesizer as a spectrum characteristic diagram by experiment. Further, FIG. 20 shows, as a spectrum characteristic diagram, the characteristics of the fractional-N frequency synthesizer of this embodiment and the characteristics of the frequency synthesizer that performs integer frequency division, which are obtained by experiments. Note that FIG.
Shows the output frequency fvco of the VCO (4) in the center of the graph. As shown in FIG. 19, the characteristic of the fractional-N frequency synthesizer of this embodiment (graph A) appears at 50 kHz above and below the frequency fvco as compared to the characteristic of the conventional fractional-N frequency synthesizer (graph B). In addition to the removal of spurious, C on the floor that spreads left and right on the paper
The / N ratio is improved. Also, as shown in FIG.
The characteristic (graph A) of the fractional-N frequency synthesizer of this embodiment is almost the same as the characteristic (graph C) of the frequency synthesizer that performs integer frequency division, although the characteristic degradation is about 1 to 2 dB. A good C / N ratio is obtained.

(Sixth Embodiment) FIG. 21 shows the configuration of a fractional-N frequency synthesizer according to a sixth embodiment of the present invention. The example of the present embodiment is that the adder 13 adds (N + F / M) which is a predetermined value of − (l + m) / 2 to the frequency division number control circuit 6 and inputs the same to the frequency division number control circuit 6. Is different from. In the fractional-N frequency synthesizer of the fourth embodiment, the period of the signal SIGM is
Since the cycle of the output signal OUT is obtained by dividing the cycle of n + (l + m) / 2, when a combination of l and m other than 1 + m = 0 is used, an offset occurs in the cycle and the average frequency division number changes. . Therefore, it is advisable to input a predetermined value to (N + F / M) input to the frequency division control circuit 6 to compensate for this offset. By doing so, the average frequency division number does not change when the modulation is applied and when it is not added.

(Seventh Embodiment) As described above, in the first and third embodiments, in the desired non-integer range of F / M, the input signal of the phase comparison circuit 1 and VCO (4) It is possible to reduce spurious due to the mixing with the output signal OUT of. However, in all non-integer ranges of 0 <F / M <1, spurious due to low frequency components are reduced, the lock time is fast, and the fractional N with low noise is used.
In order to realize the frequency synthesizer, the operation of the modulation circuit may be switchable for the following reasons.

As described above, the modulation width Δt = (1 / N × fref) is applied to either one of the input signals of the phase comparison circuit 1.
By applying modulation of × (2p−1) / 2, the frequency of the spurious component becomes (F / M) × fref from | F / M−
Shift to 1/2 | × fref. Considering that the conventional spurious without modulation is generated by being mixed with the harmonics of (N + 1) × fref instead of N × fref in the range of 1/2 <F / M <1,
The frequency component is (1-F / M) × fref. Also,
As shown in FIG. 3, the signal RE, which is a modulated signal
The harmonic component of the FM changes depending on the modulation width Δt.
Therefore, the frequency of the spurious component changes depending on the non-integer value F / M and the modulation width Δt.

Here, F / M which is a spurious component and |
When compared with F / M-1 / 2 |, 0 <F / M <1/4
In the range of | F / M-1 / 2 |> F / M, 1 /
In the range of 4 <F / M <1/2, F / M> | F / M-1
/ 2 |. In the range of 1/2 <F / M <1, (1-
F / M) and | F / M-1 / 2 |
<F / M <3/4, (1-F / M)> | F / M-1
/ 2 |, and if 3/4 <F / M <1, | F / M-1
/ 2 |> (1-F / M).

That is, 0 <F / M <1/4 and 3 /
In the range of 4 <F / M <1, the frequency of the spurious component in the case of the above embodiment in which Δt is added is higher than the frequency of the spurious component in the conventional case, and the minimum value of the frequency is fref × 1/4. Also, 1/4 <
In the range of F / M <3/4, the frequency of the conventional spurious component becomes higher than the frequency of the spurious component of the above-described embodiment in which Δt is added, and the minimum value of the frequency is fref × 1. / 4. The higher the frequency of the spurious component, the easier it can be removed by the LPF (3).
In the range of / 4 <F / M <3/4, the conventional fractional-N frequency synthesizer can suppress spurious to a lower level.

FIG. 22 shows the frequency spectrum of the conventional fractional-N frequency synthesizer and the frequency spectrum of the fractional-N frequency synthesizer of the first embodiment, (a) of the conventional F / M = 1/64. (B) is when F / M = 1/64 in the above embodiment, and (c) is when conventional F / M = 31/64.
(D) shows the frequency spectra when F / M = 31/64 in the above-described embodiment. When F / M is close to 0 (F / M <1/4) as shown in FIG. 7A, N harmonics of the unmodulated reference signal REF and the output signal OU
The frequency fsp, which is the difference from the frequency fvco of T, is in the low frequency range (100 kHz), but as in the above embodiment,
By applying the modulation of the modulation width Δt, the frequency fsp can be increased to the high frequency range (3.1 MHz) as shown in FIG. However, as shown in FIG.
When M is close to 1/2 (1/4 <F / M <3/4), the N harmonic of the unmodulated reference signal REF and the output signal OU
The frequency fsp, which is the difference from the frequency fvco of T, is in the high frequency range (3.1 MHz), but as in the above embodiment,
By applying the modulation with the modulation width Δt, the difference frequency fsp is shifted to the low frequency range (100 kHz) as shown in FIG.

FIG. 23 shows the configuration of a fractional-N frequency synthesizer according to the seventh embodiment of the present invention. The fractional-N frequency synthesizer of the present embodiment example has a reference signal REF and a signal RE depending on the value of F / M.
This is different from the first embodiment shown in FIG. 1 in that a selection circuit 14 for selecting any of the FMs is provided subsequent to the modulation circuit 7. The selection circuit 14 selects either the reference signal REF or the signal REFM according to the value of F / M, and 0 <F / M <
In the whole non-integer (fractional) frequency division range of 1, generation of low frequency components of fref × 1/4 or less is suppressed, and characteristic deterioration due to spurious is reduced. The selection circuit 14 inputs N + F / M, of which the value of F / M is 0 <F / M <1/4, 3 /
When 4 ≦ F / M <1, the signal REFM from the modulation circuit 7
Is selected and output. When 1/4 ≦ F / M <3/4, the reference signal REF is selected and output.

In FIG. 24, fref = 6.4 MHz and F =
0 to 63, a specific configuration example of the selection circuit 14 in M = 64 is shown, (a) shows the configuration of the selection circuit, and (b) shows the operation of the exclusive OR circuit in the selection circuit. The selection circuit 14 includes a reference signal REF and a signal REFM, and a signal RS.
EL and the selector 142 which outputs one of the signals in accordance with the signal RSEL and the 6-bit data F which constitutes the numerator of a non-integer (F / M), the value of MSB and the value of MSB-1. Ex to input and output signal RSEL
OR (exclusive OR circuit) 141. For example, the selector 142 selects the signal REFM while the signal RSEL is at the L level, and the reference signal REF during the H level.
Select.

As shown in FIG. 24B, the upper side 2 of F
When the two bit values are both 0 or the upper two bit values are both 1, that is, when F is 0 to 15 or F is 48 to 63, the signal RSEL is output.
Becomes L level, and the selector 142 selects the signal REFM. When one of the two higher-order bit values of F is 0 and the other is 1, that is, when F is any of 16 to 47, the signal RSEL becomes H level,
The selector 142 selects the reference signal REF. Thus, F is in the range of 16 ≦ F <48, that is, 1/4 ≦ F / M
In the case of <3/4, the unmodulated reference signal REF is selected and 0 ≦ F / M <1/4 or 3/4 ≦ F / M <1
In the range of, the signal REFM is selected.

In this embodiment, F / M which is a non-integer value
By selecting an appropriate signal according to the value of, 0 <F / M
Since the frequency of the spurious component is prevented from becoming low in the entire range of <1, the spurious can be easily removed by the LPF (3). Therefore, a fractional-N frequency synthesizer with low noise and fast lock time is realized in the whole range of non-integer values. When the fractional-N frequency synthesizer of the present embodiment is applied as, for example, a frequency synthesizer for transmission / reception of a wireless device, spurious generated in the vicinity of a desired frequency can be reduced in all channels. Note that F / M = 1
In the case of / 4 or 3/4, the frequencies of the spurious components of the above-described embodiment and the conventional example have the same value, so that the reference signal R
Which signal, EF or signal REFM, is selected can be arbitrary.

(Eighth Embodiment) FIG. 25 shows a fractional-N frequency synthesizer according to an eighth embodiment of the present invention. The fractional-N frequency synthesizer of this embodiment is provided with a plurality of modulation circuits that modulate the reference signal REF with different modulation widths, and a selection circuit that selects the output of any one of the modulation circuits according to the value of F / M. It is different from the first embodiment in points. The modulation circuit 15 is, for example,
At every other cycle of the reference signal REF, Δt = 0.5 × (1 /
The signal REFM1 delayed by (N × fref) is output. The modulation circuit 16 outputs a signal REFM2 obtained by delaying the reference signal REF by Δt = 1 × (1 / (N × fref)) every other cycle, for example.

The selection circuit 14 includes REFM1 and REFM.
2 is input, REFM1 or REFM2 is selected according to the value of F / M out of N + F / M input to the frequency division control circuit 6, and output to the phase comparison circuit 1. As described above, the harmonic component included in the modulated reference signal REF changes as shown in FIG. 3 depending on the value of the modulation width Δt. The selection circuit 14 is set so as to select a signal having an appropriate modulation width such that the frequency component of spurious does not become a low frequency. By setting in this way, the frequency range of the low frequency component generated by mixing is set to the F / M and the modulation width Δ.
It becomes possible to appropriately adjust in consideration of the relationship of t.

(Ninth Embodiment) FIG. 26 shows the configuration of a fractional-N frequency synthesizer according to the ninth embodiment of the present invention. (A) shows the configuration of the fractional-N frequency synthesizer, ) Indicates a specific configuration example of the variable modulation circuit used in the present embodiment. The fractional-N frequency synthesizer of this embodiment is shown in FIG.
The modulation circuit 7 is different from the first embodiment in that it replaces the variable modulation circuit 17, which can arbitrarily adjust the modulation width according to the value of N + F / M. The modulation circuit 17 uses the reference signal REF
To output a signal REFM delayed by an arbitrary modulation width Δt, for example, once every two times. At this time, the value of the arbitrary modulation width Δt includes 0 (non-modulation).

As shown in FIG. 26B, the variable modulation circuit 17 has a D / A conversion circuit 171 which inputs M and F and outputs a control signal corresponding to the values of M and F, and a delay amount. And a delay circuit 172 controllable by current. The variable modulation circuit 17 controls the delay amount added to the reference signal REF by the delay circuit 172 by the output of the D / A conversion circuit 171, so that the frequency component of spurious does not become a low frequency. For example, the D / A conversion circuit 171 includes the delay circuit 172.
Delay amount (Δt) of 0 <F / M <1/4 or 3/4 <
When F / M <1, Δt is 1 / N × fref (2p
-1) / 2 times (p is a natural number), 1 / 4≤F
When / M ≦ 3/4, control is performed so that Δt becomes q times 1 / N × fref (q is a natural number). Modulation width Δt is F
By changing it according to / M, it becomes possible to arbitrarily control the frequency range of the low frequency component generated by mixing according to the oscillation frequency of the VCO.

Further, 0 <F / M <1 explained in the seventh to ninth embodiments shown in FIGS. 23, 25 and 26.
The technique for preventing spurious in the entire range of (3) is similarly applicable not only to the first embodiment example but also to the fractional-N frequency synthesizer of the third embodiment example shown in FIG. In this case, a selection circuit that switches between a modulated signal and a signal that does not modulate on the side of the comparison signal SIG, which is a signal on the side to which modulation is applied, and a signal that has a different modulation width, depending on the value of F / M. A circuit or a variable modulation circuit whose modulation width can be adjusted is provided. For example, when the fractional-N frequency synthesizer of the third embodiment is provided with the selection circuit 14 of the seventh embodiment shown in FIG. 23, the selection circuit 14 outputs the output signal OUT of VCO (4) ( N + F / M) according to the non-integer value (F / M) of the frequency divider circuit 5 for dividing the frequency, the comparison signal SIG or the signal S
It suffices to select one of the IGMs and input the selected signal to the phase comparison circuit 1.

In the fifth embodiment, the divider circuit 5
By setting the frequency division number of n + 1 and n + m, the reference signal RE
Although the example in which the edge of F and the edge of the signal SIGM do not overlap has been described, it is possible to prevent the edge on the reference signal side and the edge on the comparison signal side from overlapping by controlling the modulation applied to the reference signal REF. You can For example, in the first embodiment, the reference signal has a modulation width Δ of the modulation circuit 7.
By setting t to a value larger than a predetermined value, the edges of the signal REFM and the comparison signal SIG do not overlap in the phase comparison circuit 1. For example, the signal sequence output from the frequency division number control circuit 6 is N + n1 and n−n2 (n1 and n2 are integers of 0 or more).
The fluctuation range of the comparison signal SIG is Δ
T = (n1 + n2) × VCO (4) output cycle, but the modulation width Δt of the modulation circuit 7 is set to 2 of the fluctuation width of the comparison signal.
One-half, that is, larger than the time represented by ΔT / 2. By setting the modulation width Δt as described above, the signal R
Since the edge of the EFM and the edge of the comparison signal SIG do not overlap each other and mixing between the two signals is eliminated, spurious is removed. Also in the second embodiment,
Similarly, the modulation width Δt (= clock period × | l−m | /
By appropriately setting 2), it is possible to prevent edges from overlapping.

Further, the generation of the reset signal described in the fifth embodiment is not limited to the configuration of the fifth embodiment, and any one of the signals input to the phase comparison circuit is first. The present invention can be applied to a phase comparison circuit in which it is clear which signal falls (rises) and which signal falls (rises) later. In the fifth embodiment, the edge on the comparison signal side is adjusted so that the timing does not overlap with the edge of the reference signal. However, the edge on the reference signal side is changed by the difference in frequency division of the comparison signal. The same effect can be obtained by shifting the front and back.

In the fourth to sixth embodiments, the example in which the signal SIGM is generated by modulating the comparison signal SIG and the phase is compared with the reference signal REF by the phase comparison circuit 1 has been described. The modulation circuit 7 shown in FIG. 1 is provided on the signal side,
It is also possible to add the signal REFM by modulating the reference signal REF and input it to the phase comparison circuit. That is, the two signals input to the phase comparison circuit 1 are both modulated signals. For example, even if the frequency dividing number of the frequency dividing circuit 5 is alternately switched to n + 1 and n + m so that the edges of the reference signal REF and the signal SIGM do not overlap each other as in the fifth embodiment, the frequency dividing circuit 5 does not overlap. Also, the internal operation timing of the frequency division number control circuit 6 may overlap the edge of the reference signal REF. In this case, in the phase comparison circuit 1, the reference signal REF and a signal whose timing overlaps with each other interfere with each other via the power supply line and the ground line, and although the level is low, the harmonic of the reference signal REF and V
Spurious occurs due to mixing of the frequency of the output of CO (4). Therefore, the reference signal REF is modulated with a width that is (2p-1) / 2 times the period of the N harmonic of the reference frequency fref, and is input to the phase comparison circuit as the signal REFM. By modulating both signals input to the phase comparison circuit 1 in this way, the occurrence of spurious can be reduced.

Although the present invention has been described above based on its preferred embodiments, the fractional-N frequency synthesizer of the present invention is not limited to the above-mentioned embodiments, and has the configuration of the above-mentioned embodiments. Fractional-N frequency synthesizers with various modifications and changes are also within the scope of the invention. For example, the period to apply the modulation, or
The number of cycles by which the frequency division number is +1, + m is not limited to once every two times, but may be once every plural times.

[0106]

As described above, in the fractional-N frequency synthesizer of the present invention, the frequency of the VCO output is a non-integer multiple of the periodicity (frequency) of the reference signal or the comparison signal, which causes phase comparison. It is possible to suppress the spurious of the VCO output generated on the output side of the circuit, which is based on the low frequency component peculiar to the fractional control (PLL circuit of non-integer frequency division). That is, even if a part of the VCO output goes around to the reference signal or the comparison signal side via the package or the substrate (power supply line, earth line, etc.), the signal component generated by mixing is shifted to the high frequency range. Therefore, the signal component generated at the output side of the phase comparison circuit is LP
It becomes possible to sufficiently attenuate in the F circuit, and VC
A spurious is not generated in the vicinity of the frequency of the O output, and a low spurious fractional N frequency synthesizer is realized.

[Brief description of drawings]

FIG. 1 is a fractional N according to a first embodiment of the present invention.
The block diagram which shows the structure of a frequency synthesizer.

2 is a timing chart showing a basic operation of the fractional-N frequency synthesizer shown in FIG.

FIG. 3 is a graph showing a calculation result by Fourier series expansion of harmonics of a signal REFM.

FIG. 4 is a frequency characteristic of each signal, where (a) shows a frequency characteristic of a reference signal REF, (b) shows a frequency characteristic of a signal REFM, and (c) shows a frequency characteristic of mixing in a phase comparison circuit. Spectral diagram.

5 is a spectrum characteristic diagram of a signal obtained by the fractional-N frequency synthesizer of FIG. 1. FIG.

6 is a specific configuration example of the modulation circuit 7 of FIG.
FIG. 3A is a block diagram showing the configuration of a modulation circuit, and FIG. 3B is a block diagram showing the configuration of a counter in the modulation circuit.

7 is a time chart showing the operation of the modulation circuit of FIG.

FIG. 8 is a fractional N according to a second embodiment of the present invention.
The block diagram which shows the structure of a frequency synthesizer.

9 is a specific configuration example of the modulation control circuit 9 of FIG.
9A is a block diagram showing the configuration of a modulation control circuit, and FIG. 9B is a block diagram showing the configuration of a counter in the modulation control circuit.

10 is a time chart showing the operation of the modulation control circuit of FIG.

FIG. 11 is a block diagram showing the configuration of a fractional-N frequency synthesizer according to a third embodiment of the present invention.

12 is a block diagram showing a specific configuration example of the modulation circuit 10 in FIG.

FIG. 13 is a block diagram showing the configuration of a fractional-N frequency synthesizer according to a fourth embodiment of the present invention.

14 is a block diagram showing a specific configuration example of the modulation control circuit 11 in FIG.

FIG. 15 is a block diagram showing the configuration of a fractional-N frequency synthesizer according to a fifth embodiment of the present invention.

FIG. 16 is a timing chart showing edges of a signal input to the phase comparison circuit 1, where (a) is an edge when no modulation is applied, (b) is l, m where l> Δn1 (ma
x), a timing chart showing edges when m <-Δn1 (max) is set.

FIG. 17 is an output current characteristic of the charge pump 2,
(A) is the operating range of the charge pump when no modulation is applied, (b) is l, m where l> Δn1 (max), m <−
The graph which together shows the operating range of a charge pump at the time of setting to (DELTA) n1 (max).

FIG. 18 is an operation timing of the charge pump,
9A is a timing chart showing the reset timing of the conventional charge pump, and FIG. 9B is a timing chart showing the reset timing of the charge pump of the present embodiment.

19 is a spectrum characteristic diagram of signals obtained by the conventional fractional-N frequency synthesizer and the fractional-N frequency synthesizer of FIG.

FIG. 20 is a frequency synthesizer that performs integer division, and
FIG. 16 is a spectrum characteristic diagram of a signal obtained by the fractional-N frequency synthesizer of FIG. 15.

FIG. 21 is a block diagram showing a configuration of a fractional-N frequency synthesizer according to a sixth embodiment of the present invention.

FIG. 22 is a spectrum diagram showing a numerical example of the relationship between F / M and Δf.

FIG. 23 is a block diagram showing the configuration of a fractional-N frequency synthesizer according to a sixth embodiment of the present invention.

FIG. 24 is a block diagram showing a specific configuration example of the selection circuit 14 in FIG. 23.

FIG. 25 is a block diagram showing the configuration of a fractional-N frequency synthesizer according to an eighth embodiment of the present invention.

FIG. 26 is a block diagram showing the configuration of a fractional-N frequency synthesizer according to a ninth embodiment of the present invention.

FIG. 27 is a block diagram showing the basic configuration of a conventional frequency synthesizer that performs integer frequency division.

FIG. 28 is a block diagram showing the configuration of a conventional fractional-N frequency synthesizer.

FIG. 29 is a block diagram showing a configuration example of a frequency division number control circuit having a noise shaping effect.

30 is a spectrum characteristic diagram obtained by the fractional-N frequency synthesizer of FIG. 28. FIG.

31A and 31B show how the output signal of the frequency synthesizer and the reference signal are mixed, FIG. 31A shows the frequency characteristic of the frequency synthesizer with integer division, and FIG. 31B shows the spectrum showing the frequency characteristic of the fractional N frequency synthesizer. Fig.

[Explanation of symbols]

1 Phase comparison circuit (PD) 2 Charge pump (CP) 3 Low pass filter (LPF) 4 Voltage controlled oscillator (VCO) 5 frequency divider 6 frequency division control circuit 7, 10, 15, 16 Modulation circuit 9, 11, 12 Modulation control circuit 8 divider 13 adder 14 Selection circuit 17 Variable modulation circuit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yutaka Takahashi             5-7 Shiba 5-1, Minato-ku, Tokyo NEC Corporation             Inside the company F term (reference) 5J106 AA04 BB10 CC01 CC24 CC41                       CC53 DD09 DD32 FF02 FF06                       GG09 GG18 KK26 PP03 QQ08                       RR01 RR20

Claims (31)

[Claims] 1. A frequency dividing circuit for switching an oscillation output of a voltage controlled oscillator by a plurality of frequency dividing numbers and outputting a divided signal as a comparison signal, and a time average of the frequency dividing numbers of the frequency dividing circuit is a non-integer value. And a phase comparison circuit that outputs the phase comparison result of the reference signal and the comparison signal as a phase difference signal, and controls the oscillation frequency of the voltage controlled oscillator based on the phase difference signal. In the fractional-N frequency synthesizer, a periodic signal having a predetermined frequency is modulated once in a T period (T is an integer of 2 or more) in the time axis direction by a predetermined modulation width and input to the phase comparison circuit as the reference signal. A fractional-N frequency synthesizer, comprising: 2. The modulation means receives the periodic signal and delays it by the predetermined modulation width, a counter that divides the output of the delay circuit by two, and the counter depends on the output of the counter. The fractional-N frequency synthesizer according to claim 1, further comprising a selector that selects a periodic signal or an output of the delay circuit. 3. The modulation means divides the periodic signal by any one of two frequency division numbers, and the frequency division number of the periodic signal frequency divider by the period. And a modulation control circuit that switches for each cycle that is equal to or greater than the output cycle of the sex signal divider,
The fractional-N frequency synthesizer according to claim 1, wherein the reference signal is output from the periodic signal frequency divider. 4. The modulation control circuit switches between a counter that divides the output of the periodic signal frequency divider by 2 and a frequency division number of the periodic signal frequency divider that depends on the output of the counter. A fractional-N frequency synthesizer according to claim 3, characterized in that it comprises: 5. The frequency dividing numbers of the frequency dividing circuit are N-n1 and N +.
n2 (N is a natural number, n1 and n2 are integers equal to or greater than 0), and the predetermined modulation width is larger than the period of the input side of the frequency dividing circuit × (n1 + n2) / 2. The fractional N according to any one of claims 1 to 4.
Frequency synthesizer. 6. The fractional-N frequency synthesizer according to claim 5, wherein the phase difference signal is reset at an edge of a signal having a phase lag between the reference signal and the comparison signal. 7. A selection circuit for selecting either the periodic signal or the modulation output of the modulation means as the reference signal depending on a non-integer value input to the frequency division control circuit. The fractional N frequency synthesizer according to claim 1 or 2, characterized in that it is provided. 8. The selection circuit selects the modulation output when the non-integer value is 0 or more and less than ¼ and when it is 3/4 or more and less than 1 and the non-integer value is The fractional-N frequency synthesizer according to claim 7, characterized in that a periodic signal is selected when it is equal to or greater than 1/4 and smaller than 3/4. 9. The display device further comprises a plurality of the modulation means, and further comprises a selection circuit which selects any one of the plurality of modulation means depending on a non-integer value input to the frequency division number control circuit. And the fractional N according to claim 1 or 2.
Frequency synthesizer. 10. When the frequency of the periodic signal is fref, the modulating means is (2p−1) / (2 × N × f).
ref), at least one first modulation means having a modulation width of (p and N are natural numbers), and q / (N × fref)
The fractional-N frequency synthesizer according to claim 9, further comprising at least one second modulation means having a modulation width of (q, N is a natural number). 11. The non-integer value of the selection circuit is 0.
When the value is less than 1/4 and when it is 3/4 or more and less than 1, the first modulating means is selected, and when the non-integer value is 1/4 or more and less than 3/4, the second modulating means is selected. 11. The modulation means of is selected.
A fractional-N frequency synthesizer according to. 12. The denominator of the non-integer is 2 ⁿ (n is an integer of 2 or more), and the selection circuit divides the most significant bit of the numerator of the non-integer and one bit lower than the most significant bit. The fractional N frequency synthesizer according to claim 8 or 11, wherein an exclusive OR is used as a selection control signal. 13. The modulation means includes a modulation width switching means for controlling the predetermined modulation width depending on a non-integer value input to the frequency division number control circuit. The fractional-N frequency synthesizer according to 2. 14. The fractional-N frequency synthesizer according to claim 13, wherein the modulation width switching means includes a delay circuit that outputs a delay amount according to the non-integer value. 15. The non-integer value of the delay circuit is 0.
When the above is less than ¼ and when the amount is 3/4 or more and less than 1, the delay amount is (2p−1) / (2 × N ×).
fref) (p and N are natural numbers), and when the non-integer value is 1/4 or more and less than 3/4, the delay amount is q.
/ (N × fref) (q is an integer of 0 or more, N is a natural number)
The fractional-N frequency synthesizer according to claim 14, characterized in that 16. A frequency divider circuit for switching the oscillation output of a voltage controlled oscillator by a plurality of frequency division numbers to output a frequency-divided signal,
A frequency dividing number control circuit for controlling the time average of the frequency dividing number of the frequency dividing circuit to a non-integer value, and an output of the frequency dividing circuit as a comparison signal and a phase comparison result of the phase comparison between the comparison signal and the reference signal as a phase difference signal. In a fractional N frequency synthesizer for controlling the oscillation frequency of the voltage controlled oscillator based on the phase difference signal, the output of the frequency divider circuit is output for T cycles (T is an integer of 2 or more). The fractional-N frequency synthesizer is characterized in that it further comprises a modulation means for modulating once in a time axis direction by a predetermined modulation width and inputting to the phase comparison circuit as the comparison signal. 17. The modulation means depends on a delay circuit that receives the output of the frequency dividing circuit and delays the output by the predetermined modulation width, a counter that divides the output of the delay circuit by two, and an output of the counter. 17. The fractional-N frequency synthesizer according to claim 16, further comprising a selector that selects and outputs the output of the frequency dividing circuit or the output of the delay circuit. 18. The modulation control circuit, wherein the modulation means switches and adds two different addends to the frequency division number output from the frequency division number control circuit at every cycle equal to or greater than the output cycle of the frequency division circuit. Fractional N frequency synthesizer according to claim 16, characterized in that it comprises: 19. The modulation control circuit includes a counter for dividing the output of the frequency dividing circuit into two, a selector for switching between the two different addends depending on the output of the counter, and the selector for outputting the selector. The fractional-N frequency synthesizer according to claim 18, further comprising an adder for adding the frequency division numbers output from the frequency division number control circuit. 20. The output of the frequency division number control circuit is N-n1.
And N + n2 (N is a natural number, n1 and n2 are integers of 0 or more)
And the larger of n1 and n2 is N1, the two different addends consist of a value smaller than −N1 and a value larger than + N1. The fractional N frequency synthesizer according to 18 or 19. 21. The phase difference signal includes a frequency division number output by the frequency division number control circuit, which is -N of two different addends.
21. The fractional-N frequency synthesizer according to claim 20, wherein when the addend smaller than 1 is added, the reference signal is reset, and when the addend larger than + N1 is added, the comparison signal is reset. 22. A selection for selecting either the modulation output of the modulating means or the output of the frequency dividing circuit and inputting it to the comparison circuit depending on a non-integer value input to the frequency dividing number control circuit. 18. The fractional-N frequency synthesizer according to claim 16 or 17, further comprising a circuit. 23. In the selection circuit, the non-integer value is 0.
When the above is smaller than ¼ and when it is 3/4 or more and less than 1, a modulation output is selected, and when the non-integer value is ¼ or more and less than 3/4, a comparison signal is selected. The fractional-N frequency synthesizer according to claim 22, characterized in that 24. A plurality of the modulation means are provided, and a selection circuit is further provided for selecting any one of the plurality of modulation means depending on a non-integer value input to the frequency division number control circuit. The fractional N frequency synthesizer according to claim 16 or 17. 25. When the frequency of the reference signal is fref, the modulator is (2p−1) / (2 × N × fr).
ef) (p and N are natural numbers) and at least one first modulation means having a modulation width of q / (N × fref) (q,
25. Fractional N frequency synthesizer according to claim 24, characterized in that N comprises at least one second modulation means having a modulation width of a natural number. 26. In the selection circuit, the non-integer value is 0.
When the above is less than ¼ and when 3/4 or more and less than 1, one modulation means is selected, and when the non-integer value is ¼ or more and less than 3/4, the other modulation means is selected. The fractional-N frequency synthesizer of claim 25, characterized in that 27. The denominator of the non-integer is 2 ⁿ (n is an integer of 2 or more), and the selection circuit excludes the most significant bit of the numerator of the non-integer and one bit lower than the most significant bit. The fractional-N frequency synthesizer according to claim 23 or 26, wherein a logical OR is used as a selection control signal. 28. The modulation means comprises a modulation width switching means for controlling the predetermined modulation width depending on a non-integer value input to the frequency division number control circuit. 17. A fractional-N frequency synthesizer according to item 17. 29. The fractional N according to claim 16, wherein the modulation width switching means includes a delay circuit that outputs a delay amount according to the non-integer value.
Frequency synthesizer. 30. In the delay circuit, the non-integer value is 0.
When the above is less than ¼ and when the amount is 3/4 or more and less than 1, the delay amount is (2p−1) / (2 × N ×).
fref) (p and N are natural numbers), and when the non-integer value is 1/4 or more and less than 3/4, the delay amount is q.
/ (N × fref) (q is an integer of 0 or more, N is a natural number)
The fractional-N frequency synthesizer according to claim 29, characterized in that 31. The reference signal is a signal obtained by modulating a periodic signal of a predetermined frequency once in a U cycle (U is an integer of 2 or more) by a predetermined modulation width in the time axis direction. A fractional-N frequency synthesizer according to any one of claims 16 to 21.