JP2003115662A - Method of manufacturing semiconductor device substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for removing the occurrence of migration due to residue left in the base of an insulating resin layer at the base of a pattern, and a method for making conductor width at the top of a pattern layer wider than conductor width by conventional technology for forming high density wiring. SOLUTION: In a process for forming a wiring pattern, a thin film conductor layer by a plating method is formed after the insulating resin layer is formed. A photosensitive resist layer is formed and a resist layer for forming the necessary pattern is formed by the photo-process method of exposure and development. The manufacturing method of a semiconductor device substrate is provided with a process for performing plasma processing on a whole face, a process for performing electrolytic copper plating, a process for peeling the resist layer, and a process for removing the thin film conductor layer. Thus, the semiconductor device substrate where the occurrence of migration can be prevented and conductor width can be widen can be supplied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a step of forming a high-density wiring pattern in a step of manufacturing a semiconductor device substrate of a multilayer printed wiring board, a build-up method, or a module wiring board using a film carrier. .

[0002]

2. Description of the Related Art In recent years, there has been a demand for miniaturization and thinning of electronic equipment as represented by personal computers and the like. Therefore, miniaturization and thinning are also required for the semiconductor device substrate used inside. A semiconductor device substrate is a module substrate such as a ball grid array (BGA) or pin grid array (PGA) on which a semiconductor chip and other components are mounted, and is on a multi-layer printed wiring board which is a parent substrate. In many cases, it is mounted on, but it is also used as a parent board.

Further, in manufacturing a semiconductor device substrate including a film carrier, a module substrate, and a multilayer printed wiring board, there is a manufacturing process for forming a common wiring pattern layer, so that the electronic equipment can be made smaller and thinner. In order to realize the above, in the manufacturing process for forming the wiring pattern layer, the wiring width is thin, the gap is small, the wiring layer is multi-layered, and the diameter of the via connecting the wiring layers is reduced. A device substrate is required.

As a semiconductor device substrate that meets these requirements, for example, a multilayer printed wiring board using a build-up method is known. This multilayer printed wiring board is suitable for high-density wiring because the via holes 4 can be formed between arbitrary layers using a laser drilling machine. Further, in the high-density wiring, the wiring pattern layer is made finer and the via hole 4 is made smaller in diameter, and new methods are increasing.

An example of a method for manufacturing a multilayer printed wiring board using the build-up method will be described.
4A to 4G are schematic views showing cross-sectional views of a multilayer printed wiring board using such a conventional build-up method.

First, FIG. 4a shows a wiring layer 2 made of copper foil on an insulating substrate 1 made of a rigid glass epoxy substrate or the like.
Using a copper-clad glass epoxy substrate formed by laminating, a photosensitive resist 12 is applied on the wiring layer 2, exposed and developed to pattern the photosensitive resist 12, and the exposed copper wiring layer 2 is exposed. Is used to form the wiring layer 2 having a predetermined wiring pattern.

Next, in FIG. 4b, a thermosetting insulating resin is applied on the insulating substrate 1 and the wiring layer 2 to form a thermosetting insulating resin layer 3. For example, as a coating method, a screen printing method, a curtain coating method or a spin coating method is used. A polyimide resin, an acrylic resin, an epoxy resin, or the like is used as the material of the insulating resin layer 3. For example, as a method for forming the insulating resin layer 3, there is a method of sticking a sheet-shaped insulating resin layer 3, which is preferable from the viewpoint that the insulating layer can be easily formed with a uniform thickness. The insulating resin layer 3 is subjected to laser processing using a YAG laser or the like to form a predetermined via hole 4 at a predetermined position, and an insulating resin layer 3 and a via hole 4 having a predetermined pattern are formed.

Next, the substrate 1 is immersed in potassium permanganate and washed to remove the residue attached to the hole wall in the via hole 4 and the residue remaining at the bottom of the hole.

Next, as shown in FIG. 4c, a thin film conductor layer 5 is formed by electroless plating on the entire surface of the insulating resin layer 3 and the inner wall of the via hole 4 by electroless plating. To form a resist layer 12, and the resist layer 12 is subjected to exposure by light irradiation using a photomask for exposure, and patterning is formed by processing in a developing step, and the resist layer 12 having a predetermined pattern is formed. To form. Further, electrolytic copper plating is performed on the entire surface of the thin film conductor layer 5 to form a plating layer 7, and the resist layer 12 is formed.
Peel off the film, lightly soft etching the entire surface,
The unnecessary thin film conductor layer 5 is removed. A predetermined pattern wiring layer 2 and via hole 11 are formed.

Generally, in the step of forming the wiring layer, in addition to the above-mentioned semi-additive method and subtractive method,
For example, the full additive method is also used as appropriate.

Next, as shown in FIG. 4d, an insulating resin solution is applied to the entire surface of the insulating resin layer 3 and the wiring layer 2 and the via hole 11 to form the insulating resin layer 3, and laser processing is performed at a predetermined position of the insulating resin layer 3. A via hole 4 is formed. Further, through holes 6 for through holes are formed from the front surface to the back surface of the substrate by drilling.

Next, FIG. 4e shows that a thin film conductor layer 5 is formed on the insulating resin layer 3, the via hole 4 and the through hole through hole 6 by an electroless plating method. An electrolytic copper plating layer is formed 7 on the entire surface of the conductor layer 5, and the conductor layer 8 made of copper, the via hole 11, and the through hole 9 are formed.
To form.

As shown in FIG. 4f, a wiring pattern layer 8 having a predetermined pattern is formed on the conductor layer 8 by patterning as shown in FIG. 4f.

The step of forming the wiring layer was processed by the subtractive method described above.

Next, as shown in FIG. 4g, the insulating resin layer 3 and the wiring layer 2, the via hole 11, and the through hole 9 are formed.
An insulating resin solution is applied to the entire upper surface to form the insulating resin layer 3, and a via hole 4 is formed at a predetermined position of the insulating resin layer 3 by laser processing.

Next, as shown in FIG. 4g, the insulating resin layer 3 is formed.
A thin film conductor layer 5 is formed by electroless plating on the entire surface up to the hole wall in the hole of the via hole 4, and a dry film of a photosensitive resist is bonded to both surfaces of the substrate to form a resist film on the entire surface of the thin film conductor layer. The layer 12 is formed, the resist layer 12 is exposed to light by using a photomask for exposure, and patterning is formed by a treatment in a developing step.
A resist layer 12 having a predetermined pattern is formed. Further, electrolytic copper plating is performed on the entire surface of the thin film conductor layer 5 to form a plating layer 7, and the resist layer is peeled off.
The whole surface is lightly soft-etched to remove the unnecessary thin film conductor layer 5 to form a predetermined pattern wiring layer 2 and a via hole 11.

Finally, in FIG. 4g, a solder resist layer 10 is formed on both sides of the multilayer printed wiring board to protect the wiring pattern layer 8 such as wiring and power supply, and the multilayer printed wiring board is completed.

The conventional film carrier structure and manufacturing method shown in FIG. 5 will be described. 5A to 5E show an example of a method for manufacturing a film carrier.

First, a copper foil or the like is attached to both surfaces of the insulating film 13 via an adhesive layer to form the adhesive layer 14 and the conductor layer 2 (see FIG. 5A).

Next, sprocket holes 15 are formed on both ends of the insulating film 13 by punch press or the like (see FIG. 5B).

Next, the opening 16 is formed at a predetermined position of the conductor layer 2 (see FIG. 5C).

Next, the opening 16 is formed by using the conductor layer 2 as a mask.
A laser beam is further radiated to form the holes 17 for conduction holes (see FIG. 5D).

Then, the thin film conductor layer 5 is formed by plating the inside of the through hole 17 and the electrolytic copper plating layer 7 is formed.
A conduction hole 18 for electrically connecting the conductor layers 2 on both surfaces is formed (see FIG. 5E).

Next, the conductor layers 2 on both surfaces are subjected to a patterning process to form a first wiring pattern 19 and a second wiring pattern 20.
To obtain a film carrier.

As described above, in the process of manufacturing the semiconductor device substrate of the multilayer printed wiring board using the build-up method or the module wiring board using the film carrier, it is common to the process of forming the high-density wiring pattern. I have a problem to do.

The above-mentioned semi-additive method, subtractive method, or full-additive method is generally used for the step of forming the wiring layer. In common, the place where the gap 25 of the conductor pattern is the narrowest is the bottom 2 of the pattern.
It is 1. Therefore, the surfaces of the insulating resin layers 3 of the bottom portions 21 of the adjacent patterns cause adhesion and adsorption due to plating chemicals, etching solution catalysts, ions, etc., causing migration, which may cause long-term reliability failure of the wiring circuit. Become.

Further, during the etching process, there is a problem that the conductor width 24 of the top 22 of the conductor pattern is narrowed by the side etching. Further, generally, in the above-mentioned semi-additive method, subtractive method, or full-additive method, the order of layer thickness of the conductor layer 2 is the largest, that is, the subtractive method, the semi-additive method, or the full-additive method. .

The formation of finer fine lines tends to be better when the conductor layer to be formed is thinner.

In the manufacturing process for forming the wiring pattern, the wiring width becomes narrow and the gap becomes narrow due to the high density wiring. If the gap between the wiring patterns becomes narrow, it becomes difficult to clean the surface of the insulating resin layer 3 at the bottom, the smoothness of the skirt portion 23 deteriorates, and the cleaning of the skirt portion 23 of the conductor layer is affected. Further, if the gap between the pattern wirings to be etched is narrowed, the etching time tends to be long, and the side etching reduces the conductor width 24 at the top of the pattern layer.

[0030]

DISCLOSURE OF THE INVENTION An object of the present invention is to provide a method for removing migration caused by a residue remaining at the bottom of an insulating resin layer at the bottom of a pattern for forming a high density wiring, and a top of the pattern layer. There is a method of widening the conductor width of the conventional conductor width.

[0031]

The invention according to claim 1 of the present invention comprises: (a) in the step of forming a wiring pattern in the production of a multilayer print using a build-up method.
A step of forming an insulating resin layer, (b) a step of forming a thin film conductor layer by plating over the entire surface of the insulating resin layer, and (c) a photosensitive resist layer over the entire surface of the thin film conductor layer. Forming step, (d) forming a desired pattern on the photosensitive resist layer using a photomask by a photoprocess method, and (e) forming the thin film conductor layer from the patterned resist layer. Plasma treatment on the entire surface up to the surface of (4), (f) electrolytic copper plating on the entire surface, (g) removing the resist layer, and (h) exposing the surface by soft etching And a step of removing the thin-film conductor layer described above.

The invention according to claim 2 of the present invention comprises: (a) a step of forming an insulating resin layer, and (b) a step of forming a wiring pattern in the production of a multilayer print using a build-up method. A step of forming a photosensitive resist layer on the entire surface of the insulating resin layer, and (c) a step of forming a desired pattern on the photosensitive resist layer using a photomask by a photoprocess method, and (d) A step of performing plasma treatment on the entire surface from the patterned resist layer to the surface of the insulating resin layer, (e) a step of electroless copper plating on the entire surface, and (f) peeling the resist layer The method of manufacturing a substrate for a semiconductor device is characterized by performing the following steps.

According to a third aspect of the present invention, in the step of forming a wiring pattern in the production of a film carrier, (a) a step of forming a photosensitive resist layer over the entire surface of the insulating resinous film layer, and , (B) a step of forming a desired pattern on the photosensitive resist layer by a photo process using a photomask, and (c) a step from the resist layer on which the pattern is formed to the surface of the insulating resin layer. For a semiconductor device, which is characterized by performing a step of performing plasma treatment on the entire surface, (d) a step of electroless plating on the entire surface, and (e) a step of peeling the resist layer. It is a method of manufacturing a substrate.

[0034]

1 is a sectional side view of a process for explaining an example of the present invention. A detailed description will be given below along with the embodiment with reference to FIG.

FIG. 1 shows the steps of forming a wiring pattern in the production of a multilayer print using the build-up method.

As shown in FIG. 1A, insulating resin layers 3 are formed on both surfaces of the core substrate 1. The method for forming the insulating resin layer includes a case where the insulating resin liquid is applied by a roll coating method, a curtain coating method, a silk screen printing method, and the like, and a case where the insulating resin layer is formed by bonding a dry film using an insulating resin. is there. Polyimide resin, acrylic resin, epoxy resin and the like are suitable as the insulating resin. Also, for example, it is sold under the trade name of Provicoat 5000 [manufactured by Nippon Paint Co., Ltd.].

The insulating resin layer to be formed has a thickness of 15 μm to 75 μm.
Select the optimum standard in the thickness range.

In FIG. 1B, the thin film conductor layer 5 is formed by plating on the entire surface of the insulating resin layer 3. The thin film conductor layer is formed by a generally used electroless plating method using a thin copper layer. The thickness of the layer may be as thin as possible so long as it can serve as a plating electrode.

In FIG. 1C, the photosensitive resist layer 12 is formed on the entire surface of the thin film conductor layer 5. The photosensitive resist layer 12 is formed by a commonly used photo process. There are a method using a photosensitive resist solution and a method using a dry film, which is appropriately selected and used.

As shown in FIG. 1D, a photosensitive resist layer 12 for forming a desired pattern is formed on the photosensitive resist layer 12 by a photomask using a photomask by an exposure process and a development process. In the photoprocess step, selection of a photosensitive resist resin, for example, photocurable and photosoluble resist resin, or optimization of the total irradiation amount to irradiate the photosensitive resist layer, or optimization of developing conditions in the developing step,
Utilize accumulated know-how.

As shown in FIG. 1E, the entire surface from the resist layer 12 for forming the pattern to the surface of the thin film conductor layer 5 is subjected to plasma treatment.

The plasma treatment is adopted as a means for improving the surface of the polymer material by irradiating a gas that has been turned into plasma by glow discharge under decompressing pressure. In the present invention, it is used as a method by plasma treatment using an inorganic gas.

From the resist layer 12 forming the pattern, the resist resin surface formed on the entire surface and the thin film conductor surface of electroless copper are exposed on the surface of the thin film conductor layer 5. Contamination due to the resist residue remaining on the exposed surface or the catalyst adhering to and adhering to the electroless copper thin film conductor surface 5 is generated.

On the other hand, the bottom 21, the hem 23, and the top 22 of the pattern formed near the gap 25 of the pattern.
The surface shape is not formed uniformly, and the shape of the skirt portion 23 becomes unstable in particular, and there is a problem that it becomes further unstable at the fine line pattern portion.

The surface area of the electroless copper thin film conductor exposed from the skirt portion 23 to the bottom portion 21 plays an important role as an electrode for electrolytic plating and affects the current density at which the plated metal material is deposited.

As a method for solving the above problems, a plasma irradiation step was added to the conventional steps to solve the problem.

The plasma irradiation step is to reduce the film thickness of the surface of the material to be irradiated, and removes the resist residue remaining on the exposed surface or the residue of catalyst etc. adhering to and adsorbing on the electroless copper thin film conductor surface. Remove dirt. Further, in the case of a resist resin in which the ratio of removing the film thickness of the irradiated material surface (etching rate, amount of film thickness loss per unit time) is relatively large, the bottom 21, bottom 23 and top 22 surface of the pattern are used. The shape of the resist is corrected to the optimum shape. As a result, the exposed surface is cleaned, the thin film portion at the resist end portion of the skirt portion 23 is abraded, and the boundary line of the skirt portion is scraped off.
The width of the bottom portion 21 of the pattern formed in the vicinity of is wide.
In addition, the surface corner portion of the top portion 22 has no corner portion and has an optimum shape.

Since the width of the bottom portion 21 of the pattern formed near the gap 25 is widened, the area of the plating electrode is further widened, and the shape of the wiring pattern to be plated is required.

In FIG. 1 (f), electrolytic copper plating is performed on the entire surface.

In FIG. 1G, the resist layer is peeled off.

As shown in FIG. 1H, the thin film conductor layer exposed on the surface is removed by soft etching.
A wiring pattern formed by electrolytic copper plating is formed on the surface of the insulating resin layer, and a wiring pattern layer having a wide surface width at the top 22 and having an inverse taper in the cross-sectional shape is formed.

The above is the manufacturing method for forming the wiring pattern in the manufacturing of the semiconductor device substrate.

3A to 3E show the steps of forming a wiring pattern in the production of a film carrier,

The photosensitive resist layer 12 is formed up to the entire surface of the insulating resinous film layer 13 shown in FIG. 3 (a). Apply a photosensitive resist solution. For example, a roll coater is suitable as a coating method.

In FIG. 3 (b), a required pattern is formed on the resist layer by an exposure process and a development process using a photomask by a photo process method on the photosensitive resist layer.

In FIG. 3C, plasma treatment is performed on the entire surface of the resist layer on which the pattern is formed and the surface of the insulating resin layer.

The plasma irradiation step is to reduce the film thickness of the surface of the material to be irradiated, and removes foreign matters such as resist residues remaining on the exposed surface. Further, in the case of a resist resin in which the ratio of removing the film thickness on the surface of the material to be irradiated (etching rate, amount of film thickness loss per unit time) is relatively large, the bottom 2 of the pattern is used.
On the surface of 1, the hem portion 23, and the top portion 22, the shape of the resist is corrected to an optimum shape. As a result, the exposed surface is cleaned, and the width of the bottom portion 21 of the pattern formed in the vicinity of the gap 25 is widened by adjusting mainly the resist end thin film portion of the skirt portion 23 and reducing the film thickness. In addition, the surface corner portion of the top portion 22 has no corner portion and has an optimum shape.

Since the width of the bottom portion 21 of the pattern formed near the gap 25 is widened, the area of the plating electrode is further widened, and the shape of the wiring pattern to be plated is required.

In FIG. 3D, electroless plating is applied to the entire surface.

As shown in FIG. 3E, the resist layer is peeled off.

A wiring pattern formed by electrolytic copper plating is formed on the surface of the insulating resin layer, and a wiring pattern layer having a wide surface width at the top 22 and having an inverse taper in the cross-sectional shape is formed.

The above is the manufacturing method for forming the wiring pattern in the manufacturing of the semiconductor device substrate.

[0063]

In the pattern formation, the problem of side etching is solved because the subtractive method of forming the conductor layer by the etching method is changed to the semi-additive method or the full-additive method having a step of resist formation.
It is cleaned by adding plasma processing, which has the effect of improving the cleaning of the surface of the insulating layer.

[0064]

EXAMPLES Next, specific examples of the present invention will be described.

<Embodiment 1> FIGS. 2A to 2G are side sectional views showing steps of manufacturing a wiring pattern.

In FIG. 2a, an insulating resin layer is formed on the core substrate 1. A general-purpose Probicoat 5000 (manufactured by Nippon Paint Co., Ltd.) was used as the insulating resin liquid, and the coating method was curtain coating. An insulating layer was formed with a standard thickness of 35 μm.

In FIG. 2b, a thin film conductor layer 5 is formed. A copper thin film conductor layer was formed by general electroless plating. next,
FIG. 2c has formed a photosensitive resist layer. As the photosensitive resist, a dry film was used to form a layer by pasting by a usual method. The dry film uses a general-purpose product name Fotec (manufactured by Hitachi Chemical Co., Ltd.). Chemical polishing was performed as a pretreatment. The conditions are 250 g / L sodium persulfate,
The surface of the thin film conductor layer was chemically polished by immersing it in an aqueous solution of 350 g / L sulfuric acid at a liquid temperature of 30 ° C. for 40 seconds.

In FIG. 2d, a pattern layer for forming a desired pattern is formed on the photosensitive resist layer by a photoprocess using a photomask by a light exposure process and a development process. Exposure condition is 40 mj / cm
I worked on condition 2. In the developing step, development was performed under the condition of overdevelopment. Development conditions are 1 wt% Na2Co3
Solution, liquid temperature 30 ° C., development time 30 seconds. The standard time for specifications is 15 seconds.

FIG. 2d shows a thin film conductor layer 5 and a resist layer 1.
Plasma is applied to the two surfaces. Removal of foreign matter such as resist residue remaining on the exposed surface, optimization of the shape of the resist, depletion of the film thickness of the resist end thin film portion of the correction hem portion 23, and removal of the top 22 The optimum resist shape was obtained by eliminating the corners at the surface corners.

In FIG. 2e, the plating layer 7 was formed by electrolytic plating.

In FIG. 2f, the exposed surface of the thin film conductor layer 5 was removed by soft etching.

FIG. 2g shows a wiring pattern layer in which a wiring pattern formed by electrolytic copper plating is formed on the surface of an insulating resin layer, and the top 22 of the pattern has a wide surface width and which has an inverse taper in the cross-sectional shape. Formed. The above is the manufacturing method for forming the wiring pattern in the manufacturing of the semiconductor device substrate.

[0073]

According to the method of the present invention, the surface width of the insulating layer between the patterns is wider than before and cleaning is easier, so that migration such as dirt is eliminated and the width of the top portion of the pattern formed by plating is eliminated. Is widened, and the problems of long-term reliability and pattern width can be solved.

[Brief description of drawings]

1A to 1H are side sectional views illustrating a manufacturing process of the present invention.

2A to 2G are side sectional views showing an embodiment of the present invention.

3A to 3E are side sectional views showing an embodiment of the pattern manufacturing method of the present invention.

4A to 4G are side sectional views illustrating a conventional manufacturing process.

5A to 5E are side cross-sectional views illustrating a conventional manufacturing process.

[Explanation of symbols]

1 ... Insulation board (core board) 2 ... Wiring layer (conductor layer) 3 ... Insulating resin layer 4 ... Hole for via 5 ... Thin film conductor layer 6 ... Through hole for through hole 7 ... Plating layer (copper plating layer) 8 ... Wiring pattern layer 9 ... through hole 10 ... Solder resist layer 11 ... Beer hall 12 ... Photosensitive resist (layer) 13 ... Insulating (resin) film 14 ... Adhesive layer 15 ... Sprocket Hall 16 ... Opening 17 ... Hole for through hole 18 ... Conduction hole 19 ... First wiring pattern (layer) 20 ... Second wiring pattern (layer) 21 ... Bottom of pattern (conductor layer) 22 ... Top of pattern (conductor layer) 23 ... Bottom of pattern (conductor layer) 24 ... Width of pattern (conductor layer) 25 ... Gap between patterns (conductor layers)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H05K 3/18 H01L 23/12 QF term (reference) 5E343 AA02 AA12 BB13 BB24 BB71 CC62 DD33 DD43 EE01 EE13 EE17 EE36 ER11 FF23 GG01 GG06 GG08 5E346 AA12 AA15 AA32 AA43 AA51 BB15 CC32 DD23 DD24 DD25 DD33 DD44 DD47 EE33 EE35 GG17 GG18 GG28 HH13 HH21

Claims (3)

[Claims] 1. In a process of forming a wiring pattern in manufacturing a multilayer print using a build-up method,
(A) a step of forming an insulating resin layer, (b) a step of forming a thin film conductor layer by plating over the entire surface of the insulating resin layer, and (c) photosensitivity up to the entire surface of the thin film conductor layer. A step of forming a resist layer, and (d) using a photomask on the photosensitive resist layer by a photoprocess method,
A step of forming a desired pattern, (e) a step of performing plasma treatment on the entire surface from the resist layer having the pattern to the surface of the thin film conductor layer, and (f) electrolytic copper plating on the entire surface. A semiconductor device comprising: a step of: (g) removing the resist layer; and (h) removing the thin film conductor layer exposed on the surface by a soft etching method. Substrate manufacturing method. 2. A step of forming a wiring pattern in the manufacturing of a multilayer print using a build-up method,
(A) a step of forming an insulating resin layer, (b) a step of forming a photosensitive resist layer up to the entire surface of the insulating resin layer, and (c) a photomask formed on the photosensitive resist layer by a photoprocess method. And a step of forming a desired pattern by using
A step of performing a plasma treatment on the entire surface up to the surface of the insulating resin layer, (e) a step of electroless copper plating on the entire surface, and (f) a step of peeling the resist layer A method of manufacturing a substrate for a semiconductor device, comprising: 3. A step of forming a wiring pattern in the production of a film carrier, wherein the step (a) forms a photosensitive resist layer up to the entire surface of the insulating resin film layer, and (b) the photosensitive resist layer. A step of forming a desired pattern using a photomask by a photo process method, and (c) a step of performing plasma treatment on the entire surface from the resist layer having the pattern to the surface of the insulating resin layer, A method for manufacturing a substrate for a semiconductor device, which comprises performing the steps of (d) electroless plating on the entire surface and (e) removing the resist layer.