JP3143408B2 - Manufacturing method of printed wiring board - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a printed wiring board by using a glass substrate on which a mask pattern is formed as an exposure mask material.
It is possible to suppress the dimensional change of the mask material for exposure, thereby preventing the positional deviation of the via hole, the plating resist pattern, and the solder resist pattern , and furthermore, the mask pattern drawn on the glass substrate.
By expanding the application beyond the design value, the photosensitive resin layer
Even if the resin shrinks due to cure,
The present invention relates to a method for manufacturing a printed wiring board capable of manufacturing a final product of the method.

[0002]

2. Description of the Related Art In recent years, so-called build-up multilayer wiring boards have been receiving attention due to a demand for higher density of the multilayer wiring boards. This build-up multilayer wiring board is manufactured by a method disclosed in, for example, Japanese Patent Publication No. 4-55555. That is, an adhesive for electroless plating made of a photosensitive resin is applied onto the core substrate, dried, exposed, and developed to form an interlayer insulating material layer having a via hole opening. Next, after roughening the surface of the interlayer insulating material layer by treatment with an oxidizing agent or the like, the photosensitive resin layer is exposed and developed on the roughened surface to provide a plating resist, and then, on the resist non-formed portion. A conductor circuit pattern including via holes is formed by electroless plating. By repeating such a process a plurality of times, a multilayered build-up wiring board can be obtained.

[0003]

[SUMMARY OF THE INVENTION However, in the conventional multilayer printed wiring board, which uses a resin film as a mask film to be used for exposing the photosensitive resin, the linear thermal in accordance Ma scan click film The expansion coefficient is 1.8 × 10 ^-5 / ° C, and the humidity expansion coefficient is 1.0 × 10 ^-5
/ ° C., and therefore, dimensional changes are likely to occur due to ambient temperature and humidity. As a result, there is a problem that the positions of the via holes and the positions of the plating resist patterns are shifted.

In addition to a multilayer printed wiring board, a solder resist layer is generally provided on the surface layer of the printed wiring board to protect other circuit parts when forming a solder body such as a solder bump. is there. At this time, in the solder resist layer, an opening for forming a solder body by exposing and developing the photosensitive resin layer is provided. Exposure of the photosensitive resin layer is performed in the same manner as described above. Therefore, in this case as well, the above-described dimensional change due to temperature and humidity occurs, and the position of the opening for forming the solder body is shifted. It remains.

[0005] The present invention has come to solve the conventional problems, by using a glass substrate Ma scan click pattern is formed as an exposure mask material, dimensional change of the exposure mask material Can be suppressed,
Can be prevented via holes, plating resist pattern, the positional deviation of the solder resist pattern with
Yes, and the mask pattern drawn on the glass substrate
By expanding beyond the design value, the photosensitive resin layer
Even if the shrinkage occurs,
An object of the present invention is to provide a method for manufacturing a printed wiring board capable of manufacturing a final product .

[0006]

Means for Solving the Problems A method of manufacturing a printed wiring board according to claim 1 for achieving the above object, a conductor circuit
Forming a photosensitive resin layer on the resin substrate on which
The glass substrate on which the mask pattern is drawn
And develop it to open via holes.
An opening is provided, and the photosensitive resin layer is cured by heating.
Conductor circuits and via holes are formed on the photosensitive resin layer
In the method of manufacturing a printed wiring board, the glass substrate
The mask pattern drawn on the
It becomes.

[0007] Here, in the previous SL Manufacturing method, not hygroscopic for photomask is glass, and the linear expansion coefficient of 8.5 × 10 ^-6 / ℃ soda lime glass, quartz glass 5.0 Since it is as small as ^10-7 / C, there is almost no dimensional change due to humidity and temperature. As a result, no displacement occurs in the mask pattern or the resist pattern, and as a result, the via hole position, the plating resist pattern position,
There is no shift in the solder resist pattern position. Also, since there is almost no dimensional change due to humidity and temperature, there is no need to replace the mask, which is suitable for mass production.

[0008] As a photomask, for example,
Mask pattern drawn on a glass substrate
Is desirable. The glass substrate on which the mask pattern is drawn by the light-shielding ink has a mask pattern layer drawn by the light-shielding ink of about 1 to 10 μm on the surface of the glass substrate (see FIG. 24A). Specifically, the mask pattern layer 1 is formed on the surface of the glass substrate 13 shown in FIG.
4 is formed of light-shielding ink, and it is desirable to irradiate light from the opposite side of the mask pattern layer 14 when performing exposure, so that the surface of the glass substrate 13 opposite to the mask pattern layer 14 is reflected. The prevention film 15 may be formed. Further, the mask pattern layer 14 may be covered with a light-transmitting protective layer 16. The mask pattern layer 14 is formed by applying a photosensitive light-shielding ink composition to the glass substrate 13, scanning a laser beam on the composition, drawing a pattern, and developing the pattern with an acid or alkali.
And

The glass substrate on which the mask pattern is drawn by the metal layer is 100 to 1000
There is a mask pattern layer made of a metal layer of about Å (see FIG. 24B). Specifically, FIG.
In the glass substrate 13 shown in FIG.
Desirably, it is made of a chromium layer. This is because a sharp pattern can be formed by etching with an acid or the like, and oxidation is difficult. Further, an oxide film may be formed on the surface of the chromium layer.

The glass used as the glass substrate is preferably soda lime glass or quartz glass having a thickness of 1 to 10 mm. The linear thermal expansion coefficient of soda lime glass is 8.5 × 10 ⁻⁶ / ° C., which is small and inexpensive. Further, the linear thermal expansion coefficient of quartz glass is extremely small at 5.0 × 10 ⁻⁷ / ° C.

[0011] Further, a more desirable embodiment of the present invention is described in claims 2-6 .

According to a second aspect of the present invention, a conductor circuit is provided.
Forming a photosensitive resin layer on the resin substrate on which the path is formed;
Glass substrate on which photosensitive resin layer is masked
And develop it to form via holes.
Open the opening, heat cure the photosensitive resin layer, and then
Conductor circuits and via holes are formed on the photosensitive resin layer.
Repeating the steps of forming the photosensitive tree at least twice.
When laminating the resin layer and the conductor circuit , each photosensitive resin
Layer draws a mask pattern that is larger than the design value
Exposure through a broken glass substrate and drawing on the glass substrate
The magnification of the mask pattern to the design value on the surface
The smaller the closer, the smaller

[0013] Further, as described in claim 4 ,
Forming a photosensitive resin layer on a thermoset resin substrate
Then, the photosensitive resin layer is applied to the mask on which the mask pattern is drawn.
Exposure through a glass substrate to form a resist pattern
In the method for manufacturing a printed wiring board, the glass substrate
The drawn mask pattern is enlarged beyond the design value.
Become.

Further, as described in claim 5 ,
Place the adhesive on the thermosetting adhesive layer for electroless plating.
A photosensitive resin layer for forming a resist is provided.
The glass substrate on which the mask pattern is drawn
Through the substrate to form a plating resist pattern.
Printing process that repeats the process of applying
In the manufacturing method of wire plate, for forming each plating resist
The photosensitive resin layer has a mask pattern that is larger than the design value.
Exposed through the glass substrate on which
Expansion of the mask pattern drawn on the
The larger the ratio is, the smaller it is near the surface.

According to the first and second aspects of the present invention, the photosensitive resin for forming the interlayer resin insulating layer is cured by heating (post-baking) to improve the basic resistance. Since the electroless plating solution is strongly basic, such heating is required.
However, the heating causes the resin substrate and the photosensitive resin to cure and shrink, and the dimensions of the final product become smaller than the design values. If the design values are not met, semiconductor components such as IC chips cannot be mounted, and they do not function as printed wiring boards.

Further, when such a photosensitive resin is formed into a multilayer, the resin substrate and the lower photosensitive resin are also heated at the same time, and the resin substrate and the lower photosensitive resin are further cured and shrunk. The dimensions of the final product will be smaller than the design values . When the photosensitive resin is multilayered, polishing may be performed in order to smooth the surface, but the dimensions of the resin substrate become larger than designed values due to the polishing.

For example, FIG. 25 is a diagram showing how the size of a resin substrate changes when a printed wiring board is multilayered. X indicates the dimensional change of the substrate in the X-axis direction, and Y indicates the dimensional change in the Y-axis direction. Denotes a stage in which the resin substrate is buffed, denotes a stage immediately before the innermost (1-2) photosensitive resin layer is applied, denotes a stage immediately before forming the second plating resist layer, and denotes a next layer (2-3). The step immediately before applying the photosensitive resin layer of (layer) is a step immediately before forming the third layer plating resist. From FIG. 25, the dimensional change is increased by polishing, the size is reduced by heat curing, and finally -0.025 with respect to the initial substrate size.
It can be seen that a% shift occurs.

As described above, the dimensions of the final product must be adjusted to the design values. To this end, a mask pattern larger than the design values is drawn on the glass substrate in anticipation of curing shrinkage. If the mask pattern is larger than the designed value, heat curing after exposure and development (post bake)
Thus, even if the resin substrate or the photosensitive resin shrinks, it can be made to converge to the design value. The mask pattern enlarged for such a design value must be drawn on a glass substrate. Even if a mask pattern is drawn on a resin film, the size of the film changes due to moisture absorption or temperature change, and changes to the size of the mask pattern. This is because changes must be considered.

In the present invention, a glass substrate is used, and since the size of the glass substrate does not change due to moisture absorption or a change in temperature, a change in the size of the mask pattern is extremely small. If the mask pattern is enlarged in consideration of the above, it is possible to reliably converge to the design value.

Further, when the photosensitive resin is multilayered,
By examining in advance how much the resin substrate and the photosensitive resin layer will cure and shrink due to the heating of each photosensitive resin layer, and drawing the pattern at an enlargement ratio commensurate with the shrinkage, the final design value Can be converged. The enlargement ratio with respect to the design value increases as the pattern exposes the photosensitive resin layer in the inner layer of the printed wiring board, and decreases as the pattern exposes the photosensitive resin layer closer to the surface layer. This is because, when a photosensitive resin layer close to the surface layer is exposed, curing shrinkage proceeds and the size of the resin substrate approaches the design value, so that the enlargement ratio decreases. It is desirable that the mask pattern is enlarged by 0.001 to 0.100% larger than a design value. If the printed wiring board of a single-sided three-layer (double-sided six layers), the curing shrinkage of about 0.03%, in the case of the printed wiring board of a single-sided four-layer (double-sided 8 layers), about 0.06%,
In the case of a printed wiring board with 5 layers on one side (10 layers on both sides),
It is necessary to expect a cure shrinkage of about 0.100%.

[0021] In the present invention of claim 4 to 6, and a plating resist and a solder resist is formed in the thermosetting treated substrate. For example, the plating resist is formed directly on the adhesive layer for electroless plating in the full additive process according to claim 5 , and the adhesive layer for electroless plating in the semi-additive process according to claim 6. Formed on a thinly formed electroless plating film, and in any case, heat-cured adhesive for electroless plating (post bake)
To improve base resistance.

However, the heating causes the resin substrate to cure and shrink, and the dimensions of the final product become smaller than designed values. If the design values are not met, semiconductor components such as IC chips cannot be mounted, or connection failure of via holes may be caused, so that the printed circuit board does not function.

Further, when such an adhesive layer for electroless plating is multilayered, the resin substrate is also heated at the same time, so that the resin substrate is further cured and shrunk, and the dimensions of the final product are more than the design values. It will be smaller. In some cases, polishing is performed to smooth the resin substrate, but the dimensions of the resin substrate become larger than designed values due to the polishing.

As described above, the final product dimensions must be adjusted to the design values. To this end, a mask pattern larger than the design values is drawn on the glass substrate in consideration of the curing shrinkage as described above. If the mask pattern is larger than the design value, it can be made to converge to the design value even if the resin substrate shrinks due to heat curing (post-baking) of the adhesive layer for electroless plating. Further, as described above, the mask pattern must be drawn on the glass substrate.

Further, when the adhesive for electroless plating is multilayered, it is necessary to examine in advance how much the resin substrate will cure and shrink by heating, and draw a pattern at an enlargement ratio commensurate with the shrinkage. Thereby, it is possible to finally converge to the design value. The enlargement ratio with respect to the design value increases with the pattern for forming the plating resist in the inner layer of the printed wiring board, and decreases with the pattern for forming the plating resist closer to the surface layer. This is because, when a plating resist close to the surface layer is formed, the shrinkage on curing progresses and the size of the resin substrate approaches the design value, so that the enlargement ratio decreases. The mask pattern is 0.01 to the design value.
Desirably, it is enlarged by 0.100%. In the case of a printed wiring board having three layers on one side (six layers on both sides), 0.0
In the case of a printed wiring board having about 4% of curing shrinkage on one side and 4 layers (8 layers on both sides), about 0.06%, and in the case of a printed wiring board having 5 layers on one side (10 layers on both sides), 0.1
It is necessary to allow for cure shrinkage of about 00%.

In the method for manufacturing a printed wiring board according to claims 1 to 7 of the present invention, the enlargement ratio of the mask pattern is
It may be different in the X and Y directions. Claim 2
In the manufacturing methods of the printed wiring boards of Nos. 5 and 6 , in principle, the enlargement ratio with respect to the design value of the mask pattern drawn on the glass substrate is reduced as it approaches the surface layer.
When performing polishing or the like, since the substrate is stretched, the enlargement ratio with respect to the design value of the mask pattern closer to the surface layer, the mask used to expose the photosensitive resin layer on the inner layer side of the mask pattern A pattern larger than the magnification of the pattern can be used.

The printed wiring board applied to the manufacturing method is not particularly limited. For example, when a plating resist is formed, a substrate having an electroless plating adhesive layer formed thereon, an electroless plating adhesive A substrate or the like in which an electroless plating film is formed on an agent layer can be applied. When a solder resist is formed, a substrate provided with a conductor layer serving as a solder pad is applied.

Further, with respect to the photosensitive resin layer, it is desirable to use a photosensitive adhesive layer for electroless plating as the photosensitive resin layer provided with openings for forming via holes. This photosensitive electroless plating adhesive is obtained by dispersing heat-resistant resin particles soluble in a cured acid or oxidizing agent in an uncured photosensitive resin hardly soluble in an acid or oxidizing agent. Optimal. By treating with an acid or an oxidizing agent, the heat-resistant resin particles are dissolved and removed, and a roughened surface composed of an octopus-shaped anchor can be formed on the surface.

In the above-mentioned adhesive for photosensitive electroless plating, the cured heat-resistant resin particles are preferably:
Heat-resistant resin powder having an average particle size of 10 μm or less, agglomerated particles obtained by aggregating heat-resistant resin powder having an average particle size of 2 μm or less, heat-resistant powder resin powder having an average particle size of 2 μm to 10 μm and an average particle size of 2 μm or less Mixture with a heat-resistant resin powder having a mean particle size of 2 to 10 μm, and a pseudo-particle obtained by adhering at least one of a heat-resistant resin powder having a mean particle size of 2 μm or less and an inorganic powder to the surface of the heat-resistant resin powder having a mean particle size of 2 to 10 μm. It is desirable to use at least one selected from particles. This is because they can form more complex anchors.

As a photosensitive resin composition for forming a plating resist or a solder resist, it is particularly desirable to use a composition comprising an acrylate of cresol novolak or a phenol novolak type epoxy resin and an imidazole curing agent. Commercially available products can also be used. When forming a solder resist,
Dyes such as phthalocyanine green, alumina, silica particles and the like may be added.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a method for manufacturing a printed wiring board according to the present invention will be described with reference to the drawings based on an embodiment in which the method for manufacturing a printed wiring board according to the present invention is embodied with respect to a semi-additive method. . It goes without saying that a full additive method may be employed as the manufacturing method.

(1) First, a wiring board PC having an inner layer copper pattern (conductor circuit) 2 formed on the surface of a core substrate 1 is manufactured (FIGS. 1 and 2). The copper pattern 2 is formed on the core substrate 1 by etching a copper-clad laminate, or a glass epoxy substrate, a polyimide substrate,
An adhesive layer for electroless plating is formed on a substrate such as a ceramic substrate or a metal substrate, and the surface of the adhesive layer is roughened to a roughened surface. There is a method in which after formation and electrolytic plating, a plating resist is removed and etching treatment is performed to form a conductor circuit composed of an electrolytic plating film and an electroless plating film. still,
A through hole H is formed at a predetermined position of the wiring board PC, and a copper pattern 2 is formed on the inner surface of the through hole H and the periphery of the opening.

It is preferable that a roughening layer is provided on the inner wall of the through hole, the side surface of the land of the through hole, and the side surface of the conductor circuit 2. By providing the roughened layer on the side surface, the adhesion with the filling resin 18 described later can be improved, and the heat cycle causes the boundary between the resin 18 and the conductor circuit 2 as a starting point to be generated in the interlayer insulating layer on the boundary. This is because cracking can be suppressed.

Next, the resin 18 is filled between the inside of the through hole H and the conductor circuit 2 of the wiring board PC to ensure smoothness (FIG. 3). Further, a roughened layer 5 made of copper-nickel-phosphorus is formed on the surface of the lower conductor circuit 2 in the wiring board PC (FIG. 4). The roughened layer 5 is formed by electroless plating. As the plating solution composition, the copper ion concentration, the nickel ion concentration, and the hypophosphite ion concentration were 2.2 × 10 ^{−2 to} 4.1 × 10 ⁻² mol, respectively.
/ L, 2.2 × 10 ^{−3 to} 4.1 × 10 ⁻³ mol / l,
Desirably, it is 0.20 to 0.25 mol / l.

This is because the crystal structure of the film deposited in this range has a needle-like structure, and thus has an excellent anchor effect. A complexing agent or an additive may be added to the electroless plating bath in addition to the above compounds.

Other methods of forming the roughened layer 5 include the above-described oxidation-reduction treatment and a method of forming a roughened surface by etching the copper surface along grain boundaries. In particular,
As an oxidation bath (blackening bath), NaOH (10 g / l),
NaClO2 (40 g / l) and Na3PO4 (6 g / l)
l), and NaOH (1
(0 g / l) and NaBH4 (6 g / l).

The copper pattern 2 on the front surface and the back surface is electrically connected through a through hole H formed in the wiring board PC.

(2) Next, a photosensitive resin layer 6 is formed on the surface of the wiring board PC manufactured in (1) (FIG. 5). At this time, it is particularly preferable to use the above-mentioned adhesive for photosensitive electroless plating as the photosensitive resin layer 6 in the manufacturing method of the present embodiment.

(3) After drying the adhesive layer 6 for photosensitive electroless plating formed as described above, the glass substrate 13 on which the above-described circular pattern (mask pattern) 14 for forming via holes is drawn. Then, the circular pattern 14 is placed so as to be in close contact with the adhesive layer 6 for photosensitive electroless plating, exposed (FIG. 6), and developed (FIG. 7). As a result, a via hole opening B is formed. Although FIG. 6 shows a state where the glass substrate 13 is placed on the upper surface of the wiring board PC, the same processing is performed on the lower surface of the wiring board PC.

(4) Next, the epoxy resin particles present on the surface of the cured adhesive layer 6 for photosensitive electroless plating are dissolved and removed with an acid or an oxidizing agent to roughen the surface of the adhesive layer ( (FIG. 8).

Here, the acid includes phosphoric acid, hydrochloric acid,
Although there are inorganic acids such as sulfuric acid and organic acids such as formic acid and acetic acid, it is particularly preferable to use organic acids. This is because when the roughening treatment is performed, the metal conductor layer exposed from the via hole is hardly corroded.

On the other hand, it is desirable to use chromic acid and permanganate (such as potassium permanganate) as the oxidizing agent.

(5) Next, a catalyst nucleus is applied to the wiring board PC whose surface of the adhesive layer 6 has been roughened. To provide the catalyst core,
It is desirable to use a noble metal ion or a noble metal colloid, and generally, palladium chloride or a palladium colloid is used. Note that it is desirable to perform a heat treatment to fix the catalyst core. Palladium is preferred as such a catalyst core.

(6) Next, electroless plating is performed on the surface of the adhesive layer 6 for electroless plating, and the electroless plating film 3 is formed on the entire roughened surface (FIG. 9). The thickness of the electroless plating film 3 is 1
５5 μm, more preferably 2-3 μm.

(7) Subsequently, a photosensitive resin film (dry film) 19 is laminated on the electroless plating film 3 formed as described above, and the glass substrate 13 on which the plating resist pattern 14 is drawn is removed. The mask pattern 14 is placed so as to be in close contact with the photosensitive electroless plating adhesive layer 6 via the photosensitive resin film 19, and is further exposed and developed (FIG. 10). Thereby, a plating resist layer 7 is formed on the electroless plating film 3 (FIG. 1).
1). Although FIG. 10 illustrates the processing state on the upper surface of the wiring board PC, the same processing is performed on the lower surface of the wiring board PC.

(8) Next, the electrolytic plating film 4 is formed on the portion where the plating resist is not formed (the portion where the plating resist layer 7 is not formed), and the conductor circuit and the via hole 10 are formed.
0 is provided (FIG. 12). Here, it is desirable to use copper plating as the electroless plating.

(9) Further, after removing the plating resist layer 7, a mixed solution of sulfuric acid and hydrogen peroxide, sodium persulfate,
The electroless plating film 3 is dissolved and removed with an etching solution such as ammonium persulfate to form an independent conductor circuit (FIG. 1).
3). Further, residual Pd catalyst nuclei on the exposed roughened surface are removed with chromic acid.

(10) Subsequently, the roughened layer 5 is formed on the surface of the via hole 100 and the conductor pattern 4 (FIG. 14).
Here, as a method of forming the roughened layer 5, there are an etching process, a polishing process, an oxidation-reduction process, and a plating process. The oxidation-reduction treatment includes NaOH (10 g / l), NaClO2
(40 g / l), Na3 PO4 (6 g / l) in an oxidation bath (blackening bath), NaOH (10 g / l), NaBH4 (5
g / l) is used as a reducing bath.

When forming the roughened layer 5 of a copper-nickel-phosphorus alloy layer, it is deposited by electroless plating. As an electroless plating solution for this alloy, copper sulfate 1-4
0 g / l, nickel sulfate 0.1-6.0 g / l, citric acid 10-20 g / l, hypophosphite 10-100 g / l
1, boric acid 10 to 40 g / l, surfactant 0.01 to 1
It is desirable to use a plating bath having a liquid composition of 0 g / l.

(11) Next, an adhesive layer 6 for photosensitive electroless plating is formed as a photosensitive resin layer on the wiring board PC obtained by the above processing (FIG. 15).

(12) Further, the above steps (3) to (9) are repeated to provide a further upper layer conductor circuit, and the conductor layer 10 functioning as a solder pad and the via hole 100 are formed (FIGS. 16 to 16). (FIG. 19).

(13) Then, if necessary, a roughened layer 5 is provided on the surface of via holes, conductor layers, lands and the like (FIG. 2).
0). The method of forming the roughened layer 5 is the same as the method described in (10).

(14) Next, a solder resist composition is applied to both sides of the printed wiring board PC after the process (12) (FIG. 21). When applying the solder resist layer 8 on both sides of the printed wiring board PC, the printed wiring board PC is sandwiched between a pair of application rolls of a roll coater in a state of being vertically erected, and is transported upward from below. It is desirable that the solder resist composition is simultaneously applied to both surfaces of the wiring board PC. The reason for this is that the current basic specifications of the printed wiring board PC are on both sides, and the curtain coating method (a method in which the resin is flowed from top to bottom like a waterfall and the substrate is passed through the "curtain" of this resin and applied) This is because only one side can be applied. When the viscosity of the solder resist composition is set to 1 to 10 Pa · s at 25 ° C., the composition does not flow even when the substrate is applied vertically and the transfer is good.

(15) Next, the coating film of the solder resist composition is dried, and the glass substrate 13 having the opening drawn as a circular pattern 14 is formed on the coating film with the side on which the circular pattern 14 is drawn as the solder resist layer. 8 and exposed and developed to form an opening exposing the pad portion (FIG. 21). The lands are exposed on the opposite side of the printed wiring board PC. The solder resist layer 8 having the opening thus formed is further heated to 80 ° C. to 15 ° C.
Cured by heat treatment at 0 ° C. for 1 to 10 hours. As a result, the solder resist pattern layer 8 having the opening is in close contact with the roughened layer provided on the surface of the conductor circuit.

(16) Next, the nickel layer 11 and the gold layer 1 are formed on the solder pads and lands exposed from the openings.
2 is formed.

(17) Next, the solder bodies 9 and 90 are supplied onto the solder pad portions exposed from the openings. (Figure 2
2). As a method of supplying the solder bodies 9 and 90, a solder transfer method or a printing method can be used. Here, in the solder transfer method, a solder foil is bonded to a prepreg, and the solder foil is etched leaving only a portion corresponding to an opening to form a solder pattern, thereby obtaining a solder carrier film. After applying a flux to the solder resist opening of the substrate, the solder pattern is laminated so as to be in contact with the pad, and this is heated and transferred.

On the other hand, the printing method is a method in which a metal mask having a through hole at a position corresponding to a pad is placed on a substrate, and a solder paste is printed and heated.

The printed wiring board PC is manufactured by the method described above.

[0059]

Embodiments will be described below with reference to embodiments.

(Examples) (1) Glass epoxy resin or BT having a thickness of 0.6 mm
Core substrate 1 made of (bismaleimide triazine) resin
A copper-clad laminate obtained by laminating a 18 μm copper foil on both sides of the substrate was used as a starting material. The copper foil of the copper-clad laminate was etched in a pattern according to a conventional method, drilled, and subjected to electroless plating to form an inner conductor circuit 2 and through holes H on both surfaces of the substrate. The above-described oxidation (blackening) -reduction treatment was performed on the inner conductor circuit, the through hole, and the inner wall thereof on the substrate to roughen the entire surface.

Further, a through hole H is provided between the lower conductor circuits 2.
The inside was filled with a bisphenol F type epoxy resin. After the bisphenol F type epoxy resin is cured, it is polished by belt sander and buffing to obtain bisphenol F
The mold epoxy resin and the roughened layer formed by the oxidation (blackening) -reduction treatment were removed to expose the upper surface of the inner conductor circuit and the land upper surface of the through hole. The distance between the holes provided in the BT resin substrate was measured in advance, and the elongation of the resin substrate before and after polishing was measured (in FIG. 25). The elongation of the substrate is about 0.01% in the X direction and about 0.1% in the Y direction by the two polishing operations.
007%.

(2) The substrate on which the inner layer copper pattern has been formed in the above (1) is washed with water, dried, and then subjected to acidic degreasing and soft etching, followed by treatment with a catalyst solution comprising palladium chloride and an organic acid. To provide a Pd catalyst,
After activating this catalyst, copper sulfate 8 g / l, nickel sulfate 0.6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l, boric acid 31 g / l, surfactant 0.1 g / l.
Plating was performed in an electroless plating bath consisting of 1 g / l and pH = 9 to form a 2.5 μm thick roughened layer 5 (uneven layer) of Cu—Ni—P alloy on the entire surface of the copper conductor circuit. . The roughened layer of oxidation-reduction present on the side surface of the conductor circuit, the side surface of the land of the through hole, and the inner wall of the through hole is omitted for simplification.

Further, 0.1 mol / l tin borofluoride-
It was immersed in an electroless tin displacement plating bath made of a 1.0 mol / l thiourea solution at 50 ° C. for 1 hour to provide a 0.3 μm thick tin displacement plating layer on the surface of the roughened layer 5.

(3) 35% by weight of a 25% acrylate of a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight 2500) dissolved in DMDG (diethylene glycol dimethyl ether), polyether sulfone (P
ES) 12 parts by weight, imidazole curing agent (Shikoku Chemicals,
Trade name: 2E4MZ-CN) 2 parts by weight, photosensitive monomer, caprolactone modified tris (acryloxyethyl) isocyanurate (Toagosei Co., trade name: Aronix M325)
4 parts by weight, 2 parts by weight of benzophenone as a photoinitiator (manufactured by Kanto Kagaku), 0.2 parts by weight of Michler's ketone as a photosensitizer (manufactured by Kanto Kagaku), and the average particle size of epoxy resin particles based on this mixture 10.3 μm 10.3
Parts by weight and 3.09 parts by weight of an average particle diameter of 0.5 μm were mixed, and then NMP (normal methylpyrrolidone) was added to 3 parts by weight.
The mixture is mixed while adding 0 parts by weight, the viscosity is adjusted to 7 Pa · s by a homodisper stirrer, and then kneaded with three rolls to obtain a photosensitive adhesive solution (interlayer resin insulating material).

(4) The photosensitive adhesive solution obtained in the above (3) is applied to both surfaces of the substrate after the treatment in the above (2) using a roll coater, and left in a horizontal state for 20 minutes. Then, drying was performed at 60 ° C. for 30 minutes to form an adhesive layer 6 having a thickness of 60 μm.

(5) A circular pattern (mask pattern) 14 having the same shape as the via hole is drawn on both surfaces of the substrate on which the adhesive layer 6 has been formed in the above (4) with light-shielding ink having a thickness of 5 μm. The soda lime glass substrate 13 was placed with the side on which the circular pattern was drawn in close contact with the adhesive layer 6, and was exposed to ultraviolet light. The mask pattern is formed to be 0.03% larger than the design value.

(6) The exposed substrate was spray-developed with a DMTG (triethylene glydimethyl ether) solution to form an opening serving as a 100 μmφ via hole in the adhesive layer. Further, the substrate was exposed at 3000 mJ / cm2 with an ultra-high pressure mercury lamp, and was exposed at 100 ° C. for 1 hour.
After that, by heating at 150 ° C for 5 hours,
An adhesive layer having excellent dimensions corresponding to a photomask film and having an opening (opening for forming a via hole) and having a thickness of 50 μm was formed. Note that the roughened layer is partially exposed in the opening serving as the via hole.

(7) The substrate in which the openings for forming via holes were formed in (5) and (6) was immersed in chromic acid for 2 minutes to dissolve and remove the epoxy resin particles present on the surface of the adhesive layer. The surface of the adhesive layer was roughened, then immersed in a neutralizing solution (manufactured by Shipley), and then washed with water.

(8) A palladium catalyst (manufactured by Atotech) is applied to the substrate that has been subjected to the surface roughening treatment (roughening depth: 5 μm) in the above (7), so that the adhesive layer and the opening for the via hole are formed. Catalyst nuclei were provided on the surface. At this stage (FIG. 25), about -0.009% in the X direction and about -0.002% in the Y direction with respect to the initial size of the resin substrate.
A dimensional change of a degree is shown. Therefore, the dimensional change is about 0.02%. Therefore, a via hole opening formed by a mask pattern larger than the design value by 0.03% is larger by 0.01% than the design value.

(9) The substrate was immersed in an electroless copper plating bath having the following composition to form an electroless copper plating film 3 having a thickness of 3 μm on the entire rough surface.

Electroless plating solution EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l Electroless plating conditions 70 ° C. 30 minutes at temperature (10) Commercially available photosensitive resin film (dry film)
Is adhered to the electroless copper plating film, and a portion where the plating resist is not formed is drawn as a mask pattern 14 by a chromium layer having a thickness of 600 Å.
The soda lime glass substrate 13 having a thickness of 110 mm is adhered to the photosensitive resin film on the side on which the chromium layer is formed.
Exposure was performed at J / cm ² and development processing was performed with 0.8% sodium carbonate to provide a plating resist pattern 7 having a thickness of 15 μm. The mask pattern is formed to be 0.008% larger than the designed value.

(11) Next, electrolytic copper plating was performed under the following conditions to form an electrolytic copper plating film 4 having a thickness of 15 μm.

Electrolytic plating solution Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (captoside GL, trade name, manufactured by Atotech Japan) 1 ml / l Electroplating conditions Current density 1 A / dm ² hours 30 minutes Temperature Room temperature (12) Plating resist After stripping and removing 7 with 5% KOH, etching is performed with a mixed solution of sulfuric acid and hydrogen peroxide to dissolve and remove the electroless plating film 3 to form a 18 μm thick film composed of the electroless copper plating film 3 and the electrolytic copper plating film 4. Was formed. Furthermore, it was immersed in 800 g / l of chromic acid for 1 to 2 minutes to remove residual Pd catalyst nuclei.

(13) The substrate on which the conductor circuit was formed was coated with 8 g / l of copper sulfate, 0.6 g / l of nickel sulfate, and 15 g of citric acid.
g / l, sodium hypophosphite 29 g / l, boric acid 31
g / l, 0.1 g / l of a surfactant, and immersed in an electroless plating solution having a pH of 9 and a thickness of 3 μm on the surface of the conductor circuit.
A roughened layer 5 made of copper-nickel-phosphorus was formed.

The roughened layer 5 is formed by EPMA (X-ray fluorescence analyzer)
As a result, Cu (98 mol%) and Ni (1.
5 mol%) and P (0.5 mol%).

Then, the substrate is washed with water.
Immersion for 1 hour at 50 ° C. in an electroless tin displacement plating bath composed of 1 mol / l tin borofluoride-1.0 mol / l thiourea solution, and a 0.3 μm-thick tin displacement plating layer on the surface of the roughened layer Was formed. At this stage (FIG. 25), the resin substrate is about -in both the X and Y directions with respect to the initial size.
It shows a dimensional change of 0.010%.

(14) By repeating the steps (4) to (13), a solder pad was further formed, and a roughened layer 5 was provided on the surface of the solder pad. However, the tin-substituted plating layer was not formed on the roughened layer surface. The mask pattern for forming the via hole is formed to be 0.003% larger than the designed value. The mask pattern for forming the plating resist has a size as designed.

The stage immediately before the formation of the plating resist (FIG. 2)
In (5), the resin substrate shows a dimensional change of -0.025% in the X direction and -0.020% in the Y direction with respect to the size of the first substrate.

(15) On the other hand, 60
46.67 parts by weight of a photosensitizing oligomer (molecular weight 4000) obtained by acrylated 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co.)
80% by weight bisphenol A type epoxy resin dissolved in methyl ethyl ketone (Yuika Shell, Epicoat 10
01) 15.0 parts by weight, 1.6 parts by weight of an imidazole curing agent (manufactured by Shikoku Chemicals, trade name: 2E4MZ-CN), polyvalent acrylic monomer which is a photosensitive monomer (manufactured by Nippon Kayaku, trade name: R)
604) 3 parts by weight, 1.5 parts by weight of a polyacrylic monomer (manufactured by Kyoeisha Chemical, trade name: DPE6A), and 0.71 parts by weight of a dispersion defoaming agent (manufactured by San Nopco, trade name: S-65). 2 parts by weight of benzophenone (manufactured by Kanto Kagaku) as a photoinitiator and 0.2 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to the mixture, and the viscosity was adjusted to 25 ° C. To obtain a solder resist composition adjusted to 2.0 Pa · s.

The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type) at 60 rpm with a rotor No.
In the case of 4, 6 rpm, the rotor No. According to 3.

(16) A solder resist composition was applied to a thickness of 20 μm on a substrate.

(17) Then, at 70 ° C. for 20 minutes,
After performing a drying process at 30 ° C. for 30 minutes, a 5 mm thick soda lime glass substrate 13 on which a circular pattern (mask pattern) 14 of the solder resist opening is drawn by a chromium layer having a thickness of 600 Å is formed. The side on which is formed is brought into close contact with the solder resist
It was exposed to ultraviolet light of 0 mJ / cm ² and subjected to DMTG development processing.

Further, heat treatment was performed at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours to open the upper surface of the solder pad, the via hole, and the land. A 200 μm diameter solder resist pattern layer 8 (20 μm thickness) was formed.

(18) Next, the substrate having the solder resist pattern layer formed thereon was treated with nickel chloride 30 g / l, sodium hypophosphite 10 g / l, and sodium citrate 10 g.
/ L of electroless nickel plating solution of pH = 5
For 5 minutes, a nickel plating layer having a thickness of 5 μm was formed in the opening. Further, the substrate was placed on an electroless gold plating solution consisting of potassium gold cyanide 2 g / l, ammonium chloride 75 g / l, sodium citrate 50 g / l, and sodium hypophosphite 10 g / l at 93 ° C. for 23 seconds. By dipping, a gold plating layer 12 having a thickness of 0.03 μm was formed on the nickel plating layer 11.

(19) Then, a solder paste is printed on the opening of the solder resist pattern layer and reflowed at 200 ° C. to form a solder bump (solder body) 9 to manufacture a printed wiring board having the solder bump. did.

According to the above-described method for manufacturing a printed wiring board, it is possible to completely prevent the positional deviation of the via holes and the positional deviation of the resist pattern, which are observed in the conventional resin photomask film. At the time of mass production,
Although a misregistration defect of about 5% was found, such a defect can be prevented by the manufacturing method.

A photomask made of a glass substrate can be exposed several tens of times without dimensional change due to temperature and humidity. FIG. 23 shows the relationship between the number of exposures and the dimensional change of the mask. In FIG. 23, the horizontal axis represents the number of exposures, and the vertical axis represents the mask dimension change (μm). In addition, the round circles indicate the results of experiments performed using a photomask made of a glass substrate, and the black circles indicate the results of experiments performed using a conventional resin photomask.

As is clear from FIG. 23, when a photomask of a glass substrate is used, the mask dimensions hardly change until the number of exposures is about 50 times. On the other hand, when a resin photomask is used, it can be seen that even when the number of exposures is about 50, the mask dimensions change significantly, and that the mask dimensions change as the number of exposures increases. It is getting bigger.

From these experimental results, the change in the mask dimensions is smaller when the photomask made of a glass substrate is used than when a photomask made of a resin is used. It is possible to prevent misalignment of holes, plating resist patterns, and solder resist patterns.

[0090]

As described above, according to the method of manufacturing a printed wiring board according to the present invention , the dimensional change of the photomask can be suppressed, and as a result, the positional deviation of the via hole, the plating resist pattern, the solder resist Pattern displacement can be completely prevented. Also,
The mask pattern to be drawn on the glass substrate is
When the photosensitive resin layer shrinks due to curing
Also, converge the dimensions of the printed wiring board to the design values.
Can be

[0091] Thus, the present invention is by using a glass substrate Ma scan click pattern is formed as an exposure mask material, it is possible to suppress the dimensional change of the exposure mask material, it has been via It is possible to prevent misalignment of holes, plating resist patterns, and solder resist patterns .
By expanding the mask pattern from the design value,
Even if the conductive resin layer cures and shrinks,
It is possible to provide a method for manufacturing a printed wiring board capable of manufacturing a final product having an appropriate size .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a core substrate.

FIG. 2 is a sectional view of a wiring board on which an inner layer copper pattern is formed.

FIG. 3 is a cross-sectional view of the wiring board in a state where a resin is filled between the inner layer copper patterns and inside the through holes.

FIG. 4 is a cross-sectional view of a wiring board having a roughened layer formed on an inner copper pattern.

FIG. 5 is a sectional view of a wiring board in which a photosensitive resin layer is formed on an inner layer copper pattern.

FIG. 6 is a cross-sectional view of the wiring board showing a state in which a glass substrate is placed on a photosensitive resin layer and exposure is being performed.

FIG. 7 is a cross-sectional view of the wiring board after a photosensitive resin layer has been developed.

FIG. 8 is a cross-sectional view of the wiring board after the photosensitive resin layer has been subjected to a roughening treatment.

FIG. 9 is a sectional view of a wiring board in which an electroless plating film is formed on a photosensitive resin layer.

FIG. 10 is a cross-sectional view of a wiring board showing a state in which a glass substrate is placed on a dry film on an electroless plating film and exposure is being performed.

FIG. 11 is a sectional view of a wiring board having a plating resist layer formed on an electroless plating film.

FIG. 12 is a sectional view of a wiring board on which an electrolytic plating film is formed.

FIG. 13 is a sectional view of a wiring board on which a conductor circuit is formed.

FIG. 14 is a sectional view of a wiring board in which a roughened layer is formed on a conductive circuit.

FIG. 15 is a sectional view of a wiring board on which a photosensitive resin layer is formed.

FIG. 16 is a sectional view of a wiring board in which a roughened layer is formed on a photosensitive resin layer.

FIG. 17 is a sectional view of a wiring board in which an electroless plating film is formed on a roughened layer of a photosensitive resin layer.

FIG. 18 is a sectional view of a wiring board in which an electrolytic plating film is formed on an electroless plating film.

FIG. 19 is a sectional view of a wiring board in which a conductor layer and a via hole are formed.

FIG. 20 is a sectional view of a wiring board in which a roughened layer is formed in a conductor layer and a via hole.

FIG. 21 is a cross-sectional view of a wiring board showing a state where a glass substrate is placed on a solder resist layer and exposure is being performed.

FIG. 22 is a cross-sectional view of a wiring board in which a solder body is supplied to an opening of a solder resist layer.

FIG. 23 is a graph showing a relationship between the number of times of exposure and a dimensional change of a mask.

FIG. 24 is a cross-sectional view schematically showing a glass substrate.

FIG. 25 is a diagram showing how a dimensional change of a resin substrate occurs when a printed wiring board is multilayered.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Core board 2 Inner layer conductor circuit 3 Electroless copper plating film 4 Electrolytic copper plating film 5 Roughening layer 6 Photosensitive resin layer (adhesive layer for photosensitive electroless plating) 7 Plating resist 8 Solder resist 9, 90 Solder body ( Solder bump) 10 Solder pad 11 Nickel layer 12 Gold layer 13 Glass substrate 14 Mask pattern PC wiring board

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-63366 (JP, A) JP-A-4-1622642 (JP, A) JP-A-5-323574 (JP, A) JP-A 8- 335780 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H05K 3/46

Claims (7)

(57) [Claims] 1. A photoconductor is formed on a resin substrate on which a conductive circuit is formed.
A photosensitive resin layer is formed, and a mask pattern is formed on the photosensitive resin layer.
Exposure through the drawn glass substrate, develop it and
Open an opening for via hole formation, and add a photosensitive resin layer
Is cured by heating, and then a conductive circuit and
Of printed wiring board forming via and via hole
In the above, the mask pattern drawn on the glass substrate
Is characterized by being enlarged from the design value.
Manufacturing method of printed wiring board. 2. A photoconductor is formed on a resin substrate on which a conductive circuit is formed.
A photosensitive resin layer is formed, and a mask pattern is formed on the photosensitive resin layer.
Exposure through the drawn glass substrate, develop it and
Open an opening for via hole formation, and add a photosensitive resin layer
Is cured by heating, and then a conductive circuit and
And forming via holes at least twice
Repeat to laminate the photosensitive resin layer and conductor circuit
In each case , each photosensitive resin layer has a mask pattern that is larger than the design value.
Exposed through the glass substrate on which
Expansion of the mask pattern drawn on the
A pre-characteristic characterized in that the larger the ratio is, the smaller it is near the surface layer.
Manufacturing method of printed wiring board. 3. The mask pattern according to claim 1, wherein
Claims greatly expanded by 0.001 to 0.100%
3. The method for manufacturing a printed wiring board according to 1 or 2. 4. A photo-resist on a resin substrate subjected to a thermosetting treatment.
A photosensitive resin layer is formed, and the photosensitive resin layer is masked.
Is exposed through the glass substrate on which
In the method for manufacturing a printed wiring board for forming a pattern, the mask pattern drawn on the glass substrate may have a design value.
Printed wiring board characterized by being enlarged more than
Manufacturing method. 5. A contact for electroless plating subjected to a thermosetting treatment.
Photosensitive resin layer for forming plating resist on adhesive layer
And a mask pattern is drawn on this photosensitive resin layer.
Exposure through a glass substrate
And repeating the step of plating at least twice
Returns The method for manufacturing a printed wiring board, the photosensitive resin layer for the plating resist formation, the design value
Glass substrate with mask pattern enlarged
Exposed through a mask and drawn on a glass substrate
Magnification ratio to pattern design value is smaller as it is closer to the surface
A method for manufacturing a printed wiring board, comprising: 6. A contact for electroless plating subjected to a thermosetting treatment.
An electroless plating film is formed on the adhesive layer,
A photosensitive resin layer for forming dist
The grease layer is passed through the glass substrate on which the mask pattern is drawn.
Exposure to form plating resist pattern, electroless plating
To remove the plating resist pattern
Fewer steps to dissolve and remove the electroless plating film under the resist
At least twice or more times
There are, photosensitive resin layer for the plating resist formation, the design value
Glass substrate with mask pattern enlarged
Exposed through a mask and drawn on a glass substrate
Magnification ratio to pattern design value is smaller as it is closer to the surface
A method for manufacturing a printed wiring board, comprising: 7. A mask pattern according to claim 1, wherein
Claims that are greatly enlarged by 0.001 to 0.100%
Manufacturing of the printed wiring board according to any one of 4 to 13
Method.