JP2003092611A - Communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reset a slave device with a simple and convenient configuration. SOLUTION: An inhibit means inhibits transmission of data from a master device to the slave device through a predetermined data communication line among communication lines. A reset signal transmission means transmits a reset signal to the data communication line. A detection means detects the reset signal. That is, the detection means detects the reset signal sent to the predetermined communication line for data transmission. When the detection means detects the reset signal, a reset means resets the slave device. Since the communication system uses the data communication line to transmit the reset signal, the communication system can reset the slave device without the need for a reset signal line being an exclusive line to which the reset signal is sent.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system, and more particularly, in a system for performing communication such as serial communication and differential communication between a master device and a slave device, the slave device is reliably reset from the master device. To a communication system capable of doing.

[0002]

2. Description of the Related Art Conventionally, a master CPU (main device) and a plurality of slave CPUs (slave devices) are provided, and the master C
A communication system typified by a multi-CPU system that communicates between a PU and a plurality of slave CPUs is known. This multi-CPU system is specifically configured as shown in FIG. Note that only one slave CPU is shown here for the sake of simplification of the description.

As shown in FIG. 7, a master CPU 80 is provided on a master substrate 80, and a transceiver 84 and a receiver 86 are connected to the master CPU 82. A slave CPU 92 is provided on the slave board 90, and a transceiver 94 and a receiver 96 are connected to the slave CPU 92. A communication line 88A is provided between the transceiver 84 and the receiver 96 to enable differential communication,
It is connected by 88B. Similarly, transceiver 9
4 and the receiver 86 are connected by communication lines 89A and 89B so that differential communication is possible.

A master CPU 82 and a slave CPU
In order to reset the slave CPU 92 from the master CPU 82, 92 is connected via a reset signal line 98 independent of a communication line for data transfer. The reset signal output from the terminal P of the master CPU 82 is transmitted to the slave CPU 92 via the reset signal line 98, and the terminal RST of the slave CPU 92 is reset by receiving this reset signal.

[0005]

However, in the conventional communication system, from the master CPU 82 to the slave CP.
A reset signal line 98 for resetting U92 is provided. In this way, the system configuration is complicated by providing the dedicated line for reset. When an abnormality such as a failure or runaway occurs in the master CPU 82 itself,
The reset signal could not be sent from the master CPU to the slave CPU.

Therefore, in order to simplify the system configuration, there is a technique of eliminating the reset signal line and resetting the slave unit from the master unit via the communication line. An example of an application of this technique is an image forming apparatus that performs image forming processing such as image recording and copying. In this image forming apparatus, the main unit of the main body of the copying machine (or printer) issues an instruction to a post-processing device such as a finisher, and when there is no response, a display for turning off the power source is displayed. Therefore, the reset depends on the ON / OFF operation of the power supply. However, when such a display is performed, there is a problem that the abnormal state of the post-processing apparatus is not released unless the power of the user of the image forming apparatus is turned on / off.

Further, for example, Japanese Unexamined Patent Publication No. 11-163885 discloses a technique in which a slave controller detects a communication error with a master controller and controls the load to stop. However, this technique has a problem in that if the slave controller has a failure, it cannot be reset.

The present invention has been made to solve the above problem, and an object of the present invention is to provide a communication system capable of reliably resetting a slave device with a simple and simple structure without using a dedicated line.

[0009]

In order to achieve the above object, the invention as set forth in claim 1 is such that a main device and a slave device are connected by a communication line for exchanging data, and the master device and the slave device are connected to each other. In a communication system for resetting the slave device by transmitting a reset signal to the slave device, a prohibition unit that prohibits data transmission from the master device to the slave device for a predetermined data communication line of the communication lines. ,
Reset signal sending means for sending the reset signal to the predetermined data communication line, and detection for detecting a reset signal connected to the predetermined data communication line and sent by the reset signal sending means Means and reset means for resetting the slave device by the reset signal detected by the detection means.

In the communication system of the present invention, the prohibiting means prohibits the transmission of data from the main device to the slave device on a predetermined data communication line of the communication lines. In this prohibition, for example, there is a case where an abnormality occurs in communication such as when the slave device goes out of control. Therefore, no data is transmitted to the data communication line. The reset signal sending means sends a reset signal to the data communication line. This reset signal is detected by the detection means. That is, this detecting means detects the reset signal sent to the predetermined data communication line for data transmission. Then, when the reset signal is detected by the detection means, the reset means forcibly resets the slave device. in this way,
Since the data communication line for transmitting the reset signal is used, the slave device can be surely reset without providing the reset signal line which is a dedicated line for transmitting the reset signal.

According to a second aspect of the present invention, in the communication system according to the first aspect, the data communication line is connected so that communication between the main device and the slave device can be performed differentially. Is characterized by.

When the signal transmitted through the data communication line is a single signal, it is difficult to distinguish the noise from the signal. Therefore,
By making the communication between the main device and the slave device differential communication, noise generated in one signal can be excluded, and it is resistant to noise and high-frequency transmission becomes possible.

According to a third aspect of the present invention, in the communication system according to the first or second aspect, the reset signal transmitting means maintains the transmission state of the data, and the reset means transmits data. When the transmission is prohibited, the reset signal is transmitted by changing the transmission state of the data to the reset state.

During normal data communication, the reset signal transmitting means maintains the data transmission state on the data communication line in order to ensure reliable communication between the main device and the slave device. When data transmission is prohibited by the prohibition means, for example, when an abnormality occurs in communication, the transmission state is changed to the reset state. As a result, a reset signal can be sent to the data communication line, and the slave device can be forcibly reset. In this case, the reset signal sending means has an element that shifts to a high level signal or a low level signal when there is no signal input (for example, maintaining a high level by a pull-up resistor).

According to a fourth aspect of the present invention, in the communication system according to the third aspect, three or more data communication lines are predetermined as the data communication lines among the communication lines,
The prohibition unit sets the reset state different from the data transmission state for the three or more data communication lines.

During normal communication, that is, the state of data transmission, with respect to three or more predetermined data communication lines,
By making different settings for the reset state, more combinations of three or more data communication line states can be used, and the reset signal can be reliably transmitted.

According to a fifth aspect of the present invention, the main device and the slave device are connected by a communication line for exchanging data, a clock line is connected, and a reset signal is sent from the main device to the slave device. In a communication system for resetting the slave device by transmitting a clock signal sent by the clock line, and a reset means for sending a reset signal when the clock signal is not detected. It has a feature.

Generally, a clock line for transmitting a clock signal is provided between the main device and the slave device. During the operation of the main device and the slave device, a clock signal is sent to this clock line. However, when an abnormality occurs in the main device, the transmission of this clock signal may stop. Therefore, the reset means detects the clock signal, and when it is not detected, at least the operation of the main device is stopped. Therefore, the reset signal is transmitted in response to the occurrence of an abnormality in the main device. This ensures that the slave device is reset. Further, the clock line for the slave device is provided with a switch means or the like which is normally ON, and the switch means is turned off when an abnormality occurs in the slave device and it is necessary to forcibly reset the slave device. Therefore, the slave device may be forcibly reset.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows a communication system 10 according to a first embodiment of the present invention. It should be noted that here, in order to simplify the description, the slave C
Only one PU is shown. This communication system 10
Is applied to the image forming apparatus 70 shown in FIG.
In FIG. 2, for example, the main control unit 78 corresponds to the master substrate 20 (described later), and the finisher control unit 79B corresponds to the slave substrate 30 (described later). In the image forming apparatus 70 of FIG. 2, a computer (PC) 72, a scanner (not shown) that reads an image from a document, an image processing unit 79A that performs predetermined image processing based on image information received from the scanner, an image processing unit. A printer including an image output unit (not shown) that forms and outputs an image on a predetermined recording sheet under the control of the main control unit 78 based on the image information (print data) image-processed by 79A. A main body 74 and a post-processing device such as a finisher 76 for performing post-processing such as punching and stapling on the recording paper output from the printer main body 74 and recording an image under the control of the finisher control unit 79A. .

The communication system 10 includes a master CPU 22.
Master board 20 including (main device) and master CPU
The slave substrate 30 includes a slave CPU 32 (slave device) that communicates with the slave substrate 30. Master CPU
A transceiver 24 is connected to the terminal Tx of 22, and a receiver 26 is connected to the terminal Rx. Also, the terminal P
A reset signal sending circuit 18 is connected to the, and a pull-up resistor 16 is connected between the terminal P and the reset signal sending circuit 18. Further, the transceiver 24 and the inverter 25 described above are connected to the terminal E.
A pull-up resistor 1 is connected between the terminal E and the inverter 25.
6 is connected, and the inverter 25 is connected to the reset signal sending circuit 18.

A transceiver 34 is connected to the terminal Tx of the slave CPU 32, and a receiver 36 is connected to the terminal Rx. Further, the NAND circuit 3 is connected to the terminal RST.
7 output terminals are connected.

The transceiver 24 is a data communication line 28A,
The receiver 24 is connected to the receiver 36 via 28B, and the transceiver 24 is capable of differential output to the receiver 36. Similarly, transceiver 34 includes data communication line 38A,
38B, the transceiver 34 is connected to the receiver 26, and the transceiver 34 can perform differential output with respect to the receiver 26.

Data communication lines 14A and 14B are connected to the reset signal transmission circuit 18, and the data communication lines 14A and 14B are connected to the reset signal transmission circuit 18.
14B are connected to the data communication lines 28A and 28B, respectively. The transceiver 24 has a data communication line 28.
It has a terminal 24A for inhibiting differential output to A and 28B. The terminal E of the master CPU 22 is connected to the terminal 24A, and the output of the transceiver 24 is prohibited when the terminal E becomes L level. In addition, the data communication line 28
A and 28B are connected to the data communication lines 13A and 13B, respectively, and the data communication lines 13A and 13B are connected to the NAND circuit 37.

The master CP in the communication system 10 according to the present embodiment will be described below with reference to the flowchart of FIG.
The flow of data communication between the U22 and the slave CPU 32 will be described.

In step 100, it is determined whether communication has failed, that is, whether data transmission / reception between the master CPU 22 and the slave CPU 32 has failed. For example, the master CPU 22 uses the data communication lines 28A and 28B.
Command transmitted to the slave CPU 32 via the slave CP via the data communication lines 28A and 28B.
By determining whether or not the status is returned from U32, it is determined whether or not the communication has failed, that is, whether or not an abnormality has occurred in the communication. If the status is returned, it is determined that no abnormality has occurred, the result is negative in step 100, and the process proceeds to step 102. On the other hand, if the status is not returned, it is determined that an abnormality has occurred, the affirmative determination is made in step 100, and the flow proceeds to step 106.

In step 102, the signal levels at the terminals P and E of the master CPU 22 are both at the L level (P =
0, E = 0). As a result, an L level signal (low level signal: hereinafter referred to as L signal) is output from the terminals E and P. That is, in normal communication, the outputs from the terminals P and E of the master CPU 22 are L signals. The L signal output from the terminal E is inverted by the inverter 25 and input to the terminal E1 of the reset signal sending circuit 18 as an H level signal (high level signal: hereinafter referred to as H signal). In response to the input of the H signal, the reset signal sending circuit 18 outputs the output terminals Q1 and Q2.
Becomes high impedance. Then, the transceiver 24 of the master CPU 22 is enabled by the L signal of the terminal E, and the output signal from the terminal Tx can be transmitted to the slave CPU 32.

In the next step 104, the master CPU 2
Data is transmitted and received between the slave CPU 2 and the slave CPU 32 for performing a predetermined process (in the present embodiment, the "copy mode" is used in consideration of the case of being applied to the image forming apparatus). Specifically, the master CPU 22
Various signals in the copy mode output from the terminal Tx of
The signal is transmitted to the transceiver 24, converted from the TTL level signal into the differential signal in the transceiver 24 and transmitted to the receiver 36, converted into the TTL level signal again in the receiver 36, and the slave CPU 32
Is input to the terminal Rx. The transmission from the terminal Tx of the slave CPU 32 to the terminal Rx of the master CPU 22 is performed in the same manner.

When an affirmative decision is made in step 100 and the operation proceeds to step 106, in step 106 the master CP
The signal levels at the terminals P and E of the U22 are both set to the H level (E = 1, P = 1). As a result, the H signal is output from the terminals E and P.

That is, the master CPU 22 is the master C
The signal level from the terminal E of the PU 22 is set to H level (E = 1). The H signal output from the terminal E is input to the terminal 24A of the transceiver 24, so that the output of the transceiver 24 becomes high impedance. As a result, the master CPU for the data communication lines 28A and 28B
Data transmission from 22 to the slave CPU 32 is prohibited.

The H signal from the terminal E is input to the terminal E1 of the reset signal sending circuit 18 as an L signal inverted by the inverter 25. As a result, the output terminals Q1 and Q2 enter the Enable state. In this state, the H signal is output from the terminal P of the master CPU 22 (P = 1). That is, the process proceeds to step 108 and shifts to the "reset mode".

In the reset mode of step 108, the H signal is input to the reset signal sending circuit 18 by setting the terminal P to the H level. In the reset signal sending circuit 18, when the input of the terminal P1 is the H signal, the output terminals Q1 and Q
The two outputs are both H signals. As a result, since the H signal is output from both the output terminals Q1 and Q2, the predetermined data communication lines 14A, 14B, 28A,
All of 28B, 13A, and 13B are in the reset state where they are at the H level, and the reset signal is transmitted.

The H signal output from the output terminal Q1 is transmitted to the NAND circuit 37 via the data communication lines 14B, 28B and 13B. The H signal output from the output terminal Q2 is transmitted to the NAND circuit 37 via the data communication lines 14A, 28A, and 13A, and the NAND circuit 37 outputs the L signal. Since the NAND circuit 37 outputs the L signal only when both inputs are at the H level,
When the reset signal is detected, an instruction signal (here, the L signal) for resetting the slave CPU 32 is output to the terminal RST. The slave CPU 32 is reset by inputting this L signal to the terminal RST of the slave CPU 32.

Since the H signal is normally input to the terminal RST of the slave CPU 32, the slave CPU 32
32 is never reset. That is, NAND
Since the differential signal from the master CPU 22 is input to the circuit 37, its output is always an H level signal. Therefore, the slave CPU 32 is not reset during normal communication.

When reset is released, the output from the terminal E is set to the L signal, the reset signal sending circuit 18 is set to the disable state, and the transceiver 24 is set to the E state.
The state is enabled. As a result, the slave CPU3
2 enters a standby state for receiving a communication start command from the master CPU 22, and the master CPU 22 transmits the command, whereby communication between the master CPU 22 and the slave CPU 32 is restarted.

Further, when the master CPU 22 runs out of control, the so-called WDT (watchdog timer) resets the master CPU 22, and the output of the master CPU 22 becomes high impedance. As a result, the output of the master CPU 22 is pulled up by the pull-up resistor 16 to become the H signal, and the slave CPU 32 can be reset.

As described above, according to this embodiment described above, the transmission of the data transmitted through the data communication lines 28A and 28B is prohibited, and the reset signal is transmitted to the data communication lines 28A and 28B. Therefore, the data communication line 28
A and 28B can also be used as the reset signal line, and it is not necessary to separately provide the reset signal line. In addition, since only the slave CPU 32 can be reset, it is not necessary to reconnect the power to the communication system 10 or to a device such as an image forming apparatus to which the communication system is applied. In addition, master CPU22, slave CPU
Even if one of 32 becomes abnormal, the slave CP
The load controlled by U32 does not run away or malfunction and can be controlled in a safe state. For example,
In the post-processing device, it is possible to prevent runaway of the motor that drives the transport roll that transports the recording paper, and malfunction of the solenoid. Therefore, it is possible to prevent jamming or the like of the recording sheet conveyed by the conveying rolls.

In the above embodiment, the master C
A signal is output from the terminal E of the PU 22 and the transceiver 24
Setting the output of H to high impedance corresponds to the processing of the prohibition means of the present invention. Further, the H signal is output from the terminal P, and the output terminal Q of the reset signal sending circuit 18 is output.
The output of the H signal from both 1 and Q2 corresponds to the operation of the reset signal transmitting means of the present invention. Furthermore, NA
Both of the two inputs to the ND circuit 37 become H signals,
The output of the L signal from the NAND circuit 37 corresponds to the operation of the detecting means of the present invention. Furthermore, when the L signal is input to the slave CPU 32, the slave 32
The process of resetting the slave CPU 32 itself corresponds to the operation of the reset means of the present invention.

(Second Embodiment) The second embodiment of the present invention will be described below.
A communication system 50 according to the embodiment will be described with reference to the drawings. In this embodiment, the same components as those in the first embodiment described above are designated by the same reference numerals, and the description thereof will be omitted.

The communication system 50 shown in FIG.
Master board 20 with PU 22 and slave CPU 32
And a slave substrate 30 having a. Master CP
A transceiver 24 is connected to the terminal Tx of the U22, and a receiver 26 is connected to the terminal Rx. Slave C
The transceiver 34 is connected to the terminal Rx of the PU 32 by the terminal Rx.
Is a receiver 36, and the terminal RST is a NAND circuit 37.
Are connected respectively.

The transceiver 24 and the receiver 36 are connected via the data communication lines 28A and 28B, and the transceiver 24 can output a differential signal to the receiver 36. In the present embodiment, the data communication line 2 is replaced with the reset signal sending circuit 18 in the first embodiment.
8A and 28B are normally configured to maintain a communicable state. That is, the pull-up resistors 16A and 16B are connected to the data communication lines 28A and 28B, respectively. For example, when the terminal E is L level and the differential output of the transceiver 24 is high impedance, both are L level output, and when the terminal E is H level, the differential output of the transceiver 24 is H level and L level output. Pull-up resistor 1 in relation to the internal resistance of each transceiver 24
The resistance values of 6A and 16B are defined. The transceiver 24 has a terminal 24A for inhibiting differential output to the data communication lines 28A and 28B. The terminal E of the master CPU 22 is connected to this terminal 24A, and the terminal E is L
When the level becomes the level, the output of the transceiver 24 is prohibited.

Data communication lines 13A and 13B are connected to the data communication lines 28A and 28B, and the data communication line 1
The ends of 3A and 13B are connected to the NAND circuit 37. Similarly, the transceiver 34 and the receiver 26 are connected via the data communication lines 38A and 38B, and the transceiver 3
4 is capable of differential output to the receiver 26.

When performing normal communication, the above-mentioned first
Similarly to the above embodiment, the output of the terminal E of the master CPU 22 is the L signal. At this time, the data transmission state from the master CPU 22 to the slave CPU 32 is maintained. When the master CPU 22 detects a communication error such as a runaway of the slave CPU 32, the output of the terminal E becomes H.
Signaled. Since the H signal output from the terminal E is input to the terminal 24A of the transceiver 24, the output of the transceiver 24 becomes high impedance. This prohibits the transmission of data from the transceiver 24.

At this time, since the output of the transceiver 24 is pulled up by the pull-up resistor 16, all the output signals are H signals. This allows
This means that the reset signal has been sent. This H signal is transferred to N via the data communication lines 28A, 13A, 28B, 13B.
It is input to the AND circuit 37, the output of the NAND circuit 37 becomes L, and the reset signal is detected. Then, the L signal which is the output signal of the NAND circuit 37 is input to the terminal RST of the slave CPU 32, and the slave CPU 32
32 is reset.

As described above, according to the present embodiment, during normal communication, the data transmission state to the data communication lines 28A and 28B is maintained, and, for example, when an abnormality occurs in the slave CPU 32, the H signal from the terminal E is output. Is sent to prohibit data transmission. And the pull-up resistor 16
The data communication lines 28A and 28B are changed to the reset state by A and 16B, and the reset signal is transmitted to the data communication lines 28A and 28B. Therefore, the data communication line can also be used as the reset signal line, and it is not necessary to separately provide the reset signal line. Further, in the present embodiment, since the reset signal can be sent out only by the configuration of the pull-up resistors 16A and 16B, the device configuration becomes simpler.

In this embodiment, when the transceiver 24 becomes high impedance, the output 24 of the transceiver is pulled up by the pull-up resistors 16A and 16B, and the H signal is transmitted to the data communication lines 28A and 28B. This corresponds to the reset signal transmitting means of the present invention.

(Third Embodiment) The third embodiment of the present invention will be described below.
A communication system 50 according to the embodiment will be described with reference to the drawings. In this embodiment, the same components as those in the above-described first and second embodiments are designated by the same reference numerals, and the description thereof will be omitted.

The communication system 52 shown in FIG.
Master board 20 with PU 22 and slave CPU 32
And a slave substrate 30 having a. Master CP
A transceiver 24 is connected to the terminal Tx of the U22, and a receiver 26 is connected to the terminal Rx. Slave C
The transceiver 34 is connected to the terminal Rx of the PU 32 by the terminal Rx.
Is a receiver 36, and the terminal RST is a NAND circuit 37.
Are connected respectively.

The transceiver 24 is connected to the terminal Tx of the master CPU 22, the receiver 36 is connected to the terminal Rx of the slave CPU 32, and the transceiver 24 and the receiver 36 are connected via the data communication line 28.
Similarly, the transceiver 34 is connected to the terminal Tx of the slave CPU 32, the receiver 26 is connected to the terminal Rx of the master CPU 22, and the transceiver 34 and the receiver 2 are connected.
6 is connected via a data communication line 38.

In the first embodiment, the master CPU
The case where the reset signal is transmitted as the terminal P of 22 has been described, but in the present embodiment, a plurality of control signal lines are used for reset. Specifically, the master CPU 22
The terminals P0, P1, and P2 of the slave CPU32 are connected to the terminals of the slave CPU 32 through the data communication lines 12A, 12B, and 12C. These terminals P0, P1 and P2 are used for exchanging control signals other than reset between the master CPU 22 and the slave CPU 32.

Then, the data communication lines 12A, 12B, 1
Pull-up resistors 16A, 16B and 16C are connected to 2C, respectively. In addition, the data communication lines 12A, 12
Data communication lines 13A, 13B and 13C are connected to B and 12C, and data communication lines 13A, 13B and 13C are NA.
It is connected to the ND circuit 37.

When the master CPU 22 detects the communication abnormality of the slave CPU 32, the outputs from the terminals P0, P1 and P2 of the master CPU 22 are all H signals. As a result, the reset signal is transmitted. The H signal corresponds to the data communication lines 12A, 12B, 12C, 13A, 1
It is input to the NAND circuit 37 via 3B and 13C.
As a result, the output of the NAND circuit 37 becomes the L signal,
The reset signal is detected. And this L
The signal is input to the terminal RST of the slave CPU 32, and L
The slave CPU 32 is reset by the input of the signal.

The data communication lines 12A, 12B, 12
The signal transmitted to C is set to be different between the normal time and the reset time. That is, during normal communication, all the signals transmitted by the data communication lines 12A, 12B, 12C are prevented from becoming H signals. Further, the number of the data communication lines 12A, 12B, 12C is not necessarily limited to three, and if there are two or more, the communication system 52 according to the present embodiment can be configured.

As described above, according to the present embodiment described above, the data communication line 12 is thus used during normal communication.
The terminals P0, P1 and P2, which are predetermined combinations for maintaining the data transmission state to the three data communication lines A, 12B and 12C and resetting when an abnormality occurs in the slave CPU 32, are The three data communication lines 1 are set to the H level by sending the H signal.
Data transmission to 2A, 12B, and 12C is prohibited.

The pull-up resistors 16A, 16B,
16B changes the data communication lines 12A, 12B, 12C to the reset state, and these data communication lines 12A, 12B
A reset signal is transmitted to B and 12C. Therefore,
The data communication line can also be used as the reset signal line,
There is no need to separately provide a reset signal line. Further, by using three data communication lines as in this embodiment, more combinations of data communication line states can be used.

Although three data communication lines 12A, 12B and 12C are used in this embodiment, four or more data communication lines may be used. In this case, all the signals sent to the four data communication lines may be H signals, or may be a combination of a predetermined H signal and L signal. A combination of signals that do not normally appear can be used.

In the present embodiment, the slave CPU 3 uses a combination of signals that do not normally appear.
2 to the signal, that is, the master CPU as an example
Setting all the outputs of the terminals P0, P1, P2 of 22 to H signals corresponds to the prohibition means of the present invention.

(Fourth Embodiment) The fourth embodiment of the present invention will be described below.
A communication system 50 according to the embodiment will be described with reference to the drawings. In this embodiment, the same components as those in the first to third embodiments described above are designated by the same reference numerals, and the description thereof will be omitted.

The communication system 54 shown in FIG.
Master board 20 with PU 22 and slave CPU 32
And a slave substrate 30 having a. Master CP
A transceiver 24 is connected to the terminal Tx of the U22, and a receiver 26 is connected to the terminal Rx. Slave C
The transceiver 34 is connected to the terminal Rx of the PU 32 by the terminal Rx.
A receiver 36 is connected to each of the.

In the above-described embodiment, the NAND circuit 3
Although the reset signal is output by means of No. 7, in the present embodiment, the slave CPU 32 is reset by the presence or absence of that signal using the clock signal line output during normal operation. Specifically, the terminal C of the master CPU 22
The LK and the terminal RST of the slave CPU 32 are connected via the clock line 40, and the terminal CLK and the terminal RS
An IC 39 is provided between T and T.

A one-shot multivibrator, for example, is applied to the IC 39 to detect a clock signal and send a reset signal when the clock signal is not detected. That is, the IC 39 holds the output of the H signal by receiving the clock signal within a predetermined cycle, and outputs the L signal when the clock signal is not received within the cycle.

The clock signal line 40 is branched before the input to the IC 39, and as a result, the terminal CL of the master CPU 22 is connected.
K and the terminal CLK of the slave CPU 32 are clock lines 4
0 and the clock line 40A.

The transceiver 24 is connected to the terminal Tx of the master CPU 22, the receiver 36 is connected to the terminal Rx of the slave CPU 32, and the transceiver 24 and the receiver 36 are connected via a data communication line 28.
Similarly, the transceiver 34 is connected to the terminal Tx of the slave CPU 32, the receiver 26 is connected to the terminal Rx of the master CPU 22, and the transceiver 34 and the receiver 2 are connected.
6 is connected via a data communication line 38. Further, the terminals P0 and P1 of the master CPU 22 and the terminals P0 and P1 of the slave CPU 32 are connected to the data communication line 1
It is connected via 2A and 12B.

When the master CPU 22 detects the communication abnormality of the slave CPU 32, the output of the clock signal from the terminal CLK of the master CPU 22 is stopped. After a lapse of a fixed time after the output of the clock signal is stopped, the IC 39 outputs the L signal in response to the fact that the clock signal is not detected.
Is input to the terminal RST, and the slave CPU 32 is reset. Note that the master CPU 22 does not output a clock signal during a non-normal operation such as when the master CPU 22 itself runs out of control.
U32 is also reset.

As described above, according to the present embodiment, the presence or absence of the control signal such as the clock signal from the master CPU 22 is detected, and the slave CPU 32 is detected based on the detection result.
Therefore, the slave CPU 32 can be reset without providing a dedicated line for transmitting a reset signal. Therefore, the slave CPU 32 can be reset from the master CPU 22 with a simple and simple configuration. Further, the slave CPU 32 can be reset even when the master CPU 22 runs out of control.

Although the clock signal is used in the present embodiment, the present invention is not limited to this, and a control signal which is constantly output during normal operation of the master CPU 22 may be used. .

In the present embodiment, the master CPU 22
Reset by non-detection of the control signal normally sent from the IC 39.
Detecting the clock signal sent from 0 and outputting the L signal when the clock signal is not detected corresponds to the reset means of the present invention.

[0068]

As described above, according to the present invention, the transmission of data or the like transmitted through a specific communication line is prohibited,
Since the reset signal is transmitted to the communication line, the specific communication line can be used also as the reset signal line, and it is not necessary to separately provide the reset signal line. Therefore, since the slave device can be surely reset without providing a dedicated line for sending the reset signal, there is an excellent effect that the slave device can be reset with a simple and simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a communication system according to a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing an outline of an image forming apparatus to which the communication system of the present invention is applied.

FIG. 3 is a flowchart showing a communication flow between a master CPU and a slave CPU in the communication system according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a communication system according to a second exemplary embodiment of the present invention.

FIG. 5 is a block diagram showing a communication system according to a third exemplary embodiment of the present invention.

FIG. 6 is a block diagram showing a communication system according to a fourth exemplary embodiment of the present invention.

FIG. 7 is a block diagram showing a conventional communication system.

[Explanation of symbols]

10 communication systems 12A, 13A, 14A, 14B, 28, 28A, 3
8, 38A Data communication line 16 Pull-up resistor 18 Reset signal sending circuit 20 Master substrate 22 Master CPU 24 Transceiver 25 Inverter 26 Receiver 30 Slave substrate 32 Slave CPU 34 Transceiver 36 Receiver 37 NAND circuit 40, 40A Clock line 50, 52, 54 Communications system

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2C061 AP04 HH01 HN21                 5H209 CC07 CC09 CC13 EE11 HH06                       JJ05                 5K033 AA04 DA01 DB14 EC01                 5K034 AA12 DD01 EE08 FF01 HH01                       HH02 KK13 PP01

Claims (5)

[Claims] 1. A communication system in which a master device and a slave device are connected by a communication line for exchanging data, and a reset signal is transmitted from the master device to the slave device to reset the slave device, Prohibition means for inhibiting transmission of data from the main device to the slave device with respect to a predetermined data communication line of the communication lines, and reset signal transmission for transmitting the reset signal to the predetermined data communication line Means, detection means connected to the predetermined data communication line and detecting a reset signal sent by the reset signal sending means, and resetting the slave device by the reset signal detected by the detecting means. A communication system comprising: reset means. 2. The communication system according to claim 1, wherein the data communication line is connected so that communication between the main device and the slave device can be performed differentially. 3. The reset signal transmitting means maintains the data transmission state, and when the data transmission is prohibited by the prohibiting means, the reset signal transmitting means changes the data transmission state to a reset state. The communication system according to claim 1 or 2, wherein a reset signal is transmitted. 4. A three or more data communication line is predetermined as the data communication line among the communication lines, and the prohibition unit is in a reset state different from a data transmission state for the three or more data communication lines. The communication system according to claim 3, wherein the communication system is set to. 5. A master device and a slave device are connected by a communication line for exchanging data, and a clock line is connected, and by transmitting a reset signal from the main device to the slave device, the slave device is connected. A communication system for resetting a device, comprising: reset means for detecting a clock signal transmitted by the clock line and transmitting a reset signal when the clock signal is not detected.