JP2003069537A - Data processing device and data processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and a method for data processing comprising multiple data processing systems, in which, even if a data processing system is switched to another system, the continuity of output signals is ensured before and after switching. SOLUTION: A signal processing circuit 15 processes input data under a first circumstance, and a driver 11 outputs a synchronization signal under a second circumstance for synchronization between data processing systems. A receiver 21 receives a synchronization signal output from the driver 11, a synchronizer circuit 24 performs synchronization with the active data processing system 10 according to the synchronization signal received by the receiver 21, and a signal processing circuit 25 executes data transmission processing under the second circumstance in accordance with the synchronization performed by the synchronizer circuit 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device and a data processing method thereof for processing provided data, and more particularly to a data processing device having a plurality of data processing systems and a data processing method thereof.

[0002]

2. Description of the Related Art In digital satellite broadcasting, a distribution system is constituted by a plurality of broadcasting stations sharing one transmitting station.

FIG. 9 is a conceptual diagram exemplifying a program distribution system in such digital satellite broadcasting. As illustrated in FIG. 9, a program distribution system in digital satellite broadcasting includes, for example, from a plurality of broadcasting stations 501 to 504 and a plurality of broadcasting stations 501 to 504 that provide program content as a transport stream (TS: Transport Stream). Sending station 51 that multiplex-combines a plurality of provided transport streams into one carrier
0, the transmitting station 510 has an antenna 520 for transmitting the carrier waves multiplexed and combined to a broadcasting satellite. Here, the transport stream is, for example, image data or the like that constitutes the program content, and is MPEG (Movie).
ng Picture Experts Group)
-2 or the like, a transport packet (Transport Packet) having information compressed and encoded.
t) means the set.

Further, the sending station 510 has, for example, a plurality of input boards 511a-51 for receiving the input of each transport stream provided from each broadcasting station 501-504.
1d, a TS synthesizing substrate 512 that multiplex-synthesizes a plurality of transport streams, a transmission path coding device 513 that performs transmission coding processing of a carrier that multiplex-combines transport streams, and modulation / transmission that performs modulation and transmission of this carrier Device 514 is included. Here, the input boards 511a to 511d are, for example, the broadcasting stations 501 to 50, respectively.
In order to ensure the reliability of the handling of the transport stream provided from No. 4, there are two data processing systems that perform data processing of the provided transport stream. These data processing systems are divided into, for example, a working data processing system used in a normal state and a spare data processing system used when a failure occurs in the working data processing system, and each of the input boards 511a to 511d.
Automatically switches between the active data processing system and the spare data processing system according to the data processing status in each of the input boards 511a to 511d.

In the case of distributing program contents in digital satellite broadcasting, first, for example, each broadcasting station 501-5.
04 provides the sending station 510 with the program content provided by each as a transport stream. Sending station 5
Each transport stream provided to the 10 is acquired by, for example, the input boards 511a to 511d, and the TS synthesis board 5 is transmitted via the input boards 511a to 511d.
12 provided. The TS synthesizing board 512 multiplex-combines the transport streams provided from the input boards 511a to 511d, for example, into one carrier wave, and provides the carrier wave to the transmission path coding device 513. The carrier wave provided to the transmission path coding device 513 is, for example, subjected to transmission path coding processing by this transmission path coding device 513, further modulated by the modulation / transmission device 514, and then the antenna 5
It is output to the broadcasting satellite via 20.

[0006]

However, conventionally, when the working data processing system and the spare data processing system are switched, the output signal from the working data processing system and the output signal from the spare data processing system are continuously connected. There is a problem that it was difficult to secure the sex.

For example, the number of clock counters counted in the active data processing system or the standby data processing system is added to the output signal output from the active data processing system or the standby data processing system, and the added clock is added. The number of counters may be used in subsequent processing after the current data processing system or the spare data processing system. However, it is general that the counting of the number of clock counters is started for each data processing system after the power supply of each of these data processing systems is turned on. Therefore, the number of clock counters in the active data processing system may not match the number of clock counters in the standby data processing system depending on the power-on state. In this case, the number of clock counters of the output signal changes before and after the switching of the data processing system, and as a result, the subsequent processing performed using this number of clock counters may be hindered. In particular,
For example, when the clock counter counts up at a high clock frequency such as 7 MHz,
As described above, it is extremely difficult to match the number of clock counters between mutually independent data processing systems. In general, even if the output signal of either the active data processing system or the backup data processing system is being used in the subsequent processing, the data processing system of the active data processing system and the backup data processing system will not , The same transport stream is input at the same timing.
However, if the input transport stream is delayed or disconnected between the active data processing system and the backup data processing system for some reason, the timings of the output signals output from both data processing systems are different. As a result, there arises a problem that the timings of the output signals are different before and after the switching of the data processing system, which hinders the subsequent processing.

The present invention has been made in view of the above point, and even when the data processing system for processing the provided data is switched, the output signal is continuously output before and after the switching of the data processing system. It is an object of the present invention to provide a data processing device capable of ensuring reliability.

Another object of the present invention is to ensure the continuity of the output signal before and after the switching of the data processing system even when the data processing system for processing the provided data is switched. It is to provide a possible data processing method.

[0010]

According to the present invention, in order to solve the above-mentioned problems, a data processing apparatus having a plurality of data processing systems performs processing of provided data under a first situation. A first data processing system having a data processing means and a synchronization signal output means for outputting a synchronization signal which is a signal required for synchronization between the data processing systems under the second situation; A synchronization signal receiving means for receiving the synchronization signal output from the signal output means, and a synchronization processing for performing synchronization processing for the first data processing system using the synchronization signal received by the synchronization signal receiving means. Means and said second
Under the above conditions, the second data processing unit having a second data processing unit for processing the provided data according to the synchronization processing by the synchronization processing unit, and a second data processing system having the second data processing unit. A processing device is provided.

Here, the first data processing means processes the provided data under the first condition, and the synchronization signal output means synchronizes the data processing systems under the second condition. A synchronization signal which is a signal necessary for obtaining the synchronization signal is output, the synchronization signal receiving means receives the synchronization signal output by the synchronization signal output means, and the synchronization processing means receives the synchronization signal by the synchronization signal receiving means. By using the synchronization processing for the first data processing system,
The second data processing means processes the provided data according to the synchronization processing by the synchronization processing means under the second situation.

In the data processing device of the present invention,
Preferably, the second data processing system further includes a synchronization signal reception permission unit that enables reception of the synchronization signal only under the second situation.

In the data processing device of the present invention,
Preferably, the first data processing system further includes counter number information output means for outputting counter number information indicating the number of clock counters in the first data processing system under the second situation, and the second data processing system. The data processing system further includes counter number information receiving means for receiving the counter number information output by the counter number information output means.

In the data processing device of the present invention,
Preferably, the first data processing system includes change number information output means for outputting change number information, which is information indicating the number of changes of the data provided to the first data processing system, in the second situation. The second data processing system further includes a change number information receiving unit that receives the change number information output by the change number information output unit.

Further, the data processing apparatus of the present invention preferably comprises a clock providing means for providing the same clock to the first data processing system and the second data processing system,
Further, the synchronization signal has a timing advanced by one clock in the clock provided by the clock providing means, as compared with the first basic synchronization signal which is a signal for timing the data processing in the first data processing system. The synchronization processing means is a signal to be output, and the synchronization processing means generates the first synchronization processing signal by latching the synchronization signal received by the synchronization signal receiving means with the clock provided by the clock providing means. Second synchronization processing for generating a second synchronization processing signal by latching the signal generation means and the first synchronization processing signal generated by the first synchronization processing signal generation means with the clock provided by the clock providing means. Signal generation means, first synchronization processing signal generated by the first synchronization processing signal generation means, and second synchronization A third synchronization processing signal generating means for generating a third synchronization processing signal which is the logical sum of the inverted signal of the second synchronization processing signal generated by the logic signal generating means, and a third synchronization processing signal. A second basic synchronization signal generation means for generating a second basic synchronization signal by latching the third synchronization processing signal generated by the generation means with the clock provided by the clock providing means.

In the data processing device of the present invention,
Preferably, the synchronization signal is a signal having a pulse width of 2 clocks or more in the clock provided by the clock providing means.

In the data processing device of the present invention,
Preferably, the first situation is a situation in which the data in the first data processing system is normal, and the second situation is a situation in which the data in the first data processing system is defective.

Further, in a data processing device having a plurality of data processing systems, first data processing means for processing the provided data under the first situation, and data processing system under the second situation. A first synchronization signal which is a signal required for synchronizing between the first
A first data processing system having a synchronization signal output means, a first synchronization signal receiving means for receiving the first synchronization signal output from the first synchronization signal output means, and the first synchronization signal output means. Second synchronization processing means for performing the synchronization processing for the first data processing system using the first synchronization signal received by the synchronization signal receiving means of the second synchronization processing means, and the second synchronization processing means under the second situation. Second data processing means for processing the provided data according to the synchronization processing by the second synchronization processing means, and under the first situation,
A second data processing system having a second synchronization signal output means for outputting a second synchronization signal which is a signal necessary for synchronization between the data processing systems, and the first data processing system. A second data processing system receives the second synchronization signal output from the second synchronization signal output means.
Of the second synchronization signal received by the second synchronization signal receiving means and the second synchronization signal receiving means of the second synchronization signal receiving means.
A first synchronization processing means for performing synchronization processing for the data processing system, and, in the first situation, for processing the provided data in accordance with the synchronization processing by the first synchronization processing means. There is provided a data processing device, further comprising a first data processing means.

Here, the first data processing means processes the provided data under the first situation, and the first data processing means
In the second situation, the synchronization signal output means of 1 outputs the first synchronization signal which is a signal necessary for synchronization between the data processing systems, and the first synchronization signal receiving means,
The first synchronization signal output means receives the first synchronization signal output, and the second synchronization processing means uses the first synchronization signal received by the first synchronization signal receiving means,
The synchronization processing for the first data processing system is performed, and the second processing is performed.
In the second situation, the data processing means for processing the provided data according to the synchronization processing by the second synchronization processing means, and the second synchronization signal output means under the first situation, The second synchronization signal receiving means outputs the second synchronization signal which is a signal necessary for synchronization between the data processing systems, and the second synchronization signal receiving means outputs the second synchronization signal output from the second synchronization signal output means. The first synchronization processing means receives and uses the second synchronization signal received by the second synchronization signal receiving means to perform the synchronization processing on the second data processing system, and the first data processing means. Processes the provided data according to the synchronization processing by the first synchronization processing means under the first situation.

Further, in the data processing method for processing the provided data, the first data processing step of processing the provided data under the first situation, which is performed in the first data processing system, Under the second situation, a synchronization signal output step of outputting a synchronization signal that is a signal necessary for synchronization between the data processing systems, and an output in the synchronization signal output step performed in the second data processing system. A synchronization signal receiving step of receiving the synchronized signal received, and the synchronization signal received in the synchronization signal receiving step,
A synchronization processing step of performing a synchronization processing for the data processing system, and a second data processing step of processing the provided data according to the synchronization processing by the synchronization processing step under the second situation. There is provided a data processing method comprising:

Here, the first data processing step processes the provided data under the first situation,
The synchronization signal output step outputs a synchronization signal that is a signal necessary for synchronizing between the data processing systems under the second situation, and the synchronization signal reception step outputs the synchronization signal output in the synchronization signal output step. Received
The synchronization processing step uses the synchronization signal received in the synchronization signal receiving step to perform synchronization processing for the first data processing system, and the second data processing step
Under the second situation, the provided data is processed according to the synchronization process by the synchronization process step.

In the data processing method of the present invention,
Preferably, it is performed in the second data processing system,
Only under the second situation, there is further provided a synchronization signal reception permission step that enables reception of the synchronization signal by the synchronization signal reception step.

In the data processing method of the present invention,
Preferably, it is performed in the first data processing system,
Outputting the counter number information, which further includes a counter number information output step of outputting counter number information indicating the number of clock counters in the first data processing system under the second situation, and is performed in the second data processing system. The method further includes a counter number information receiving step of receiving the counter number information output in the step.

In the data processing method of the present invention,
Preferably, it is performed in the first data processing system,
The second data processing system further includes a change number information output step of outputting change number information, which is information indicating the number of changes of the data provided to the first data processing system, under the second situation. The method further includes a change number information receiving step of receiving the change number information output in the change number information output step.

In the data processing method of the present invention,
Preferably, the method further comprises a clock providing step of providing the same clock to the first data processing system and the second data processing system, and the synchronization signal indicates the timing of data processing in the first data processing system. It is a signal that is output at a timing one clock ahead of the clock provided by the clock providing step than the first basic synchronization signal that is a signal for measuring, and the synchronization processing step is received by the synchronization signal receiving step. A first synchronization processing signal generating step of generating a first synchronization processing signal by latching the synchronization signal generated by the clock with the clock provided by the clock providing step; and a first synchronization processing signal generated in the synchronization processing signal generating step. To
A second synchronization processing signal generating step for generating a second synchronization processing signal latched by the clock provided by the clock providing step; a first synchronization processing signal generated in the synchronization processing signal generating step; A third synchronization processing signal generation step of generating a third synchronization processing signal which is a logical sum of an inversion signal of the second synchronization processing signal generated in the synchronization processing signal generation step, and a third synchronization processing Third generated in the signal generation step
And a second basic synchronization signal generating step of generating a second basic synchronization signal by latching the synchronization processing signal of 1) by the clock provided by the clock providing step.

In the data processing method of the present invention,
Preferably, the synchronization signal is a signal having a pulse width of 2 clocks or more in the clock provided by the clock providing step.

In the data processing method of the present invention,
Preferably, the first situation is a situation in which the data in the first data processing system is normal, and the second situation is a situation in which the data in the first data processing system is defective.

In a data processing method having a plurality of data processing systems, a first data processing step for processing the provided data under the first situation, which is performed in the first data processing system, In a second situation, a first synchronization signal output step of outputting a first synchronization signal which is a signal necessary for establishing synchronization between the data processing systems, and the second data processing system, Using a first synchronization signal receiving step of receiving the first synchronization signal output in the first synchronization signal output step and the first synchronization signal received in the first synchronization signal receiving step, A second synchronization processing step for performing a synchronization processing for the first data processing system; and a second synchronization processing step under the second situation. A second data processing step of processing the provided data according to the synchronization processing according to the above, and a second synchronization signal which is a signal necessary for establishing synchronization between the data processing systems under the first situation. And a second synchronization signal reception step of receiving the second synchronization signal output in the second synchronization signal output step, which is performed in the first data processing system. And a first synchronization processing step of performing a synchronization processing for the second data processing system using the second synchronization signal received in the second synchronization signal reception step; And in a circumstance, the first data processing step of processing the provided data according to the synchronization processing by the first synchronization processing step. Data processing method according to claim is provided.

Here, the first data processing step processes the provided data under the first situation,
The first synchronization signal output step outputs a first synchronization signal, which is a signal necessary for establishing synchronization between the data processing systems under the second situation, and the first synchronization signal reception step includes The first synchronization signal output in the first synchronization signal output step is received, and the second synchronization processing step uses the first synchronization signal received in the first synchronization signal reception step, The synchronization processing for the data processing system is performed, and the second data processing step is
Under the second situation, the provided data is processed according to the synchronization process by the second synchronization process step,
In the first situation, the second synchronization signal output step outputs the second synchronization signal which is a signal necessary for synchronizing the data processing systems, and the second synchronization signal reception step includes the second synchronization signal reception step. The second synchronization signal output in the synchronization signal output step is received, and the first synchronization processing step uses the second synchronization signal received in the second synchronization signal reception step to perform the second data processing. The synchronization processing for the system is performed, and the first data processing step processes the provided data according to the synchronization processing by the first synchronization processing step under the first situation.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a conceptual diagram exemplifying a program distribution system for digital satellite broadcasting in which the data processing device according to the present embodiment is used.

As illustrated in FIG. 1, a program distribution system for digital satellite broadcasting, for example, converts program content into a transport stream (TS: Tansport St).
a plurality of broadcasting stations 1a to 1d provided as a ream), a sending station 2 that multiplex-combines a plurality of transport streams provided from the plurality of broadcasting stations 1a to 1d into one carrier, and a carrier multiplexed by the sending station 2. Has an antenna 3 for transmitting to the broadcasting satellite. Here, the transport stream is, for example, image data or the like that constitutes the program content and is MPEG (Moving P).
image Experts Group) -2 etc. means a set of transport packets (Transport Packets) having information compressed and encoded by a method such as image experts group-2.

The sending station 2 is, for example, each broadcasting station 1a.
A plurality of input boards 2aa to 2ad that receive the input of each transport stream provided from 1d to 1d, a TS combining board 2b that multiplex-combines a plurality of transport streams, and a transmission encoding process of a carrier wave that multiplex-combines a transport stream. It has a transmission path coding device 2c for performing the above, and a modulation / transmission device 2d for performing the modulation and transmission of this carrier wave. As will be described later, each of the input boards 2aa to 2ad is
For example, in order to ensure the reliability of handling the transport stream provided from each broadcasting station 1a to 1d, there are two data processing systems that perform data processing of the provided transport stream. These data processing systems are divided into, for example, a working data processing system used in a normal state and a spare data processing system used when a failure occurs in the working data processing system, and each of the input boards 2aa to 2ad is , The active data processing system and the spare data processing system are automatically switched according to the data processing status in each of the input boards 2aa to 2ad.

In the case of distributing program contents in digital satellite broadcasting, for example, first, each broadcasting station 1a-1d
Provides the sending station 2 with the program content provided by each as a transport stream. Each transport stream provided to the transmission station 2 is acquired by, for example, the input boards 2aa to 2ad, and the input boards 2aa to 2ad are acquired.
~ 2ad to the TS composite substrate 2b. TS
The combining board 2b multiplex-combines the transport streams provided from the respective input boards 2aa to 2ad into one carrier, and provides the carrier to the transmission path encoder 2c. The carrier wave provided to the channel coding device 2c is subjected to channel coding processing such as power spreading, convolutional coding, and puncturing in the channel coding device 2c. After being modulated by 2d, it is output to the broadcasting satellite via the antenna 3.

FIG. 2 is a block diagram illustrating the configuration of the input board 2aa illustrated in FIG. The input board 2aa is
For example, the data processing device corresponds to the data processing device of the present invention, and the data processing is performed when a defect occurs in the data processing in the current device 10 and the current device 10 which is the first data processing system that performs data processing in the normal state. A standby machine 20 which is a second data processing system to perform, a reference clock generator 30 which is a clock providing means for generating a reference clock signal, an input terminal 40 to which a TS signal is input, an active machine 10.
An output terminal 51 for outputting a signal processed in the auxiliary equipment 20 and an output terminal 52 for outputting a signal processed in the standby equipment 20
have.

Here, as illustrated in FIG. 2, the active machine 1
0 is, for example, under the second situation, a driver 11 which is a sync signal output means for outputting a sync signal which is a signal necessary for synchronizing the data processing systems, a CPU 12 which controls the active machine 10, and a sync. A switch 13 that gives a signal output instruction, a synchronization circuit 14 that performs a synchronization process between the active device 10 and the standby device 20, and a first data that processes the provided data under the first condition. It has a signal processing circuit 15 which is a processing means. Further, the standby machine 20 gives, for example, a receiver 21 which is a synchronization signal receiving means for receiving the synchronization signal output from the synchronization signal output means, a CPU 22 which controls the standby machine 20, and an instruction for enabling reception of the synchronization signal. The switch 23 which is the synchronization signal reception permission means, the synchronization circuit 24 which is the synchronization processing means which performs the synchronization processing for the first data processing system by using the synchronization signal received by the synchronization signal reception means, and the second Under the circumstances, it has the signal processing circuit 25 which is the second data processing means for processing the provided data in accordance with the synchronization processing by the synchronization processing means. Here, the first situation means, for example, a situation in which the data in the active machine 10, which is the first data processing system, is normal, and the second situation means the first data processing system. It means a situation in which a defect has occurred in data in a certain active machine 10.

As illustrated in FIG. 2, for example, the reference clock generator 30 is configured so as to be able to provide a clock signal to the synchronizing circuits 14 and 24, and the CPU 12, the synchronizing circuit 14, and the CPU 22 are provided. , And the synchronizing circuit 24, respectively, so that information can be exchanged. Also,
The switch 13 includes a synchronization circuit 14 and a synchronization circuit 14
To the driver 11 and the signal processing circuit 15
1 is a receiver 21, and switch 23 is a synchronization circuit 2
4, the synchronizing circuit 24 is configured to provide information to the signal processing circuit 25, and the receiver 21 is configured to provide information to the synchronizing circuit 24. Further, for example, the input terminal 40
So that the signal processing circuits 15 and 25 can provide the TS signals to the signal processing circuits 15 and 25.
2 are each configured so that a processing signal can be provided.

Although FIG. 2 illustrates only the configuration of the input substrate 2aa, the other input substrates 2ab to 2ad have the same configuration as the input substrate 2aa illustrated in FIG. 2, for example.

FIG. 3 is provided from the broadcasting stations 1a to 1d,
TS signal 100 input to each of the input boards 2aa to 2ad
It is a conceptual diagram which illustrated the data structure of. As illustrated in FIG. 3, the TS signals 100 are, for example, 204b each.
It is composed of a plurality of transport packets 101 to 104 having an information amount of y. The number of each of the transport packets 101 to 104 is determined, for example, by the content of the program content provided by each of the broadcasting stations 1a to 1d.

FIG. 4 is a conceptual diagram illustrating the data structure of the transport packet 101 illustrated in FIG. As illustrated in FIG. 4, the transport packet 101
Is, for example, 1-byte sync word 101a, 18
Main information 101b of 7 bytes, TMC of 8 bytes
C (Transmission add Multip
lexingConfiguration Control
ol: Transmission multiplex control) Basic information 101c and 8 bytes
A total of 204b of the parity (Parity) 101d of e
It is composed of yte.

The sync word 101a is, for example, information for identifying the beginning of each of the transport packets 101 to 104, and the synchronization processing between TS signals is, for example,
It is performed with reference to the detection timing of the sync word 101a. Further, the main information 101b is, for example, information obtained by compressing and encoding image data or the like constituting program content by a method such as MPEG-2, and the TMCC basic information 101c is generated in the transmitting station 2, for example. TMCC (Transmissio), which is information indicating the carrier modulation method, the number of slots, the coding rate, the transmission rate, and the like.
n add Multiplexing Config
means basic information used to generate the Duration Control) information. As long as the TMCC basic information 101c is the same TS signal 100, in principle,
It is assumed that they are composed of common data contents.

Next, the processing operation of the input substrate 2aa in this embodiment will be described. As described above, the TS signal 100 transmitted from the broadcasting station 1a is first input to the input terminal 40 of the input board 2aa of the transmitting station 2, for example. The TS signal 100 input to the input terminal 40 is separated into, for example, two TS signals 100 which are equal to each other, one of the TS signals 100 thus separated is supplied to the signal processing circuit 15 of the active machine 10, and the other is spare. Signal processing circuit 25 of machine 20
, Respectively.

The signal processing circuit 15 to which the TS signal 100 is input performs various processes on the TS signal 100, for example, and outputs the processed TS signal to the output terminal 51.
As the processing performed by the signal processing circuit 15, for example, input monitoring processing, TMCC inspection processing and the like can be exemplified. Here, the input monitoring process is, for example, the transport packets 101 to 1 which form the TS signal 100.
04 means a process for determining whether or not 04 is input to the signal processing circuit 15 at an appropriate cycle, and the specific determination is
Each transport packet 10 based on the sync word 101a of each transport packet 101-104
It is performed by detecting the head portion of 1 to 104 and whether or not the head portion can be detected at a constant cycle. Also, TMC
The C inspection processing is, for example, each transport packet 1
01 to 104 means a process for inspecting whether or not the contents of the TMCC basic information 101c included in each of the transport packets 101 to 104 are specific. 10
The contents of 1c are the transport packets 101 to 104.
Examples include a check as to whether they match each other and a check as to whether or not information such as the number of slots included in the TMCC basic information 101c is correct.

On the other hand, the signal processing circuit 25 to which the TS signal 100 is input also performs various processing similar to that of the above-described signal processing circuit 15 on the input TS signal 100, for example.
The processed TS signal is output to the output terminal 52.

The TS signal 100 output from each of the output terminals 51 and 52 as described above is, for example, input board 2
It is input to an output signal selection device (not shown) of aa, and this output signal selection device outputs the output terminals 51, 52.
Only one of the TS signals 100 respectively input from is selected, and only the selected TS signal is input to the TS synthesis substrate 2b. Usually, this output signal selection device, for example,
TS signal 100 output from the output terminal 51 (active device 1
The TS signal 100 processed by 0) is selected as a signal to be input to the TS synthesis substrate 2b, and the TS signal 100 output from the output terminal 51 is output as an input signal to the TS synthesis substrate 2b (first situation). ). However, for example, the processing in the signal processing circuit 15 described above (input monitoring processing,
As a result of the TMCC inspection process, etc.), when it is detected that the TS signal 100 in the active machine 10 has a defect (second situation), the output signal selection device supplies the TS to the TS synthesis substrate 2b. The processing system of the signal 100 is switched so that the output terminal 52 does not output from the output terminal 51.
The TS signal 100 output from (the TS signal 100 processed by the standby device 20) is selected as a signal to be input to the TS synthesis substrate 2b. By this selection, the output signal selection device causes the TS of the TS signal 100 output from the output terminal 51.
The output to the synthetic substrate 2b is stopped and the output terminal 5 is used instead.
The TS signal 100 output from 2 is output to the TS synthesis substrate 2b.

TS signal 10 by this output signal selection device
When switching the processing system of 0 (switching from the active machine 10 to the standby machine 20), the input board 2aa synchronizes the TS signal 100 output from the active machine 10 with the TS signal 100 output from the standby machine 20. Process. It should be noted that this synchronization processing may occur with switching of the processing system of the TS signal 100, and the TS signal 1 output from the active machine 10 may be generated.
00 and the TS signal 100 output from the standby device 20 are corrected, and a process performed for the purpose of ensuring continuity before and after the switching of the processing system of the TS signal 100 supplied to the TS synthesis substrate 2b. Is. The procedure of this synchronization processing will be described below.

When it is detected as a result of the processing in the signal processing circuit 15 that the TS signal 100 in the active machine 10 is defective, for example, the CPU (not shown) that controls the entire input board 2aa , And gives an instruction signal to the effect that the synchronization processing is performed to the switches 13 and 23 illustrated in FIG. Switch 13 that received this instruction
, For example, instructs the synchronizing circuit 14 to output the synchronizing signal, and the switch 23 gives the synchronizing circuit 24 an instruction to enable reception of the sent synchronizing signal. By these instructions, for example, the synchronization circuit 14 causes the CPU 12
Under the control of, the synchronizing circuit 24 outputs the synchronizing signal.
Under the control of the CPU 22, the T signal 100 output from the signal processing circuit 25 is output to the T signal output from the active machine 10.
Synchronize with the S signal 100. Note that the receiver 21 and the synchronization circuit 24 can receive the synchronization signal output from the driver 11 only when receiving an instruction to enable reception of the synchronization signal sent from the switch 23. By doing so, the synchronization circuit 24
However, it is possible to prevent an erroneous signal such as noise from being erroneously recognized as a synchronization signal and perform an erroneous synchronization process.

FIG. 5 is a timing chart exemplifying how this synchronization processing is performed. As illustrated in FIG. 5, for example, the reference clock generator 30 illustrated in FIG.
Supplies the same clock signals 111 and 122 to the synchronization circuit 14 of the active machine 10 and the synchronization circuit 24 of the standby machine 20.

When the synchronization process is started and the switch 13 instructs the synchronization circuit 14 to output the synchronization signal, the synchronization circuit 14 is controlled by the CPU 12 so that the TS input to the signal processing circuit 15 is controlled. The sync word 101a (FIG. 4) is detected from the signal 100, and the sync word 101a is detected.
With the clue as a clue, the transport packets 101 to 104 that become the synchronization timing (timing A illustrated in FIG. 5) are obtained.
Determine the start position of. In FIG. 5, the basic synchronization signal 11 which is a signal for timing the timing of this head position for timing the data processing in the first data processing system.
Shown as 2.

When the head positions of the transport packets 101 to 104, that is, the basic synchronization signal 112 is detected, then, for example, the synchronization circuit 14 synchronizes at a timing one clock ahead of the basic synchronization signal 112. The driver 11 is instructed to output the signal 113, and the driver 1
In accordance with this instruction, the receiver 1 receives the synchronization signal 113 at a timing one clock ahead of the basic synchronization signal 112.
Output to 1. It should be noted that, for example, it is desirable that the pulse width of the synchronization signal 113 is 2 clocks or more. This is because when the pulse width of the synchronization signal 113 is one clock, attenuation by a cable or IC (Integrated Circu
The variation of (it) causes attenuation, delay, etc. of the synchronization signal 113 output from the active machine 10. Due to these influences, the pulse width of the synchronization signal 121 received by the standby machine 20 is within one clock pulse. This is to prevent the synchronization signal 121 in the standby device 20 from being overlooked without being latched.

Sync signal 11 output from driver 11
For example, 3 is received by the receiver 21 and input to the synchronization circuit 24 (synchronization signal 121). Note that FIG.
Then, the synchronization signal 113 output from the active machine 10 is
An example in which the data is transmitted to the standby device 20 with a delay of 0.5 clocks is shown.

Synchronization circuit 2 to which synchronization signal 121 is input
4, for example, first, under the control of the CPU 22, the synchronization signal 121 is latched at the rising edge of the clock signal 122, and the synchronization processing signal 123 is generated. Synchronized signal 12
3 is generated, for example, next, the synchronization circuit 24
The synchronous processing signal 123 is latched at the rising edge of the clock signal 122 to generate the synchronous processing signal 124. When the synchronization processing signal 124 is generated, for example, next, the generated synchronization processing signal 123 and the inverted signal of the synchronization processing signal 124 are logically ORed to generate the synchronization processing signal 125. The generated synchronization processing signal 125 is latched at the rising edge of the clock signal 122, for example, and the basic synchronization signal 126 illustrated in FIG. 5 is generated.

When the basic synchronization signal 126 is generated in this way, for example, the synchronization circuit 24 causes the basic synchronization signal 1 to be generated.
On the basis of 26, the TS signal 100 output from the signal processing circuit 25 is synchronized with the TS signal 100 output from the signal processing circuit 15. Specifically, the sync word 101a is extracted from the TS signal input to the signal processing circuit 25, and the leading positions of the transport packets 101 to 104 detected with the sync word 101a as a clue are
It is synchronized with the timing of the basic synchronization signal 126.

In this way, when the processing of the TS signal 100 is switched from the active machine 10 to the standby machine 20, the TS signal 100 output from the signal processing circuit 25 of the active machine 10 is transferred from the signal processing circuit 25 of the standby machine 20. Output TS signal 100
By synchronizing with the TS signal 100, it is possible to easily ensure the continuity of the TS signal 100 when the processing system of the TS signal 100 is switched from the active machine 10 to the standby machine 20.

Note that, for example, when the sync signal 113 is output from the active machine 10 to the standby machine 20 as described above, the active machine 1
0, additional data for ensuring the continuity and reliability of the TS signal 100 between the standby device 20 (for example, the active device 10).
Information indicating the number of clock counters, or the change number information indicating the number of changes of the TS signal 100 processed by the active machine 10) is output from the driver 11 of the active machine 10 to the standby machine 20. It may be that. The additional data (counter number information, change number information, etc.) output in this way is received by, for example, the receiver 21 of the standby device 20, and the standby device 20 uses such additional data in The TS signal 100 is processed.

Here, it is desirable that the additional data sent from the active machine 10 to the standby machine 20 have a pulse width of 3 clocks or more. This is to ensure the delivery of the additional data from the active machine 10 to the standby machine 20.

The pulse width of the additional data is preferably a pulse width that is a multiple of 2 with respect to the clock width. This is to reduce the circuit size. in this way,
In this embodiment, the signal processing circuit 15 processes the provided data under the first condition, and the driver 1
1 outputs a synchronization signal, which is a signal required for synchronization between the data processing systems under the second situation, and the receiver 21 receives the synchronization signal output from the driver 11 to synchronize the data. 24 using the synchronization signal received at the receiver 21,
Since the synchronization process for the active machine 10 is performed and the provided data is processed by the signal processing circuit 25 according to the synchronization process by the synchronization circuit 24 under the second situation, the provided TS signal 100 is processed. Even when the data processing system to be processed is switched from the active machine 10 to the standby machine 20, the continuity of the output signal before and after the switching of the data processing system can be ensured.

Further, the standby device 20 can receive the synchronization signal transmitted from the active device 10 only under the second condition by switching the switch 23. Therefore, the standby device 20 occurs in the active device 10. It is possible to prevent a problem that a false signal such as noise is mistakenly recognized as a sync signal and the TS signal is synchronized at a wrong timing.

Further, when synchronizing the active machine 10 and the standby machine 20, the active machine 10 outputs counter number information indicating the number of clock counters in the active machine 10 to the standby machine 20, and the output counter number. Information on standby machine 20
It is possible to match the number of clock counters of the standby device 20 with the number of the active device 10 by receiving the signal at.
As a result, it is possible to make the number of clock counters the same before and after the switching of the data processing system, and it is possible to prevent a situation in which the subsequent process performed using this number of clock counters is disturbed.

When synchronizing the active machine 10 and the standby machine 20, the active machine 10 outputs change number information, which is information indicating the number of changes of the data provided to the active machine 10, to the standby machine 20. Then, by receiving the output change number information in the standby device 20, it is possible to match the change number information of the standby device 20 with the active device 10. As a result, it is possible to match the change count information before and after the switching of the data processing system, and it is possible to prevent a situation in which the subsequent process performed in association with the change count is hindered.

Further, the reference clock generator 30 supplies the same clock to the active machine 10 and the standby machine 20, and a first basic synchronization signal which is a signal for timing the data processing in the active machine 10. A signal output at a timing one clock ahead of the clock provided by the reference clock generator 30 than 112 is used as a synchronization signal, and the synchronization circuit 24 receives the synchronization signal received by the receiver 21 as a reference clock generator. A first synchronization processing signal 123 latched by a clock provided by 30 and a second synchronization processing latched by the clock provided by the reference clock generator 30. The signal 124 is generated, and the generated first synchronization processing signal 123 and the second synchronization processing signal 123 are generated. A third synchronous processing signal 125 is ORed with the inverted signal of the processing signal 124, and the generated third synchronous processing signal 125 is latched by the clock provided by the reference clock generator 30. By generating the second basic synchronization signal 126, even if the synchronization signal 113 output from the active machine 10 is delayed by one clock or less before reaching the standby machine 20, the synchronization signal 113 is generated. It is possible to perform the synchronization processing of the TS signal 100 in the standby device 20 without being affected by the delay of.

Further, by making the synchronization signal 113 a signal having a pulse width of two clocks or more of the clock provided by the reference clock generator 30, attenuation due to the cable, variations in IC, etc. may cause the active machine 10 The sync signal 113 output from the device is attenuated and delayed, and due to these effects, the sync signal 12 received by the standby device 20
It is possible to prevent a situation in which the pulse width of 1 falls within the pulse for one clock and the synchronization signal 121 in the standby device 20 is not latched and is missed.

Furthermore, the first situation is that the data in the active machine 10 is normal, and the second situation is that the data in the active machine 10 has a problem. It is possible to secure the continuity of the output signal before and after the switching of the data processing system, which is performed when the data output from 10 has a problem.

The present invention is not limited to the above embodiment. Next, a second embodiment of the present invention will be described. This embodiment is a modification of the first embodiment, and the switches 13 and 2 as illustrated in FIG.
3 is not provided, which is a difference from the first embodiment. Below, it demonstrates centering around difference with 1st Embodiment, and abbreviate | omits description about the matter common to 1st Embodiment.

FIG. 6 is a block diagram illustrating the configuration of the input substrate 200 in this embodiment. The input board 200 is
For example, the data processing device corresponds to the data processing device in the present invention, and the data processing is performed when a problem occurs in the data processing in the active device 210 and the active device 210, which are the first data processing system that performs data processing in the normal state. A standby device 220 which is a second data processing system to perform, a reference clock generator 230 which is a clock providing means for generating a reference clock signal, an input terminal 240 to which a TS signal is input,
It has an output terminal 251 for outputting a signal processed in the active machine 210 and an output terminal 252 for outputting a signal processed in the standby machine 220.

Here, as illustrated in FIG. 6, the active machine 1
0 has, for example, a driver 211, a synchronization circuit 214, and a signal processing circuit 215, and the standby unit 22.
0 has, for example, a receiver 221, a synchronization circuit 224, and a signal processing circuit 225.

As illustrated in FIG. 6, for example, the reference clock generator 230 is configured so as to be able to provide a clock signal to the synchronization circuits 214 and 224.
14 is the driver 211 and the signal processing circuit 215, and the driver 211 is the receiver 221 and the receiver 221.
Is configured to be able to provide information to the synchronization circuit 224, and the synchronization circuit 224 to the signal processing circuit 225, respectively. In addition, for example, the input terminal 240 can provide the TS signal to the signal processing circuits 215 and 225,
The signal processing circuits 215 and 225 have output terminals 251 and 25, respectively.
2 are each configured so that a processing signal can be provided.

Next, the processing operation of the input substrate 200 in this embodiment will be described. Similar to the first embodiment, the TS signal 100 transmitted from the broadcasting station is, for example,
It is input to the input terminal 240 of the input board 200. The TS signal 100 input to the input terminal 240 is separated into, for example, two TS signals 100 that are equal to each other. To the signal processing circuit 225 of the machine 220.

The signal processing circuit 215 to which the TS signal 100 is input is, for example, as in the first embodiment, this TS.
Various processes are performed on the signal 100, and the processed TS signal is output to the output terminal 251. On the other hand, the signal processing circuit 225 to which the TS signal 100 is input also performs various processes on the input TS signal 100, for example, and outputs the processed TS signal to the output terminal 52.

Similar to the first embodiment, the TS signals 100 output from the output terminals 251 and 252 as described above are input to, for example, an output signal selection device (not shown) included in the input board 200, The output signal selection device selects only one of the TS signals 100 input from the output terminals 251 and 252, and inputs only the selected TS signal to the TS synthesis board. Normally, this output signal selection device is, for example, a TS signal 100 output from the output terminal 251 (TS processed by the active machine 210).
Signal 100) is selected as a signal to be input to the TS synthesis substrate, and the TS signal 10 output from the output terminal 251 is selected.
0 is output as an input signal to the TS synthesis substrate (first situation). However, for example, the above-described signal processing circuit 215
When it is detected that the TS signal 100 in the active machine 210 is defective as a result of the processing (input monitoring processing, TMCC inspection processing, etc.) in step 2 (second situation),
This output signal selection device supplies TS to the TS synthesis substrate.
The processing system of the signal 100 is switched, and the output terminal 25
TS signal 100 output from output terminal 252, not from 1 (TS signal 100 processed by standby unit 220)
Is selected as a signal to be input to the TS synthesis substrate. By this selection, the output signal selection device stops the output of the TS signal 100 output from the output terminal 251 to the TS synthesis board, and instead outputs the TS signal 100 output from the output terminal 252 to the TS synthesis board. To do.

TS signal 10 by this output signal selection device
0 processing system switching (active machine 210 to standby machine 22
(When switching to 0), the input board 200 is
The TS signal 100 output from 10 and the TS signal 100 output from the standby device 220 are synchronized with each other. The synchronization processing in the present embodiment is performed, for example, at every timing when the power of the active device 210 and the standby device 220 is turned on, or in a super frame (SF: Super Frame (B).
S) This is performed for each unit of synthesized wave in digital broadcasting)). Note that details of the synchronization processing in this embodiment are the same as those in the first embodiment, for example, and description thereof is omitted in this embodiment.

As described above, in the present embodiment, the signal processing circuit 215 processes the provided data under the first situation.
In the second situation, the driver 211 outputs a synchronization signal that is a signal necessary for synchronization between the data processing systems, and the receiver 221 receives the synchronization signal output by the driver 211. The synchronization signal received at 221 is used to perform the synchronization processing for the active machine 210.
4 and under the second situation, the synchronization circuit 2
Since the provided data is processed by the signal processing circuit 225 in accordance with the synchronization processing by 24, the data processing system for processing the provided TS signal 100 is switched from the active machine 210 to the standby machine 220. Even in this case, the continuity of the output signal before and after the switching of the data processing system can be ensured.

In this embodiment, for example, the active machine 21
0, every time the power of the standby machine 220 is turned on,
Alternatively, since the synchronization process is always performed for each superframe, a CPU, a switch, etc. for controlling the timing of performing the synchronization process are unnecessary, and the active machine 21
0, the circuit of the standby machine 220 can be simplified.

The present invention is not limited to the above embodiment. Next, a third embodiment of the present invention will be described. This embodiment is also a modification of the first embodiment. Below, it demonstrates centering around difference with 1st Embodiment, and abbreviate | omits description about the matter common to 1st Embodiment.

FIG. 7 is a block diagram illustrating the configuration of the input board 300 in this embodiment. The input board 300 is
For example, the data processing device corresponds to the data processing device in the present invention, and the data processing is performed when a problem occurs in the data processing in the active device 310 and the active device 310 that are the first data processing system that performs data processing in the normal state. A standby device 320 which is a second data processing system to perform, a reference clock generator 330 which is a clock providing means for generating a reference clock signal, an input terminal 340 to which a TS signal is input,
It has an output terminal 351 for outputting a signal processed in the active machine 310 and an output terminal 352 for outputting a signal processed in the standby machine 320.

Here, as illustrated in FIG. 7, the active machine 3
Reference numeral 10 denotes a driver 3 which is a sync signal output means for outputting a first sync signal which is a signal necessary for synchronizing the data processing systems under the second situation, for example.
11, a receiver 316 which is a second synchronization signal receiving means for receiving the second synchronization signal output from the standby device 320,
A CPU 312 that controls the active machine 310, a switch 313 that gives a synchronization signal output instruction, an active machine 310 and a standby machine 3
20 includes a synchronization circuit 314 that performs a synchronization process with the first and second signals and a signal processing circuit 315 that is a first data processing unit that processes the provided data under the first situation. In addition, the standby device 320 receives, for example, a first synchronization signal output from the synchronization signal output means.
321 which is a synchronization signal receiving means of
A CPU 322 for controlling 0, and a switch 3 which is a synchronization signal reception permission means for giving an instruction to enable reception of a synchronization signal.
23, the first received by the first synchronization signal receiving means
The synchronization circuit 3 which is the second synchronization processing means for performing the synchronization processing for the first data processing system using the synchronization signal of
24, under the second situation, the signal processing circuit 325 which is the second data processing means for processing the provided data according to the synchronization processing by the second synchronization processing means, and under the first situation, It has a driver 326 which is a second synchronizing signal output means for outputting a second synchronizing signal which is a signal necessary for synchronizing the data processing systems.

As illustrated in FIG. 7, for example, the reference clock generator 330 is configured so as to be able to provide a clock signal to the synchronizing circuits 314 and 324, and the CPU 312 is provided.
The synchronization circuit 314 and the CPU 322 are configured to exchange information with the synchronization circuit 324. In addition, the switch 313 has a synchronization circuit 314.
The synchronization circuit 314 is used for the driver 311 and the signal processing circuit 315, and the driver 311 is used for the receiver 321.
The receiver 316 includes a synchronization circuit 314 and a switch 32.
3 is the synchronizing circuit 324, the synchronizing circuit 324 is the signal processing circuit 325 and the driver 326, and the driver 326.
Is configured to be able to provide information to the receiver 316 and the receiver 321 to the synchronization circuit 324, respectively. Further, for example, the input terminal 340 can provide the TS signals to the signal processing circuits 315 and 325, and the signal processing circuits 315 and 325 can provide the processing signals to the output terminals 351 and 352. Each is composed.

Next, the processing operation of the input substrate 300 in this embodiment will be described. Similar to the first embodiment, the TS signal 100 transmitted from the broadcasting station is, for example,
It is input to the input terminal 340 of the input board 300. The TS signal 100 input to the input terminal 340 is separated into, for example, two TS signals 100 that are equal to each other. To the signal processing circuit 325 of the machine 320.

The signal processing circuit 315 to which the TS signal 100 is input is, for example, this TS as in the first embodiment.
Various processes are performed on the signal 100, and the processed TS signal is output to the output terminal 351. On the other hand, the signal processing circuit 325 to which the TS signal 100 is input also performs various processes on the input TS signal 100, for example, and outputs the processed TS signal to the output terminal 352.

Similar to the first embodiment, the TS signals 100 respectively output from the output terminals 351 and 352 as described above are input to, for example, an output signal selection device (not shown) included in the input board 300, The output signal selection device selects only one of the TS signals 100 input from the output terminals 351 and 352, and inputs only the selected TS signal to the TS synthesis board. Normally, this output signal selection device is, for example, the TS signal 100 output from the output terminal 351 (TS processed by the active machine 310).
Signal 100) is selected as the signal to be input to the TS synthesis substrate, and the TS signal 10 output from the output terminal 351 is selected.
0 is output as an input signal to the TS synthesis substrate (first situation). However, for example, the signal processing circuit 315 described above is used.
As a result of the processing (input monitoring processing, TMCC inspection processing, etc.) in step 3, it is detected that the TS signal 100 in the active machine 310 has a defect (second situation),
This output signal selection device supplies TS to the TS synthesis substrate.
The processing system of the signal 100 is switched, and the output terminal 35
TS signal 100 output from output terminal 352, not from 1 (TS signal 100 processed by standby device 320)
Is selected as a signal to be input to the TS synthesis substrate. By this selection, the output signal selection device stops the output of the TS signal 100 output from the output terminal 351 to the TS synthesis board, and instead outputs the TS signal 100 output from the output terminal 352 to the TS synthesis board. To do.

TS signal 10 by this output signal selection device
0 processing system switching (active device 310 to standby device 32
(When switching to 0), the input board 300 is
The TS signal 100 output from 10 and the TS signal 100 output from the standby device 320 are synchronized with each other. The synchronization process here is, for example, the same process as the synchronization process in the first embodiment, and the description thereof is omitted in this embodiment.

Further, in the present embodiment, it is possible to perform the synchronization processing when switching the processing system or the like from the standby machine 320 to the active machine 310. It should be noted that the switching of the processing system or the like from the standby device 320 to the active device 310 is performed, for example, when the TS signal in the active device 310 becomes normal (first situation).

In this case, for example, a CPU (not shown) that controls the entire input board 300 gives an instruction signal to the switches 313 and 323 illustrated in FIG. 7 to perform the synchronization process. Upon receiving this instruction, the switch 323, for example, instructs the synchronizing circuit 324 to output a synchronizing signal, and the switch 313 issues an instruction to the synchronizing circuit 314 to enable reception of the transmitted synchronizing signal. give. By these instructions, for example, the synchronization circuit 324 causes the CPU 3
Under the control of 22, the synchronizing signal is output and the synchronizing circuit 3
14 is a signal processing circuit 315 under the control of the CPU 312.
The TS signal 100 output from the backup device 320 is synchronized with the TS signal 100 output from the standby device 320. Note that the receiver 316 and the synchronization circuit 314 can receive the synchronization signal output from the driver 326 only when receiving an instruction to enable reception of the synchronization signal sent from the switch 313. By doing so, it is possible to prevent the synchronization circuit 314 from erroneously recognizing an erroneous signal such as noise as a synchronization signal and performing an erroneous synchronization process. Note that the synchronization processing here is also the same as the synchronization processing in the first embodiment, for example, and description thereof is omitted in this embodiment.

As described above, in the present embodiment, the signal processing circuit 3
The first synchronization signal, which is a signal necessary for processing the provided data under the first condition by the driver 15, and the synchronization between the data processing systems under the second condition by the driver 311. And the receiver 321 receives the first synchronization signal output from the driver 311 and the synchronization circuit 324 uses the first synchronization signal received from the receiver 321 to perform a synchronization process for the active device 310. Then, the driver 326 outputs a second synchronization signal, which is a signal required to synchronize the data processing systems under the first condition, and the receiver 316 outputs the second synchronization signal output by the driver 326. Of the second synchronization signal received at the receiver 316 by the synchronization circuit 314. Is provided by the signal processing circuit 315 to process the provided data according to the synchronization processing by the synchronization circuit 314 under the first condition. Whether the data processing system for processing the TS signal 100 is switched from the active machine 310 to the standby machine 320 or the standby machine 320 is switched to the active machine 310, this data processing system is switched. It is possible to secure the continuity of the output signal before and after.

The present invention is not limited to the above embodiment. Next, a fourth embodiment of the invention will be described. This embodiment is a modification of the third embodiment, and is different from the third embodiment only in that the data processing system can be remotely switched. Below, it demonstrates centering around difference with 3rd Embodiment, and abbreviate | omits description about the matter common to 3rd Embodiment.

FIG. 8 is a block diagram illustrating the configuration of the input substrate 400 in this embodiment. The input board 400 is
For example, a working machine 410 that is a first data processing system that performs data processing in a normal state, a standby machine 420 that is a second data processing system that performs data processing when a problem occurs in data processing in the working machine 410, A reference clock generator 430 which is a clock providing means for generating a reference clock signal, an input terminal 440 to which a TS signal is input,
It has an output terminal 451 for outputting a signal processed in the active machine 410 and an output terminal 452 for outputting a signal processed in the standby machine 420, and via a hub 461,
It is connected so that information can be exchanged with the control device 460 that controls each input board.

The active machine 410, for example, in the second situation, the driver 411 which is the synchronization signal output means for outputting the first synchronization signal which is a signal necessary for synchronizing the data processing systems, and the spare A receiver 416 which is a second synchronization signal receiving means for receiving the second synchronization signal output from the machine 420, and a CPU 4 which controls the active machine 410.
12, a switch 413 for giving an instruction to output a synchronization signal, a synchronization circuit 414 for performing a synchronization process between the active device 410 and the standby device 420, and a first process for processing the provided data under the first situation. And a signal processing circuit 415 which is a data processing means, and an Ethernet I / F 417 for connecting the active device 410 to an Ethernet (registered trademark) configured by a control device 460, a hub 461, and the like. Further, the standby device 420 receives, for example, a receiver 421 that is a first synchronization signal receiving unit that receives the first synchronization signal output from the synchronization signal output unit, a CPU 422 that controls the standby device 420, and a synchronization signal reception. A switch 42 which is a synchronization signal reception permission means for giving an enabling instruction.
3. The synchronization circuit 42 which is the second synchronization processing means for performing the synchronization processing for the first data processing system by using the first synchronization signal received by the first synchronization signal receiving means.
4. Under the second situation, the second processing the provided data according to the synchronization processing by the second synchronization processing means.
The signal processing circuit 425, which is the data processing means, is the second synchronization signal output means that outputs the second synchronization signal that is a signal necessary to establish synchronization between the data processing systems in the first situation. Driver 426 and active machine 4
It has an Ethernet I / F 427 that connects 10 to the Ethernet configured by the control device 460, the hub 461, and the like.

As illustrated in FIG. 8, for example, the reference clock generator 430 is configured so as to be able to provide a clock signal to the synchronization circuits 414 and 424, and has a CPU 412.
Is a synchronization circuit 414 and an Ethernet I / F 417.
The CPU 422 is configured to exchange information with the synchronization circuit 424 and the Ethernet I / F 427. Further, the switch 413 is the synchronization circuit 414, the synchronization circuit 414 is the driver 411 and the signal processing circuit 415, and the driver 411 is the receiver 42.
1, the receiver 416 is connected to the synchronization circuit 414, the switch 423 is connected to the synchronization circuit 424, and the synchronization circuit 424 is connected to the synchronization circuit 424.
Is configured to be able to provide information to the signal processing circuit 425 and the driver 426, the driver 426 to the receiver 416, and the receiver 421 to the synchronization circuit 424. Furthermore, for example, the input terminal 440 can provide the TS signal to the signal processing circuits 415 and 425, and the signal processing circuits 415 and 425 have the output terminals 451 and 425.
Each is configured to be capable of providing a processed signal to 452.

Next, the processing operation of the input substrate 400 in this embodiment will be described. Similar to the first embodiment, the TS signal 100 transmitted from the broadcasting station is, for example,
It is input to the input terminal 440 of the input board 400. The TS signal 100 input to the input terminal 440 is separated into, for example, two TS signals 100 that are equal to each other. To the signal processing circuit 425 of the machine 420.

The signal processing circuit 415 to which the TS signal 100 is input is, for example, similar to the first embodiment, this TS.
Various processes are performed on the signal 100, and the processed TS signal is output to the output terminal 451. On the other hand, the signal processing circuit 425 to which the TS signal 100 is input also performs various processes on the input TS signal 100, for example, and outputs the processed TS signal to the output terminal 452.

As in the first embodiment, the TS signals 100 output from the output terminals 451 and 452 as described above are input to, for example, an output signal selection device (not shown) included in the input substrate 400, The output signal selection device selects only one of the TS signals 100 input from the output terminals 451 and 452, and inputs only the selected TS signal to the TS synthesis board. Normally, this output signal selection device is, for example, the TS signal 100 output from the output terminal 451 (TS processed by the active machine 410).
Signal 100) is selected as the signal to be input to the TS synthesis board, and the TS signal 10 output from the output terminal 451 thereof is selected.
0 is output as an input signal to the TS synthesis substrate (first situation). However, for example, the signal processing circuit 415 described above
As a result of the processing (input monitoring processing, TMCC inspection processing, etc.) in (2), it is detected that the TS signal 100 in the active machine 410 is defective (second situation),
This output signal selection device supplies TS to the TS synthesis substrate.
The processing system of the signal 100 is switched, and the output terminal 45
TS signal 100 output from output terminal 452, not from 1 (TS signal 100 processed by standby unit 420)
Is selected as a signal to be input to the TS synthesis substrate. By this selection, the output signal selection device stops the output of the TS signal 100 output from the output terminal 451 to the TS synthesis board, and instead outputs the TS signal 100 output from the output terminal 452 to the TS synthesis board. To do.

TS signal 10 by this output signal selection device
0 processing system switching (active device 410 to standby device 42
(When switching to 0), the input board 400 is
The TS signal 100 output from 10 and the TS signal 100 output from the standby device 420 are synchronized with each other.

When this synchronization processing is performed, for example, the control device 460 uses the hub 461 and the Ethernet I / F 41.
7 and 427 to the CPUs 412 and 422 to instruct execution of the synchronization process (specifically, for example, TCP
/ IP (Transmission Control)
Protocol / Internet Protoco
l) command etc. are given. With this instruction signal, for example, the synchronization circuit 414 outputs the synchronization signal under the control of the CPU 412, and the synchronization circuit 424 outputs the C signal.
Under the control of the PU 422, the TS signal 100 output from the signal processing circuit 425 is transferred to the T signal output from the active machine 410.
Synchronize with the S signal 100. Note that the receiver 421 and the synchronization circuit 424 can receive the synchronization signal output from the driver 411 only when receiving an instruction to enable reception of the synchronization signal sent from the control device 460. . By doing so, it is possible to prevent the synchronization circuit 424 from erroneously recognizing an erroneous signal such as noise as a synchronization signal and performing an erroneous synchronization process. The details of the synchronization processing here are the same as those in the first embodiment, for example, and the description thereof is omitted in this embodiment.

Further, in the present embodiment, it is possible to perform the synchronization processing when switching the processing system or the like from the standby machine 420 to the active machine 410. It is assumed that the switching of the processing system or the like from the standby device 420 to the active device 410 is performed, for example, when the TS signal in the active device 410 becomes normal (first situation).

Also in this case, for example, the control device 460 is
Via the hub 461 and the Ethernet I / Fs 417 and 427, the CPUs 412 and 422 are given an instruction signal to the effect that the synchronization processing is to be performed. According to this instruction signal, for example, the synchronization circuit 424 outputs the synchronization signal under the control of the CPU 422, and the synchronization circuit 414 outputs the TS signal 10 output from the signal processing circuit 415 under the control of the CPU 412.
0 is synchronized with the TS signal 100 output from the standby device 420. The receiver 416 and the synchronization circuit 414
The driver 426 receives the synchronization signal from the control device 460 only when receiving the instruction to enable reception of the synchronization signal.
It is possible to receive the synchronization signal output from the.
By doing so, it is possible to prevent the synchronization circuit 414 from erroneously recognizing an erroneous signal such as noise as a synchronization signal and performing an erroneous synchronization process. The details of the synchronization processing here are the same as those in the first embodiment, for example, and the description thereof is omitted in this embodiment.

As described above, in the present embodiment, the signal processing circuit 4
The first synchronization signal, which is a signal necessary for processing the provided data under the first condition by the driver 15 and the synchronization between the data processing systems under the second condition by the driver 411. And the receiver 421 receives the first synchronization signal output by the driver 411, and the synchronization circuit 424 uses the first synchronization signal received by the receiver 421 to perform a synchronization process on the active device 410. Then, the driver 426 outputs the second synchronization signal, which is a signal necessary for synchronizing the data processing systems under the first situation, and the receiver 416 outputs the second synchronization signal output by the driver 426. Of the second synchronization signal received at the receiver 416 by the synchronization circuit 414. Was performed by the signal processing circuit 415 to process the provided data according to the synchronization processing by the synchronization circuit 414 under the first condition. Whether the data processing system for processing the TS signal 100 is switched from the active device 410 to the standby device 420 or the standby device 420 is switched to the active device 410, this data processing system is switched. It is possible to secure the continuity of the output signal before and after.

Further, in the present embodiment, since the control device 460 integrally issues an instruction to perform the synchronization processing of the TS signal 100 between the active device 410 and the standby device 420, the management of each input board is performed. It is possible to improve the above convenience.

The present invention is not limited to the above embodiment. For example, in this embodiment, the control device 4
Although the instruction to perform the synchronization processing of the TS signal 100 between the active device 410 and the standby device 420 is collectively performed by the 60, the switches 413 and 423 are used to perform this instruction similarly to the third embodiment. An instruction to perform the synchronization process may be given.

[0098]

As described above, in the data processing device of the present invention, the first data processing means processes the provided data under the first situation, and the synchronization signal output means performs the second processing. Under the above circumstances, a synchronization signal which is a signal required for synchronization between the data processing systems is output, and the synchronization signal receiving means receives the synchronization signal output by the synchronization signal output means, and the synchronization processing means. Synchronizes the first data processing system with the synchronization signal received by the synchronization signal receiving means, and the second data processing means synchronizes with the synchronization processing means under the second situation. Since it was decided to process the provided data according to the processing, even if the data processing system for processing the provided data is switched, It is possible to ensure the continuity of the output signal before and after switching of the over data processing system.

In the data processing method of the present invention, the first
Is a signal necessary for processing the provided data under the first situation by the data processing step of step S4, and under the second situation by the synchronization signal output step for synchronizing the data processing systems. Outputting a synchronization signal, receiving the synchronization signal output in the synchronization signal output step in the synchronization signal reception step, and using the synchronization signal received in the synchronization signal reception step in the synchronization processing step, the first data processing The provided data is processed because the system is synchronized and the second data processing step processes the provided data under the second situation in accordance with the synchronization processing by the synchronization processing step. Even if the data processing system to be It is possible to ensure the continuity of that output signal.

[Brief description of drawings]

FIG. 1 is a conceptual diagram illustrating a digital satellite broadcast program distribution system.

FIG. 2 is a block diagram illustrating a configuration of an input board illustrated in FIG.

FIG. 3 is a conceptual diagram illustrating the data configuration of a TS signal.

FIG. 4 is a conceptual diagram illustrating the data structure of the transport packet illustrated in FIG.

FIG. 5 is a timing chart exemplifying how synchronization processing is performed.

FIG. 6 is a block diagram illustrating the configuration of an input board.

FIG. 7 is a block diagram illustrating the configuration of an input board.

FIG. 8 is a block diagram illustrating the configuration of an input board.

FIG. 9 is a conceptual diagram illustrating a program distribution system in digital satellite broadcasting.

[Explanation of symbols]

2aa-2ad, 200, 300, 400, 511a-
511d ... Input board, 10, 210, 310, 410 ...
Working machine, 20, 220, 320, 420 ... Standby machine, 1
1, 211, 311, 326, 411, 426 ... Driver, 21, 221, 321, 316, 421, 416 ...
Receiver, 13, 23, 313, 323, 413, 42
3 ... switches, 14, 24, 214, 224, 314,
324, 414, 424 ... Synchronizing circuit, 15, 25, 2
15, 225, 315, 325, 415, 425 ... Signal processing circuit, 30, 230, 330, 430 ... Reference clock generator, 111, 122 ... Clock signal, 112, 1
26 ... Basic sync signal, 113, 121 ... Sync signal, 12
3, 124, 125 ... Synchronous processing signal

Claims (16)

[Claims] 1. A data processing device having a plurality of data processing systems, comprising: a first data processing means for processing provided data under a first situation; and a data processing system under a second situation. A first data processing system having a sync signal output means for outputting a sync signal which is a signal required for synchronization between the two; and a sync signal for receiving the sync signal outputted by the sync signal output means. Receiving means, synchronization processing means for performing synchronization processing for the first data processing system using the synchronization signal received by the synchronization signal receiving means, and the synchronization processing under the second situation. A second data processing system having second data processing means for processing the provided data according to the synchronization processing by the means. Data processing device. 2. The second data processing system further includes a synchronization signal reception permission unit that enables reception of the synchronization signal only under the second situation. The described data processing device. 3. The first data processing system further includes counter number information output means for outputting counter number information indicating the number of clock counters in the first data processing system under the second situation. 2. The data processing according to claim 1, wherein the second data processing system further includes a counter number information receiving unit that receives the counter number information output from the counter number information output unit. apparatus. 4. The change in which the first data processing system outputs change number information, which is information indicating the number of changes of the data provided to the first data processing system, in the second situation. A number of times information output means is further included, and the second data processing system further includes a number of times of change information receiving means for receiving the number of times of change information output by the number of times of change information output means. The data processing device according to claim 1. 5. The system further comprises clock providing means for providing the same clock to the first data processing system and the second data processing system, wherein the synchronization signal is the first data processing system. Is a signal output at a timing one clock ahead of the clock provided by the clock providing means with respect to the first basic synchronization signal which is a signal for timing the data processing in the synchronization processing means. A first synchronization processing signal generating means for generating a first synchronization processing signal by latching the synchronization signal received by the synchronization signal receiving means with the clock provided by the clock providing means; The first synchronization processing signal generated by the first synchronization processing signal generating means is provided by the clock providing means. Second synchronization processing signal generation means for generating a second synchronization processing signal latched by the clock, the first synchronization processing signal generated in the first synchronization processing signal generation means, and the first synchronization processing signal Third synchronization processing signal generation means for generating a third synchronization processing signal that is the logical sum of the inversion signal of the second synchronization processing signal generated by the second synchronization processing signal generation means; Second basic synchronization signal generation means for generating a second basic synchronization signal by latching the third synchronization processing signal generated by the third synchronization processing signal generation means with the clock provided by the clock providing means. The data processing device according to claim 1, further comprising: 6. The data processing device according to claim 5, wherein the synchronization signal is a signal having a pulse width of two clocks or more in the clock provided by the clock providing means. 7. The first situation is a situation in which the data in the first data processing system is normal, and the second situation is a problem in the data in the first data processing system. The data processing apparatus according to claim 1, which is a situation. 8. A data processing device having a plurality of data processing systems, comprising: first data processing means for processing provided data under the first situation; and data processing system under the second situation. A first data processing system having a first synchronization signal output means for outputting a first synchronization signal which is a signal required for synchronization between the two; and a first data processing system for outputting the first synchronization signal output means. First synchronization signal receiving means for receiving the first synchronization signal, and the first synchronization signal receiving means for receiving the first synchronization signal.
Second synchronization processing means for performing the synchronization processing for the first data processing system by using the synchronization signal of the second synchronization processing means, and in the second situation, according to the synchronization processing by the second synchronization processing means. A second data processing means for processing the provided data, and a second data processing means for outputting a second synchronization signal which is a signal necessary to establish synchronization between the data processing systems under the first situation. Sync signal output means,
A second data processing system having: a second data processing system, wherein the first data processing system receives the second synchronization signal output from the second synchronization signal output means, Means and said second synchronization signal receiving means receives said second synchronization signal
According to the first synchronization processing means for performing the synchronization processing for the second data processing system by using the first synchronization processing means and the synchronization processing by the first synchronization processing means under the first situation. And a first data processing unit that processes the provided data, and a data processing device. 9. A data processing method for processing provided data, comprising: a first data processing step, performed in a first data processing system, under the first situation, for processing the provided data; Under the second situation,
A synchronization signal output step of outputting a synchronization signal which is a signal necessary for establishing synchronization between data processing systems, and receiving the synchronization signal output in the synchronization signal output step performed in a second data processing system. Using a synchronization signal receiving step, and the synchronization signal received in the synchronization signal receiving step,
A synchronization processing step for performing a synchronization processing for the first data processing system, and a second data for processing the provided data according to the synchronization processing by the synchronization processing step under the second situation. A data processing method comprising: a processing step; 10. A synchronization signal reception permission step, which is performed in the second data processing system, enables the reception of the synchronization signal by the synchronization signal reception step only under the second situation. 10. The data processing method according to claim 9, wherein: 11. A counter number information output step, which is performed in the first data processing system, for outputting counter number information indicating the number of clock counters in the first data processing system under the second situation, The method further comprising: a counter number information receiving step of receiving the counter number information output in the counter number information output step, which is performed in the second data processing system. Described data processing method. 12. The change number information, which is information indicating the number of changes of the data provided to the first data processing system, which is performed in the first data processing system, is output under the second situation. And a change count information receiving step of receiving the change count information output in the change count information output step, which is performed in the second data processing system.
The data processing method according to claim 9, further comprising: 13. The first data processing system and the second data processing system.
A clock providing step of providing the same clock to the data processing system according to the first basic method, wherein the synchronization signal is a signal for timing the data processing in the first data processing system. The synchronization signal is a signal output at a timing one clock ahead of the synchronization signal in the clock provided by the clock providing step, wherein the synchronization processing step includes the synchronization signal received in the synchronization signal receiving step, A first synchronous processed signal generating step of generating a first synchronous processed signal latched by the clock provided by the clock providing step; and the first synchronous processed signal generated in the synchronous processed signal generating step. , To the clock provided by the clock providing step Second synchronization processing signal generating step for generating the second synchronization processing signal latched by the above, the first synchronization processing signal generated in the synchronization processing signal generating step, and the second synchronization processing signal generation A third synchronization processing signal generation step of generating a third synchronization processing signal by ORing the inversion signal of the second synchronization processing signal generated in step; and the third synchronization processing signal generation. A second basic synchronization signal generation step of generating a second basic synchronization signal by latching the third synchronization processing signal generated in the step by the clock provided by the clock providing step, The data processing method according to claim 9, which is characterized in that. 14. The data processing method according to claim 13, wherein the synchronization signal is a signal having a pulse width of two clocks or more in the clock provided by the clock providing step. 15. The first situation is a situation in which data in the first data processing system is normal, and the second situation is a problem in data in the first data processing system. The data processing method according to claim 9, which is a situation. 16. A data processing method having a plurality of data processing systems, comprising: a first data processing step performed in the first data processing system under the first situation, for processing the provided data; Under the second situation,
A first synchronization signal output step of outputting a first synchronization signal which is a signal required for synchronization between data processing systems, and a first synchronization signal output step performed in a second data processing system A first synchronization signal receiving step of receiving the first synchronization signal output in step 1), and the first data processing system using the first synchronization signal received in the first synchronization signal receiving step A second synchronization processing step for performing a synchronization processing for the second data processing and a second data processing for processing the provided data according to the synchronization processing by the second synchronization processing step under the second situation. Step and the first
A second synchronization signal output step of outputting a second synchronization signal that is a signal required for synchronization between the data processing systems under the above conditions; and the first data processing system, A second synchronization signal receiving step of receiving the second synchronization signal output in the second synchronization signal output step, and the second synchronization signal received in the second synchronization signal receiving step, Processing a provided data according to a first synchronization processing step of performing a synchronization processing for a second data processing system, and in the first situation, according to the synchronization processing of the first synchronization processing step; And a first data processing step of: