JP2003068877A - Semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device which enables dynamic storing of data with less number of signal lines using a simplified transistor structure as a memory cell. SOLUTION: A one-bit memory cell MC is formed of a MOS transistor having a floating bulk region which is electrically isolated from the other circuits and is composed of a p-type silicon layer 12 of the SOI structure. The gate electrode 13 of MOS transistor is connected to the word line WL, while the drain diffusion layer 14 is connected to the bit line BL and the source diffusion layer 15 is connected to the fixed potential line, respectively. A first threshold state which implants and holds a number of carriers generated by impact ionization in the bulk region 12 of MOS transistor and a second threshold state which discharges a number of carriers in the bulk region 12 of the MOS transistor by a bias in the forward direction of a pn connection at the drain side are stored as the binary data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device (DRAM).

[0002]

2. Description of the Related Art In a conventional DRAM, a memory cell is composed of a MOS transistor and a capacitor. DR
The miniaturization of AM has been greatly advanced by adopting a trench capacitor structure or a stacked capacitor structure. Current,
The size (cell size) of the unit memory cell is reduced to an area of 2F × 4F = 8F ^{2 with} the minimum processing dimension being F. That is, the minimum processing dimension F decreases with generation, and when the cell size is generally αF ² , the coefficient α also decreases with generation, and at the present time of F = 0.18 μm, α = 8.
Has been realized.

In order to secure the same trend in cell size or chip size as in the past, F <0.
At 18 μm, α <8, and at F <0.13 μm, α
It is required to satisfy <6, and how to form the cell size in a small area becomes a major issue with fine processing. Therefore, various proposals have been made to make the memory cell of 1 transistor / 1 capacitor to have a size of 6F ² or 4F ² . However, it is not easy to put it into practical use due to technical difficulties such as the need to make the transistor vertical, the problem of increased electrical interference between adjacent memory cells, and the difficulties in manufacturing technology such as processing and film formation. Absent.

On the other hand, there have been some proposals of DRAMs which use one transistor as a memory cell without using a capacitor as described below. JOHN E.LEISS et al, "dRAM Design Using the Taper-
Isolated Dynamic Cell "(IEEE JOURNAL OF SOLID-STATE
CIRCUITS, VOL.SC-17, NO.2, APRIL 1982, pp337-344) Japanese Patent Laid-Open No. 3-171768 Marnix R. Tack et al, "The Multistable Charge-Cont
rolled Memory Effect in SOI MOS Transistors at Low
Temperatures "(IEEE TRANSACTIONS ON ELECTRONDEVICE
S, VOL.37, MAY, 1990, pp1373-1382) Hsing-jen Wann et al, "A Capacitorless DRAM Cell
on SOI Substrate "(IEDM93, pp635-638)

[0005]

The memory cell of the present invention is formed by using a MOS transistor having a buried channel structure. The parasitic transistor formed in the tapered portion of the element isolation insulating film is used to charge and discharge the surface inversion layer to perform binary storage. The memory cell of (1) uses MOS transistors whose wells are individually separated, and the threshold value determined by the well potential of the MOS transistors is used as binary data.
The memory cell of is composed of a MOS transistor on the SOI substrate. A large negative voltage is applied from the side of the SOI substrate to utilize hole accumulation in the oxide film of the silicon layer and the interface portion, and binary storage is performed by emitting and injecting this hole. The memory cell of is composed of a MOS transistor on the SOI substrate. Although there is one MOS transistor in terms of structure, an opposite conductivity type layer is formed so as to overlap the surface of the drain diffusion layer, and a writing PMOS transistor and a reading NMOS transistor are substantially combined together. The substrate region of the NMOS transistor is used as a floating node to store binary data according to its potential.

However, since the structure is complicated and the parasitic transistor is used, there is a problem in controllability of characteristics. Has a simple structure, but it is necessary to connect both the drain and source of the transistor to the signal line to control the potential. In addition, because of the well separation, the cell size is large and rewriting cannot be performed for each bit. However, since the potential control from the SOI substrate side is required, rewriting cannot be performed for each bit, and controllability is difficult. Requires a special transistor structure, and the memory cell requires a word line, a write bit line, a read bit line, and a purge line, so that the number of signal lines increases.

It is an object of the present invention to provide a semiconductor memory device having a simple transistor structure as a memory cell, which enables dynamic data storage with a small number of signal lines, and a manufacturing method thereof.

[0008]

In a semiconductor memory device according to the present invention, a memory cell is composed of a transistor formed in a floating semiconductor layer electrically isolated from other memory cells. The transistor has a drain and a source diffusion layer formed in a semiconductor layer separated from each other, and a gate electrode formed on the semiconductor layer between these drain and source diffusion layers via a gate insulating film, The gate electrode is connected to the word line, the drain diffusion layer is connected to the bit line, and the source diffusion layer is connected to the fixed potential line. The transistor has a first data state having a first threshold voltage in which excess majority carriers are retained in the semiconductor layer and a second data state having a second threshold voltage in which excess majority carriers in the semiconductor layer are released. Dynamically store two data states.

In the present invention, more specifically, the first
The data state is written by operating the transistor to cause impact ionization in the vicinity of the drain junction and holding excess majority carriers generated in the semiconductor layer, and the second data state is written in the semiconductor layer and the drain diffusion layer. Writing is performed by applying a forward bias between and to draw excess majority carriers of the semiconductor layer into the drain diffusion layer.

In the present invention, the semiconductor layer is preferably a silicon layer formed on a silicon substrate via an insulating film. Further, in this case, more preferably, the silicon layer is p-type and the transistor is an N-channel MOS transistor.

In the semiconductor memory device according to the present invention, when writing data, the fixed potential line is used as a reference potential, a first potential higher than the reference potential is applied to the selected word line, and a second potential lower than the reference potential is applied to the non-selected word line. A potential is applied, and a third potential higher than the reference potential and a fourth potential lower than the reference potential are applied to the bit line according to the first and second data states, respectively. As a result, in the selected cell to which the first data is applied from the bit line, the transistor operates as a pentode, impact ionization occurs in the semiconductor layer near the drain junction, and excess holes generated are injected into the semiconductor layer. Retained. Further, in the selected cell to which the second data is applied, a forward bias is applied between the drain diffusion layer and the semiconductor layer, and excess holes in the semiconductor layer are emitted to the drain diffusion layer.

In the data reading, a potential higher than a reference potential between the first threshold voltage and the second threshold voltage is applied to the selected word line, and conduction or non-conduction of the selected memory cell is detected. The method of doing is used. Alternatively, a potential higher than the first and second threshold voltages and higher than the reference potential may be applied to the selected word line to detect the conductivity of the selected memory cell.

In the semiconductor memory device according to the present invention, the transistors are arranged in a matrix with a cell size of 2F × 2F, where F is the minimum processing size, to form a memory cell array.

According to the present invention, one memory cell is
It is formed by one simple transistor having a floating semiconductor layer as a bulk region (channel body), and the cell size can be reduced to 4F ² . The source of the transistor is connected to a fixed potential line, and read, rewrite and refresh are performed only by controlling the bit line connected to the drain and the word line connected to the gate electrode without controlling the back gate bias to the semiconductor layer. Is controlled. That is, the data can be rewritten in arbitrary bit units. Further, since the memory cell according to the present invention is basically nondestructive read, it is not necessary to provide a sense amplifier for each bit line. In other words, the sense amplifier is not provided for all the memory cells selected simultaneously by the word line. It is not necessary to provide it, and therefore the layout of the sense amplifier is easy. Furthermore, since the memory cell is a current read type, it has excellent noise resistance and an open bit line system can be used.

In the memory cell according to the present invention, it is preferable to store a high threshold voltage state and a low threshold voltage state, which are binary data, in a state where the difference between the threshold voltages is large. Further, since the data is held as the charge storage state of the floating semiconductor layer, it is desired that the leak current is as small as possible. As a preferable structure for satisfying these requirements, the semiconductor layer serving as the bulk region is arranged in the first impurity-added region in contact with the drain and source diffusion layers and in the central portion in the channel length direction away from the drain and source diffusion layers. And a second impurity-added region having a higher impurity concentration than the first impurity-added region thus formed. More preferably, at least the drain diffusion layer of the drain and source diffusion layers is located at a position apart from the third impurity addition region forming a pn junction in contact with the first impurity addition region and the first impurity addition region. A structure having a fourth impurity added region having a higher impurity concentration than the formed third impurity added region is formed.

The method of manufacturing a semiconductor memory device according to the present invention for forming a memory cell having a high-concentration layer in the center of the bulk region is a first conductive film formed on a semiconductor substrate and separated by an insulating film. Forming a mask having an opening in the gate electrode formation region on the mold semiconductor layer,
Forming a sidewall insulating film on the sidewall of the opening of the mask;
A step of introducing an impurity into the semiconductor layer through an opening of the mask to form a first-conductivity-type impurity-added layer with a higher impurity concentration than that of the semiconductor layer; And a step of forming a second conductivity type drain and source diffusion layer by introducing impurities into the semiconductor layer after the mask is removed. Prepare

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a DRA according to the present invention.
FIG. 2 shows a sectional structure of an M unit memory cell, and FIG. 2 shows its equivalent circuit. The memory cell MC has an SOI structure of N.
It is composed of a channel MOS transistor. That is, the SOI substrate in which the silicon oxide film 11 is formed as the insulating film on the silicon substrate 10 and the p-type silicon layer 12 is formed on the silicon oxide film 11 is used.
A gate electrode 13 is formed on a silicon layer 12 of this substrate via a gate oxide film 16, and n-type source / drain diffusion layers 14 and 15 are formed in self alignment with the gate electrode 13.

The source / drain diffusion layers 14 and 15 are formed so as to reach the bottom silicon oxide film 11. Therefore, in the bulk region made of the p-type silicon layer 12, if the oxide film is used to separate in the channel width direction (direction orthogonal to the paper surface of the drawing), the bottom surface and the side surface in the channel width direction are insulated and separated from each other. In the channel length direction, a pn junction is separated to be in a floating state. This memory cell M
When Cs are arranged in a matrix, the gate electrode 13 is connected to the word line WL, the source diffusion layer 15 is connected to the fixed potential line (ground potential line), and the drain diffusion layer 14 is connected to the bit line BL.

FIG. 3 shows a layout of the memory cell array, and FIGS. 4 (a) and 4 (b) respectively show AA 'and FIG.
The BB 'cross section is shown. The p-type silicon layer 12 is patterned into a lattice by embedding the silicon oxide film 21. That is, the regions of the two transistors sharing the drain are arranged in the word line WL direction with element isolation by the silicon oxide film 21. Or silicon oxide film 2
Instead of burying 1, the silicon layer 12 may be etched to perform lateral element isolation. The gate electrode 13 is continuously formed in one direction, and this becomes the word line WL. The source diffusion layer 15 is a word line WL
Are formed continuously in the direction, and this becomes a fixed potential line (common source line). The transistor is covered with an interlayer insulating film 23, and the bit line BL is formed thereon. Bit line BL
Is a drain diffusion layer 14 shared by two transistors.
And is arranged so as to intersect with the word line WL.

As a result, the bottom surface and the side surface in the channel width direction of the silicon layer 12 which is the bulk region (channel body) of each transistor are separated from each other by the oxide film.
In the channel length direction, they are separated from each other by a pn junction and kept in a floating state. In this memory cell array configuration, assuming that the word lines WL and the bit lines BL are formed at the pitch of the minimum processing dimension F, the unit cell area is 2F × 2F = 4F ² as shown by the broken line in FIG.

DRA composed of this NMOS transistor
The operating principle of the M cell utilizes the accumulation of holes, which are the majority carriers, in the bulk region of the MOS transistor (the p-type silicon layer 12 that is isolated from the others). That is, by operating the MOS transistor in the pentode region, a large current is caused to flow from the drain diffusion layer 14 to cause impact ionization in the vicinity of the drain diffusion layer 14. Holes, which are excess majority carriers generated by this impact ionization, are held in the p-type silicon layer 12, and the hole accumulation state (state in which the potential is higher than the thermal equilibrium state) is, for example, data “1”. The state in which the pn junction between the drain diffusion layer 14 and the p-type silicon layer 12 is forward biased and excess holes of the p-type silicon layer 12 are emitted to the drain side is set as data “0”.

The data "0" and "1" are differences in the potentials of the bulk regions and are stored as differences in the threshold voltages of the MOS transistors. That is, the threshold voltage Vth1 in the data "1" state in which the potential of the bulk region is high due to hole accumulation.
Is lower than the threshold voltage Vth0 in the data “0” state. In order to hold the "1" data state in which holes, which are majority carriers, are accumulated in the bulk region, it is necessary to apply a negative bias voltage to the word line. This data holding state does not change even if a read operation is performed unless a reverse data write operation (erase) is performed. That is, unlike a 1-transistor / 1-capacitor DRAM that utilizes charge storage of a capacitor, non-destructive read is possible.

There are several possible data reading methods. The relationship between the word line potential Vwl and the bulk potential VB is as shown in FIG. 5 in relation to the data "0" and "1".
Therefore, the first method of reading data is that the threshold voltage Vth of data “0” and “1” is applied to the selected word line WL.
By giving a read potential in the middle of 0 and Vth1,
It is utilized that no current flows in the memory cell of “0” data and current flows in the memory cell of “1” data. Specifically, for example, the bit line BL is precharged to a predetermined potential VBL, and then the word line WL is driven. As a result, as shown in FIG. 6, the bit line precharge potential VBL does not change in the case of "0" data, and the precharge potential VBL decreases in the case of "1" data.

In the second reading method, after the selected word line WL is raised, a current is supplied to the bit line BL to raise the bit line potential in accordance with the conductivity of "0" or "1". Take advantage of the different speeds. Briefly, bit line B
L is precharged to 0V, the word line WL is raised to a potential higher than the threshold voltage of "0" data as shown in FIG. 7, and the bit line current is supplied. At this time, the data can be discriminated by detecting the difference in the potential rise of the bit line by using the dummy cell.

The third reading method is a method of reading the difference between different bit line currents between "0" and "1" when the bit line BL is clamped to a predetermined potential. That is, the selected word line is raised to a potential higher than the threshold voltage of "0" data, and then a current is supplied to the bit line via the clamp circuit. Data can be determined by detecting the difference between different bit line currents of "0" and "1" when the potential of the bit line BL is clamped. A current-voltage conversion circuit is required to read out the current difference, but finally the potential difference is differentially amplified and a sense output is output.

In the present invention, in order to selectively write "0" data, that is, in excess of only the bulk region of the memory cell selected by the potentials of the word line WL and the bit line BL selected in the memory cell array. Capacitive coupling between the word line WL and the bulk region is essential for releasing holes. As will be described later in detail, when holes are accumulated in the bulk region with data “1”, the word line is sufficiently biased in the negative direction so that the gate-substrate capacitance of the memory cell becomes equal to the gate oxide film capacitance. It is necessary to maintain the above state (that is, the state in which the depletion layer is not formed on the surface). Further, in the write operation, it is preferable that both “0” and “1” be pulse write to reduce power consumption. At the time of writing “0”, a hole current flows from the bulk region of the select transistor to the drain and an electron current flows from the drain to the bulk region, but holes are not injected into the bulk region.

A more specific operation waveform will be described. Figure 8 ~
FIG. 11 shows operation waveforms of read / refresh and read / write in the case of using the first read method in which data is discriminated by the presence / absence of discharge of the bit line by the selected cell. 8 and 9 show "1" data and "0", respectively.
This is a data read / refresh operation. Up to time t1, the data holding state (non-selected state), and the word line WL is given a negative potential. At time t1, the word line WL is raised to a predetermined positive potential. At this time, the word line potential is "0", "1" data threshold values Vth0, Vt.
Set during h1. As a result, in the case of "1" data, the pre-charged bit line VBL becomes low potential due to discharge. In the case of "0" data, the bit line potential VBL is held. As a result, "1" and "0" data are discriminated.

Then, at time t2, the potential of the word line WL is further increased, and at the same time, when the read data is "1", a positive potential is applied to the bit line BL (FIG. 8), and the read data is "0". In that case, a negative potential is applied to the bit line BL (FIG. 9). As a result, when the selected memory cell has "1" data, a large channel current flows due to the pentode operation, impact ionization occurs, excess holes are injected and held in the bulk region, and "1" data is written again.
In the case of "0" data, the drain junction is forward biased, and "0" data in which excess holes are not held in the bulk region is rewritten.

Then, at time t3, the word line WL is biased in the negative direction to complete the read / refresh operation. In another unselected memory cell connected to the same bit line BL as the memory cell from which the "1" data is read, the word line WL is held at a negative potential, and thus the bulk region is held at a negative potential, and impact ionization does not occur. In other non-selected memory cells connected to the same bit line BL as the memory cell from which "0" data is read, the word line WL is still held at a negative potential, and hole emission does not occur.

10 and 11 show read / write of "1" data and "0" data respectively by the same read method.
It is a write operation. The read operation at time t1 in FIGS. 10 and 11 is the same as that in FIGS. 8 and 9, respectively.
After reading, at time t2, the word line WL is set to a higher potential, and when writing "0" data to the same selected cell, a negative potential is applied to the bit line BL at the same time (FIG. 10) and "1".
When writing data, a positive potential is applied to the bit line BL (FIG. 11). As a result, in the cell to which "0" data is applied, the drain junction becomes forward biased, and holes in the bulk region are emitted. In the cell to which “1” data is given, impact ionization occurs near the drain, and excess holes are injected and held in the bulk region.

In FIGS. 12 to 15, the second read is performed in which the bit line BL is precharged to 0V, a current is supplied to the bit line BL after the word line is selected, and data is discriminated by the potential rising speed of the bit line BL. Lead when using the method /
It is an operation waveform of refresh and read / write. 12 and 13 show read / refresh operations of "1" data and "0" data, respectively. The word line WL held at the negative potential is raised to the positive potential at time t1. At this time, the word line potential is as shown in FIG.
It is set to a value higher than any of the threshold values Vth0 and Vth1 of "0" and "1" data. Alternatively, the word line potential may be set between the threshold values Vth0 and Vth1 of the “0” and “1” data, as in the first reading method. Then, at time t2, a current is supplied to the bit line. As a result, in the case of "1" data, the memory cell is deeply turned on and the potential rise of the bit line BL is small (FIG. 12).
In the case of “0” data, the current of the memory cell is small (or no current flows) and the bit line potential rises rapidly. As a result, "1" and "0" data are discriminated.

Then, at time t3, when the read data is "1", a positive potential is applied to the bit line BL (FIG. 12), and when the read data is "0", the bit line BL.
A negative potential is applied to (FIG. 13). As a result, when the selected memory cell has "1" data, a drain current flows and impact ionization occurs, excess holes are injected and held in the bulk region, and "1" data is written again.
In the case of "0" data, the drain junction is forward biased, and "0" data without excess holes is rewritten in the bulk region. At time t4, the word line WL is biased in the negative direction, and the read / refresh operation ends.

14 and 15 show read / write of "1" data and "0" data by the same read method, respectively.
It is a write operation. The read operations at times t1 and t2 in FIGS. 14 and 15 are the same as those in FIGS. 12 and 13, respectively. After reading, when writing "0" data in the same selected cell, a negative potential is applied to the bit line BL (FIG. 14), and when writing "1" data, the bit line BL is written.
A positive potential is applied to (FIG. 15). As a result, in the cell to which "0" data is applied, the drain junction becomes forward biased, and excess holes in the bulk region are emitted.
In the cell to which “1” data is given, a large drain current flows, impact ionization occurs near the drain, and excess holes are injected and held in the bulk region.

As described above, the DRAM cell according to the present invention
Is a floating bulk that is electrically isolated from the others
It consists of a simple MOS transistor with a region,
4F ²A cell size of is feasible. Also, float
The potential control of the bulk region of the gate is controlled by the capacitance from the gate electrode.
It uses the quantity coupling, and for example,
The clock gate control is not used. Fixed source diffusion layer
It is a potential. In other words, read / write control
It is simple because it is performed only with the line WL and the bit line BL. Change
Since memory cells are basically nondestructive read,
It is not necessary to provide a sense amplifier for each bit line,
Layout is easy. Further current reading method
Therefore, it is resistant to noise, for example, open bit line
It is also possible to read by the method. Also, the memory cell
The manufacturing process is also simple.

Further, the SOI structure is based on future logic LS.
This is an important technology when considering the performance improvement of I. The DRAM according to the present invention is a logic L having such an SOI structure.
It is also very promising when mixed with SI. Unlike conventional DRAMs that use capacitors, logic LSIs
This is because the manufacturing process is simplified without the need for a process different from the above process.

Further, the DRA of the SOI structure according to the present invention
M is a conventional 1-transistor / 1-capacitor type DRA
Compared to the case where M has an SOI structure, there is an advantage that excellent memory retention characteristics can be obtained. That is, if the conventional 1-transistor / 1-capacitor type DRAM has an SOI structure, holes are accumulated in the floating semiconductor bulk, the threshold value of the transistor is lowered, and the subthreshold current of the transistor is increased. This deteriorates the memory retention characteristic. On the other hand, in the memory cell having only one transistor according to the present invention, there is no transistor path for reducing the storage charge, and the data retention characteristic is purely pn.
The problem of subthreshold leakage is eliminated because it is determined only by junction leakage.

Whether or not the memory cell according to the present invention can actually be used for practical purposes is determined by the following criteria. (A) Whether the hole retention characteristics in the bulk region are sufficient (1
Whether a holding time of about 0 sec can be obtained). (B) Whether or not a sufficient "1" write speed can be obtained (whether a write speed of 10 nsec is possible, 2
Whether a bulk current of about 0 nA or more can be obtained). (C) Sufficient "0" write selectivity (whether a difference ΔVB = 1V or so between bulk potentials of "0" data and "1" data is obtained). (D) Whether the capacitance between the gate and the bulk region can be made sufficiently larger than the pn junction capacitance, and whether the threshold value of "1" data can be made large. Below, these criteria will be verified.

[Capacity / Holding Time / Leakage Current of Memory Cell] It is considered that the average value of the memory holding time of the memory cell of the DRAM having 1 G memory cells is RT = 10 sec. If the gate oxide film thickness of the memory cell is set tox = 2.5 nm according to the 0.1 μm rule, the gate oxide film capacitance is
Since it is 14 fF / cm ² , the gate area is 0.01 μm.
As m ^2, the gate oxide film capacitance Cox is, Cox = 0.
It becomes 14 fF. A pn junction capacitance Cj = 0.
Including 08fF, the total capacity is Ctotal = 0.22.
It becomes fF.

When electric charges are accumulated in this gate capacitance, the leak current Ileak / node per cell that causes a potential change of ΔV = 0.1V during the memory retention time RT = 10 sec.
Is the following formula 1.

[0040]

[Equation 1] Ileak / node = Ctotal · ΔV / RT =
2.2 × 10 ^-18 A / node

The thickness of the silicon layer on the SOI substrate is 100
nm, the pn junction area is 0.1 μm × 0.1 μm
Since x2 = 0.02 μm ² , the leak current Ileak / area per unit area is calculated as the following formula 2.

[0042]

[Equation 2] Ileak / area = 2.2 × 10 ⁻¹⁸ /0.02=
1.1 x 10 ^-16 A / μm ²

If the leak current of the pn junction on the SOI substrate at the time of reverse bias of about 2 V is less than this level, the storage retention time RT = 10 sec of the average cell is guaranteed, and 1 transistor / 1 capacitor is guaranteed. A memory retention characteristic similar to that of DRAM can be obtained. Incidentally, so far, the leakage current of the pn junction on the SOI substrate is 1 to 3 × 10 ⁻¹⁷ A / μm (1 μm in the word line direction).
A value of (per m) has been reported (1995 Sym
p. VSLI Tech. , P. 141). From now on, it seems that the above memory retention characteristics can be sufficiently realized.

["1" Writing Time and Bulk Current] The writing time is determined by the capacitance of the cell node (gate) and the bulk current Isub. As described above, the gate capacitance is Cto
Let tal = 0.22 fF. Write time specification is t
With wr = 10 nsec, the bulk current required to write a voltage of ΔV = 1 V in the bulk region within this time is
The following formula 3 is obtained.

[0045]

[Equation 3]

Assuming that the drain current Ids flowing through the channel of the cell transistor is 10 μA, the above bulk current Is
ub is about 2/1000 of that. If a drain-source voltage Vds = 2 V is applied to cause impact ionization, a necessary bulk current can be passed.

[Selectivity and Signal Amount for Writing "0"] C-V curve of memory cell (voltage Vgb between gate and bulk)
And the capacitance Cgb) are as shown in FIG. With the acceptor concentration in the bulk region being NA = 10 ¹⁸ / cm ³ ,
The flat band voltage is VFB = -1.2V. Assuming that "1" is written at the word line voltage Vwl = 1V (bulk potential VB = 0.6V), the word line potential is lowered after the writing, and the capacitance is initially shielded by the channel inversion layer. Cgb is zero. Assuming that the threshold value of the "1" cell is Vth1 = 0V,
Even if the word line potential is lowered to 0V, the bulk potential VB does not change, and the capacitance Cgb becomes apparent when the word line potential is the threshold voltage Vth1, that is, Vwl = 0V. At this time, the gate-bulk voltage is Vgb = -0.6V.

The capacitance per unit area of the pn junction is NA = 10 ¹⁸ / cm ³ , and the drain voltage Vd = 0V.
In the case of, it is 4 fF / μm ² . Bonding area is 0.1 μm
In the case of × 0.1 μm × 2 = 0.02 μm ² , the capacitance of the pn junction is Cj = 0.08 fF. In FIG.
Assuming that Cgb / Cox at Vgb = -0.5V is 0.8, the capacitive coupling ratio λ of the gate voltage to the bulk region is given by the following Expression 4 when Cox = 0.14fF.

[0049]

[Equation 4] λ = Cgb / (Cgb + Cox) = 0.14 x 0.8 / (0.14 x 0.8 + 0.08) = 0.58

Therefore, when the potential of the word line decreases and the capacitance Cgb between the gate and the bulk begins to be seen, the ratio of the potential change in the bulk region to the potential change in the word line is:
It is about 60%. When the word line potential is further lowered, the bulk potential is also lowered, but Vgb becomes larger than -0.5V on the negative side. Along with this, the capacitance Cgb increases, and the bulk potential can be lowered by capacitive coupling. Finally, as shown in FIG. 16, the word line potential Vwl
= −1.3V, and assuming that the average capacitive coupling ratio λ is 0.6, the bulk region is changed from the first 0.6V to
ΔVB = 1.3V × 0.6 = 0.78V lower,
It becomes 0.18V. At this time, Vgb = -1.12V.

That is, when "1" data is written so that the bulk potential becomes VB = 0.6V by injecting excess holes and then the word line potential is set to Vwl = -1.3V to hold the data, the bulk potential is capacitively coupled. Is -0.18V
Hold. In this state, when the bit line potential of a certain selected cell is lowered to a negative potential and "0" is written to lower the bulk potential, the word line potential is -1. Even in a non-selected cell of 3V, bulk holes flow to the drain, and the data is destroyed. Therefore, the minimum value of the bulk potential at the time of writing "0" data is -0.
It will be 18V. The maximum value of the write voltage of the “1” data is the built-in voltage of 0.6V, and therefore the maximum value of the signal amount is 0.6V − (− 0.18V) = 0.78.
It becomes V. Therefore, the above-mentioned ΔVB itself becomes a signal amount difference (bulk potential difference) between “0” data and “1” data.

[Confirmation of Non-Destructive Readability] As described above, the memory cell according to the present invention is non-destructive read in principle. In order to actually guarantee the non-destructive read, (1) hole injection is not performed in the bulk region even if the read operation is repeated for the “0” data cell,
(2) It is necessary to confirm that the holes in the bulk region are not lost even if the read operation is repeated for the cells of "1" data.

Maximum value Nmax of the number of repetitions at this time
Is between one refresh and the next (eg 12
In 8 msec, the read operation (10
0 nsec) corresponds to the case where Nma is continuous.
x = 128 msec / 100 nsec = 1.28 × 10
It will be about ¹⁶ times. It is considered that the non-destructiveness (1) of "0" data that holds the bulk hole accumulation state becomes more critical. Therefore, even if the current is passed during reading,
For example, it may be necessary to read in a low current linear region at about Vds = 0.5V. Alternatively, it is preferable to employ a method in which no current flows in the cell of “0” data, like the first reading method described above, in order to guarantee nondestructiveness.

In the above, the judgment criteria showing the basic feasibility of the DRAM according to the present invention have been verified. Next, the results of further analysis of the performance of the DRAM according to the present invention will be sequentially described.

[Regarding Bit Line Potential Change During Reading] First, the bit line potential change during the second reading method described in FIGS. 12 and 13, that is, when reading is performed by supplying a constant current to the bit line. To verify. FIG. 17 is an equivalent circuit used for this verification. For the sake of simplicity, the potential of the bit line BL is precharged to 0V, and the potential Vwl of the word line WL is t> 0, and the threshold Vth (Vth (Vth
0, Vth1) or more.

[0056]

[Formula 5] Vwl> Vth

The bit line BL has Ic at t> 0.
The following constant current is supplied, and this current Ic is
As shown in the following Equation 6, Vgs = V of the cell transistor
It is smaller than the saturation current Idsat at wl.

[0058]

## EQU6 ## Ic <Idsat = (k / 2) (Vwl-Vth) ² where k = (W / L) (εox / tox) μeff

At this time, the change in the potential Vbl of the bit line BL is expressed by the following equation 7 using the drain current of the cell transistor as Ids.

[0060]

[Equation 7] dVbl / dt = (1 / Cbl) (Ic-Ids)

Since the cell transistor operates in the linear region, Vbl <Vwl-Vth is established, and the drain current Ids of the cell transistor at this time is expressed by the following equation 8.

[0062]

## EQU00008 ## Ids = k [Vwl-Vth- (1/2) Vb
l] Vbl

[Mathematical formula-see original document] By substituting the equation 8 into the equation 7 and integrating, the following equation 9 is obtained.

[0064]

[Formula 9] Vbl = α · β [1-exp (t / t0)] /
[Β−α · exp (t / t0)] where α = Vwl−Vth + [(Vwl−Vth) ² −
2Ic / k] ^1/2 β = Vwl-Vth-[(Vwl-Vth) ² -2Ic
/ K] ^1/2 t0 = 2Cbl / [k (α-β)]

From the assumptions of Equations 5 and 6, α>β> 0 is satisfied. Therefore, Equation 9 is an increasing function that is convex downward with respect to time t, and Vbl (0) = 0 and Vbl (∞) = β.
FIG. 18 shows the calculation result of Expression 9. The threshold value of the cell of “0” data is Vth0 = 0.3V, the threshold value of the cell of “1” data is Vth1 = −0.3V, the threshold value of the dummy cell is Vthd = 0.05V, and the bit line capacitance is Cbl =
100 fF, cell current gain coefficient k = 2.0 × 10 ⁻⁵
(A / V ² ), and Ic = 0.9Idsat =
Using 13 μA and Vwl = 1.5 V, the bit line voltage Vbl0 for “0” data and the bit line voltage Vbl1 for “1” data are set to respective signal voltages Vsig.
0, Vsig1, and the voltage Vbld of the reference bit line are shown. From this result, it can be seen that a signal of 100 mV is obtained 10 nsec after the word line is activated.

As for the dummy cell, it is preferable to use a MOS transistor having the same structure as the memory cell so that the bulk potential can be appropriately set. This is because it follows the process variation of the threshold value of the memory cell and the temperature variation in a self-aligned manner. In this case, by selecting the bulk potential of the dummy cell, it becomes possible to optimally set the signal amounts of "0" and "1" data.

[Regarding "0" Writing Speed] In the present invention, "0" writing is performed by forward-biasing the p-type bulk region of the memory transistor and the pn junction of the n-type drain, as described above. Pull out the hole. The speed of writing "0" will be examined below using the equivalent circuit of FIG.

At t = 0, the pn junction is assumed to be in an equilibrium state at 2.2V for both the p layer and the n layer. When t> 0 and the n side is set to 0 V, how the potential of the bulk (p-type layer) having the capacitance C changes will be calculated. When the potential of the p-type layer at time t is V, the following formula 10 is established.

[0069]

[Equation 10]

Here, I is the current of the pn junction and is expressed by the following equation 11.

[0071]

[Expression 11] I = Is [exp (V / η · Vt) -1]

In Equation 11, Is is a saturation current and η is 1
The coefficient between 2 and Vt is the thermal voltage (Thermal Vo).
and Vt = kT / q. By substituting the equation 11 into the equation 10 and integrating, the following equation 12 is obtained.

[0073]

[Formula 12] V = η · Vt · ln [1 / {1- [1-exp (-
V0 / η ・ Vt)] exp (-t / t0)}]

Here, t0 is t0 = CηVt / I
is a time constant given by s. FIG. 20 shows the result of numerical calculation of Expression 12 using the numerical values of Expression 13 below.

[0075]

[Formula 13] Is = Js · Aj Js = 6.36 × 10 ⁻⁵ A / m ² Aj = 0.01 μm ² T = 85 ° C. Vt = 0.0309 η = 1 t0 = 10.7 sec V0 = 2.2V

From the numerical calculation results of FIG. 20, when writing "0", the potential of the bulk (p-type layer) is about 0.
It can be seen that the voltage settles below 7V.

[Regarding potential change in bulk region] First,
Regarding the selectivity of "0" writing, the relationship between the word line potential and the bulk potential has been described with reference to FIG. 16, but the bulk potential change will be examined in more detail below. That is, in the operation of performing writing with a positive word line potential Vwl, lowering the word line potential to a negative value to retain data, raising the word line again to a positive potential and reading with the read potential Vr, in the bulk region A detailed description will be given of what kind of potential change is shown by.

Capacitance Cgb per unit area between the gate of the cell transistor and the bulk (p-type layer) of the SOI substrate
Is expressed by the following Expression 14 using the potential difference Vgb between the gate and the bulk.

[0079]

## EQU14 ## Cgb / Cox = 1 / [1 + 2.ld ² (V
gb-δ) / Vt] ^1/2

Capacitance Co per unit area of gate oxide film
x is Cox using the dielectric constant εox and the oxide film thickness tox.
= Εox / tox 1D is the Debye length (De
bye Length) LD, γ = (εsi / εo
x) is a dimensionless number standardized by tox and is given by the following Expression 15.

[0081]

## EQU15 ## ID = (εox / εsi) LD / tox = (εox / εsi) [kT · εsi / (q ² NA)] ^1/2 / tox

Here, the parameter δ is determined under the following conditions. That is, since the thickness 14 of the depletion layer that spreads in the bulk is expressed by the following Expression 16, the thickness Wp (which is the actual thickness Wp of the depletion layer that is also normalized by γ and made dimensionless) is expressed by the following Expression 16. Have been guided.

[0083]

## EQU16 ## wp = -1 + [1 + ld ² (Vgb-δ) / Vt] ^1/2

Here, the condition that Vgb = VFB (flat band voltage) and wp = 1D, that is, the following expression 17 is given.

[0085]

## EQU17 ## 1D = -1 + [1 + 1D ² (Vgb-δ) / Vt] ^1/2

By solving this equation 17, the parameter δ becomes the following equation 18.

[0087]

Δ = VFB− (1 + 2 / ld) Vt

From the equations (14) and (18), the Vgb dependence of Cgb is obtained, but this does not cover a wide Vgb region. Therefore, when the gate-source voltage Vgs exceeds the threshold value Vth of the transistor, Cgb = 0.
In addition, when Cgb / Cox exceeds 1, this is replaced with 1, and the Cgb value for a wide range of Vgb values is calculated.

FIG. 21 shows the calculation result. this is,
Voltage Vgb between word line and bulk of cell of "0" data
And the capacitance Cgb are obtained when the word line is a p-type polycrystalline silicon gate. The condition is t
ox = 2.5 nm, NA = 5 × 10 ¹⁸ / cm ³ , temperature 8
5 ° C., VFB = 0.1v, Vth0 = 1.5v, VB =
-0.7V, Cox = 0.14fF, Cj = 0.08f
It is F.

On the other hand, the bulk potential change ΔVb with respect to the gate voltage change ΔVg is expressed by the following equation 19.

[0091]

[Formula 19] ΔVb = [Cgb / (Cgb + Cj)] ΔVg

Here, Cj is the capacitance that enters into the bulk in series (the pn junction capacitance described above), and if this is kept constant, the equation (20) can be transformed into the equation (20).

[0093]

ΔVg = (1 + Cgb / Cj) ΔVgb

When the equation 20 is integrated, the following equation 21 is obtained.

[0095]

[Equation 21]

Rewriting equation 21 gives equation 22.

[0097]

[Equation 22]

If this equation 22 is calculated, the gate voltage Vw
The change ΔVb of the bulk voltage VB can be obtained from the voltage change ΔVg of l (word line). FIG. 22 shows the result of calculation under the same parameter condition as the case of the calculation of FIG. 21 described above for the cell of “0” data. From this result, for example, when "0" is written to the word line at 2.0V, the bulk is set to -0.7V, the word line is lowered to -2V, and the data is held, the bulk potential is held at -2.1V. I understand that When the word line is further raised to 1.0V and reading is performed, the bulk voltage rises only up to about -0.9V. That is, for the cell of "0" data, the bulk potential at the time of reading is lower than that at the time of writing, so that the reading margin is expanded by 0.2V.

FIG. 23 shows the result of performing the same calculation for the "1" data cell. The capacity Cg at this time
FIG. 24 shows the voltage Vgb dependency of b. The parameters used are the same as those in FIGS. 21 and 22. In the case of “1” data, the bulk becomes 0.6V immediately after writing, and the bulk becomes −V when the word line is held at −2.0V.
It turns out that it becomes 1.0V. In principle, "0" data can be written up to the bulk potential of -1.0V.
0V for the bit line that has been lowered to -1.5V by writing "0"
Bulk capacity rises by 0.3V and -0.7V by capacitive coupling (coupling ratio is 18%) of pn junction when returning to
become. Therefore, in the case of "0" data in FIG. 22, the potential immediately after writing is set to -0.7V.

Similarly, in the case of writing "1", there is capacitive coupling from the bit line, but the difference from writing "0" is that the bulk current Isub is passed and "1" data is being written. That is, the built-in voltage is higher than 0.6 V up to the potential V shown by the following formula 23.

[0101]

[Equation 23] Isub = Is [exp {V / (η · Vt) -1}]

Isub = 14 nA, Is = 6.36 × 1
Substituting 0 ⁻²⁰ A, Vt = 0.031V and η = 1.2 gives V = 0.96V. Therefore, the bulk potential is close to 1V immediately after writing "1" data, and is 0.6V or more even if the bit line drops from 1.5V to 0V and drops by 0.3V due to coupling. Becomes 0.6V. That is, it is considered that the bulk potential immediately after writing the "1" data is substantially 0.6V.

Up to this point, the flat band voltage is calculated by V
This is the case when FB = 0.1V. This corresponds to the case where the gate electrode (word line) made of p-type polycrystalline silicon is formed on the p-type silicon layer of the SOI substrate. Next, the same calculation results are shown for the case of using a gate electrode with an n-type crystalline silicon film on the same SOI substrate. In this case, the flat band voltage is VFB = -1.
It becomes 1V.

FIG. 25 shows the result of obtaining the capacitance Cgb-voltage Vgb for the "1" data cell. Similarly, FIG. 26 shows the word line voltage Vwl for the "1" data cell.
It is the result of obtaining the relationship between and the bulk voltage VB. Parameters other than the flat band voltage are shown in FIGS.
It is similar to the case of. In both cases, the threshold value is Vth1 =
It is set to 0V.

From these results, it is assumed that the threshold value Vth0 = 1V of "0" data can be secured, and the word line is 1.5V for writing and 0.5V for reading. If the word line voltage during data retention is -2.5V, then "1"
The bulk of the data cell drops to -0.8V. Therefore, using the p-type polycrystalline silicon gate, VFB = 0.
Compared to the case of 1 V, 0.
Only 2V will be a disadvantage.

27 and 28 similarly show the capacitance Cgb-voltage Vgb characteristic and the word line voltage Vwl-bulk voltage VB in the case of FB = -1.1V for the "0" data cell.
It is the result of obtaining the characteristics. The threshold value is Vth0 = 1V
And The bulk potential immediately after writing “0” data is −
Although it is 0.8V, it is assumed that when the bit line returns to near the precharge potential of 0V, the bulk potential rises by 0.3V due to the coupling of the pn junction to become -0.5V. Also in this case, the word line at the time of writing is 1.5V, but at the time of reading it is 0.5V, so the bulk potential is restored by 0.15V, and -0.65V.
It has become.

The operating conditions in the case of the p-type polycrystalline silicon gate and in the case of the n-type polycrystalline silicon gate described above are summarized in Tables 1 and 2 below.

[0108]

Table 1 In the case of p-type polycrystalline silicon gate Vwl (read) = 1V Vwl (hold) =-2V Vwl (write) = 2V Vbl (“0” write) = − 1.6V Vbl (“1” write) = 1.6V Vth0 = 1.5V Vth1 = 0.5V Bulk potential VB = 0.
Bulk potential VB = -1 when reading a 6V "0" data cell
V

[0109]

Table 2 In case of n-type polycrystalline silicon gate Vwl (read) = 0.5V Vwl (hold) = − 2.5V Vwl (write) = 1.5V Vbl (“0” write) = − 1.4V Vbl (“1” write) = 1.4V Vth0 = 1.0V Vth1 = 0V Bulk potential VB = 0.
Bulk potential VB = − when reading 6V “0” data cell
0.6V

In Tables 1 and 2 above, the bit line level Vbl (“1” write) at the time of writing “1”
Is to be determined by the substrate current (Hall current) and the writing time, and is undetermined, but shows a temporary setting value.
From the above, the advantage of using the p-type polycrystalline silicon gate was clarified. The word line amplitude is 4V in both cases. The following measures are required to reduce this voltage further. (A) To reduce the variation of the threshold value Vth (B) To secure the memory cell current (c) To reduce the ratio of Cj / Cox

As for (A) and (B), Δ
It is assumed that Vth = Vth0−Vth1 = 1.0V, but there is a possibility that this can be strictly controlled up to about 0.8V to 0.6V. If ΔVth = 0.6V can be realized, there is a possibility that the word line amplitude can be reduced to 2 × 1.2V = 2.4V. Below, (C) is examined in detail. This is because the word line amplitude can be lowered without reducing the ΔVth margin.

The requirement of (C) is that the thickness Tsi of the silicon layer of the SOI substrate is made thinner than 100 nm which has been assumed so far, and at the same time or independently, the impurity concentration of the n-type source / drain diffusion layer is set. Can be met by lowering. The former corresponds to reducing the pn junction capacitance Cj by reducing the pn junction area. Since the latter gives a condition that the depletion layer extends to the n-type diffusion layer side, the junction capacitance Cj between the source / drain diffusion layer and the bulk region is also reduced.

Therefore, instead of the junction capacitance Cj = 0.08fF used in the verification so far, the case where the junction capacitance is halved to Cj = 0.04fF, the Cgb-Vgb curve and Vw are obtained.
The l-VB curves are shown in FIGS. 29 and 30, respectively. C
The conditions other than j are the same as those in FIGS. 23 and 24, and the gate electrode is p-type polycrystalline silicon. Cj = 0.04f
F corresponds to the case where the silicon layer thickness is 50 nm.

From this result, when the word line is lowered to -2.0V after the bulk potential of 0.6V is written in the "1" data cell, the bulk potential is lowered to -1.3V. Therefore, the word line potential required to lower the bulk potential to -1V, that is, the word line potential Vwl (hold) required to hold data is Vwl (hold) =-1.
It can be seen that it is 6V.

Similarly, for the "0" data cell, Cj
And a Cgb-Vgb curve when 0.04 fF is used,
The Vwl-VB curves are shown in FIGS. 31 and 32, respectively. Conditions other than Cj are the same as in the case of FIGS. 21 and 22 described above.

As described above, the thin silicon layer (Tsi =
Table 3 below summarizes the operating conditions of the DRAM cell in the case where Ci is reduced using an SOI substrate of 50 nm) in correspondence with Table 1.

[0117]

Table 3 Vwl (read) = 0.8V Vwl (hold) = − 1.6V Vwl (write) = 1.6V Vbl (“0” write) = − 1.6V Vbl (“1” write) = 1 .6V Vth0 = 1.3V Vth1 = 0.3V Bulk potential VB = 0.
Bulk potential VB = -1 when reading a 6V "0" data cell
V

From the above results, it is understood that the word line amplitude can be reduced from 4V to 3.2V by reducing the capacitance Cj by reducing the silicon layer thickness Tsi from 100 nm to 50 nm by half. It should be noted that the difference ΔVth between the threshold values of data “0” and “1” is still 1V.
Is being secured.

If the silicon layer of the SOI substrate can be further thinned to about 30 nm, it is possible to further reduce the voltage. However, if the silicon layer is made too thin, there is a risk that the silicon layer will be completely depleted and the memory function itself will be lost. Therefore, it seems appropriate that the thickness of the silicon layer is about 50 nm.

In FIG. 33, the bulk potential VB is -1V and 0.
The relationship between the threshold difference ΔVth at 6 V and the impurity concentration NA of the silicon layer is shown. However, the gate oxide film thickness is Tox = 2.5 nm and the temperature is T = 85 ° C.
From now on, in order to secure ΔVth = 1V, NA =
It is understood that about 1.0 × 10 ¹⁹ / cm ³ is necessary. This is because the impurity concentration is a little too high, so NA =
Setting to 0.8 × 10 ¹⁸ / cm ³ , ΔVth = 0.8
V. At this time, the operating conditions in Table 3 were slightly corrected,
It is as shown in Table 4 below.

[0121]

Table 4 Vwl (read) = 0.7V Vwl (hold) = − 1.6V Vwl (write) = 1.4V Vbl (“0” write) = − 1.6V Vbl (“1” write) = 1 .4V Vth0 = 1.1V Vth1 = 0.3V Bulk potential VB = 0.
Bulk potential VB = -1 when reading a 6V "0" data cell
V

In Table 4, the bit line level Vbl ("1" write) at the time of writing "1" is determined by the substrate current (Hall current) and the writing time, so 1.4V is a temporary set value. It is considered possible to reduce the voltage to this level by increasing the substrate current Isub by setting the cell transistor to have a normal structure instead of the LDD structure.

Under the above operating conditions, the maximum voltage across the cell transistor is 3.0V. Gate oxide film thickness is To
Since x = 2.5 nm, the gate oxide film has
An electric field of about 12 MV / cm is applied at the moment of writing "1" data, and there is concern about reliability. However, increasing the gate oxide film thickness in order to ensure reliability deteriorates the capacitive coupling ratio for controlling the bulk potential, which is not preferable. Therefore, regarding the gate insulating film,
Instead of the silicon oxide film, it is preferable to use another insulating film such as Al 2 O 3 having a high dielectric constant.

In order to further reduce the voltage, the thickness Tsi of the silicon layer of the SOI substrate is reduced to about 30 nm, the threshold controllability of the cell transistor is improved, and the mobility can be increased. That is desired. Considering these, it seems that the voltage can be lowered to about 2.0V to 2.5V.

The cell current Ids1 of the "1" write cell transistor that can be secured when the threshold difference ΔVth shown in FIG. 33 and the corresponding data read time Δt are obtained.
Are shown in FIGS. 34 and 35, respectively. Cell current is Ids
1 = (k / 2) (ΔVth / 2) ²
Further, for the read time Δt, the word line potential at the time of read is set to the middle of Vth1 and Vth0, only the cells of “1” data are turned on, and the bit line having the capacitance Cbl = 100fF is discharged from the precharge potential by 200 mV. Seeking as time to go. From this result, NA = 6 × 10
^{At 18} / cm ³ , Ids1 = 1.4 μA and Δt = 1
5 nsec is obtained.

FIG. 36 shows the result of examining how much the bulk potential VB at the time of holding the "1" data cell falls in relation to the threshold value Vth1. The conditions are as follows: gate oxide film thickness tox = 2.5 nm, impurity concentration NA = 5 × 10 ¹⁸ /
cm ³ , flat band voltage VFB = 0.1V, “1”
Data bulk potential VB1 = 0.6V, gate oxide film capacitance Cox = 0.14fF, junction capacitance Cj = 0.04fF
Is. The hold potential of the word line is Vwl = Vt
It is h1-2V.

From this result, when Vth1 = 0.5V or more, the bulk potential during hold rises with Vth1. When Vth1 <0.5V, the bulk potential is -0.9.
Saturated to 3V. This means that when the word line drops to Vth1 <0.5 V or less, the capacitance Cgb is saturated as the gate oxide film capacitance Cox. Therefore,
When the flat band voltage VFB = 0.1 V, that is, when the gate electrode is a p-type polycrystalline silicon film, Vth1 <
Should be set to 0.5V. On the other hand, ΔVth = Vth
Since it is known that 0-Vth1 = 0.8V can be ensured, Vth0 <1.3V. Therefore, Vth0
= 1.1V and Vth1 = 0.3V are good choices. The above operation points are summarized in Table 5 below, and the device parameters are summarized in Table 6 below.

[0128]

Table 5 Vth0 = 1.1V, Vth1 = 0.3V Vwl (read) = 0.7V Vwl (hold) =-1.7V Vwl (write) = 1.5V Vbl (“0” write) = − 1 .5V Vbl (“1” write) = 1.5V VB (“1” read) = 0.6V VB (“0” read) = − 1.0V VB (“1” write) = 0.6V VB (“ 0 "write) =-0.9V VB (" 1 "hold) =-1.0V VB (" 0 "hold) =-2.4V Vmax = 3.2V (non-selected WL and" 1 "write BL)
Vds between

[0129]

Table 6 p-type polycrystalline silicon gate NA = 5 × 10 ¹⁸ / cm ³ tox = 2.5 nm Channel length L = 0.1 μm, channel width W = 0.1 μm Tsi = 50 nm k = (W / L) ( εox / tox) μeff = 2.0 ×
10 ^-5 A / V ²

At this time, the read characteristic of the DRAM cell is
It takes Δt = 15 nsec until a potential difference of 200 mV is applied to the bit line capacitance Cbl = 100 fF.

FIG. 37 shows that in the case of VFB = -1.1V (that is, in the case of n-type polycrystalline silicon gate), the bulk potential VB at the time of holding the "1" data cell is the threshold Vth1. It is the result of investigating how far down the relationship. The other conditions are the same as those in FIG. Also in this case,
It is suggested that Vth1 <0.5V should be set. The operation points and device parameters at this time are shown in Tables 7 and 8 below, in contrast to Tables 5 and 6.

[0132]

[Table 7] Vth0 = 0.1V, Vth1 = −0.7V Vwl (read) = 0.3V Vwl (hold) = − 2.7V Vwl (write) = 0.5V Vbl (“0” write) = − 1.5V Vbl (“1” write) = 0.5V VB (“1” read) = 0.6V VB (“0” read) = − 1.0V VB (“1” write) = 0.6V VB ( “0” write) = − 0.9V VB (“1” hold) = − 1.0V VB (“0” hold) = − 2.4V Vmax = 3.2V (non-selected WL and “1” write BL)
Vds between

[0133]

Table 8 n-type polycrystalline silicon gate NA = 5 × 10 ¹⁸ / cm ³ tox = 2.5 nm Channel length L = 0.1 μm, channel width W = 0.1 μm Tsi = 50 nm k = (W / L) ( εox / tox) μeff = 2.0 ×
10 ^-5 A / V ²

At this time, the read characteristic of the DRAM cell is
It takes Δt = 15 nsec until a potential difference of 200 mV is applied to the bit line capacitance Cbl = 100 fF. However, whether Vbl (“1” write) is 0.5V and a sufficient substrate current Isub flows or not is a problem. If it is necessary to raise this to 0.5V or more, the maximum voltage Vmax increases accordingly. To do. In this respect, it is more advantageous to use p-type polycrystalline silicon for the gate electrode. That is,
With respect to the threshold Vth0 determined by the read characteristic and the "1" write characteristic, the word line level Vw at the time of writing
l (write) is determined, but independently of this, the bit line potential Vbl (“1” wr determined by the “1” write characteristic).
ite) becomes higher than the word line potential Vwl, Vmax is Vbl (“1” write) −Vwl.
It is determined by (h01d). If Vwl (Write) ≧
If Vbl (“1” write), Vmax = Vw
l (write) -Vwl (hold), and the operating voltage can be minimized.

The above calculation is based on a standard DRAM
About the cell. Actually, there are variations in the threshold value and k of cell transistors in lots, wafers, wafers, and chips due to processes, variations in bit line capacitance, variations in design word line level, and the like. It is also necessary to consider coupling noise between bit lines.

Besides this, the threshold value Vth depending on the temperature
Fluctuations are included. When a reference cell having the same structure as that of the memory cell is used, it is possible to compensate for a portion of the element of the threshold variation so that it is not affected. In other words, by doing so, basically, it is possible to limit only the variation of the above threshold value variation element within the chip. In addition, the threshold fluctuation due to the temperature fluctuation can be completely canceled systematically.

As described above, the memory cell according to the present invention is in principle non-destructive read and current read. FIG. 38 shows a layout example of a sense amplifier utilizing this memory cell characteristic. The paired bit lines BL, bBL are arranged on both sides of the sense amplifier SA to adopt an open bit line system. Bit line pair BL, bB
When the word line WL is activated on the one hand of L, the dummy word line DWL which selects the dummy cell DC is activated on the other hand. The dummy cell DC is composed of the same MOS transistor as the memory cell MC,
An intermediate bulk potential of data "0" and "1" is applied to the bulk region.

In the illustrated example, two bit line pairs BL and bB are used.
L is selected by the selection gate SG and connected to one sense amplifier SA. Bit lines connected to a certain sense amplifier SA and bit lines connected to an adjacent sense amplifier SA are arranged alternately. In this case, for four memory cells MC that are simultaneously selected by one word line WL,
There are two sense amplifiers SA. That is, of the data of the four memory cells MC selected at the same time, only two are actually detected by the sense amplifier SA, and the remaining memory cell data is read but not sent to the sense amplifier. . According to the present invention, such a sense amplifier system is possible because it is not the destructive read as in a normal DRAM.

By the way, in realizing the DRAM cell according to the present invention as a DRAM generation of the 0.1 μm rule, it is important to satisfy the following two conditions. Condition 1: Fully utilize the substrate bias effect. Condition 2: Reduce leakage current of pn junction These conditions 1 and 2 are contradictory requirements regarding the impurity concentration in the bulk region.

Condition 1 is due to the large substrate bias effect.
Increase the threshold voltage difference between “0” and “1” data.
It is necessary to do so, and for that, the p-type silicon of FIG.
Impurity concentration (acceptor concentration) of layer 12 (bulk region)
NA is, for example, NA = 5 × 10 ¹⁸/ Cm³More than necessary
It This situation will be described with reference to FIG. Figure 40
Potential VB and the threshold value Vth of the NMOS transistor
Showing how the relationship of
There is.

When the acceptor concentration is NA1, "0",
The threshold voltage difference of “1” data is ΔVth1, and the threshold voltage difference when the acceptor concentration NA2 is lower than this is ΔVth1.
If Vth2, then ΔVth1> ΔVth2. That is, in order to increase the threshold voltage difference between “0” and “1” data, it is necessary that the acceptor concentration be higher than a certain level. The acceptor concentration of NA = 5 × 10 ¹⁸ / cm ³ or more is also necessary for reliable operation in a fine MOS transistor having a channel length of L = 0.1 μm.

On the other hand, the condition 2 is necessary in order to guarantee the data retention characteristic, and in this case, the impurity concentration in the bulk region should naturally be low. In the DRAM generation of the 0.1 μm rule, in order to hold data for 10 seconds in the bulk area,
Source / drain pn junction leakage is 3 × 10 ^-17 A
/ Cm ² It is necessary to control below. In order to reduce the tunnel current, which is the main component of leakage current, p
The electric field in the depletion layer formed at the n-junction is 2.5 × 10 5.
Must be kept below ⁵ V / cm. This is because the acceptor concentration in the bulk region is NA = 1.0 × 10 ¹⁷ / cm.
It is a value that can be realized with ³ or less. With the above-mentioned acceptor concentration required from condition 1, the electric field in the depletion layer is 1.7 ×
10 ⁶ V / cm (at 2 V reverse bias), and condition 2
Can not meet the request of.

FIG. 39 shows the contradictory conditions 1 and 2.
DRAM cell MC of the embodiment having a possibility of satisfying 2
The structure of is shown in correspondence with FIG. The difference from the cell structure of FIG. 1 lies in the bulk region formed of the p-type silicon layer 12. That is, in the case of this embodiment, the p-type diffusion layer 12a having a relatively low boron concentration (acceptor concentration) in contact with the drain and source diffusion layers 14 and 15 in the bulk region
The p ⁺ -type diffusion layer 12b having a high boron concentration (acceptor concentration) is arranged in the central portion in the channel length direction away from the drain and source diffusion layers 14 and 15.
The p ⁺ type diffusion layer 12b is formed to a depth reaching the bottom silicon oxide film 11.

This cell structure is equivalently formed by sandwiching an NMOS transistor having a high threshold voltage between two NMOS transistors having a low threshold voltage. At this time, the entire threshold voltage is the p ⁺ -type diffusion layer 12 in the central portion.
dominated by b. On the other hand, the drain / source diffusion layer 1
4, 15 form a pn junction with the low-concentration p-type diffusion layer 12a, so that the entire bulk region has a high-concentration p ⁺
The leakage current is smaller than that in the case of forming the type diffusion layer. As a result of the above, the two contradictory conditions 1 and 2 described above are
Will be able to meet.

Concretely, the examination results will be described below as to whether or not the effect can be obtained by the cell structure of FIG. 39, and what kind of density setting and position setting are necessary. First, as a preliminary study, as shown in FIGS. 41A and 41B, a reverse bias of the voltage V is applied to the pn junction of the n-type diffusion layer (donor concentration ND) and the p-type diffusion layer (acceptor concentration NA). Then, the expansion of the depletion layer and the intensity distribution of the internal electric field E are calculated. The pn junction is an abrupt junction.
). As shown in FIG. 41, the x-axis is defined in the direction crossing the pn junction. At this time, the potentials in the n-type diffusion layer and the p-type diffusion layer are φD and φA, the tip position of the depletion layer in the n-type diffusion layer is -xn, and the tip position in the p-type diffusion layer is xp, and Poisson is set. And the electric fields ED and EA in the n-type diffusion layer and the p-type diffusion layer are expressed by Equation 24. ε is the dielectric constant of silicon.

[0146]

D ² φD / dx ² = − (q / 2ε) ND (−xn <x <0) d ² φA / dx ² = (q / 2ε) NA (0 <x <xp) ED = −dφD / Dx (-xn <x <0) EA = -dφA / dx (0 <x <xp)

The boundary condition is that the built-in potential is φ.
It is represented by the following formula 25 as bi.

[0148]

ED (-xn) = 0 φD (-xn) = φbi + V ED (0) = EA (0) φD (0) = φA (0) EA (xp) = 0 φA (xp) = 0

When these boundary conditions are put and the equation 24 is solved, the following equation 26 is obtained.

[0150]

ED = (q / ε) ND · x + A (−xn <x <0) φD = − (q / 2ε) ND · x ² −A · x + B (−xn <x <0) EA = − ( q / ε) NA · x + C (0 <x <xp) φA = (q / 2ε) NA · x ² −C · x + D (0 <x <xp)

In Expression 26, A to D are constants determined by the boundary condition of Expression 25. Substituting the solution of the equation 26 into the boundary condition equation of the equation 25, the following equation 27 is obtained.

[0152]

-(Q / ε) ND · xn + A = 0 − (q / 2ε) ND · xn ² + A · xn + B = φbi +
VA = CB = D- (q / ε) NA · xp + C = 0 (q / 2ε) NA · xp ² −C · xp + D = 0

Expression 27 is six unknowns, xn, x
is an equation that determines p, A, B, C and D. By solving this, the following Expression 28 is obtained.

[0154]

Xn = {2εNA (φbi + V) / qND
(NA + ND)} ^1/2 xp = {2εND (φbi + V) / qNA (NA + N
D)} ^1/2

The maximum electric field strength Emax is the electric field at the point of x = 0 and is represented by the following formula 29.

[0156]

Emax = A = (q / ε) ND · xn = {2qNA · ND (φbi + V) / ε (NA + ND)} ^1/2

The width W = xn + xp of the entire depletion layer is given by the following equation 30.

[0158]

(30) W = {2ε (NA + ND) (φbi + V) /
qNA / ND} ^1/2

The electric field intensity distribution is as shown in FIG. 41 (b). Next, based on the above preliminary examination results, FIG.
As shown in (a) and (b), a case where the p-type diffusion layer is divided into a high acceptor concentration NA portion and a low acceptor concentration na portion will be examined. This corresponds to the structure on the drain junction side in the cell structure of the embodiment of FIG. Also in this case, the junction is assumed to be a steep junction. The distance axis uses a capital letter X instead of a lower case letter x for comparison with the results of the previous preliminary study. The tip position Xp of the depletion layer extending to the p-type diffusion layer exceeds the low acceptor concentration na region,
It is assumed that Xp> L. At this time, the Poisson's formula and the electric field formula are as shown in the following formula 31 by considering the p-type diffusion layer separately for the region of high acceptor concentration NA and the region of low acceptor concentration na with respect to formula 24. With respect to the potential φA and electric field EA in the high acceptor concentration NA region, the potential and electric field in the low acceptor concentration na region are φa and
Shown as Ea.

[0160]

D ² φD / dX ² = − (q / 2ε) ND (−Xn <X <0) d ² φa / dX ² = (q / 2ε) na (0 <X <L) d ² φA / dX ² = (q / 2ε) NA (L <X <Xp) ED = −dφD / dX (−Xn <X <0) Ea = −dφa / dX (0 <X <L) EA = −dφA / dX ( L <X <Xp)

The boundary condition is expressed by the following equation 32.

[0162]

ED (-Xn) = 0 φD (-Xn) = φbi + V ED (0) = Ea (0) φD (0) = φa (0) Ea (L) = EA (L) φa (L) = φA (L) EA (Xp) = 0 φA (Xp) = 0

By solving the equation 31, the following equation 33 is obtained.

[0164]

ED = (q / ε) ND × X + A (−Xn <X <0) φD = − (q / 2ε) ND × X ² −A × X + B (−Xn <X <0) Ea = − ( q / ε) na · X + C (0 <X <L) φa = (q / 2ε) na · X ² −C · X + D (0 <X <L) EA = − (q / ε) NA · X + E (L < X <Xp) φA = (q / 2ε) NA · X ² −E · X + F (L <X <Xp)

In Expression 33, A to F are constants determined by the boundary condition of Expression 32. Substituting the solution of Expression 33 into the boundary condition expression of Expression 32, the following Expression 34 is obtained.

[0166]

-(Q / ε) ND · Xn + A = 0 − (q / 2ε) ND · Xn ² + A · Xn + B = φbi +
VA = CB = D- (q / ε) na · L + C = − (q / ε) NA · L + E (q / 2ε) na · L ² −C · L + D = (q / 2ε) N
A · L ² −E · L + F − (q / ε) NA · Xp + E = 0 (q / 2ε) NA · Xp ² −E · Xp + F = 0

Equation 34 is the eight unknowns, Xn and X.
is an equation that determines p, A, B, C, D, E and F. By solving this, the following Expression 35 is obtained.

[0168]

[Formula 35] Xn = -L ・ (NA-na) / (NA + ND) + L ・ {(NA / ND)
(NA-na) (ND + na) / (NA + ND) ² + (xn / L) ² } ^1/2 Xp = (1 / NA) ・ [ND ・ Xn + (NA-na) ・ L]

Here, xn in the equation (35) is obtained from FIG.
The extension of the depletion layer to the n-type diffusion layer solved for the pn junction of No. 1 is shown by Equation 28. The maximum electric field Emax is an electric field at X = 0 and is represented by the following formula 36.

[0170]

[Equation 36] Emax = A = (q / ε) ND · Xn

The electric field strength distribution at this time is shown in FIG. 42 (b).
As shown in. In Expression 35, L is brought as close as possible to 0, or the acceptor concentration na is made as close to N as possible.
It is confirmed that Xn = xn holds when the value is closer to A.

Based on the above examination results, the optimization conditions of the cell structure of FIG. 39 will be concretely examined next. First, FIG.
3 is a high acceptor concentration of the p-type diffusion layer NA = 5 × 10
¹⁸ / cm ³ , low acceptor concentration na = 1 × 10 ¹⁷ / c
m ³ , the donor concentration of the n-type diffusion layer is ND = 1 × 10 ²⁰ / c
m ³ , applied voltage V = 2.0 V, ambient temperature 85 ° C., width L of low acceptor concentration region and extension X of depletion layer
It is the result of obtaining the relationship between n and Xp.

In the cell of FIG. 39, the channel length is 0.
If it is 1 μm and the extension of the depletion layer from the source and drain is symmetric, it is necessary that Xp <5 × 10 ⁻⁶ cm in order to prevent punch-through.
To satisfy this condition, from FIG. 43, L <4.0 ×
It must be 10 ⁻⁶ cm = 0.04 μm. Looking at some margin, L = 0.02 μm is a reasonable place. At this time, the extension Xp of the depletion layer to the p-type diffusion layer is
It can be seen that 0.01 μm is cut into the region of high acceptor concentration NA.

Under the same conditions as in FIG. 43, the maximum electric field strength Em
FIG. 44 shows the dependency of ax on the distance L. When the reasonable distance L obtained above is 0.02 μm, the maximum electric field strength is Emax = 9.0 × 10 ⁵ V / cm. This is because the entire bulk region has a high acceptor concentration NA = 5 × 1.
The maximum electric field is still weakened to about ½, although it is smaller than that in the case where only the region of 0 ¹⁸ / cm ³ is formed. Further, it is desired to reduce the electric field to about 1/3.

Then, next, referring to FIG. 42, an n-type diffusion layer is formed.
The effect of lowering the donor concentration ND will be examined. this is,
The depletion layer extends further to the n-type diffusion layer side, and the maximum
This is because it is expected that the electric field strength will be weakened. Figure 45
43, the donor concentration ND of the n-type diffusion layer is
ND = 1 × 10 ¹⁷/ Cm³And if low, low
The width L of the acceptor concentration region and the extensions Xn and Xp of the depletion layer
Is the result of seeking the relationship. Also, FIG. 46 shows
The dependence of the maximum electric field strength Emax of
It is shown in correspondence with 35.

From this result, if the concentration of the source and drain diffusion layers is lowered, for example, L = 0.025 μm, Xp =
Maximum electric field strength Emax = 3.0 × 10 at 0.03 μm
A value of ⁵ V / cm is obtained. Under this optimized condition,
FIG. 47 shows the dimensions and extension of the depletion layer in the cell structure of FIG.

If the n-type diffusion layer concentration of the source and drain is lowered, the contact resistance to them becomes a problem.
On the other hand, it is preferable to perform re-diffusion in the contact hole, as is done for a normal DRAM bit line contact. Alternatively, it is also effective to adopt a salicide structure in which a metal silicide film is formed on the surface of the source / drain diffusion layer.

However, when the n-type diffusion layer concentration of the source and drain is as low as ND = 1 × 10 ¹⁷ / cm ³ , as shown in FIG. 47, the depletion layer having a large width of Xn = 0.1 μm is used as the source, It also extends into the drain diffusion layer. In order to suppress such large depletion of the source and train, it is desirable to adopt a so-called LDD structure.

FIG. 48 shows an embodiment of a cell structure adopting an LDD structure with respect to the cell structure of FIG. The drain diffusion layer 14 is in contact with the channel region and has a low donor concentration n-type diffusion layer 14a and a high donor concentration n ⁺ -type diffusion layer 1
4b and. Similarly, the source diffusion layer 15 is composed of a low donor concentration n-type diffusion layer 15a in contact with the channel region and a high donor concentration n ⁺ -type diffusion layer 15. The source and drain diffusion layers and the gate electrode are
The metal silicide film 18 is formed by the salicide process. However, this LDD structure can be provided only on the drain side, which is connected to the bit line, of the drain and the source.

Next, the extension of the depletion layer and the electric field strength distribution in the case of a cell structure adopting such an LDD structure will be specifically examined. FIGS. 49 (a) and (b) show a schematic pn junction structure and electric field distribution focusing on, for example, the drain side junction of this cell structure, in association with FIGS. 42 (a) and (b). The n-type diffusion layer includes a low donor concentration nd region and a high donor concentration ND region, and the p-type diffusion layer includes a low acceptor concentration na region and a high acceptor concentration NA region. The width of the region of low donor concentration nd is Ln, and the width of the region of low acceptor concentration na is Lp. The region of high donor concentration ND and the region of high acceptor concentration NA each have a concentration determined by the resistance of the bit line contact and the source line contact and the constraint required in terms of transistor characteristics.

The extension of the depletion layer is Xp> Lp, Xn> Ln
A reverse bias condition such that At this time, Poisson's equation is expressed as in the following Expression 37 with respect to Expression 32. With respect to the electric potential ΦA of the region of high acceptor concentration NA and the electric field EA, the electric potential of the region of low acceptor concentration na,
The electric fields are represented by φa and Ea, respectively, and the electric potential and electric field in the region of low donor concentration nd are represented by φd and Ed with respect to the electric potential φD and electric field ED of the region of high donor concentration ND, respectively.

[0182]

D ² φD / dX ² = − (q / 2ε) ND (−Xn <X <−Ln) d ² φd / dX ² = − (q / 2ε) nd (−Ln <X <0) d ² φa / dX ² = (q / 2ε) na (0 <X <Lp) d ² φA / dX ² = (q / 2ε) NA (Lp <X <Xp) ED = −dφD / dX (−Xn <X <-Ln) Ed = -dφd / dX (-Ln <X <0) Ea = -dφa / dX (0 <X <Lp) EA = -dφA / dX (Lp <X <Xp)

The boundary condition is expressed by the following equation 38.

[0184]

ED (-Xn) = 0 φD (-Xn) = φbi + V ED (-Ln) = Ed (-Ln) φD (-Ln) = φd (-Ln) Ed (0) = Ea (0) φd (0) = φa (0) Ea (Lp) = EA (Lp) φa (Lp) = φA (Lp) EA (Xp) = 0 φA (Xp) = 0

By solving the equation 37, the following equation 39 is obtained.

[0186]

ED = (q / ε) ND · X + A (−Xn <X <−Ln) φD = − (q / 2ε) ND · X ² −A · X + B (−Xn <X <−Ln) Ed = (Q / ε) nd · X + C (−Ln <X <0) φd = − (q / 2ε) nd · X ² −C · X + D (−Ln <X <0) Ea = − (q / ε) na · X + E (0 <X <Lp) φa = (q / 2ε) na · X ² −E · X + F (0 <X <Lp) EA = − (q / ε) NA · X + G (Lp <X <Xp) φA = (Q / 2ε) NA · X ² −G · X + H (Lp <X <Xp)

In Expression 39, A to H are constants determined by the boundary condition of Expression 38. Substituting the solution of Expression 39 into the boundary condition expression of Expression 38, the following Expression 40 is obtained.

[0188]

-(Q / ε) ND · Xn + A = 0 − (q / 2ε) ND · Xn ² + A · Xn + B = φbi +
V − (q / ε) nd · Ln + C = − (q / ε) ND · Ln
+ A − (q / 2ε) nd · Ln ² + C · Ln + D = − (q /
ε) ND · Ln ² + A · Ln + B C = ED D = F − (q / ε) na · Lp + E = − (q / ε) NA · Lp
+ G (q / 2ε) na · Lp ² −E · Lp + F = (q / 2
ε) NA · Lp ² −G · Lp + H − (q / ε) NA · Xp + G = 0 (q / 2ε) NA · Xp ² −G · Xp + H = 0

By solving 10 equations of the equation 40, 10 variables Xn, Xp, A to H are obtained. Depletion layer width L
n and Lp are represented by the following equation 41.

[0190]

[Expression 41] Xn = [(ND-nd) Ln- (NA-na) Lp] / (NA + ND) + [1 /
(NA + ND)] (NA / ND) ^1/2・ [(NA-na) (ND + na) Lp ² ＋ (ND-nd) (N
A + nd) Ln ² ＋2 (NA-na) (ND-nd) LpLn + (NA + ND) (2ε / q) (φbi
+ V)] ^1/2 Xp = [(NA-na) Lp- (ND-nd) Ln] / (NA + ND) ＋ [1 / (NA + ND)] (N
D / NA) ^1/2・ [(ND-nd) (NA + nd) Ln ² ＋ (NA-na) (ND + na) Lp ²
+2 (ND-nd) (NA-na) LpLn + (NA + ND) (2ε / q) (φbi + V)] ^1/2

The electric field strength distribution is as shown in FIG. 49 (b), and the maximum electric field Emax is that at the point of X = 0,
From the third equation of the equation 39, the following equation 42 is given.

[0192]

[Equation 42] Emax = C = (q / ε) {NA · Xp−
(NA-na) / Lp}

Xp, Xn and Em calculated above
The result of obtaining ax by entering a specific numerical value will be described below. FIG. 50 shows that the high acceptor concentration of the p-type diffusion layer is NA =
5 × 10 ¹⁸ / cm ³ , low acceptor concentration na = 1 × 1
0 ¹⁷ / cm ³ , the high donor concentration of the n-type diffusion layer is ND = 1 ×
10 ¹⁹ / cm ³ , low donor concentration nd = 2 × 10 ¹⁷ / c
and m ^3, the applied voltage V = 2.0V, 85 ℃ ambient temperature
As a result, the relationship between the width Lp of the low acceptor concentration region and the extensions Xn and Xp of the depletion layer when the width of the low donor concentration region is fixed to Ln = 0.03 μm is shown. Figure 5
No. 1 is the result of obtaining the maximum electric field strength Emax under the same conditions.

From these results, Lp = 0.025 μm
If set to, Xp = 0.03 μm, and the maximum electric field strength is Emax = 5.0 × 10 ⁵ V / cm. Figure 52
Shows how the depletion layer spreads and the dimensions of each part in the cell structure of FIG. 48 at the above-mentioned maximum electric field strength on the drain region side.

As described in FIG. 42, the above-mentioned maximum electric field strength is 1/3 or less of that in the case where the source and drain diffusion layers have no low concentration layer. Therefore, as shown in FIG. 48, the bulk region is formed by the high-concentration layer and the low-concentration layer, and at the same time, the drain and source are LDD
With the structure, it becomes possible to suppress the maximum electric field strength to reduce the leakage current and to sufficiently exert the substrate bias effect. That is, excellent DRAM characteristics can be obtained by satisfying the contradictory conditions 1 and 2 described above.

Next, a specific manufacturing method for realizing the structure of the memory cell MC shown in FIG. 48 will be described with reference to FIGS. 53 to 56. The memory cell MC of FIG. 48 is actually arranged as a cell array similar to that described with reference to FIGS. That is, the p-type silicon layer 12 is patterned as a stripe-shaped element region in which the side surface in the direction perpendicular to the paper surface is in contact with the element isolation insulating film, but the description of the element isolation step is omitted.

As shown in FIG. 53, the p-type silicon layer 12 is formed.
First, a mask 31 having an opening in the element region is formed on the surface (which becomes the low-concentration p-type layer 12a), and the mask 31 is further formed.
A side wall insulating film 32 is formed on the side wall of the opening. Specifically, for the mask 31, for example, a silicon oxide film is deposited and patterned by RIE. Then, a silicon nitride film is deposited and etched back to leave it as the sidewall insulating film 32.
In this state, boron ion implantation is performed to form a high concentration p ⁺ -type layer 12b on the p-type silicon layer 12.

Next, as shown in FIG. 54, the sidewall insulating film 3
After 2 is selectively removed by etching, a gate insulating film 16 is formed on the exposed surface of the p-type silicon layer 12, a polycrystalline silicon film is deposited and a planarization process is performed to embed the gate electrode 13.

Then, the mask 31 is removed by etching,
Arsenic ion implantation is performed using the gate electrode 13 as a mask to form low-concentration drain and source diffusion layers 14a and 15a. Then, as shown in FIG. 46, the gate electrode 1
3, a side wall insulating film 33 is formed on the side wall, and arsenic ion implantation is performed again to form high concentration drain and source diffusion layers 14b,
15b is formed. After this, by the salicide process,
As shown in FIG. 48, the drain and source diffusion layers 14, 1
A metal silicide film 18 is formed on the gate electrode 13 and the gate electrode 13.

As described above, by applying the damascene method to the formation of the gate electrode, the p ⁺ -type layer 12b is formed in a self-aligned state in the central portion in the channel length direction of the bulk region of the transistor. You can

The structure in which the central portion of the bulk region of the cell transistor is the high concentration layer is not limited to the case where the cell transistor has the planar structure. 57A and 57B are a plan view of one memory cell MC portion and an AA ′ cross-sectional view of an embodiment in which a one-transistor / one-cell structure according to the present invention is realized by using a columnar semiconductor layer. Is shown.

A columnar silicon layer 49 is formed on the silicon substrate 40.
Is formed, and so-called SGT (Surrounding Ga) is formed by utilizing the side peripheral surface of the columnar silicon layer 49.
teTransistor) is created. The columnar silicon layer 49 has an n ⁺ -type source diffusion layer 43 formed at the bottom,
The p ⁺ type layer 46 is sandwiched between the p type layers 45 in the height direction. An n ⁺ type drain diffusion layer 44 is formed on the surface of the columnar silicon layer 49.

A gate insulating film 41 is formed on the side peripheral surface of the columnar silicon layer 41, and a gate electrode 42 is formed so as to surround the gate insulating film 41. The gate electrode 42 is continuously formed in one direction to form the word line WL. SGT formed in this way
Is covered with an interlayer insulating film 47, and a bit line (BL) is formed on this.
48 is formed. The bit line 48 is the n ⁺ type diffusion layer 44.
Connected to.

In the memory cell of this SGT structure, the bulk region is floating, and it is said that the majority majority carrier is held in the bulk region or released in the bulk region by the same writing method as described in the previous embodiment. The operation allows dynamic data storage. Then, by optimizing the impurity concentration and dimensions of the high concentration p ⁺ type layer 46 and the low concentration p type layer 45 arranged in the central portion of the bulk region, the threshold voltage difference between the binary data is increased. It is possible to obtain a sufficient substrate bias effect, reduce the leak current, and obtain excellent data retention characteristics.

58A and 58B show a 1-transistor / 1-cell DRAM cell structure according to still another embodiment. FIG. 58A is a perspective view in which the bit line (BL) 58 is shown by an imaginary line to facilitate understanding of the structure below it, and FIG. 58B is a sectional view taken along the bit line direction.

In the case of this embodiment, the silicon substrate 50
P-type silicon layer 5 separated by a silicon oxide film 51 on top
2 (this becomes the low concentration layer 52a) is formed in an island shape with the upper surface and both side surfaces exposed. Then, a gate electrode 54 is formed on the upper surface and both side surfaces of the silicon layer 52 with a gate insulating film 54 interposed therebetween, thereby forming a cell transistor. The gate electrode 54 is continuously patterned in one direction to form the word line WL.

In the transistor region of the silicon layer 52,
High concentration p in the central part in the channel length direction ⁺Mold layer 52b is formed
To be done. The drain and source diffusion layers 55 and 56 have a low concentration
n-type diffusion layers 55a and 56a and high concentration n⁺Type diffusion layer 55
The LDD structure is composed of b and 56b. To
The transistor region is covered with the inter-layer insulating film 57, and the transistor region is covered therewith.
A bit line 58 contacting the rain diffusion layer is formed.
It

Also in the memory cell of this embodiment, the bulk region is in a floating state, and an excess majority carrier is held in the bulk region or released in the bulk region by the same writing method as described in the previous embodiments. This operation enables dynamic data storage. Then, by optimizing the impurity concentration and dimensions of the high concentration p ⁺ type layer 52b and the low concentration p type layer 52a arranged in the central portion of the bulk region, the threshold voltage difference of the binary data is increased. It is possible to obtain a sufficient substrate bias effect, reduce the leak current, and obtain excellent data retention characteristics.

The cell array structure having a unit cell area of 4F ² was briefly described above with reference to FIGS. 3 and 4, and a more specific embodiment of the cell array structure and manufacturing method will be described below. 59A is a layout of the cell array, FIG. 59B is a sectional view taken along the line II ′, and FIG. 59C is the same.
It is a II-II 'sectional view. An SOI substrate is used in which an insulating film 102 such as a silicon oxide film is formed on a silicon substrate 101, and a p-type silicon layer 103 is formed thereon. The silicon layer 103 is an element isolation insulating film 10 formed by the STI method.
9 are embedded, and stripe-shaped element formation regions elongated in the direction of the bit line BL are partitioned at a predetermined pitch in the direction of the word line WL.

The silicon layer 103 thus element-isolated
The transistors are arranged in a matrix. That is, the gate electrode 105 is patterned on the silicon layer 103 via the gate insulating film 104 so as to be continuous as the word line WL. The upper surface and the side surface of the gate electrode 105 serve as a protective film capable of achieving a large etching selection ratio with respect to the interlayer insulating films 110 and 115 which will be formed later.
Covered with 6. Source and drain diffusion layers 107 and 108 are formed on the gate electrode 105 in a self-aligned manner. The source / drain diffusion layers 107 and 108 are formed to a depth reaching the insulating film 102 at the bottom of the silicon layer 103.

The surface on which the transistor is formed is covered with an interlayer insulating film 110 such as a silicon oxide film to be planarized. The source diffusion layer 107 is formed on the interlayer insulating film 110.
A contact hole 111 for is formed in a stripe shape continuous in the direction of the word line WL, and a source wiring layer 112 made of a polycrystalline silicon film or WSi is embedded therein.

An interlayer insulating film 1 such as a silicon oxide film is further formed on the interlayer insulating film 110 in which the source wiring layer 112 is embedded.
15 is formed and planarized. This interlayer insulating film 1
15, the contact hole 1 for the drain diffusion layer 108
16 is opened, and a contact plug 117 such as a polycrystalline silicon film is embedded therein. And the interlayer insulating film 11
A bit line (BL) 118 that intersects the word line WL is formed on the wiring 5 so that the contact plugs 117 are commonly connected.

Next, a specific manufacturing process will be described. Fig. 60
A, FIG. 60B and FIG. 60C show a plan view and a cross-sectional view taken along the line II ′ and II-II ′ of the stage where the element isolation insulating film 109 is formed on the p-type silicon layer 103 of the SOI substrate.
This can be obtained, for example, by etching the silicon layer 103 by RIE to form an element isolation groove and burying the element isolation insulating film 109 in the element isolation groove. As a result, a plurality of stripe-shaped element formation regions continuous in the bit line direction are defined in the silicon layer 103.

61A, 61B, and 61C are a plan view and a cross-sectional view taken along the line II 'and II-II' of the stage in which transistors are arranged in the silicon layer 103. That is, the gate electrode 105 is connected to the word line W through the gate insulating film 104.
The pattern is formed so as to be continuous as L. The upper surface and the side surface of the gate electrode 106 are covered with the silicon nitride film 106. Specifically, this gate electrode protection structure is obtained by patterning a laminated film of a polycrystalline silicon film and a silicon nitride film, and further forming a silicon nitride film on the side wall thereof. Then, ion implantation is performed using the gate electrode 105 as a mask to form source and drain diffusion layers 107 and 108.

62A and 62B, the substrate on which elements are formed is covered with an interlayer insulating film 110, and the interlayer insulating film 110 is covered.
FIG. 3 is a plan view and a cross-sectional view taken along the line II ′ of FIG. That is, after the interlayer insulating film 110 such as a silicon oxide film is formed flat, contact holes 111 continuous in a stripe shape are formed on the source diffusion layer 107 by RIE in parallel with the word lines WL. And
A polycrystalline silicon film is deposited and etched back to fill the contact hole 111 with the source wiring layer 112.

63A and 63B show the source wiring layer 1
An interlayer insulating film 115 is further formed on the interlayer insulating film 110 on which 12 and the contact plug 117 for the drain diffusion layer 108 is embedded in the interlayer insulating film 115. is there. That is, after the interlayer insulating film 115 such as a silicon oxide film is formed flat, R
The contact hole 11 is formed on the drain diffusion layer 108 by IE.
Open 6 Then, a polycrystalline silicon film is deposited and etched back to form a contact plug 117 in the contact hole 116. Thereafter, as shown in FIG. 59B, the contact plug 11 is formed on the interlayer insulating film 115.
A bit line 118 is formed so as to connect 7 in common.

As described above, the word lines WL and the bit lines BL are formed at the pitch of the minimum processing size F, and the structure shown in FIG.
As indicated by the chain line in A, a DRAM cell array having a cell area of 4F ² can be obtained. In the case of the element isolation structure as shown in FIG. 60A, the source diffusion layers 107 are formed discretely in the direction of the word lines WL, but in the case of this embodiment, the source diffusion layers 107 are commonly connected. By forming the source wiring layer 112 in, a low resistance common source line is obtained.

Contact hole 111 of source wiring layer 112
The contact hole 116 for the bit line contact plug 117 and the contact hole 116 for the bit line contact plug 117 are both self-aligned with the gate electrode 105 protected by the silicon nitride film 106.
Therefore, by setting the mask opening larger than F in the RIE process for processing the contact hole, the contact hole can be formed without being affected by the misalignment of the mask.

In the case of the above embodiment, as shown in FIG. 63A, the bit line contact hole 116 is formed only on the drain diffusion layer 108. On the other hand, FIG.
4, the bit line contact hole 116b
In the same manner as the source contact hole 111, the word line W
It is also possible to form stripes continuous in the L direction. In this case, the bit line contact plug 117 is also embedded in a stripe shape, but it is necessary to finally leave it only under the bit line BL. For example, after patterning the bit line BL, the bit line BL is
The contact plug 117 may be etched using this as a mask.

In the above embodiment, the source wiring layer 1
If the upper surface and the side surface of 12 are covered with the protective film similarly to the gate electrode 105, the alignment margin of the bit line contact is further increased. Such an embodiment will be described below. The steps up to the element forming step in FIG. 61B are the same as those in the previous embodiment, and the subsequent steps will be described using only the cross section corresponding to the cross section in FIG. 61B. First, as shown in FIG. 65, an interlayer insulating film 2 such as a silicon oxide film is formed on a substrate on which elements are formed.
01 is deposited and etched back to be flattened. Here, the interlayer insulating film 201 is buried in the gate gap by etching using the silicon nitride film 106 that covers the gate electrode 105 as a stopper.

Thereafter, as shown in FIG. 66, contact holes for the source and drain diffusion layers 107, 108 are opened in the interlayer insulating film 201, and the contact plugs 20 are formed by depositing polysilicon and etching back.
Embed 2,203. In the RIE of the contact hole opening, a contact hole self-aligned with the gap of the gate electrode 105 is formed by using a mask having a stripe-shaped opening continuous in the direction of the bit line BL. However, the contact plug 202 on the source diffusion layer 107 may be continuous in parallel with the word line WL as in the previous embodiment.

After that, as shown in FIG. 67, a source wiring layer 204 which connects the contact plugs 202 on the source diffusion layers 107 in common in the word line WL direction is formed by patterning. The upper surface and the side surface of the source wiring layer 204 are covered with a silicon nitride film 205 which is a protective film. Specifically, this protective structure can be obtained by patterning a laminated film of a polycrystalline silicon film and a silicon nitride film to form the source wiring layer 204, and further forming a silicon nitride film on the side surface thereof.

Next, as shown in FIG. 68, an interlayer insulating film 206 such as a silicon oxide film is deposited again and planarized. And the dual damascene
A wiring embedding groove and a contact hole for the bit line are formed in the interlayer insulating film 206 by the method e), and the bit line 207 is embedded as shown in FIG.

According to this embodiment, the source wiring layer 2
Since the periphery of 04 is protected by the silicon nitride film 205, the width of the bit line contact in the bit line direction can be made sufficiently large. As a result, a low resistance bit line contact can be formed without being affected by misalignment.

In the two embodiments described above, FIG.
As shown in, the stripe-shaped continuous element forming region was divided. Therefore, each element formation region is not continuous in the word line direction. On the other hand, as shown in FIG.
It is also possible to divide the element formation region so that the stripe-shaped element formation region is continuous in the word line direction at the position where the source diffusion layer is formed. In this case, the source diffusion layer itself is continuously formed in the word line direction and becomes the common source line itself. In this case as well, the source wiring layer 112 is not formed as in the above embodiment. , Effective for lowering the resistance of the common source line.

The present invention is not limited to the above embodiment.
In the embodiment, the NMOS transistor formed in the p-type silicon layer is used, but a P-channel MOS transistor using the n-type silicon layer can be used as a memory cell to perform dynamic storage on the same principle. In this case, majority carriers are used to utilize accumulation and emission of electrons in the bulk region. Further, although the SOI substrate is used in the embodiment, it is also possible to form a memory cell of the same principle by using a MOS transistor using a semiconductor layer which is made floating by pn junction separation.

[0227]

As described above, according to the present invention, it is possible to provide a semiconductor memory device in which a simple transistor structure is used as a memory cell and data can be dynamically stored with a small number of signal lines.

[Brief description of drawings]

FIG. 1 is a sectional view showing a memory cell structure of a DRAM according to the present invention.

FIG. 2 is an equivalent circuit of a memory cell of the DRAM.

FIG. 3 is a layout of a memory cell array of the DRAM.

4 is a cross-sectional view taken along the lines A-A 'and B-B' of FIG.

FIG. 5 is a diagram showing a relationship between a word line potential and a bulk potential of the DRAM cell.

FIG. 6 is a diagram for explaining a reading method of the same DRAM cell.

FIG. 7 is a diagram for explaining another reading method of the DRAM cell.

FIG. 8 is a diagram showing operation waveforms of “1” data read / refresh of the same DRAM.

FIG. 9 is a diagram showing operation waveforms of “0” data read / refresh of the same DRAM.

[FIG. 10] “1” data read / “0” of the same DRAM
It is a figure which shows the operation waveform of data writing.

FIG. 11: “0” data read / “1” of the same DRAM
It is a figure which shows the operation waveform of data writing.

FIG. 12 is a "1" according to another read method of the same DRAM.
It is a figure which shows the operation waveform of data read / refresh.

FIG. 13 shows “0” according to another read method of the same DRAM.
It is a figure which shows the operation waveform of data read / refresh.

FIG. 14 is a "1" according to another read method of the same DRAM.
It is a figure which shows the operation waveform of data read / "0" data write.

FIG. 15 is “0” according to another read method of the same DRAM.
FIG. 6 is a diagram showing operation waveforms of data read / “1” data write.

FIG. 16: Gate capacitance Cgb-voltage V of the same DRAM cell
It is a figure which shows the characteristic of gb.

FIG. 17 is an equivalent circuit diagram of the DRAM cell according to a constant current reading method.

FIG. 18 is a diagram showing a change in bit line potential due to a read operation of the DRAM cell.

FIG. 19 is an equivalent circuit for explaining the “0” write speed of the DRAM cell.

20 is a diagram showing a potential change in the p-type layer of FIG.

FIG. 21 is a diagram showing a gate capacitance Cgb-voltage Vgb curve (in the case of a p-type polycrystalline silicon gate) of a “0” data cell of the same DRAM cell.

FIG. 22 is a word line potential Vw of a “0” data cell.
It is a figure which shows the relationship between 1 and the bulk electric potential VB.

FIG. 23 is a diagram showing a relationship between a word line potential Vwl and a bulk potential VB of a “1” data cell of the DRAM cell.

FIG. 24 is a diagram showing a gate capacitance Cgb-voltage Vgb curve (in the case of a p-type polycrystalline silicon gate) of a “1” data cell.

FIG. 25 is a diagram showing a gate capacitance Cgb-voltage Vgb curve (in the case of an n-type polycrystalline silicon gate) of a “1” data cell.

FIG. 26 is a diagram showing a relationship between a word line potential Vwl and a bulk potential VB of a “1” data cell (in the case of an n-type polycrystalline silicon gate).

FIG. 27 is a diagram showing a gate capacitance Cgb-voltage Vgb curve (in the case of a p-type polycrystalline silicon gate) of a “0” data cell.

FIG. 28 is a diagram showing a relationship between a word line potential Vwl and a bulk potential VB (in the case of an n-type polycrystalline silicon gate) of the same “0” data cell.

FIG. 29 is a diagram showing a gate capacitance Cgb-voltage Vgb curve (in the case of a p-type polycrystalline silicon gate) of a “1” data cell when a thin silicon layer is used.

FIG. 30 is a diagram showing a relationship between a word line potential Vwl and a bulk potential VB of the same “1” data cell.

FIG. 31 is a diagram showing a gate capacitance Cgb-voltage Vgb curve (in the case of a p-type polycrystalline silicon gate) of a “0” data cell when a thin silicon layer is used.

FIG. 32 is a diagram showing a relationship between a word line potential Vwl and a bulk potential VB of the same “0” data cell.

FIG. 33 is a diagram showing the relationship between the impurity concentration of a silicon layer and the difference between the threshold values of “0” and “1” data.

FIG. 34 is a diagram similarly showing a relation between the impurity concentration of the silicon layer and the cell current of the “1” data cell.

FIG. 35 is a diagram showing the relationship between the impurity concentration of the silicon layer and the time for which the bit line potential changes during reading.

FIG. 36 is a diagram showing a relationship between a bulk potential and a threshold value (in the case of p-type polycrystalline silicon gate) at the time of holding data of a “1” data cell.

FIG. 37 is a diagram showing a relationship between a bulk potential and a threshold value (in the case of an n-type polycrystalline silicon gate) at the time of holding data of a “1” data cell.

FIG. 38 is a diagram showing an example of a sense amplifier layout according to the present invention.

FIG. 39 is a cross-sectional view showing a DRAM cell structure according to another embodiment, corresponding to FIG. 1;

FIG. 40 is a diagram showing the relationship between the bulk potential and the threshold voltage of a MOS transistor.

41 is a diagram showing a basic pn junction structure and its electric field distribution for a preliminary study for studying the effectiveness of the cell structure of FIG. 39. FIG.

42 is a diagram showing a drain side pn junction structure and its electric field distribution for examining the effectiveness of the cell structure of FIG. 39. FIG.

43 is a diagram showing the relationship between the width of the low-concentration p-type layer and the extension of the depletion layer in FIG. 42.

FIG. 44 is a diagram showing the relationship between the width of the low-concentration p-type layer and the maximum electric field strength.

FIG. 45 is a diagram showing the relationship between the width of the low-concentration p-type layer and the extension of the depletion layer, which corresponds to FIG. 43, when the concentration of the n-type diffusion layer is lowered.

FIG. 46 is a diagram showing a relationship between the width of the low-concentration p-type layer and the maximum electric field strength.

47 is a diagram showing how the depletion layer expands under the optimized conditions of the cell structure of FIG. 39.

48 is a sectional view showing a cell structure of an embodiment in which the cell structure of FIG. 39 is improved.

49 is a diagram showing a drain side pn junction structure and its electric field distribution for examining the effectiveness of the cell structure of FIG. 48. FIG.

50 is a diagram showing the relationship between the width of the low-concentration p-type layer and the extension of the depletion layer in FIG. 49.

FIG. 51 is a diagram showing a relationship between the width of the low-concentration p-type layer and the maximum electric field strength.

52 is a diagram showing how the depletion layer expands under the optimized conditions of the cell structure of FIG. 48.

FIG. 53 is a diagram illustrating a manufacturing process of the cell in FIG. 48.

FIG. 54 is a diagram for explaining manufacturing steps of the cell in FIG. 48.

FIG. 55 is a diagram illustrating a manufacturing process of the cell in FIG. 48.

FIG. 56 is a diagram illustrating a manufacturing process of the cell in FIG. 48.

FIG. 57A is a plan view showing a cell structure according to another embodiment.

57B is a cross-sectional view taken along the line A-A ′ of FIG. 57A.

FIG. 58A is a perspective view showing a cell structure according to another embodiment.

58B is a cross-sectional view taken along the bit line direction of FIG. 58A.

FIG. 59A is a layout of a DRAM cell array of the preferred embodiment.

59B is a cross-sectional view taken along the line I-I ′ of FIG. 59A.

59C is a cross-sectional view taken along the line II-II ′ of FIG. 59A.

FIG. 60A is a plan view showing the element isolation step of the same embodiment.

FIG. 60B is a cross-sectional view taken along the line I-I ′ of FIG. 60A.

FIG. 60C is a cross-sectional view taken along the line II-II ′ of FIG. 60A.

FIG. 61A is a plan view showing a transistor forming step in the same embodiment;

61B is a cross-sectional view taken along the line I-I ′ of FIG. 61A.

61C is a cross-sectional view taken along the line II-II ′ of FIG. 61A.

FIG. 62A is a plan view showing a step of forming the source wiring layer in the same embodiment.

62B is a cross-sectional view taken along the line I-I ′ of FIG. 62A.

FIG. 63A is a plan view showing a step of filling the bit line contact plugs of the embodiment.

63B is a cross-sectional view taken along the line I-I ′ of FIG. 63A.

FIG. 64 is a plan view showing another step of burying bit line contact plugs.

FIG. 65 is a cross-sectional view showing the step of forming an interlayer insulating film after element formation according to another embodiment.

FIG. 66 is a cross-sectional view showing the step of filling the contact plugs of the embodiment.

67 is a cross-sectional view showing the step of forming the source wiring layer in the same embodiment. FIG.

FIG. 68 is a cross-sectional view showing the interlayer insulating film forming step of the same embodiment.

FIG. 69 is a cross-sectional view showing the bit line forming step of the same embodiment.

FIG. 70 shows an element isolation structure according to another embodiment.
It is a top view shown corresponding to A.

[Explanation of symbols]

10 ... Silicon substrate, 11 ... Silicon oxide film, 12 ... Silicon layer (floating), 12 ... Gate oxide film, 1
3 ... Gate electrode (word line), 14 ... N-type drain diffusion layer (bit line), 15 ... N-type source diffusion layer (fixed potential).

Claims (59)

[Claims] 1. A semiconductor layer that forms a memory cell, wherein the transistor is formed on the semiconductor layer of a first conductivity type that is electrically isolated from other memory cells and is in a floating state. A second conductivity type drain diffusion layer connected to a bit line; a second conductivity type source diffusion layer formed in the semiconductor layer and separated from the drain diffusion layer and connected to a source line; And a gate electrode that is formed on the semiconductor layer between the source diffusion layers via a gate insulating film and connected to a word line, and the transistor has an excess majority carrier in the semiconductor layer. A first data state having a retained first threshold voltage and a second data state having a second threshold voltage from which excess majority carriers of the semiconductor layer have been released. The semiconductor memory device which is characterized in that. 2. The first data state is a state in which impact ionization occurs near the drain junction by operating the transistor, and excess majority carriers generated by the impact ionization are held in the semiconductor layer. The second data state is a state in which a forward bias is applied between the semiconductor layer and the drain diffusion layer to extract excess majority carriers of the semiconductor layer into the drain diffusion layer. The semiconductor memory device according to claim 1. 3. The semiconductor memory device according to claim 1, wherein the semiconductor layer is a silicon layer formed on a silicon substrate via an insulating film. 4. The semiconductor memory device according to claim 3, wherein the silicon layer is p-type, and the transistor is an N-channel MOS transistor. 5. The semiconductor memory device according to claim 1, wherein the potential of the source line is fixed. 6. When writing data, the source line is used as a reference potential, a first potential higher than the reference potential is applied to a word line of a selected transistor, and a word line of an unselected transistor is lower than the reference potential. A second potential is applied to the bit line. When writing the first data state, a third potential higher than the reference potential is applied to the bit line and the second potential is applied to the bit line.
6. The semiconductor memory device according to claim 5, wherein when writing the data state, a fourth potential lower than the reference potential is applied. 7. When data is read, the source line is used as a reference potential, and the word line of the selected transistor is between the first threshold voltage and the second threshold voltage and is higher than the reference potential. 2. The semiconductor memory device according to claim 1, wherein a high potential is applied to detect conduction or non-conduction of a selected transistor. 8. The semiconductor layer comprises: a first impurity-doped region in contact with the drain diffusion layer and the source diffusion layer; a first impurity-doped region separated from the drain diffusion layer and the source diffusion layer; 8. The semiconductor memory device according to claim 7, further comprising a second impurity-doped region having a higher impurity concentration than the first impurity-doped region, which is arranged in contact with the region. 9. When reading data, the source line is used as a reference potential and the first and second word lines of the selected transistor are connected to the word line of the selected transistor.
2. The semiconductor memory device according to claim 1, wherein the conductivity of the selected transistor is detected by applying a potential higher than the threshold voltage of the above and higher than the reference potential. 10. The semiconductor layer comprises: a first impurity-added region in contact with the drain diffusion layer and the source diffusion layer; a first impurity-added region separated from the drain diffusion layer and the source diffusion layer; 10. The semiconductor memory device according to claim 9, further comprising a second impurity-doped region having a higher impurity concentration than the first impurity-doped region, the second memory-doped region being in contact with the region. 11. The semiconductor layer comprises: a first impurity-added region in contact with the drain diffusion layer and the source diffusion layer; a first impurity-added region separated from the drain diffusion layer and the source diffusion layer; 2. The semiconductor memory device according to claim 1, further comprising a second impurity-doped region having a higher impurity concentration than the first impurity-doped region, the second impurity-doped region being disposed in contact with the region. 12. A third impurity-doped region in which at least a drain diffused layer of the drain diffused layer and the source diffused layer is in contact with the first impurity-doped region to form a pn junction, and the first impurity-doped region. A fourth region formed away from the region and having a higher impurity concentration than the third impurity doped region.
2. The impurity-doped region according to claim 1,
1. The semiconductor memory device according to 1. 13. When reading data, it is possible to detect a potential difference appearing on the bit line by raising a selected word line higher than the second threshold voltage and then applying a constant current to the bit line. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device. 14. When reading data, after raising the selected word line higher than the second threshold voltage, a current necessary for clamping the bit line to a constant voltage is passed to reduce the current level. The semiconductor memory device according to claim 1, wherein a difference is detected. 15. The semiconductor layer comprises: a first impurity-doped region in contact with the drain diffusion layer and the source diffusion layer; a first impurity-doped region separated from the drain diffusion layer and the source diffusion layer; 14. The semiconductor memory device according to claim 13, further comprising a second impurity-doped region having a higher impurity concentration than the first impurity-doped region, the second memory-doped region being in contact with the region. 16. The semiconductor layer comprises: a first impurity-doped region in contact with the drain diffusion layer and the source diffusion layer; a first impurity-doped region separated from the drain diffusion layer and the source diffusion layer; 15. The semiconductor memory device according to claim 14, further comprising a second impurity-doped region having a higher impurity concentration than the first impurity-doped region, the second memory-doped region being in contact with the region. 17. The sense amplifier according to claim 1, wherein one sense amplifier is provided for the plurality of bit lines, and one selected bit line of the plurality of bit lines is connected to the sense amplifier. Semiconductor memory device. 18. An SOI substrate in which a silicon layer is formed on a silicon substrate with an insulating film interposed therebetween, and two of the two, which are formed in the silicon layer and share a drain diffusion layer, are element-separated in the channel width direction to form a matrix arrangement. Transistor, a word line commonly connected to the gate electrodes of the transistors arranged in one direction, and a plurality of bit lines arranged in a direction intersecting the word line and connected to the drain diffusion layer of the transistor, A source diffusion layer of the transistor is continuously arranged in the word line direction and is provided with a common source line to which a fixed potential is applied; and the transistor has a first first layer in which excess majority carriers are held in the silicon layer. A first data state having a threshold voltage and a second threshold voltage having excess majority carriers emitted from the bulk region. The semiconductor memory device characterized by having a data state. 19. The semiconductor memory device according to claim 18, wherein the transistors are arranged in a matrix with a cell size of 2F × 2F, with a minimum processing dimension being F. 20. The semiconductor memory device according to claim 18, wherein the drain diffusion layer and the source diffusion layer are formed to a depth reaching the insulating film below the silicon layer. 21. The first data state is a state in which impact ionization occurs near the drain junction by operating the transistor, and excess majority carriers generated by this impact ionization are held in the semiconductor layer. The second data state is a state in which a forward bias is applied between the silicon layer and the drain diffusion layer to extract excess majority carriers of the semiconductor layer to the drain diffusion layer. The semiconductor memory device according to claim 18. 22. The semiconductor memory device according to claim 21, wherein the silicon layer is p-type, and the transistor is an n-channel MOS transistor. 23. The semiconductor memory device of claim 18, wherein the potential of the common source line is fixed. 24. When writing data, the common source line is used as a reference potential, a first potential higher than the reference potential is applied to a selected word line, and a second potential lower than the reference potential is applied to an unselected word line. A potential is applied to the bit line, and when writing the first data state, a third potential higher than the reference potential is applied to the bit line and the second potential is applied to the bit line.
24. The semiconductor memory device according to claim 23, wherein when writing the data state, a fourth potential lower than the reference potential is applied. 25. When reading data, the common source line is used as a reference potential, and a word line of a selected transistor is located between the first threshold voltage and the second threshold voltage and has the reference potential. 19. The semiconductor memory device according to claim 18, wherein a higher potential is applied to detect conduction or non-conduction of a selected transistor. 26. When reading data, the common source line is used as a reference potential, and the word line of the selected transistor is connected to the first and second word lines.
19. The semiconductor memory device according to claim 18, wherein the conductivity of the selected transistor is detected by applying a potential higher than the threshold voltage of the above and higher than the reference potential. 27. The silicon layer comprises: a first impurity-doped region in contact with the drain diffusion layer and the source diffusion layer; a first impurity-doped region separated from the drain diffusion layer and the source diffusion layer; 26. The semiconductor memory device according to claim 25, further comprising: a second impurity-doped region having a higher impurity concentration than the first impurity-doped region, the second impurity-doped region being in contact with the region. 28. The silicon layer comprises a first impurity doped region in contact with the drain diffusion layer and the source diffusion layer, a first impurity doped region separated from the drain diffusion layer and the source diffusion layer, and the first impurity doped region. 27. The semiconductor memory device according to claim 26, further comprising a second impurity-doped region having a higher impurity concentration than the first impurity-doped region, the second memory-doped region being in contact with the region. 29. At the time of reading data, after raising a selected word line higher than the second threshold voltage, a constant current is passed through the bit line to detect a potential difference appearing on the bit line. The semiconductor memory device according to claim 18, wherein the semiconductor memory device is a semiconductor memory device. 30. When reading data, after raising a selected word line to a voltage higher than the second threshold voltage, a current necessary for clamping the bit line to a constant voltage is passed to reduce the current. 19. The semiconductor memory device according to claim 18, wherein a difference is detected. 31. The silicon layer includes a first impurity-doped region that is in contact with the drain diffusion layer and the source diffusion layer, and is separated from the drain diffusion layer and the source diffusion layer, and the first impurity addition region. 30. The semiconductor memory device according to claim 29, further comprising: a second impurity-doped region having a higher impurity concentration than the first impurity-doped region, the second impurity-doped region being in contact with the region. 32. The silicon layer includes a first impurity-doped region that is in contact with the drain diffusion layer and the source diffusion layer, and is separated from the drain diffusion layer and the source diffusion layer, and the first impurity addition region. 31. The semiconductor memory device according to claim 30, further comprising a second impurity-doped region having a higher impurity concentration than the first impurity-doped region, the second memory-doped region being in contact with the region. 33. At the time of data reading, after raising a selected word line higher than the second threshold voltage, a constant current is passed through the bit line to detect a potential difference appearing on the bit line. 25. The semiconductor memory device according to claim 24. 34. At the time of data reading, after raising a selected word line higher than the second threshold voltage, a current necessary for clamping the bit line to a constant voltage is passed to reduce the current. 25. The semiconductor memory device according to claim 24, wherein a difference is detected. 35. The silicon layer is separated from the drain diffusion layer and the source diffusion layer by a first impurity addition region in contact with the drain diffusion layer and the source diffusion layer, and the first impurity addition region. 34. The semiconductor memory device according to claim 33, further comprising a second impurity-doped region having a higher impurity concentration than the first impurity-doped region, the second impurity-doped region being in contact with the region. 36. The silicon layer comprises a first impurity doped region in contact with the drain diffusion layer and the source diffusion layer, a first impurity doped region separated from the drain diffusion layer and the source diffusion layer, and the first impurity doped region. 35. The semiconductor memory device according to claim 34, further comprising a second impurity-doped region having a higher impurity concentration than the first impurity-doped region, the second memory-doped region being in contact with the region. 37. A plurality of bit lines are provided with one sense amplifier, and one selected bit line of the plurality of bit lines is connected to the sense amplifier. Semiconductor memory device. 38. An SOI substrate in which a silicon layer is formed on a silicon substrate via an insulating film, and the SOI substrate is arranged in a matrix in the silicon layer and is continuous in one direction with the upper surface and side surfaces covered with a protective film. A plurality of transistors each having a gate electrode patterned as a word line and source and drain diffusion layers formed in self alignment with the gate electrode; a first interlayer insulating film covering the plurality of transistors; A source wiring layer embedded in a first contact hole formed in the first interlayer insulating film on the source diffusion layer of each transistor in a stripe shape continuous in parallel with the word line; and the first interlayer A second interlayer insulating film formed on the insulating film, and a second contact formed on the second interlayer insulating film on the drain diffusion layer of each transistor. A bit line contact plug embedded in the bit line, and a bit disposed on the second interlayer insulating film to intersect the word line and connected to the drain diffusion layer of the transistor through the bit line contact plug. A first data state having a first threshold voltage with excess majority carriers retained in the bulk region and excess majority carriers in the bulk region being released into the drain diffusion layer. A semiconductor memory device characterized by dynamically storing a second data state having a second threshold voltage. 39. The silicon layer of the SOI substrate is divided by an element isolation insulating film as stripe-shaped element formation regions continuous in the bit line direction at predetermined pitches in the word line direction. Claim 38
A semiconductor memory device as described. 40. The first data state is a state in which impact ionization occurs near the drain junction by operating the transistor and excess majority carriers generated by the impact ionization are held in the silicon layer. The second data state is a state in which a forward bias is applied between the silicon layer and the drain diffusion layer to extract excess majority carriers of the silicon layer to the drain diffusion layer. The semiconductor memory device according to claim 38. 41. The semiconductor memory device according to claim 38, wherein the silicon layer is p-type and the transistor is an n-channel MOS transistor. 42. The semiconductor memory device of claim 38, wherein the potential of the source wiring layer is fixed. 43. When reading data, the source wiring layer is used as a reference potential, and the selected word line is between the first threshold voltage and the second threshold voltage and higher than the reference potential. 39. The semiconductor memory device according to claim 38, wherein a potential is applied to detect conduction or non-conduction of a selected transistor. 44. When data is read, a potential higher than the first and second threshold voltages and higher than the reference potential is applied to the selected word line with the source wiring layer as a reference potential, and the selected word line is selected. 39. The semiconductor memory device according to claim 38, wherein the conductivity of the formed transistor is detected. 45. At the time of reading data, after raising a selected word line higher than the second threshold voltage, a constant current is passed through the bit line to detect a potential difference appearing on the bit line. 39. The semiconductor memory device according to claim 38, wherein 46. At the time of reading data, after raising a selected word line higher than the second threshold voltage, a current necessary for clamping the bit line to a constant voltage is passed to reduce the current. 39. The semiconductor memory device according to claim 38, wherein a difference is detected. 47. The one sense amplifier is provided for a plurality of bit lines, and one selected bit line of the plurality of bit lines is connected to the sense amplifier. Semiconductor memory device. 48. An SOI substrate in which a silicon layer is formed on a silicon substrate via an insulating film, and an SOI substrate arranged in a matrix in the silicon layer, the upper surface and the side surface of which are covered with a first protective film. A gate electrode patterned as a word line continuous in the direction, and
A plurality of transistors having source and drain diffusion layers formed in self-alignment with the gate electrode; a first interlayer insulating film covering the plurality of transistors; and a source diffusion layer of each transistor of the interlayer insulating film. Source contact plugs buried in the contact holes formed in the contact holes, drain contact plugs respectively buried in the contact holes formed on the drain diffusion layers of the transistors of the interlayer insulating film, and in the word line direction. A source wiring layer having the source contact plugs connected in common and having an upper surface and a side surface covered with a second protective film; a second interlayer insulating film covering the source wiring layer; and a second interlayer insulating film on the second interlayer insulating film. Of the transistor is connected to the word line through the drain contact plug. A first data state having a first threshold voltage with excess majority carriers retained in the bulk region, and an excess majority region in the bulk region. A semiconductor memory device characterized in that a carrier dynamically stores a second data state having a second threshold voltage released to the drain diffusion layer. 49. The silicon layer of the SOI substrate is divided by an element isolation insulating film as stripe-shaped element formation regions continuous in the bit line direction at predetermined pitches in the word line direction. Claim 48
A semiconductor memory device as described. 50. The first data state is a state in which the transistor is operated to cause impact ionization in the vicinity of a drain junction, and excess majority carriers generated by the impact ionization are held in the silicon layer. The second data state is a state in which a forward bias is applied between the silicon layer and the drain diffusion layer to extract excess majority carriers of the silicon layer to the drain diffusion layer. The semiconductor memory device according to claim 48. 51. The semiconductor memory device according to claim 48, wherein the silicon layer is p-type and the transistor is an n-channel MOS transistor. 52. The semiconductor memory device of claim 48, wherein the potential of the source wiring layer is fixed. 53. When data is read, the source wiring layer is used as a reference potential, and the selected word line is located between the first threshold voltage and the second threshold voltage and higher than the reference potential. 49. The semiconductor memory device according to claim 48, wherein a potential is applied to detect conduction or non-conduction of a selected transistor. 54. When data is read, a potential higher than the first and second threshold voltages and higher than the reference potential is applied to the selected word line with the source wiring layer as a reference potential to select the word line. 49. The semiconductor memory device according to claim 48, wherein the conductivity of the formed transistor is detected. 55. At the time of data reading, after raising a selected word line higher than the second threshold voltage, a constant current is passed through the bit line to detect a potential difference appearing on the bit line. 49. The semiconductor memory device as claimed in claim 48. 56. At the time of data reading, after raising a selected word line higher than the second threshold voltage, a current necessary for clamping the bit line to a constant voltage is supplied to reduce the current. 49. The semiconductor memory device according to claim 48, wherein a difference is detected. 57. The sense amplifier is provided for a plurality of bit lines, and one bit line selected from the plurality of bit lines is connected to the sense amplifier. Semiconductor memory device. 58. A step of forming a mask having an opening in a gate electrode formation region on a first conductive type semiconductor layer formed on a semiconductor substrate and separated by an insulating film; and a sidewall on an opening sidewall of the mask. Forming an insulating film; adding an impurity to the semiconductor layer through an opening of the mask to form a first conductivity type impurity added layer having an impurity concentration higher than that of the semiconductor layer; A step of embedding a gate electrode in the opening of the mask through a gate insulating film after removing the insulating film; and an impurity added to the semiconductor layer after removing the mask to form a drain and a source of the second conductivity type. And a step of forming a diffusion layer. 59. A step of forming a mask having an opening in a gate electrode formation region on a first conductivity type semiconductor layer formed on a semiconductor substrate and separated by an insulating film; and a step of forming a mask on an opening sidewall of the mask. A step of forming a sidewall insulating film of No. 1 and an impurity is added to the semiconductor layer through the opening of the mask to form a first conductivity type first impurity added layer having an impurity concentration higher than that of the semiconductor layer. A step of filling the gate insulating film and the gate electrode in the opening of the mask after removing the first sidewall insulating film, and removing the mask, adding an impurity to the semiconductor layer, and draining the semiconductor layer. And forming a second conductivity type second impurity added layer in the source region, forming a second side wall insulating film on the side wall of the gate electrode, adding impurities to the semiconductor layer, and draining the semiconductor layer. as well as Forming a third impurity-added layer of the second conductivity type having an impurity concentration higher than that of the second impurity-added layer in the source region.