JP2003044840A - Information processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit for generating a pulse width modulation signal or a pulse phase modulation signal representing the difference between two analog values and to provide also a processing unit circuit which is of a small area and power saving and is fast in an image processing system characterized in applying the circuit to image processing and making a pixel parallel operation type processing unit update a state by an operation with an adjacent pixel processing unit. SOLUTION: A binary signal representing the magnitude relation of two voltages and the pulse width modulation signal or pulse phase modulation signal having information of the absolute value of the difference between the two voltages are generated by holding two analog voltages in two capacitors and serially connecting the capacitors. Also, a subtraction circuit is sued for an image processing unit circuit to convert results operated on the basis of information of adjacent pixels as an analog voltage into a pulse phase modulation signal, and a nonlinear current source is switched with the signal to update a self-state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating a pulse width modulation signal or a pulse phase modulation signal which represents a difference between two analog values, and particularly to a circuit which is applied to image processing and is of a pixel parallel operation type. The present invention relates to a circuit that performs image processing by a processing unit updating the state by calculation with an adjacent pixel processing unit.

[0002]

2. Description of the Related Art Several methods using analog dynamics in a network in which resistive elements and the like are combined have been proposed for image processing and the like. For example, a resistor network circuit (CA Mead and M.
A. Mahowald, "A silicon model of early visual proc
essing, "Neural Networks, vol. 1, pp. 91-97, 198
8: Reference 1), a resistive fuse network circuit that smoothes while preserving edge information (eg, PC Yu, S.
J. Decker, HS Lee, CG Sodini, JL Wyatt,
Jr., "CMOS resistive fuses for image smoothing an
d segmentation, "IEEE Journal of Solid-State Circu
its, vol. 27, pp. 545-553, 1992: Reference 2), a two-layer resistor network circuit that realizes a Gabor filter (B.
E. Shi, "Gabor-type filtering in space and time w
ith cellular neural networks, "IEEE Transactions o
n Circuits and Systems I, vol. 45, pp. 121-132, 19
98: Reference 3).

In these circuits, the brightness value of each pixel is given by the value of the voltage source or the current source for each node, and each node voltage when the circuit reaches a stable state is taken out as a processing result. Since the stable state is reached in the time of the order of the time constant determined by the resistance and (parasitic) capacitance, there is an advantage that extremely fast calculation can be performed.

Of these circuits, a resistance fuse network circuit utilizing non-linear characteristics will be described with reference to FIG. This is a network circuit in which nodes 902 corresponding to each pixel are connected by a resistive fuse element 901 having a non-linear characteristic. Here, 903 is a voltage source that generates a voltage Ii corresponding to the luminance value of the pixel i of the input image, and 904 is a resistor having a conductance σ. A typical resistance fuse characteristic G (V) is shown in FIG. 3 (b). The function G (V) changes the shape in order, for example, from (1) to (4). That is, the linear function (1) is used in the initial stage of the operation, and linear at the end of the operation when V is equal to or less than a predetermined threshold value δ, and 0 otherwise (4) To use. By doing so, good edge preservation and smoothing can be performed.

Conventionally, the resistance fuse element is realized by a circuit in which MOS transistors are combined as described in the above-mentioned reference 2, and a method of integrating the analog network circuit itself into an integrated circuit has been tried. Since such an analog circuit system requires a small circuit scale, a pixel parallel type integrated circuit can be realized. However, due to the difficulty of controlling the analog characteristics and manufacturing variations of the device, practical products have not been designed and manufactured until now.

Now, in order to algorithmically obtain the solution of the resistive fuse network, the circuit dynamics may be expressed by a discrete time system and solved. That is, the state Oi of the i-th pixel is updated according to the following formula, and is updated until all the pixels converge.

[Equation 1] Where ν is a constant and Ni is the set of adjacent pixels of pixel i. As described above, the function G (V) changes the function shape in order from (1) to (4) as the updating process progresses.

Therefore, a method has been proposed in which a processing unit corresponding to each pixel is prepared and arithmetic processing is executed in parallel with pixels by exchanging information between adjacent pixels (T. Morie, M. Miyak.
e, S. Nishijima, M. Nagata, and A. Iwata, "A multi
-functional cellular neural network circuit using
pulse modulation signals for image recognition, "7t
h International Conference on Neural Information P
rocessing ICONIP-2000 Proceedings, pp. 613-617, Ta
ejon, Korea, Nov. 2000 .: Reference 4). This is to store the state value at each time point in each processing unit, calculate its own state value at the next time point based on the state values of adjacent pixels, and process the state value at the time point when the update converges. By using the results, the analog dynamics in the resistance network can be realized approximately.

Such pixel parallel processing is difficult to realize in a digital circuit whose circuit scale becomes large. Therefore, Reference 4
Pixel parallel processing is realized in a small circuit scale by using pulse modulation circuit technology. Here, the pulse modulation circuit technology is a technology of an information processing circuit in which pulse width and pulse phase (deviation time from a reference time) have analog information. Compared to analog voltage signals, pulse width modulation (PWM) signals or pulse phase modulation (PPM) signals are less susceptible to noise, and many calculation and input / output circuits can use digital methods, so design and control are possible. Easy,
There is an advantage that accuracy can be easily secured.

A conventional circuit disclosed in Document 4 is shown in FIG. The operating principle will be described below with reference to the timing chart of FIG.

In this processing, the state value and the initial value of the processing unit are held in the capacitor as electric charges respectively, the terminal voltage of the capacitor is read out and converted into a PWM signal. The difference between the PWM signals is obtained by exclusive OR.
The state value can be updated by switching the current source with the PWM signal and charging / discharging the capacitor with a charge amount proportional to the pulse width.

The following description ("Embodiment of the Invention")
It is assumed that all the current sources described in (1) include the saturation region of the MOS transistor, so a switch connected in series to the current source (this is also assumed to be composed of MOS transistors). The current source can be switched by opening and closing. However, similar means may be used for this part as long as it is a switchable current source. Further, it is assumed that all capacitors in the circuit are reset to a predetermined initial voltage by a switch (not shown) before the operation. Further, the voltage sources 50 to 53, and 59 shall supply a voltage waveform commonly to all the processing units.
The operating principle will be described.

(1) An initial voltage based on the brightness value of each pixel is stored in the capacitor 10 from the node 89 through the switch 26 and is held as the voltage of the node 80. On the other hand, prepare a capacitor 11 that holds the state value of each processing unit, and
The state value is held in 81.

(2) The voltages at nodes 80 and 81 are fed into linear ramp voltage sources 50 and 51 using comparators 30 and 31, respectively.
By comparing the PWM signal to nodes 90 and 91
To generate. Similarly, PW generated by another processing unit
The M signal, the PWM signal generated by a similar circuit for bias, and the like are supplied to the nodes 87 and 88.

(3) The selector 100 selects two desired signals from the PWM signals, and the nodes 92 and 9 are selected.
It is input to the subtraction circuit 110 via 3.

(4) The subtraction circuit 110 calculates the magnitude relationship of the pulse widths of the PWM signals input from the nodes 92 and 93 and the absolute value of the difference, and outputs the binary signal representing the magnitude relationship to the node 95.
Then, a PWM signal having a pulse width corresponding to the absolute value of the difference is output to the node 94. That is, as shown in FIG. 4B, the input PWM signal is used to generate a PWM signal by the exclusive OR operation circuit composed of the logic gates 61 to 65, and at the same time, a binary value indicating the magnitude relationship is expressed. Signal to RS
It is held by the flip-flop 66.

(5) The PWM signal generated at the node 94 closes the switch 24 and causes the current source 42 to store the charge proportional to the pulse width in the capacitor 12 and hold the voltage proportional to the pulse width at the node 82.

(6) A PWM signal is generated at node 96 by comparing the voltage at node 82 with linear ramp voltage source 52 using comparator 32. Here, by adjusting the current amount of the current source 42 and the voltage change amount of the linear ramp voltage source 52,
The pulse width of the PWM signal at node 96 should be equal to that at node 94.

(7) The PWM signal generated at the node 96 closes the switch 25, and when the pulse falls and the switch 25 opens, the voltage of the non-linear voltage source 59 whose voltage changes with an arbitrary non-linear function with time. The value is held in the capacitor 13. As a result, the node 83 holds the voltage value obtained by converting the pulse width of the PWM signal generated at the node 96 by the non-linear function.

(8) A PWM signal is generated at node 97 by comparing the voltage at node 83 with linear ramp voltage source 53 using comparator 33.

(9) Switch 20 by the binary signal of node 95
Alternatively, either 21 is closed and PWM generated at node 97
By closing the switch 22 or 23 for the time corresponding to the pulse width of the signal, the electric charge is discharged from the current source 40 or 41 to the capacitor 11. As a result, the status value of the processing unit is updated.

By repeating the above process, the state is updated and a stable state is obtained. For example, when executing the equation (1), each processing unit first selects the state value of itself and the state value of the processing unit corresponding to the adjacent pixel with the selector, and the voltage waveform of the nonlinear voltage source 59 at time t G (t) is used as a function, the first term on the right-hand side of Equation 1 is sequentially calculated, and the state value of itself is updated. Further, by selecting its own initial value and its own state value and making the voltage waveform a linear function having a slope of σ, the second term on the right side is calculated and the state is updated. By repeating these series of processes, the solution of the resistance fuse network can be obtained. Other resistance network models can be similarly implemented. In the circuit described above, the input difference is processed by dividing it into a sign and an absolute value, so that the function that can be realized is limited to an odd function such as G (V).

Note that in the above process, the pulse width of the PWM signal at node 96 is equal to that of the PWM signal at node 94, but the latter cannot be used in place of the former. That is, the non-linear voltage source 59
Is to be supplied to all processing units in common, so in accordance with the start timing of voltage waveform generation,
The PWM signal must also rise. However,
In the case shown in FIG. 5, the PWM signal of the node 94 is the node
Since the PWM signal of 92 rises from the fall,
The rising timing is not uniform for each processing unit. Therefore, this is once converted into a voltage value, and a PWM signal that matches the rising timing of the lamp voltage source 52 common to each processing unit is generated.

[0023]

Since the operation described above requires a large amount of processing, the circuit scale becomes large, the power consumption increases, and the processing time becomes long. That is, since four comparators that occupy a large area and consume a large amount of power are required, the occupied area on the chip of the processing unit circuit and the power consumption increase. Further, since the pulse width modulation signal has to be sequentially generated three times, the processing time becomes long.

Further, the non-linear voltage source 59 needs to charge the capacitor 13, and the capacitance of this capacitor needs to be relatively large in order to ensure accuracy (1 pF).
Therefore, it is necessary to increase the driving force of the non-linear voltage source. Further, in order to prevent the influence of charging / discharging in each processing unit from affecting other processing units, it is necessary to provide a buffer for each processing unit in the non-linear voltage source 59, which causes an increase in circuit area and power consumption. Was there.

For the above reasons, this circuit configuration has a problem that the number of processing units that can be integrated on one chip is reduced.

[0026]

In order to eliminate such drawbacks, the present invention discloses a pulse modulation circuit that subtracts two signals and applies it to an image processing circuit to reduce the area and size. A power processing circuit is disclosed.

That is, according to the first aspect of the invention, in the circuit for calculating the magnitude relationship between two analog voltages and the absolute value of the difference, the two analog voltages are respectively combined in a predetermined combination so that the first and second capacitors have the first and second analog voltages. Of the two capacitors by applying a first predetermined voltage to the second terminal of the first capacitor and a second predetermined voltage to the second terminal of the second capacitor. After charging, a first means for connecting the first terminals of the two capacitors to each other to form a series-connected capacitor set, and a second predetermined voltage for the second terminal of the first capacitor are applied. A second signal is applied to obtain a result of comparing the voltage generated at the second terminal of the second capacitor with the second predetermined voltage, and the binary signal is the third signal. If the specified value of is not The two analog voltages are applied to the first terminals of the two capacitors in a combination opposite to the predetermined combination, and are charged again by the first means to form a series-connected capacitor set, A pulse width having a pulse width corresponding to an absolute value of a difference between the two analog voltages according to the binary signal when the first predetermined voltage is monotonically changed with time in the second means. There is provided an information processing circuit characterized by generating a modulation signal or a pulse phase modulation signal having a time delay corresponding to an absolute value of a difference between the two analog voltages.

Further, in the second invention, by using the circuit provided in the first invention, the circuit is composed of a plurality of processing units that are connected in a predetermined manner, and each processing unit has a processing unit for each processing unit. First and second analog value storage means for storing the associated analog state value and analog initial value, respectively, and a plurality of other analog state values and analog initial values for each processing unit and a plurality of other processing units coupled to the processing unit. Means for selecting two predetermined analog values from the analog state value of the processing unit and a predetermined bias analog value, and the absolute value of the difference between the two selected analog values is calculated, and the absolute value is arbitrarily set to the absolute value. A function for increasing or decreasing the amount obtained by performing the function conversion of the above from the first analog value storage means according to the magnitude relation between the two selected analog values. In the information processing circuit, the processing unit holds each of the two analog values as a voltage in each of the two capacitors and couples the two capacitors in series, thereby Means for generating a binary signal representing the magnitude relationship, means for generating a pulse phase modulation signal having a time delay corresponding to the absolute value of the difference between the two voltages, and a current amount temporally in accordance with a predetermined function. By switching the varying current source with the pulse phase modulation signal,
There is provided an information processing circuit including means for increasing or decreasing the storage amount from the first analog value storage means according to the binary signal.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to a circuit diagram 1 and a timing chart FIG. These drawings are examples of the embodiment for carrying out the invention,
In the figure, the parts denoted by the same reference numerals as those in FIGS. 4 to 5 represent the same parts.

The basic structure of the processing unit circuit shown in FIG. 1 is the same as that of the conventional circuit shown in FIG. 4, but the subtraction circuit 110 is mainly changed. Modified subtraction circuit 1
11 is more complicated than the conventional circuit, but the output of node 94 is P
Instead of a WM signal, it is a pulse phase modulated (PPM) signal, which switches the current source directly through switches 20-23. That is, the circuit block after the subtraction circuit 110, which is included in the conventional circuit, is eliminated and the configuration is simple. Also, the processing time is shortened as described below.

The subtraction circuit 110 is disclosed as an independent circuit block as a pulse modulation type subtraction circuit as described in claim 1.

In FIG. 1, analog buffers 300 and 301 are installed instead of the comparators 30 and 31, respectively. A source follower circuit, for example, is used as the analog buffer. Therefore, the signal generated at the nodes 90 to 93 is not the PWM signal as in the conventional circuit,
It is an analog voltage. Signals sent from other processing units, such as via node 87 or 88, are also analog voltages. The analog voltage has a drawback that it is weak against noise as compared with the PWM signal, but since it is a local wiring between adjacent pixels, it is possible to perform a design less susceptible to noise. In connection with this, the selector 100 is configured to switch the analog voltage.

Further, the current sources 40 and 41 are respectively
Non-linear current source 400 whose current changes as an arbitrary function over time
And 401.

In FIG. 1, similar to FIG. 4, the analog state value and the analog initial value of each processing unit are held in the capacitors 11 and 10, respectively, but other analog value storage means such as a floating gate device or a strong gate device is used. A circuit using a dielectric or ferromagnetic device is also applicable. The operation of the processing unit circuit will be described in detail below. In this circuit, clock control is used, and in FIGS. 1 and 2, clk0 to clk5 are used as control clock signals given from the outside. Further, clk1 and clk2 control the switches 200 to 203 as clkA to clkD by a changeover switch.

(1) The selector 100 selects a pair of signals to be calculated and inputs them to 92 and 93.

(2) First, the switch 207 is set by clk0.
Is temporarily closed, the latch circuit composed of the inverters 603 and 604 is reset, and the node 95 is set to "High". As a result, the clk1 signal appears at clkA and the clk2 signal appears at clkD.

(3) The switches 200, 203, and 205 are closed by setting clk1, clk2, and clk4 to "High". Further, the node 70 is held at 0V level, the potential of the node 92 is given to the node 71, the potential of the node 93 is given to the node 72, and the node 73 becomes the threshold potential (Vth) of the inverter 600. .

(4) clk4 is set to "Low", the switch 205 is opened, clk1 (that is, clkA in this case) is set to "Low", and the switch 200 is opened. Next, set clk3 to "High" and switch 204
And then clk2 (ie clkD in this case) "Low"
Then switch 203 is opened. The reason why the switches are operated in this order is to prevent the influence of the parasitic capacitance of the MOS transistors that make up the switches.

As a result, the capacitors 14 and 15 are connected in series, and the potential of the node 73 (V73) is the difference between the potential of the node 92 (V92) and the potential of the node 93 (V93) plus Vth. (V73 = V92-V93 + Vth). Therefore, if V92> V93, the node 74 becomes "Low", and vice versa. This makes it possible to determine the magnitude relationship between V92 and V93. The inverters 601 and 602 are installed to arrange the waveform when the inverter 600 is inverted, and the threshold value is set so that an unnecessary waveform does not appear at the node 74 when the switch 205 is closed.

(5) The switch 206 is temporarily closed by clk5, the potential of the node 74 is taken into the latch circuit, and the node 74
The inverted potential of the potential of is held at node 95. V93 in Figure 2
It shows the case of> V92. When clk5 becomes "High", V95 is inverted and becomes "Low". At this time (Tx), the magnitude of the potentials of the nodes 92 and 93 was determined. Since the above process is only the process of charging and discharging the capacitors 14 and 15, the process can be performed at extremely high speed.

(6) According to the potential of the node 95, clk1 and clk
k2 is set to clkA or clkC, clkD or clkB, respectively. (Inverted in the case of FIG. 2). In this state, the processes (3) and (4) are re-executed. As a result, the node
At 73, the voltage that is the difference between the absolute values of V92 and V93 plus Vth appears.

(7) The ramp voltage is applied to the node 70 from time T0. For example, the potential is increased linearly. V70 potential is |
The inverter 600 reverses when it becomes equal to V92-V93 |. If this time is T1, T1-T0 is proportional to | V92-V93 |. Note that this lamp voltage does not necessarily need to change the potential linearly with time, and when it is changed by an arbitrary monotonically increasing function, T1-T0 is the inverse function of | V92-V93 | . However, the case where a linear ramp voltage is used will be described below.

(8) A pulse phase modulation circuit having inverters 605 to 607 and a NOR gate 608 having a pulse width (Δt) determined by the delay time of the inverters 605 to 607 when the potential of the node 74 falls. (PPM)
The signal appears at node 94.

(9) Either the switch 20 or 21 is closed according to the potential of the node 95, and the PPM signal at the node 94 closes either the switch 22 or 24 by the minute width Δt at time T1. On the other hand, the current value that the current sources 400 and 401 can flow is
Let G (t) be a function of time t based on time T0. As a result, the charge of G (T1-T0) Δt only at time T1 is
Is charged or discharged and the status value is updated. T1-T0 is |
Since it is proportional to V92-V93 |, the first term on the right-hand side of the equation of Formula 1 can be calculated. Further, a linear function can be realized by linearly increasing the current value that can be passed by the current sources 400 and 401 with respect to the time T0 as a base point, and the second term on the right side of the expression of Formula 1 can be calculated.

As the current sources 400 and 401, MOS transistors operating in the saturation region may be used, and the gate voltage may be changed so that a desired current change can be obtained. Since the gate voltage that changes non-linearly with respect to time may be commonly applied to all the processing units, only one circuit for generating the non-linear voltage waveform may be provided in the entire processing circuit. Since this voltage waveform generation circuit only needs to have a driving capability capable of charging the gate capacitance, it requires less driving force than the non-linear voltage waveform generation circuit required in the prior art, and can reduce the circuit area and power consumption. it can.

The above process may be repeated for a predetermined combination of two signal amounts, until the state values converge.

Compared with the conventional circuit shown in FIG. 4, the circuit disclosed here requires a very short time to first determine the magnitude relationship between two inputs, and therefore the processing time is almost zero.
It is fast because it is determined only by the time to generate one PWM signal. That is, in FIG. 2, the processing up to time T0 is exaggeratedly expressed in the time axis direction so as to be easily seen, but most of the processing time is spent after T0 when the PWM signal is generated. In addition, it has the feature of saving power because it requires only one comparator (which corresponds to the inverter 600 here) that consumes most of the power.

Needless to say, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the present invention.
For example, the set potential, the direction of the lamp voltage, etc. are appropriately determined.

[0049]

As described above, according to the present invention,
PWM takes up most of the processing time compared to conventional circuits
Since the time to generate the signal can be reduced to about 1/3,
Higher speed can be achieved. Further, since the number of comparators that occupy most of the power consumption can be reduced from four to one, there is an effect of saving power. Furthermore, by changing the non-linear voltage source of the conventional circuit to use the non-linear current source, the buffer circuit for increasing the driving force and for preventing the interference with other processing units is not required. And the effect that power consumption can be reduced was produced. With the above effects, more processing units can be integrated on a chip, and when used for image processing, it becomes possible to handle an image having a larger number of pixels.

[Brief description of drawings]

FIG. 1 is a circuit diagram illustrating an image processing apparatus of the present invention. The detailed diagram (b) of the entire circuit (a) and the subtraction circuit 111, and the clock signal distribution diagram (c). The switch positions are shown when the control signal is "Low".

FIG. 2 is a timing diagram illustrating a circuit operation of the image processing apparatus of the present invention. V with a subscript is the voltage of the corresponding node, and I is the current that can flow through the current source (not the current that actually flows).

FIG. 3 is a diagram for explaining a “resistive fuse network” of the related art.

FIG. 4 is a circuit diagram illustrating a conventional image processing apparatus. A detailed view of the entire circuit (a) and the subtraction circuit 110 (b). The switch positions are shown when the control signal is "Low".

FIG. 5 is a timing diagram illustrating a circuit operation of a conventional image processing apparatus.

[Explanation of symbols]

10 to 15 ... Capacitors 20 to 26, 200 to 211 ... Switches 30 to 33 ... Comparators 300, 301 ... Analog buffers 40, 41 ... Constant current sources 400, 401 ... Current sources whose current value changes as a function of desired time 50-53, 59 ... Voltage sources 60-62, 600-607 whose current value changes as a function of desired time ... Inverters 63-65, 608 ... Logic gate 66 ... RS flip-flops 70-74, 80-83, 87 ... 89, 90 to 97 ... Node 100 ... Selector 110, 111 ... Subtraction circuit clk0-clk5 ... Control clock signal

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Minoru Iwata             2-360 Kagamiyama, Higashihiroshima City, Hiroshima Prefecture (72) Inventor Makoto Nagata             2-1-19 Danbara, Minami-ku, Hiroshima City, Hiroshima Prefecture             Tote N Building 2707 F-term (reference) 5B057 CH01 CH20

Claims (2)

[Claims] 1. A circuit for calculating the magnitude relationship between two analog voltages and the absolute value of the difference, wherein the two analog voltages are applied to the first terminals of the first and second capacitors in predetermined combinations, respectively. The second of the first capacitor
The first predetermined voltage to the terminal of the second capacitor of the second
By applying a second predetermined voltage to the terminal of the
After charging one capacitor, first means for connecting the first terminals of the two capacitors to each other to form a series-connected capacitor set, and a first predetermined terminal for the second terminal of the first capacitor. And a second means for obtaining the result of comparing the voltage generated at the second terminal of the second capacitor with the second predetermined voltage by a binary signal. Is not a third predetermined value, the two analog voltages are applied to the first terminals of the two capacitors in a combination opposite to the predetermined combination, and the second analog voltage is charged again by the first means. And forming a set of capacitors connected in series, the first means in the second means.
Pulse-width modulation signal having a pulse width corresponding to the absolute value of the difference between the two analog voltages, or the two analog voltages, according to the binary signal when the predetermined voltage of is changed monotonically with time. An information processing circuit, which generates a pulse phase modulation signal having a time delay corresponding to the absolute value of the difference between the two. 2. A circuit comprising a plurality of processing units having a predetermined connection, wherein each processing unit stores an analog state value and an analog initial value associated with each processing unit, respectively. A predetermined value is selected from the analog value storage means, the analog state value and the analog initial value of each processing unit, and the analog state value of a plurality of other processing units coupled to the processing unit and the predetermined biasing analog value. Means for selecting one analog value and an absolute value of a difference between the two selected analog values, and an amount obtained by performing an arbitrary function conversion on the absolute value, from the first analog value storage means, In the information processing circuit having means for increasing or decreasing according to the magnitude relation between the two selected analog values, each processing unit Doo, holds the two analog values into two capacitors respectively as voltages, the 2
Means for generating a binary signal representing the magnitude relationship between the two voltages by connecting two capacitors in series, and a pulse phase modulation signal having a time delay corresponding to the absolute value of the difference between the two voltages And a current source whose current amount changes with time according to a predetermined function by the pulse phase modulation signal, thereby increasing the storage amount from the first analog value storage unit according to the binary signal. Alternatively, an information processing circuit including a means for reducing the information processing circuit.