JP2003044177A - Computer system, power supply controller and method or managing power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a computer system, a power supply managing method, etc., capable of performing power supply rich in variation. SOLUTION: This computer system performs power supply control in a gate array 42 based on an indication of an OS and a BIOS on an on mode with respect to a bay device 33 connected to a bay 32, and performs power supply control by an embedded controller 41 in a sleep mode and an off mode. By using an OR gate 71, setting is performed so that output signals (BAY- ON- EC and BAY- ON- GA) from the embedded controller 41 and the gate array 42 do not interfere with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer device to which an external expansion device can be attached, a power supply control device therefor, and a power supply management method.

[0002]

2. Description of the Related Art Conventionally, a notebook PC (Perso
nal Computer), built-in HDD (Hard Disk Dr
In addition to ive), FDD (Floppy Disk Drive), CD (Compac
t Disk) -ROM (Read Only Memory) drive, DVD
(Digital Versatile Disk) -ROM drive, built-in H
Various devices other than the DD, such as additional HDDs, could be equipped as external expansion devices. At the time of purchase, the user selected a desired device from various devices. In recent PCs, these various devices are detachably attached to a portion called a bay or the like, and the devices can be replaced with one touch if necessary. Generally, when attaching or detaching such a device, it is necessary to turn off the power supply of the PC, but recently, when the power supply mode of the PC is an on mode, which is called hot swap, warm swap, or the like, ,
Sleep / suspend state, hibernation state, etc.
Some devices allow the device to be attached and detached even in the mode.

In order to perform hot-swap / warm-swap on such a device, the computer system is shown in FIG.
It has a power supply control configuration as shown in. That is, I attached to a bay (not shown) in a detachable state
The DE device 1 and the FDD 2 are FET (Field Effect Tr
Power is supplied from a power source via an ansistor (field effect transistor) switch 3. The FET switch 3 is under the control of the OS, and the IDE device 1 and F
At the time of hot swap / warm swap of the DD2, the power supply to the IDE device 1 and the FDD2 was cut off by the control of the OS. More specifically, for example, when the user tries to remove the IDE device 1 or the FDD 2 from the bay, an event corresponding to this is notified to the OS via the BIOS. If the OS accepts the removal,
The BIOS is notified of this, and the BIOS
Rewrite the register value of register 4. by this,
The FET switch 3 is operated by switching the output signal from the gate array register 4 to cut off the power supply to the IDE device 1 and FDD 2 in the bay. In this state, the IDE device 1 and the FDD 2 can be attached and detached (in this case, detached). It has been common sense that a device capable of hot-swap / warm-swap in this manner does not turn on / off power supply to the device when it is not under the control of the OS.

By the way, a PC, especially a notebook type P
In order to save the power consumption of the battery, C is a so-called sleep mode or off mode (shutdown mode) that saves power when the idle state without input continues for a certain period of time. It is possible to switch to the mode. ACPI (Advance
d Configuration and Power Interface), the power-saving mode is divided into five stages of "S1" to "S5", in contrast to "S0" which is a normal use mode in the ON mode,
"S1", "S2", and "S3" are sleep modes,
"S4" is the hibernation mode, and "S5" is the off mode in which the power is off. here,
The power saving modes of "S1" to "S5" are set in stages from "S1" to "S5" so that the target (parts or devices) to which power is supplied gradually decreases.

Since the removable devices as described above are generally used when the power of the PC is on, power supply to these devices is limited when the PC is in the ON mode. It was normal. Therefore, sleep mode and hibernation mode
In the off mode (hereinafter, appropriately referred to as sleep mode), these devices are not targets for power supply, that is, power supply to the devices is off.

[0006]

However, in recent years, in addition to IDE devices and FDDs, for example, USB (Universal Serial Bus) devices and cradle for PDA (communication function between PDA and PC) have been recently used as removable devices. Have been attempted to commercialize devices and the like that can be used as (for example, having a charging function for PDAs).
In addition, mobile phone terminals and PDAs (Personal Digital Assi
With the widespread use of various peripheral devices such as stants), devices that can be attached to and detached from a PC have come to be used in a sleep mode even when in a sleep mode. For example, when you want to charge the PDA with the PDA cradle when the PC is in sleep mode, or when you want to return the sleep mode PC to the on mode by operating an external keyboard or the like as a USB device. Etc. In these cases, PD
It is necessary to supply power to the A cradle and the USB device even when the PC is in the sleep mode.

In response to such a problem, as shown in FIG. 13, an IDE / FDD power supply system L1 for IDE devices and FDDs and a USB power supply system L2 for USB devices are provided.
And the cradle power supply system L3 for the cradle,
It is conceivable that these can be switched by the FET switch 5. However, this not only complicates the structure and raises the cost, but also F
Since the ET switch 5 also causes a voltage loss, it cannot be said to be the optimum solution. In addition, due to the actual device configuration, for example, the already shipped IDE device or FDD
However, in order to be able to use the new type PC, it is necessary to standardize the connectors and the like. When the power supply system is divided into the systems L1, L2, and L3 as described above, there may be a case where the number of pins is insufficient to make the connector common, and in such a case, it is impossible to realize. In some cases.

The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a computer device, a power management method, and the like capable of supplying power with a wide variety.

[0009]

With such an object, the computer apparatus of the present invention controls the power supply to the external expansion device by the first control means when the computer apparatus is in the ON mode, and By the second control means, the computer device
A feature is that power is supplied to the external expansion device according to the type of the external expansion device when in a sleep mode (including a hibernation mode) or an off mode such as an off mode. Normally, a computer such as a PC controls the power of an external expansion device under the control of an OS (Operating System). The first control means has the same power supply control function as the conventional one. On the other hand, the second control means controls the power supply to the external expansion device when the computer device is in the hibernation state, thereby allowing the external expansion device to function in the hibernation state without operating the OS. Etc. are possible. In this case, power supply control can be performed according to the type of external expansion device.

At this time, the second control means can control the power supply to the external expansion device according to the type of power supply for driving the computer device, that is, whether it is the AC adapter or the battery. For example, when a battery having a limited capacity is used, power is not supplied to the external expansion device, and power can be supplied only when an AC adapter is used. Further, when the external expansion device has a charging function, the second control means may supply power to the external expansion device. In this case, since charging is not always performed, it is preferable to supply power when a device to be charged is connected and a power request signal is received from an external expansion device. In addition, when the external expansion device has a function of returning the computer device to the ON mode in response to the input made to the external expansion device, the power can be supplied in the hibernation state. Is. In this case, it is preferable that the computer apparatus is set to be able to return to the ON mode by operating the external expansion device or the like.

Further, in the computer device according to the present invention, in the first controller, the basic input / output system is used.
A signal for controlling power supply to the connector is output based on the instruction of (BIOS: Basic Input / Output System). The second controller outputs a signal for controlling the power supply to the connector according to the type of the external device connected to the connector when the computer device is in the sleep mode or the off mode. Then, the determination unit determines whether or not to supply power to the connector based on the signal from the first controller and the signal from the second controller, and based on the determination result, the power supply circuit determines the connector. The power supply unit turns on and off the power supply to the. More specifically,
The signal from the first controller is unchanged when the computer device is in the sleep mode or the off mode, and the second controller outputs the signal depending on whether a predetermined external device registered in the connector is connected or not. Signal changes, and the power supply is turned on and off accordingly. Also, when the computer device is in the ON mode, the signal from the second controller is unchanged, and the signal from the first controller is detected by the BIOS depending on whether or not an external device is connected to the connector. The power supply can be turned on and off by changing It should be noted that the determination as to whether or not to supply power can be made when the power supply mode of the computer apparatus shifts, or when an external device is attached to or detached from the connector.

According to the present invention, when the operating system is under control, power is supplied to the connector under the control of the operating system, and when the operating system is not under control, the connector is operated according to the type of the external device connected to the connector. It can also be regarded as a computer device including a controller for controlling power supply to the connector.

When the present invention is regarded as an expansion-based power supply control device to which an external device can be attached, a signal for controlling the power supply is output from the first controller when it is under the control of the operating system. , The second controller outputs a signal for controlling the power supply to the expansion base according to the type of the external device when not under the control of the operating system, and the controller outputs the signal from the first controller and It can be considered as a configuration for controlling the power supply to the expansion base based on the signal from the second controller. The expansion base includes a portion called a bay or the like for mounting an external device built in the computer device, and is attachable to and detachable from the computer device to which an external device can be attached. It may include what is called a docking station or the like.

The present invention comprises the steps of identifying the type of external expansion device attached to the connector, detecting the power mode of the computer device, the type of external expansion device identified and the detected power mode. It can also be regarded as a power management method characterized by having a step of determining whether to supply power based on the above, and a step of supplying power to the connector based on the determination result. Here, when it is detected that the external expansion device is removed from the connector when the power supply mode of the computer apparatus is the sleep mode or the off mode, it may be determined whether the external expansion device can be removed from the connector. it can. As a result, when the external expansion device is an HDD used for booting the computer device, and the removal of the external expansion device from the connector is not permitted, the power mode of the computer device should be switched to the on mode. You can also

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below in detail based on the embodiments shown in the accompanying drawings. FIG. 1 is a diagram showing a hardware configuration of a computer system (computer device) 10 according to the present embodiment. A computer device including this computer system 10 is
For example, OADG (Open Architecture Developer's Gro
In accordance with the up) specification, it is configured as a notebook PC equipped with a predetermined OS (operating system).

In the computer system 10 shown in FIG. 1, the CPU 11 functions as the brain of the entire computer system 10 and executes various programs under the control of the OS. CPU 11 is FSB which is a system bus
(Front Side Bus) 12, PCI (Peripheral Component Interconnect) bus 2 as a high-speed I / O device bus
0, ISA (Industry S) as a low-speed I / O device bus
Each component is interconnected via a three-stage bus called a tandard architecture bus 40. This CPU
11 stores the program code and data in the cache memory to speed up the process. In recent years, 128K as a primary cache inside the CPU 11
Byte-sized SRAM is integrated, but in order to make up for the lack of capacity, it is a dedicated bus BSB (Back Side Bus)
A secondary cache 14 of about 512 K to 2 Mbytes is provided via 13. BSB13 is omitted and FS
By connecting the secondary cache 14 to B12 and avoiding a package having a large number of terminals, it is possible to keep the cost low.

The FSB 12 and the PCI bus 20 are connected to a memory /
It is connected by a CPU bridge 15 called a PCI chip. The CPU bridge 15 includes a memory controller function for controlling an access operation to the main memory 16 and a data buffer for absorbing a difference in data transfer speed between the FSB 12 and the PCI bus 20. Has become. The main memory 16 is a CPU
11 is a writable memory used as a read area of the execution program 11 or as a work area for writing the processing data of the execution program. This execution program includes various drivers for operating the hardware of the OS and peripherals, application programs for specific jobs, and firmware such as BIOS stored in the flash ROM 44 described later.

The video subsystem 17 is a subsystem for realizing functions related to video and includes a video controller. This video controller processes a drawing command from the CPU 11, writes the processed drawing information in the video memory, reads the drawing information from the video memory, and then displays the drawing information.
D) 18 is output as drawing data.

The PCI bus 20 is a bus capable of relatively high-speed data transfer.
O bridge 21, card bus controller 22, miniP
The CI connectors 27 are respectively connected.

The card bus controller 22 is a dedicated controller for directly connecting the bus signal of the PCI bus 20 to the interface connector (card bus) of the card bus slot 23.
It is possible to load a PC card 24 on the. mi
A mini PCI (mini PCI) device 60 is connected to the ni PCI connector 27. The mini PCI device 60 is
It is an expansion card (board) that can be expanded according to the miniPCI specifications. This mini PCI is for mobile
It is a standard and is listed as an appendix to the PCI Rev.2.2 specification. Functionally, it is equivalent to full-spec PCI.

The I / O bridge 21 has a bridge function between the PCI bus 20 and the ISA bus 40. Also,
DMA controller function, programmable interrupt controller (PIC) function, programmable interval timer (PIT) function, IDE (Integrated Device Ele)
ctronics) interface function, USB (Universal Ser
real-time clock with the SMB (System Management Bus) interface function
(RTC) is built in.

The DMA controller function transfers data between a peripheral device such as an FDD and the main memory 16 by the CPU.
11 is a function to be executed without intervention. The PIC function is a function for executing a predetermined program (interrupt handler) in response to an interrupt request (IRQ) from a peripheral device. The PIT function is a function of generating a timer signal at a predetermined cycle. The interface realized by the IDE interface function is a built-in HD.
In addition to connecting D31, a bay device (external expansion device, external device) 33 is connected. Here, the bay device 33 is attached to / detached (inserted / removed) from / into the bay (connector, expansion base) 32 provided in the notebook PC main body
It is stored as much as possible. The bay device 33 is the bay 3
It has a unit shape having a predetermined outer shape according to 2. As such a bay device 33, a CD-R
IDE device 33A such as OM drive, USB device 33B, FDD 33C, PD to which USB connection is made
By setting A (device: not shown), it is responsible for data transfer between the PDA and the computer system 10,
There is also a PDA cradle 33D having a charging function for the PDA. These bay devices 33 can be attached as appropriate by the user according to the number of bays 32 provided in the PC body.

Further, the I / O bridge 21 is provided with a USB port, and this USB port is connected to a USB connector 30 provided on the side wall surface of the notebook PC body, for example.

Furthermore, the I / O bridge 21 is connected to the power supply circuit 50. The power supply circuit 50 includes an AC adapter (power supply) 51 and a main battery as a battery (secondary battery).
(Power source) 52 or a second battery (power source) 53 and a battery switching circuit 54 for switching the power supply path from the AC adapter 51 and each battery, and a DC constant of 5V, 3.3V or the like used in the computer system 10. A circuit such as a DC / DC converter (DC / DC) 55 that generates a voltage is provided.

On the other hand, inside the core chip constituting the I / O bridge 21, internal registers for managing the power supply state of the computer system 10 and management of the power supply state of the computer system 10 including the operation of this internal register are managed. There is a logic (state machine) to do. This logic sends and receives various signals to and from the power supply circuit 50, and by sending and receiving these signals, the actual power supply state from the power supply circuit 50 to the computer system 10 is recognized. The power supply circuit 50 controls the power supply to the computer system 10 according to the instruction from this logic.

The ISA bus 40 has a lower data transfer rate than the PCI bus 20. This ISA bus 40
Includes an embedded controller (second control means, second controller) 4 connected to a gate array (first control means, first controller) 42.
1. CMOS (Complementary simmetry Metal Oxide Se)
miconductor) 43, flash ROM 44, Super
The I / O controller 45 is connected. It is also used to connect peripherals that operate at relatively low speeds, such as keyboard / mouse controllers. This S
The upper I / O controller 45 has an I / O port 46
Are connected to control the driving of the FDD 33C, parallel data input / output (PIO) via the parallel port, and serial data input / output (SIO) via the serial port.

The embedded controller 41 controls a keyboard (not shown) and is connected to the power supply circuit 50 to have a built-in power management controller (PMC).
part of the power management function together with the gate array 42. As shown in FIG. 2A, the embedded controller 41 and the gate array 42 connected to the ISA bus 40 output signals (BAY_ON_EC, B) from each.
AY_ON_GA) output signal lines L11 and L12 are O
It is connected to an R gate (determination unit, control unit) 71. The output signal line L13 that transmits the output signal (BAY_ON) from the OR gate 71 is provided between the bay 32 and the VCC 72 that supplies power to the bay 32. Section, control section) 73. Then, the embedded controller 41, the gate array 42, the OR gate 71, and the FET switch 73 constitute a controller and a power supply control device that control the power supply to the bay device 33 mounted in the bay 32.

The bay 32 is a bay device 33, that is, an IDE device 33A, a USB device 33B, an FDD.
Connector for connecting 33C, PDA cradle 33D, etc.
(Not shown), this connector outputs the identification signal (BAYIDs) according to the type of the connected bay device 33 to the embedded controller 41. Here, when the PDA cradle 33D is connected to the bay 32 and a PDA (not shown) is charged by the PDA cradle 33D, the PDA cradle 33D requests the power supply voltage for charging.
(Charge Request: power supply request signal) is output to the embedded controller 41.

In the embedded controller 41, output signals (BAYIDs) from the bay 32, PDA cradle 33D
In addition to the charge request signal (Charge Request) from
Signal obtained by detecting whether or not the AC adapter 51 is connected (AC Adapter Presence), bay 3
2 receives a signal (BAYUNLOCK) obtained when a lever or the like is operated to attach or detach the bay device 33. And, this embedded controller 41 is
Based on these input signals, a start signal (EC_WAKE) for starting the system of the computer system 10
UP) can also be output. Now, in the OR gate 71, the embedded controller 41 and the gate array 42
The judgment is made based on the output signals (BAY_ON_EC, BAY_ON_GA) from the OR gate 71, which is a predetermined output according to the power supply state to the bay device 33 in the computer system 10 as described later. (Judgment result) can be obtained.

Now, as shown in FIG. 3, in such a computer system 10, when the power mode is changed from the off mode S5 to the on mode S0 by activating the system (OS), then the power is turned off. The operation returns to the off mode S5 when an operation for performing the operation is performed, and shifts to the sleep mode S3 when a preset predetermined condition is satisfied such that the no-input state continues for a predetermined time.
Then, when a mouse or a keyboard (not shown) is operated or the 10 keypad connected as the USB device 33B is operated, the computer system 10 returns from the sleep mode S3 to the on mode S0. ing. The one shown in FIG. 4 is colored to indicate that the computer system 10 in the sleep mode S3 is not supplied with power, and the one shown in FIG. 5 is supplied with power in the computer system 10 in the off mode S5. Those that do not exist are shown by coloring. As shown in FIGS. 4 and 5, in the sleep mode S3 and the off mode S5, the OS is not running because the CPU 11 is not supplied with power.
On the other hand, the embedded controller 41 and the gate array 42 are always supplied with power not only in the on mode S0 but also in the sleep mode S3 and the off mode S5. Note that the bay device 33 is attached / detached when the power is on mode S0, and the bay device 33 is attached / detached when the power is in sleep mode S3.

Here, FIG. 6 shows a status list of power supply control in the computer system 10. In the computer system 10, when a USB device 33B such as a 10 (numeric) keypad is connected as the bay device 33, when the USB device 33B is operated when the computer system 10 is in the sleep mode S3, It is possible to set whether or not the computer system 10 can be activated (wake up) by using this as a trigger (hereinafter, this is appropriately referred to as USB wake up). If the IDE device 33A or FDD 33C that is a drive device is connected to the computer system 10 as the bay device 33 among the bay devices 33 that are subject to power supply control in the present embodiment, the IDE device 3
3A or FDD33C is a computer system 1
0 is used only when 0 is in the on mode S0, regardless of whether or not USB wakeup is possible, power is supplied only when the computer system 10 is in the on mode S0. In the sleep mode S3 and the off mode S5, the power is not supplied (marked with "x" in the figure).

When the USB device 33B is connected to the computer system 10 as the bay device 33 and the USB wakeup is set to be impossible, the system state (power supply mode) of the computer system 10 is the on mode. Power is supplied only when S0 (marked by ".largecircle." In the figure), and not supplied when in sleep mode S3 and off mode S5 (marked by "x" in the figure). On the other hand, if the USB wakeup is enabled, the on mode S
0, and power is supplied to the USB device 33B in the sleep mode S3 (marked with “◯” in the figure), and power is not supplied in the off mode S5.
(Marked with "x" in the figure). Note that the setting of whether or not the USB wakeup is possible may be automatically performed by recognizing the type of the USB device 33B connected to the computer system 10.

PDA cradle 33D having a charging function
Is connected to the computer system 10 as the bay device 33, the PDA cradle 33D charges the PDA even when the computer system 10 is in the sleep mode S3 or the off mode S5.
Therefore, the power source of the computer system 10 is A
If the C adapter 51 is connected, the computer system 10 is in the ON mode S0, the sleep mode S3,
In any of the off mode S5, power is supplied to the PDA cradle 33D. In addition, as a power source of the computer system 10,
If the C adapter 51 is not connected and the main battery 52 or the second battery 53 is used as the power source, the computer system 10 supplies power only in the ON mode S0 in order to prevent consumption of the main battery 52 or the second battery 53. 6 and the power is not supplied in the sleep mode S3 and the off mode S5.
The power supply is performed in the ON mode S0 and the sleep mode S3 (marked with “◯” in the figure) and the power supply is not performed in the off mode S5 (marked with “X” in the figure) as shown in FIG. It is possible to

Now, in performing the power supply as described above, in the computer system 10, the OR gate 71 is used.
The operation of the FET switch 73 is controlled based on the output from the. FIG. 2B is a logical value table showing the output signal from the OR gate 71 for the output signal (BAY_ON_EC) from the embedded controller 41 and the output signal (BAY_ON_GA) from the gate array 42, which will be described in detail later. Based on such processing, the OR gate 71 makes a determination according to the above logical value table. Here, if the output signal (BAY_ON) from the OR gate 71 is L, the power supply to the bay device 33 is off (off), and if the output signal is H, the power supply to the bay device 33 is on (on). The FET switch 73 is controlled.

The gate array 42 is in the ON mode S when the power mode (system state) of the computer system 10 is ON.
If "0" is written in the register 42a (BAY_ON register) when it is 0, a "L" signal (BAY_ON_GA)
Is output, and if "1" has been written, an "H" signal is output. Further, when the power mode of the computer system 10 is the sleep mode S3 or the off mode S5 (that is, when the OS is not operating), the gate array 42 always outputs the signal of "L". There is. Incidentally, conventionally, the operation of the FET switch 73 was directly controlled by the output signal (BAY_ON_GA) from the gate array 42. On the other hand, the embedded controller 41 performs the processing described later in detail on the basis of a predetermined program written in advance, so that the "L" or "H" signal (B
AY_ON_EC) is output.

Here, for example, even if the OS (gate array 42) commands the power-on, the embedded controller 4
The embedded controller 41 and the gate array 42 are arranged so that the outputs of the embedded controller 41 and the gate array 42 do not collide or contradict each other, such as when the power supply 1 is commanded to be turned off.
It is preferable to predefine the division of roles and priorities of. In the present embodiment, the gate array 42 is mainly responsible for control in the ON mode S0, and performs hot swap of the IDE devices 33A, FDD 33C, USB device 33B, and power supply control for the USB device 33B. On the other hand, the embedded controller 41 is mainly responsible for the control in the sleep mode S3 and the off mode S5, and performs the warm swap of the bay device 33 in the sleep mode S3, the US
Power supply is maintained for B wake-up and control for charging the PDA cradle 33D is performed.

Now, FIG. 7 shows the bay device 3 in the bay 32.
3 shows a flow of processing when attaching No. 3. First, when the bay device 33 is attached to the bay 32,
The embedded controller 41 detects this, and outputs the identification signal (B) corresponding to the type of the attached bay device 33.
AYIDs) are read (step S101). In the normal state, the output signal (B
AY_ON_EC) is “L”.

Next, the embedded controller 41
Determines whether the computer system 10 is in the ON mode S0 (step S102). As a result, if the computer system 10 is in the ON mode S0,
The read identification signal (BAYIDs) of the bay device 33 is BI.
The OS is notified (step S103), and the output signal (BAY_ON_E) from the embedded controller 41 to the OR gate 71 is sent.
C) maintains "L" as it is (step S104).

On the other hand, on the BIOS side which has received the notification from the embedded controller 41 in step S103, the type of the bay device 33 attached to the bay 32 is identified based on the notified identification signal (BAYIDs) of the bay device 33. (Step S105). And as a result of identification,
Whether the attached bay device 33 is a hot-attachable device or not is determined based on the information written in the BIOS in advance (step S106). As a result, if the bay device 33 is a hot-attachable device, "1" is written in the register 42a of the gate array 42 (step S107). Then, the output signal (BAY_ON_GA) from the gate array 42 becomes "H".
(Step S108). As a result, the output signal (BAY_ON) from the OR gate 71 is transmitted to the embedded controller 41.
Output signal (BAY_ON_EC) from "L", gate array 4
Since the output signal (BAY_ON_GA) from 2 is "H",
According to the logical value table of (b), it becomes "H", that is, the power supply to the bay device 33 is turned on.

On the other hand, in step S106, for example, the OS
When the processing load of the device is too large to support hot attach processing, or when the attached bay device 33 is BIOS
When it is determined that hot-attach is not possible, such as when it is not registered in the gate array 42,
The register 42a of is left as "0" (step S1).
09). Then, the output signal from the gate array 42 (BAY_
ON_GA) remains "L" (step S110). Accordingly, the output signal (BAY_ON) from the OR gate 71 is the output signal (BAY_ON_E) from the embedded controller 41.
C) is “L” and the output signal (BAY_ON_) from the gate array 42
Since GA) is also “L”, it is “L” according to the logical value table of FIG. 2B, and the power supply to the bay device 33 remains off, that is, the hot attachment of the bay device 33 to the bay 32 is not supported. Thus, if the power mode of the computer system 10 is the ON mode S0,
The same processing as the conventional hot attach processing is performed depending on the processing in the BIOS.

If it is determined in step S102 that the computer system 10 is not in the on mode S0, that is, the sleep mode S3 or the off mode S5, the control by the BIOS and OS is not performed, It depends on the control by the embedded controller 41. In this case, first, the attached bay device 33 is the PDA cradle 33D,
Moreover, it is determined whether or not a charge request signal (Charge Request) is input to the embedded controller 41 (step S111). As a result, if the attached bay device 33 is not the PDA cradle 33D, the output signal (B
AY_ON_EC) remains "L" (step S104).
On the other hand, the attached bay device 33 is the PDA cradle 33D and the charge request signal (Charge Recharge
quest) is input, it is determined whether the computer system 10 is in the sleep mode S3 (step S112). If the result is the sleep mode S3, as shown in FIG. Power supply is AC adapter 5
The output signal (BAY_ON_EC) from the embedded controller 41 is switched to "H" because the power is supplied to the PDA cradle 33D regardless of whether the battery is the main battery 52 or the second battery 53. (Step S113). Further, in step S112, the computer system 10 is set to sleep.
When it is determined that the mode is not the mode S3, that is, the off mode S5, it is determined whether or not the AC adapter 51 is connected based on the signal (AC Adapter Presence) input to the embedded controller 41 (step S114). ). When the AC adapter 51 is connected, power is supplied to the PDA cradle 33D, so the embedded controller 41
The output signal (BAY_ON_EC) from is switched to "H" (step S113). On the other hand, when the AC adapter 51 is not connected, power is not supplied to the PDA cradle 33D in order to prevent the main battery 52 and the second battery 53 from being consumed. Therefore, the output signal from the embedded controller 41 ( BAY_ON_EC) to "L"
Leave as it is. (Step S104).

Thus, after step S111,
The bay device 33 to be mounted is the PDA cradle 33D
In the sleep mode S3, the charge request signal (Charge Request) is input, and in the off mode S5, the charge request signal (Charge Request) is input.
When t) is input and the AC adapter 51 is connected, the power supply to the bay 32 is turned on.

As described above, when the bay device 33 is mounted, if the power mode of the computer system 10 is the ON mode S0, the mounting process depends on the BIOS processing as in the conventional hot attach. Then
Only when the bay device 33 to be mounted is the PDA cradle 33D when not in the ON mode S0,
Turn on the power supply to the bay 32.

FIG. 8 shows the flow of processing when the bay device 33 mounted in the bay 32 is removed. In the embedded controller 41, when it is detected that the input signal (BAYUNLOCK) is changed by operating a lever or the like to remove the bay device 33 attached to the bay 32 (step S201), Computer system 10
Is on mode S0 or not (step S202). As a result, if the computer system 10 is in the ON mode S0, the BIOS is notified that the bay 32 is unlocked (step S203), and the output signal (BAY_ON_EC) from the embedded controller 41 to the OR gate 71 is Maintain "L" as it is (step S
204).

If the power supply mode of the computer system 10 is the ON mode S0 and the bay device 33 is attached to the bay 32, the output signal (BAY_ON_GA) from the gate array 42 is "H". . In this state,
The BIOS inquires of the OS whether the bay device 33 can be removed (step S205). And O
After receiving the response from S, it is determined whether the OS permits the removal of the bay device 33 (step S206), and
If S permits, register 42 of gate array 42
"0" is written in a (step S207). Then, the output signal (BAY_ON_GA) from the gate array 42 becomes "L" (step S208). As a result, the OR gate 71
The output signal (BAY_ON) from the embedded controller 41 is “L”, and the output signal from the gate array 42 (BAY_ON_GA) is also “L”. Therefore, according to the logic table of FIG. 2B. It becomes “L”, and the power supply to the bay device 33 is turned off.

On the other hand, in step S206, when the OS does not permit the removal of the bay device 33, the BIOS
Keeps the register 42a of the gate array 42 at "1" (step S209). Then, the gate array 42
The output signal (BAY_ON_GA) from is still "H" (step S210). As a result, as for the output signal (BAY_ON) from the OR gate 71, the output signal (BAY_ON_EC) from the embedded controller 41 is “L”, and the output signal (BAY_ON_GA) from the gate array 42 is “H”, so that FIG. ), The power supply to the bay device 33 remains on, and the bay device 33
Refuse to remove and keep the state before removal.

If it is determined in step S202 that the computer system 10 is not in the ON mode S0, the following processing is performed. Here, if the computer system 10 is not in the ON mode S0 and the bay device 33 is attached to the bay 32, the output signal (BAY_ON_GA) from the gate array 42 is “L”. When the computer system 10 is not in the on mode S0, first, it is determined whether the computer system 10 is in the sleep mode S3 (step S).
211). As a result, when the computer system 10 is not in the sleep mode S3, that is, the off mode S5.
If so, the output signal (BAY_ON_EC) from the embedded controller 41 is set to "L" (step S21).
2). In this case, the output signal (BAY_
ON_GA) is “L”, the output signal (BAY_ON) from the OR gate 71 becomes “L” according to the logical value table of FIG. 2B, the power supply to the bay device 33 is turned off, and the bay device 33 is turned off. Can be removed.

On the other hand, when it is determined in step S211 that the computer system 10 is in the sleep mode S3, it is determined whether the bay device 33 attached to the bay 32 is removable (step S21).
3). Here, for example, the IDE device 33 is installed in the bay 32.
As A, when the HDD used for starting (booting) the computer system 10 is mounted, it cannot be permitted to remove it. In such a case,
The embedded controller 41 wakes up the OS to turn on the computer system 10 in the on mode S.
A signal (EC_WAKEUP) for returning to 0 is output (step S214). In this case, the output signal (BAY_ON_EC) from the embedded controller 41 maintains "H" (step S215), and the output signal (BAY_EC) from the gate array 42.
ON_GA) is “L”, so O according to the logical value table of FIG.
The output signal from the R gate 71 becomes "H", and the power supply to the bay device 33 remains on. If it is determined in step S213 that the bay device 33 is removable, the output signal (BAY_ON_EC) from the embedded controller 41 is set to "L" (step S212). Output signal from the gate array 42 (BA
Y_ON_GA) is "L", so that the output signal (BAY_ON) from the OR gate 71 becomes "L" according to the logic table of FIG. 2B, and the power supply to the bay device 33 is turned off. The bay device 33 can be removed.

As shown in FIG. 9, the computer system 10 has an off mode S5 or a sleep mode S5.
3 shows a flow in the case of shifting from 3 to the ON mode S0. In the off mode S5 or the sleep mode S3, the embedded controller 41
It has a power management function together with the gate array 42. In this state, the output signal (BAY_ON_EC) from the embedded controller 41 is "L". When the embedded controller 41 detects the transition of the computer system 10 to the on mode by detecting an event that occurs in response to some operation performed by the user (step S301), the bay device to the bay 32 is set. Whether or not the device 33 is attached is detected, and if there is the attached bay device 33, the identification signal (BAYIDs) corresponding to the type is read (step S302). Then, the read identification signal (BAYIDs) of the bay device 33 is notified to the BIOS (step S303).

On the BIOS side, the identification signal of the bay device 33 (B
The type of the bay device 33 attached to the bay 32 is identified based on AYIDs) (step S304). And
Whether or not the attached bay device 33 is operable in the computer system 10 is determined in advance by the BIOS.
A judgment is made based on the information written in S (step S305). As a result, when the attached bay device 33 is not registered in the BIOS,
When it is determined that the gate array 42 is not operable, the register 42a of the gate array 42 remains "0" (step S306). Then, the output signal from the gate array 42
(BAY_ON_GA) remains "L" (step S30)
7). On the other hand, when the attached bay device 33 is an operable device in step S305, "1" is written in the register 42a of the gate array 42 (step S308). Then, the output signal (BAY_ON_GA) from the gate array 42 becomes "H" (step S3).
09).

By the way, the embedded controller 41
In step S303, after notifying the BIOS of the identification signal (BAYIDs) of the attached bay device 33, the output signal from the embedded controller 41
(BAY_ON_EC) determines whether the power supply to the bay 32 is turned on in the computer system 10 in the off mode S5 or the sleep mode S3. For example, when power is supplied according to a charge request signal (Charge Request) output from the PDA cradle 33D, or in the sleep mode S3.
When the SB device 33B is connected and the USB wakeup is enabled, the output signal (BAY_ON_EC) from the embedded controller 41 is “H”.
And the power supply to the bay 32 is turned on,
Is determined (step S310).

As a result, the embedded controller 41
When the output signal (BAY_ON_EC) from the device is “H” and it is determined that the power supply to the bay 32 is turned on, the output signal (BAY
_ON_EC) is set to "L" (step S311). On the other hand, the output signal from the embedded controller 41 (BAY_ON_E
C) is "L", and when it is determined that the power supply to the bay 32 is not turned on, the output signal (BAY_ON_EC) from the embedded controller 41 remains "L" ( Step S312).

By the above processing, the output signal (BAY_ON_EC) from the embedded controller 41 is obtained.
Becomes "L" in any case in step S311 or S312. In contrast,
The output signal (BAY_ON_GA) from the gate array 42 changes to "L" or "H" depending on whether or not the bay device 33 attached to the bay 32 is an operable device. That is, the computer system 1
When 0 is shifted from the off mode S5 or the sleep mode S3 to the on mode S0, the power control by the embedded controller 41 until then shifts to the power control on the BIOS, that is, the OS side. Since the output signal (BAY_ON_EC) from the embedded controller 41 is “L” in any case, when the bay device 33 attached to the bay 32 is not an operable device, the output signal from the gate array 42 ( BAY_ON_GA) becomes “L” and the bay device 3
The power supply of the computer system 10 shifts to the ON mode S0 while the power supply to 3 is kept off. When the bay device 33 attached to the bay 32 is an operable device, the output signal (BAY_O
N_GA) becomes "H", the power supply to the bay device 33 is turned on, and the power supply of the computer system 10 shifts to the on mode S0.

In FIG. 10, the computer system 10 changes from the on mode S0 to the sleep mode S3.
It shows the flow when shifting to. In this case, if the computer system 10 is in the ON mode S0,
Power control for the bay 32 is under the control of the BIOS. If the BIOS detects that the computer system 10 is about to transition from the on mode S0 to the sleep mode S3, the BIOS
First, it detects whether or not the bay device 33 is attached to the bay 32 (step S401). As a result, if the bay device 33 is not attached, O
S is instructed to shift to the sleep mode S3 (step S402), and the output signal (BA
Y_ON_GA) is set to "L" (step S403).

On the other hand, in step S401, the bay device 3
If 3 is detected attached, then
The BIOS notifies the embedded controller 41 of the information as to whether the attached bay device 33 is removable during the sleep mode S3 based on the information registered in itself (step S404). . The BIOS further determines whether the attached bay device 33 is a device that requires power when in the sleep mode S3.
(Step S405). If the attached bay device 33 is a USB device 33B such as a 10 keypad,
If it is the PDA cradle 33D, it is determined that the device requires power in sleep mode S3, and
The IOS instructs the embedded controller 41 to hold the power supply to the bay device 33 even after shifting to the sleep mode S3 (step S406). After such processing, the BIOS instructs the OS to shift to the sleep mode S3 (step S40
2), the output signal (BAY_ON_GA) from the gate array 42 is set to "L" (step S403). On the other hand, in step S405, the attached bay device 33
However, if it is determined in sleep mode S3 that the device does not require power, the BIOS instructs the OS to shift to sleep mode S3 (step S40).
2), the output signal (BAY_ON_GA) from the gate array 42 is set to "L" (step S403).

Now, the embedded controller 41 obtains the information as to whether the attached bay device 33 is removable during the sleep mode S3 by the notification from the BIOS in step S404 (step S404). S407). Further, when the BIOS receives an instruction from the BIOS to keep the power supply to the bay device 33 even after shifting to the sleep mode S3 in step S406, the embedded controller 4
1, the bay device 33 attached to the bay 32
Determines whether or not a power source is required in sleep mode S3 (step S408). For example, when the embedded controller 41 is set to a state where USB wakeup is possible, or when the PDA cradle 33D is attached as the bay device 33 and a charge request signal (Charge Request) is input to the embedded controller 41. Etc. to the bay device 33
On the other hand, it is determined that the power supply is necessary in the sleep mode S3. If it is determined in step S408 that the power supply is necessary, the output signal (BAY_ON_EC) from the embedded controller 41 is set to "H" (step S409), and it is determined that the power supply is not needed. Is an output signal from the embedded controller 41 (BAY
_ON_EC) is kept at "L" (step S410).

By the above processing, the output signal (BAY_ON_GA) from the gate array 42 is changed to the step S
In 403, it becomes "L" in any case. On the other hand, the output signal (BAY_ON_EC) from the embedded controller 41 changes to "L" or "H" depending on whether power supply is necessary in the sleep mode S3. That is, the computer system 10 is switched from the on mode S0 to the sleep mode S3.
When shifting from the ON mode S0 to the ON mode S0, the power control by the BIOS, that is, the OS side until then, shifts to the power control by the embedded controller 41. Since the output signal (BAY_ON_GA) from the gate array 42 is “L” in any case, the bay device 33 attached to the bay 32 is a USB device such as a 10 keypad that requires power in the sleep mode S3.
When the device 33B or the PDA cradle 33D is used, the output signal (BAY
_ON_EC) becomes "H", the power supply to the bay device 33 remains on, and the power supply of the computer system 10 shifts to the sleep mode S3. Also, the bay 32
Bay device 33 attached to the sleep mode S3
Output signal (BAY_ON_EC) from the embedded controller 41 is “L” when the power supply is not required in
Then, the power supply of the computer system 10 shifts to the sleep mode S3 while the power supply to the bay device 33 remains off.

FIG. 11 shows a flow when the computer system 10 shifts from the on mode S0 to the off mode S5. In this case, the BIOS detects a predetermined event for shifting to the off mode S5, and based on this, instructs the shift to the off mode S5 (step S501). Then, the output signal (BAY_ON_GA) from the gate array 42 becomes "L" (step S5).
02). On the other hand, in the embedded controller 41, B
When the shift from IOS etc. to the off mode S5 is detected
(Step S503) First, it is detected whether or not the PDA cradle 33D is attached to the bay 32 (step S504).

As a result, if the PDA cradle 33D is not attached, the embedded controller 41
The output signal (BAY_ON_EC) from is kept at "L" (step S505). On the other hand, PDA cradle 33D
If is attached, then it is detected whether or not the AC adapter 51 is connected to the computer system 10 (step S506). When the AC adapter 51 is not connected, the main battery 52 and the second battery 53 are used for driving, so the output signal (BAY_ON_EC) from the embedded controller 41 is kept at "L".
(Step S505). If the AC adapter 51 is connected, the output signal (BAY_ON_EC) from the embedded controller 41 is set to "H" (step S50).
7). This turns on the computer system 10.
When the mode S0 shifts to the off mode S5, the bay 3
2 is equipped with PDA cradle 33D and AC
Only when the adapter 51 is connected, the output signal (BAY_ON_EC) from the embedded controller 41 is “H”, and the output signal from the gate array 42 (BAY_ON_GA).
Becomes “L”, and the output signal (BAY_O
N) becomes "H" and power is supplied.

By executing the above-mentioned processing, the status of the power supply control shown in the list of FIG. 6 can be realized. In the computer system 10 as described above, with respect to the bay device 33 connected to the bay 32, power control by the OS and BIOS is performed in the on mode S0 as in the conventional case, and in the sleep mode S3 and the off mode S5,
The power supply is controlled by the embedded controller 41. As a result, regardless of the type of the bay device 33 connected to the bay 32, a USB key such as a 10 keypad is set when the USB wakeup is set in the sleep mode S3 without providing a separate power supply system. Supply power to the device 33B,
It is possible to realize various variations of power supply modes such as supplying power to the PDA cradle 33D in the sleep mode S3 and the off mode S5. Further, by using the OR gate 71, it is possible to set such that the output signals (BAY_ON_EC, BAY_ON_GA) from the embedded controller 41 and the gate array 42 do not interfere with each other. Further, the power supply control status indicates that the power mode of the computer system 10 is ON mode S0, sleep mode S
3. The configuration is reviewed when changing between the off mode S5 and when the bay device 33 is hot-swapped or warm-swapped with respect to the bay 32, whereby an optimum power supply state can always be created.

In the above embodiment, as the bay device 33, the IDE device 33A and the USB device 3 are used.
3B, FDD 33C, and PDA cradle 33D are given as examples, but each of them may have any configuration, and devices other than those mentioned above may be used as the bay device 3
It is also possible to mount it in the bay 32 as 3. Also,
The external expansion device detachably attached to the computer system 10 and the bay device 33 are given as an example of the external device, but the present invention is not limited to this, and the same configuration can be applied to other devices such as a PC card. Can be applied. Further, the power supply status as shown in FIG. 6 is merely an example, and it is a matter that can be changed as appropriate as to which power supply form to be attached to the bay device 33 to be mounted. Further, with respect to the processing flows shown in FIGS. 7 to 11, there is no problem even if they are appropriately changed as long as the same function can be realized. Other than this, the configurations described in the above embodiments can be selected or changed to other configurations without departing from the gist of the present invention.

[0062]

As described above, according to the present invention,
It is possible to realize various variations of power supply forms.

[Brief description of drawings]

FIG. 1 is a diagram showing a hardware configuration of a computer system according to the present embodiment.

FIG. 2A is a diagram showing a configuration of a part that controls power supply for a bay device of a computer system;
(b) is a diagram showing a logical value table in the OR gate.

FIG. 3 is a diagram showing a transition state of a power mode in a computer system.

FIG. 4 is a diagram showing a power supply state in a sleep mode.

FIG. 5 is a diagram showing a power supply state in an off mode.

FIG. 6 shows a status list of power supply control.

FIG. 7 is a diagram showing a flow of processing when mounting a bay device.

FIG. 8 is a diagram showing a flow of processing when a bay device is removed.

FIG. 9 is a diagram showing a flow of processing at the time of transition to an on mode.

FIG. 10 is a diagram showing a flow of processing when transitioning to a sleep mode.

FIG. 11 is a diagram showing a flow of processing at the time of transition to the off mode.

FIG. 12 is a diagram showing a configuration of a part that controls power supply for a conventional bay device.

FIG. 13 is a diagram showing another example of a configuration of a part that controls power supply for a conventional bay device.

[Explanation of symbols]

10 ... Computer system (computer device), 11
... CPU, 32 ... Bay (connector, expansion base), 33 ...
Bay device (external expansion device, external device), 33
A ... IDE device, 33B ... USB device, 33C
... FDD, 33D ... PDA cradle, 41 ... Embedded controller (second control means, second controller), 42 ... Gate array (first control means, first controller), 50 ... Power supply circuit, 51 ...
AC adapter (power supply), 52 ... Main battery (power supply), 53 ...
Second battery (power supply), 71 ... OR gate (determination unit, control unit), 72 ... VCC, 73 ... FET switch (power supply unit, control unit)

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Noriyuki Kato             1623 1423 Shimotsuruma, Yamato-shi, Kanagawa Japan             BM Co., Ltd. Daiwa Office (72) Inventor Satoshi Yamazaki             1623 1423 Shimotsuruma, Yamato-shi, Kanagawa Japan             BM Co., Ltd. Daiwa Office (72) Inventor Tomoe Kosugi             1623 1423 Shimotsuruma, Yamato-shi, Kanagawa Japan             BM Co., Ltd. Daiwa Office (72) Inventor Noriyoshi Yoshiyama             1623 1423 Shimotsuruma, Yamato-shi, Kanagawa Japan             BM Co., Ltd. Daiwa Office (72) Inventor Takashi Yomo             1623 1423 Shimotsuruma, Yamato-shi, Kanagawa Japan             BM Co., Ltd. Daiwa Office F-term (reference) 5B011 DB21 EA02 EB07 LL11 MA13

Claims (18)

[Claims] 1. A computer device to which an external expansion device can be attached, comprising: first control means for controlling power supply to the external expansion device when the computer device is in an ON mode; and the computer device. Second control means for controlling the power supply to the external expansion device when in the hibernation state, the second control means being attached to the computer device when the computer device is in the hibernation state. A computer apparatus, which supplies power to the external expansion device according to the type of the external expansion device. 2. The computer device according to claim 1, wherein the second control unit controls power supply to the external expansion device according to a type of a power source for driving the computer device. 3. The second control means supplies power to the external expansion device when the external expansion device has a charging function for a device connected to the external expansion device. The computer device according to claim 1. 4. The computer apparatus according to claim 3, wherein the second control means supplies power to the external expansion device when receiving a power supply request signal from the external expansion device. 5. The second control means, when the external expansion device has a function of returning the computer apparatus to an ON mode in response to an input made to the external expansion device, 2. The computer device according to claim 1, wherein power is supplied to the external expansion device in a sleep state. 6. The second control means supplies power to the external expansion device when the external expansion device is set to return to the ON mode for the computer device. The computer device according to claim 5. 7. A computer device in which an external device is attachable / detachable and a power supply mode can be switched to an on mode, a sleep mode, and an off mode, and a connector for detachably connecting the external device, the computer. A power supply circuit for controlling power supply to the device; a first controller for outputting a signal for controlling power supply to the connector based on an instruction of a basic input / output system; and a sleep mode or an off state for the computer device. A second controller that outputs a signal for controlling power supply to the connector according to the type of the external device connected to the connector when in the mode; and a signal from the first controller and the signal Power supply to the connector based on the signal from the second controller Computer for the whether the determination unit performs, characterized in that it comprises a power supply unit for turning on and off the power supply to the connector from the power supply circuit based on the determination result of the determination unit. 8. The signal from the first controller is unchanged when the computer device is in the sleep mode or the off mode, and whether the predetermined external device registered in advance in the connector is connected. 8. The computer device according to claim 7, wherein the signal from the second controller changes depending on whether or not the second controller is used. 9. The signal from the second controller is unchanged when the computer device is in the on mode, and the first controller is dependent on whether the external device is connected to the connector. 8. A computer system as claimed in claim 7, characterized in that the signal from is varied. 10. The computer apparatus according to claim 7, wherein the determination unit determines whether or not to supply power to the connector when the power mode of the computer apparatus shifts. 11. The determination unit determines whether to supply power to the connector when the external device is attached to or detached from the connector. Computer equipment. 12. A computer device in which an external device is attachable / detachable and a power supply mode can be switched to an on mode, a sleep mode, and an off mode, and a connector for detachably connecting the external device, the computer Power is supplied to the connector when under the control of an operating system for controlling the device, and power is supplied to the connector according to the type of the external device connected to the connector when not under the control of the operating system. And a controller for controlling the computer. 13. An expansion-based power control device to which an external device can be attached, the first controller outputting a signal for controlling power supply when under control of the operating system, and the operating system. When not under the control of, the second controller that outputs a signal for controlling the power supply to the expansion base according to the type of the external device attached to the expansion base, and from the first controller And a control unit that controls power supply to the expansion base based on a signal and a signal from the second controller. 14. A power management method in a computer device having a connector to which an external expansion device can be attached, the method comprising: identifying the type of the external expansion device attached to the connector; Detecting a power supply mode, determining whether to supply power to the connector based on the type of the external expansion device identified and the detected power supply mode; And a step of supplying power to the connector. 15. The method further comprises the step of detecting the type of power supply for driving the computer device, and in the determining step, whether or not power is supplied to the connector in consideration of the detected type of power supply. 15. The power management method according to claim 14, further comprising: 16. The method further comprises a step of detecting attachment or detachment of the external expansion device to or from the computer apparatus, wherein in the determining step, the external expansion device is attached or the external expansion device is detached. 15. The power management method according to claim 14, wherein it is determined whether or not power is supplied to the connector in the state. 17. The method further comprises the step of detecting whether or not there is a power supply request from the external expansion device connected to the connector, wherein in the determining step, the connector is provided when the power supply request is made. 15. The power management method according to claim 14, wherein it is determined that power is supplied to the. 18. When it is detected that the external expansion device connected to the connector is detached from the connector when the power mode of the computer device is the sleep mode or the off mode, the connector from the connector is detected. The method further includes the step of determining whether or not the external expansion device can be removed, and the step of shifting the power mode of the computer apparatus to an on mode when the external expansion device is not removed from the connector. 15. The power management method according to claim 14, wherein: